1/* 2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <tsp.h> 34#include <xlat_tables.h> 35#include "../tsp_private.h" 36 37 38 .globl tsp_entrypoint 39 .globl tsp_vector_table 40 41 42 43 /* --------------------------------------------- 44 * Populate the params in x0-x7 from the pointer 45 * to the smc args structure in x0. 46 * --------------------------------------------- 47 */ 48 .macro restore_args_call_smc 49 ldp x6, x7, [x0, #TSP_ARG6] 50 ldp x4, x5, [x0, #TSP_ARG4] 51 ldp x2, x3, [x0, #TSP_ARG2] 52 ldp x0, x1, [x0, #TSP_ARG0] 53 smc #0 54 .endm 55 56 .macro save_eret_context reg1 reg2 57 mrs \reg1, elr_el1 58 mrs \reg2, spsr_el1 59 stp \reg1, \reg2, [sp, #-0x10]! 60 stp x30, x18, [sp, #-0x10]! 61 .endm 62 63 .macro restore_eret_context reg1 reg2 64 ldp x30, x18, [sp], #0x10 65 ldp \reg1, \reg2, [sp], #0x10 66 msr elr_el1, \reg1 67 msr spsr_el1, \reg2 68 .endm 69 70 .section .text, "ax" 71 .align 3 72 73func tsp_entrypoint 74 75 /* --------------------------------------------- 76 * Set the exception vector to something sane. 77 * --------------------------------------------- 78 */ 79 adr x0, tsp_exceptions 80 msr vbar_el1, x0 81 isb 82 83 /* --------------------------------------------- 84 * Enable the SError interrupt now that the 85 * exception vectors have been setup. 86 * --------------------------------------------- 87 */ 88 msr daifclr, #DAIF_ABT_BIT 89 90 /* --------------------------------------------- 91 * Enable the instruction cache, stack pointer 92 * and data access alignment checks 93 * --------------------------------------------- 94 */ 95 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 96 mrs x0, sctlr_el1 97 orr x0, x0, x1 98 msr sctlr_el1, x0 99 isb 100 101 /* --------------------------------------------- 102 * Zero out NOBITS sections. There are 2 of them: 103 * - the .bss section; 104 * - the coherent memory section. 105 * --------------------------------------------- 106 */ 107 ldr x0, =__BSS_START__ 108 ldr x1, =__BSS_SIZE__ 109 bl zeromem16 110 111#if USE_COHERENT_MEM 112 ldr x0, =__COHERENT_RAM_START__ 113 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 114 bl zeromem16 115#endif 116 117 /* -------------------------------------------- 118 * Allocate a stack whose memory will be marked 119 * as Normal-IS-WBWA when the MMU is enabled. 120 * There is no risk of reading stale stack 121 * memory after enabling the MMU as only the 122 * primary cpu is running at the moment. 123 * -------------------------------------------- 124 */ 125 bl plat_set_my_stack 126 127 /* --------------------------------------------- 128 * Perform early platform setup & platform 129 * specific early arch. setup e.g. mmu setup 130 * --------------------------------------------- 131 */ 132 bl tsp_early_platform_setup 133 bl tsp_plat_arch_setup 134 135 /* --------------------------------------------- 136 * Jump to main function. 137 * --------------------------------------------- 138 */ 139 bl tsp_main 140 141 /* --------------------------------------------- 142 * Tell TSPD that we are done initialising 143 * --------------------------------------------- 144 */ 145 mov x1, x0 146 mov x0, #TSP_ENTRY_DONE 147 smc #0 148 149tsp_entrypoint_panic: 150 b tsp_entrypoint_panic 151endfunc tsp_entrypoint 152 153 154 /* ------------------------------------------- 155 * Table of entrypoint vectors provided to the 156 * TSPD for the various entrypoints 157 * ------------------------------------------- 158 */ 159func tsp_vector_table 160 b tsp_std_smc_entry 161 b tsp_fast_smc_entry 162 b tsp_cpu_on_entry 163 b tsp_cpu_off_entry 164 b tsp_cpu_resume_entry 165 b tsp_cpu_suspend_entry 166 b tsp_fiq_entry 167 b tsp_system_off_entry 168 b tsp_system_reset_entry 169endfunc tsp_vector_table 170 171 /*--------------------------------------------- 172 * This entrypoint is used by the TSPD when this 173 * cpu is to be turned off through a CPU_OFF 174 * psci call to ask the TSP to perform any 175 * bookeeping necessary. In the current 176 * implementation, the TSPD expects the TSP to 177 * re-initialise its state so nothing is done 178 * here except for acknowledging the request. 179 * --------------------------------------------- 180 */ 181func tsp_cpu_off_entry 182 bl tsp_cpu_off_main 183 restore_args_call_smc 184endfunc tsp_cpu_off_entry 185 186 /*--------------------------------------------- 187 * This entrypoint is used by the TSPD when the 188 * system is about to be switched off (through 189 * a SYSTEM_OFF psci call) to ask the TSP to 190 * perform any necessary bookkeeping. 191 * --------------------------------------------- 192 */ 193func tsp_system_off_entry 194 bl tsp_system_off_main 195 restore_args_call_smc 196endfunc tsp_system_off_entry 197 198 /*--------------------------------------------- 199 * This entrypoint is used by the TSPD when the 200 * system is about to be reset (through a 201 * SYSTEM_RESET psci call) to ask the TSP to 202 * perform any necessary bookkeeping. 203 * --------------------------------------------- 204 */ 205func tsp_system_reset_entry 206 bl tsp_system_reset_main 207 restore_args_call_smc 208endfunc tsp_system_reset_entry 209 210 /*--------------------------------------------- 211 * This entrypoint is used by the TSPD when this 212 * cpu is turned on using a CPU_ON psci call to 213 * ask the TSP to initialise itself i.e. setup 214 * the mmu, stacks etc. Minimal architectural 215 * state will be initialised by the TSPD when 216 * this function is entered i.e. Caches and MMU 217 * will be turned off, the execution state 218 * will be aarch64 and exceptions masked. 219 * --------------------------------------------- 220 */ 221func tsp_cpu_on_entry 222 /* --------------------------------------------- 223 * Set the exception vector to something sane. 224 * --------------------------------------------- 225 */ 226 adr x0, tsp_exceptions 227 msr vbar_el1, x0 228 isb 229 230 /* Enable the SError interrupt */ 231 msr daifclr, #DAIF_ABT_BIT 232 233 /* --------------------------------------------- 234 * Enable the instruction cache, stack pointer 235 * and data access alignment checks 236 * --------------------------------------------- 237 */ 238 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 239 mrs x0, sctlr_el1 240 orr x0, x0, x1 241 msr sctlr_el1, x0 242 isb 243 244 /* -------------------------------------------- 245 * Give ourselves a stack whose memory will be 246 * marked as Normal-IS-WBWA when the MMU is 247 * enabled. 248 * -------------------------------------------- 249 */ 250 bl plat_set_my_stack 251 252 /* -------------------------------------------- 253 * Enable the MMU with the DCache disabled. It 254 * is safe to use stacks allocated in normal 255 * memory as a result. All memory accesses are 256 * marked nGnRnE when the MMU is disabled. So 257 * all the stack writes will make it to memory. 258 * All memory accesses are marked Non-cacheable 259 * when the MMU is enabled but D$ is disabled. 260 * So used stack memory is guaranteed to be 261 * visible immediately after the MMU is enabled 262 * Enabling the DCache at the same time as the 263 * MMU can lead to speculatively fetched and 264 * possibly stale stack memory being read from 265 * other caches. This can lead to coherency 266 * issues. 267 * -------------------------------------------- 268 */ 269 mov x0, #DISABLE_DCACHE 270 bl bl32_plat_enable_mmu 271 272 /* --------------------------------------------- 273 * Enable the Data cache now that the MMU has 274 * been enabled. The stack has been unwound. It 275 * will be written first before being read. This 276 * will invalidate any stale cache lines resi- 277 * -dent in other caches. We assume that 278 * interconnect coherency has been enabled for 279 * this cluster by EL3 firmware. 280 * --------------------------------------------- 281 */ 282 mrs x0, sctlr_el1 283 orr x0, x0, #SCTLR_C_BIT 284 msr sctlr_el1, x0 285 isb 286 287 /* --------------------------------------------- 288 * Enter C runtime to perform any remaining 289 * book keeping 290 * --------------------------------------------- 291 */ 292 bl tsp_cpu_on_main 293 restore_args_call_smc 294 295 /* Should never reach here */ 296tsp_cpu_on_entry_panic: 297 b tsp_cpu_on_entry_panic 298endfunc tsp_cpu_on_entry 299 300 /*--------------------------------------------- 301 * This entrypoint is used by the TSPD when this 302 * cpu is to be suspended through a CPU_SUSPEND 303 * psci call to ask the TSP to perform any 304 * bookeeping necessary. In the current 305 * implementation, the TSPD saves and restores 306 * the EL1 state. 307 * --------------------------------------------- 308 */ 309func tsp_cpu_suspend_entry 310 bl tsp_cpu_suspend_main 311 restore_args_call_smc 312endfunc tsp_cpu_suspend_entry 313 314 /*--------------------------------------------- 315 * This entrypoint is used by the TSPD to pass 316 * control for handling a pending S-EL1 FIQ. 317 * 'x0' contains a magic number which indicates 318 * this. TSPD expects control to be handed back 319 * at the end of FIQ processing. This is done 320 * through an SMC. The handover agreement is: 321 * 322 * 1. PSTATE.DAIF are set upon entry. 'x1' has 323 * the ELR_EL3 from the non-secure state. 324 * 2. TSP has to preserve the callee saved 325 * general purpose registers, SP_EL1/EL0 and 326 * LR. 327 * 3. TSP has to preserve the system and vfp 328 * registers (if applicable). 329 * 4. TSP can use 'x0-x18' to enable its C 330 * runtime. 331 * 5. TSP returns to TSPD using an SMC with 332 * 'x0' = TSP_HANDLED_S_EL1_FIQ 333 * --------------------------------------------- 334 */ 335func tsp_fiq_entry 336#if DEBUG 337 mov x2, #(TSP_HANDLE_FIQ_AND_RETURN & ~0xffff) 338 movk x2, #(TSP_HANDLE_FIQ_AND_RETURN & 0xffff) 339 cmp x0, x2 340 b.ne tsp_fiq_entry_panic 341#endif 342 /*--------------------------------------------- 343 * Save any previous context needed to perform 344 * an exception return from S-EL1 e.g. context 345 * from a previous IRQ. Update statistics and 346 * handle the FIQ before returning to the TSPD. 347 * IRQ/FIQs are not enabled since that will 348 * complicate the implementation. Execution 349 * will be transferred back to the normal world 350 * in any case. A non-zero return value from the 351 * fiq handler is an error. 352 * --------------------------------------------- 353 */ 354 save_eret_context x2 x3 355 bl tsp_update_sync_fiq_stats 356 bl tsp_fiq_handler 357 cbnz x0, tsp_fiq_entry_panic 358 restore_eret_context x2 x3 359 mov x0, #(TSP_HANDLED_S_EL1_FIQ & ~0xffff) 360 movk x0, #(TSP_HANDLED_S_EL1_FIQ & 0xffff) 361 smc #0 362 363tsp_fiq_entry_panic: 364 b tsp_fiq_entry_panic 365endfunc tsp_fiq_entry 366 367 /*--------------------------------------------- 368 * This entrypoint is used by the TSPD when this 369 * cpu resumes execution after an earlier 370 * CPU_SUSPEND psci call to ask the TSP to 371 * restore its saved context. In the current 372 * implementation, the TSPD saves and restores 373 * EL1 state so nothing is done here apart from 374 * acknowledging the request. 375 * --------------------------------------------- 376 */ 377func tsp_cpu_resume_entry 378 bl tsp_cpu_resume_main 379 restore_args_call_smc 380tsp_cpu_resume_panic: 381 b tsp_cpu_resume_panic 382endfunc tsp_cpu_resume_entry 383 384 /*--------------------------------------------- 385 * This entrypoint is used by the TSPD to ask 386 * the TSP to service a fast smc request. 387 * --------------------------------------------- 388 */ 389func tsp_fast_smc_entry 390 bl tsp_smc_handler 391 restore_args_call_smc 392tsp_fast_smc_entry_panic: 393 b tsp_fast_smc_entry_panic 394endfunc tsp_fast_smc_entry 395 396 /*--------------------------------------------- 397 * This entrypoint is used by the TSPD to ask 398 * the TSP to service a std smc request. 399 * We will enable preemption during execution 400 * of tsp_smc_handler. 401 * --------------------------------------------- 402 */ 403func tsp_std_smc_entry 404 msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 405 bl tsp_smc_handler 406 msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 407 restore_args_call_smc 408tsp_std_smc_entry_panic: 409 b tsp_std_smc_entry_panic 410endfunc tsp_std_smc_entry 411