feat(scmi): add base protocol agent API

Support protocol attributes and discover agents

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3879f703ec61

feat(scmi): add base protocol agent API

Support protocol attributes and discover agents

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3879f703ec6160bd794f48e3c41718ecce0ec88a

show more ...

feat(scmi): update version to 3.0

Update version to 3.0 to align with latest scmi spec implementation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-

feat(scmi): update version to 3.0

Update version to 3.0 to align with latest scmi spec implementation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I845e8863ca6e757b1da6f30833e6ec10e21b0667

show more ...

fix(intel): fix SDMMC driver when sdmclk running at 200MHz

When SDMMC sdmclk running at 200MHz setting the sdclk
to 25MHz will fail. so setting the sdclk to 50MHz for
SDMMC.

Change-Id: I56398893717

fix(intel): fix SDMMC driver when sdmclk running at 200MHz

When SDMMC sdmclk running at 200MHz setting the sdclk
to 25MHz will fail. so setting the sdclk to 50MHz for
SDMMC.

Change-Id: I56398893717afe1fa0de167aae532f8b8de03b1c
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

show more ...

fix(intel): fix eMMC driver issues in boot flow on agilex5

Fixed issue where reading the EXT_CSD register via CMD8
with DMA enabled returned 0 value. Updated the read mode
to handle this case correc

fix(intel): fix eMMC driver issues in boot flow on agilex5

Fixed issue where reading the EXT_CSD register via CMD8
with DMA enabled returned 0 value. Updated the read mode
to handle this case correctly.

Added polling for the ICS bit after enabling ICE when
setting the SDCLK rate. Introduced delay to ensure
proper clock stabilization.

Corrected SD_HOST_CLK to data driven from the clock manager
as sdmclk.

eMMC operates in legacy mode, which has a maximum
supported clock rate of 26 MHz. Updated the clock
setting to 25 MHz to meet this requirement.

Change-Id: I4ac2b9b69b5dec2c8166d06c736d9c2c549607de
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

show more ...

fix(console): create unique variable name

This corrects the MISRA violation C2012-5.7:
A tag name shall be a unique identifier.
Renamed the variable to ensure uniqueness.

Change-Id: I96e61caa8c6c7f

fix(console): create unique variable name

This corrects the MISRA violation C2012-5.7:
A tag name shall be a unique identifier.
Renamed the variable to ensure uniqueness.

Change-Id: I96e61caa8c6c7ff64759363afd24fc224d449f86
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

Merge changes Ib220a866,I38e6af65,I1554efdb,Iae99985e,I96f96267, ... into integration

* changes:
feat(stm32mp25-fdts): enable rng nodes for ST boards
feat(stm32mp2): prepare DDR secure area encr

Merge changes Ib220a866,I38e6af65,I1554efdb,Iae99985e,I96f96267, ... into integration

* changes:
feat(stm32mp25-fdts): enable rng nodes for ST boards
feat(stm32mp2): prepare DDR secure area encryption
feat(stm32mp2): add some platform helpers
feat(st-drivers): add RISAF driver
feat(fdts): add RISAF nodes for STM32MP25
feat(stm32mp2-fdts): add memory firewall node
feat(stm32mp2-fdts): add firewall nodes in fw-config
feat(stm32mp2): add RIF dt-binding defines
feat(stm32mp1-fdts): add MCE support for STM32MP13 DK board
feat(stm32mp1): prepare DDR secure area encryption for STM32MP13
feat(stm32mp1): enable MCE driver for STM32MP13
feat(st-drivers): add Memory Cipher Engine driver
feat(dt-bindings): add MCE DT bindings for STM32MP13
fix(st-crypto): improve RNG health test configuration
feat(st): add RNG minor version
feat(st-crypto): add multi instance and error management in RNG driver
feat(stm32mp2): add HASH and RNG compilation
feat(stm32mp25-fdts): add RNG node

show more ...

fix(console): match function parameter is decleration

This corrects the MISRA violation C2012-8.3:
matching the function parameter name in declaration with
the function definition.

Change-Id: Ib9a3

fix(console): match function parameter is decleration

This corrects the MISRA violation C2012-8.3:
matching the function parameter name in declaration with
the function definition.

Change-Id: Ib9a3b82db85bbf4fa94dc1e9a9203262c5606cd4
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

show more ...

feat(st-drivers): add RISAF driver

Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(t

feat(st-drivers): add RISAF driver

Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(through FCONF compliance) or statically.

The driver is enabled as BL2 sources. Add driver-related platform
services.
RISAF base addresses and key size are set in platform definitions.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iae99985e8db7cb2b27f9ca25669e74c8e08792d2

show more ...

feat(st-drivers): add Memory Cipher Engine driver

Memory Cipher Engine (MCE) defines, in a given address space, one region
with specific security setup (encryption).
FCONF compliance ensures region

feat(st-drivers): add Memory Cipher Engine driver

Memory Cipher Engine (MCE) defines, in a given address space, one region
with specific security setup (encryption).
FCONF compliance ensures region definition through DT.

Change-Id: I1bca9c0a89af88a72651e1a71e3f8950807eec40
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

show more ...

feat(st-crypto): add multi instance and error management in RNG driver

Allows the driver to initialize as many RNG instances as enabled in the
device tree. The driver will still use only one instanc

feat(st-crypto): add multi instance and error management in RNG driver

Allows the driver to initialize as many RNG instances as enabled in the
device tree. The driver will still use only one instance for the TF-A
purpose as it needs only one to work. The others are activated because
needed by specific IPs.

Seed errors are now also checked after null data read. The Reference
Manual recommends to always verify that RNG_DR is different from zero.
Because when it is the case a seed error can occur between RNG_SR
polling and RND_DR output reading (rare event).

Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: Ie4d7f01f4ffe5a9e2d0e5e7317b008edd3b80a17

show more ...

Merge "fix(console): ensured proper bitwise shift operation" into integration

fix(console): ensured proper bitwise shift operation

This corrects the MISRA violation C2012-12.2:
Used BIT_32() rather than manual bit shifting to prevent shifting
beyond the essential type width o

fix(console): ensured proper bitwise shift operation

This corrects the MISRA violation C2012-12.2:
Used BIT_32() rather than manual bit shifting to prevent shifting
beyond the essential type width of the left operand. This ensures
compliance with MISRA C 2012 Rule 12.2.

Change-Id: I1a4ed9366bd9ab773c4a5f6798508ead991593d2
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

show more ...

fix(arm): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a diff

fix(arm): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I7a2565ce6b8beb71dc9c711327ab72ce825111cc
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

Merge "build(handoff)!: switch to LibTL submodule" into integration

Merge "feat(dsu): support power control and autonomous powerdown config" into integration

Merge changes Iea4c11de,Icae1fb08 into integration

* changes:
fix(lx2160): add DDRC missing DIMMs
fix(nxp): driver crypto caam

feat(dsu): support power control and autonomous powerdown config

This patch allows platforms to enable certain DSU settings
to ensure memory retention and control over
cache power requests. We also

feat(dsu): support power control and autonomous powerdown config

This patch allows platforms to enable certain DSU settings
to ensure memory retention and control over
cache power requests. We also move the driver out of css
into drivers/arm. Platforms can configure the
CLUSTERPWRCTLR and CLUSTERPWRDN registers [1] to improve
power efficiency.

These registers enable finer-grained control of
DSU power state transitions, including
powerdown and retention.

IMP_CLUSTERPWRCTLR_EL1 provides:
- Functional retention: Allows configuration of the
duration of inactivity before the DSU uses
CLUSTERPACTIVE to request functional retention.

- Cache power request: These bits are output on
CLUSTERPACTIVE[19:16] to indicate to the power controller
which cache portions must remain powered.

IMP_CLUSTERPWRDN_EL1 includes:
- Powerdown: Triggers full cluster powerdown, including
control logic.

- Memory retention: Requests memory retention mode,
keeping L3 RAM contents while powering off
the rest of the DSU.

The DSU-120 TRM [2] provides the full field definitions,
which are used as references in the `dsu_driver_data` structure.

References:
[1]: https://developer.arm.com/documentation/100453/latest/
[2]: https://developer.arm.com/documentation/102547/0201/?lang=en

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I2eba808b8f2a27797782a333c65dd092b03208fe

show more ...

build(handoff)!: switch to LibTL submodule

Removes in-tree Transfer List implementation and updates all references
to use the external LibTL submodule. Updates include paths, Makefile
macros, and pl

build(handoff)!: switch to LibTL submodule

Removes in-tree Transfer List implementation and updates all references
to use the external LibTL submodule. Updates include paths, Makefile
macros, and platform integration logic to link with LibTL as a static
library.

If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:

git submodule update --init --recursive

BREAKING-CHANGE: LibTL is now included in TF-A as a submodule.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.

Change-Id: I1fa31f7b730066c27985d968698e553b00b07c38
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

feat(mmc): add define for no response

Introduce a new macro definition to represent the response type for
commands that do not expect a response. This is particularly applicable
to commands like Com

feat(mmc): add define for no response

Introduce a new macro definition to represent the response type for
commands that do not expect a response. This is particularly applicable
to commands like Command 0, which is used to reset the card and place it
into the idle state.

Change-Id: I6fe298504a7166ccd7e47c23f88945b2ce064cf9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

show more ...

feat(fvp): add GICv5 support

Factors out GICv3 specific code and replace it with GICv5. This can be
selected with FVP_USE_GIC_DRIVER=FVP_GICV5. Specifically, the FCONF
logic does not apply to GICv5

feat(fvp): add GICv5 support

Factors out GICv3 specific code and replace it with GICv5. This can be
selected with FVP_USE_GIC_DRIVER=FVP_GICV5. Specifically, the FCONF
logic does not apply to GICv5 as the bindings are completely different.

This patch does not include a device tree. This will be added at a later
date.

Change-Id: Ifd0c7b4e0bc2ea1e53a6779ab4c50c4aec39dafb
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

feat(gicv5): probe components

Asserts that the platform configuration is correct. No dynamic
discovery so only done in debug builds.

Change-Id: I56763cb422dcaa4a816a619ab4acfc6946427c64
Signed-off-

feat(gicv5): probe components

Asserts that the platform configuration is correct. No dynamic
discovery so only done in debug builds.

Change-Id: I56763cb422dcaa4a816a619ab4acfc6946427c64
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

feat(gicv5): initialise the IWB

Same idea as the IRS - do IWB initialisation that's only accessible from
EL3 when it is the MPPAS. Relies on the platform to provide wire domain
assignments and trig

feat(gicv5): initialise the IWB

Same idea as the IRS - do IWB initialisation that's only accessible from
EL3 when it is the MPPAS. Relies on the platform to provide wire domain
assignments and triggers as well as to map the config frame in device
nGnRnE memory. All wires will default to the NS domain and the platform
can override this.

Change-Id: I93aec5809aec4328d1cba832c2c6e5891e398e5b
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

feat(gicv5): initialise the IRS

Do IRS initialisation that's only accessible from the EL3 interrupt
domain. Relies on the platform to provide SPI domain assignments and
trigger modes as well as to m

feat(gicv5): initialise the IRS

Do IRS initialisation that's only accessible from the EL3 interrupt
domain. Relies on the platform to provide SPI domain assignments and
trigger modes as well as to map the config frame in device nGnRnE
memory. All wires will default to NS and the platform may override this.

Change-Id: Icbd43503753cd76fd3d80ed47eba6926494bc323
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

feat(gicv5): assign interrupt sources to appropriate security states

Assign the PPI interrupts we commonly have in the device tree to the NS
domain. This is a short-term solution that allows Linux t

feat(gicv5): assign interrupt sources to appropriate security states

Assign the PPI interrupts we commonly have in the device tree to the NS
domain. This is a short-term solution that allows Linux to fully boot.
This is expected to be fully replaced with context management when
adding world switching support as some of these are expected to be
shared between worlds.

Change-Id: I59a7b5a63f878c9a717ef81e977be7133a402f3f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

feat(gicv5): add a barebones GICv5 driver

This is the absolute minimum that's needed to compile an NS-only build
end exit out of EL3. The GIC is not used and/or configured in any way
but all the nec

feat(gicv5): add a barebones GICv5 driver

This is the absolute minimum that's needed to compile an NS-only build
end exit out of EL3. The GIC is not used and/or configured in any way
but all the necessary hooks are populated.

Notably, SCR_EL3.FIQ becomes RES1 as GICv5 behaves in a similar manner
to a GICv3 with FIQ set.

Change-Id: Idae52b9df97f4ca2996b2dcd1e5efc45478a43f2
Co-developed-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...