1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 26# the FVP platform. 27ifeq (${ENABLE_RME},1) 28FVP_TRUSTED_SRAM_SIZE := 384 29else 30FVP_TRUSTED_SRAM_SIZE := 256 31endif 32 33# Macro to enable helpers for running SPM tests. Disabled by default. 34PLAT_TEST_SPM := 0 35 36# By default dont build CPUs with no FVP model. 37BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 38 39ENABLE_FEAT_AMU := 2 40ENABLE_FEAT_AMUv1p1 := 2 41ENABLE_FEAT_HCX := 2 42ENABLE_FEAT_RNG := 2 43ENABLE_FEAT_TWED := 2 44ENABLE_FEAT_GCS := 2 45 46ifeq (${ARCH}, aarch64) 47 48ifeq (${SPM_MM}, 0) 49ifeq (${CTX_INCLUDE_FPREGS}, 0) 50 ENABLE_SME_FOR_NS := 2 51 ENABLE_SME2_FOR_NS := 2 52else 53 ENABLE_SVE_FOR_NS := 0 54 ENABLE_SME_FOR_NS := 0 55 ENABLE_SME2_FOR_NS := 0 56endif 57endif 58 59 ENABLE_BRBE_FOR_NS := 2 60 ENABLE_TRBE_FOR_NS := 2 61 ENABLE_FEAT_D128 := 2 62 ENABLE_FEAT_FPMR := 2 63 ENABLE_FEAT_MOPS := 2 64endif 65 66ENABLE_SYS_REG_TRACE_FOR_NS := 2 67ENABLE_FEAT_CSV2_2 := 2 68ENABLE_FEAT_CSV2_3 := 2 69ENABLE_FEAT_DEBUGV8P9 := 2 70ENABLE_FEAT_DIT := 2 71ENABLE_FEAT_PAN := 2 72ENABLE_FEAT_VHE := 2 73CTX_INCLUDE_NEVE_REGS := 2 74ENABLE_FEAT_SEL2 := 2 75ENABLE_TRF_FOR_NS := 2 76ENABLE_FEAT_ECV := 2 77ENABLE_FEAT_FGT := 2 78ENABLE_FEAT_FGT2 := 2 79ENABLE_FEAT_THE := 2 80ENABLE_FEAT_TCR2 := 2 81ENABLE_FEAT_S2PIE := 2 82ENABLE_FEAT_S1PIE := 2 83ENABLE_FEAT_S2POE := 2 84ENABLE_FEAT_S1POE := 2 85ENABLE_FEAT_SCTLR2 := 2 86ENABLE_FEAT_MTE2 := 2 87ENABLE_FEAT_LS64_ACCDATA := 2 88 89ifeq (${ENABLE_RME},1) 90 ENABLE_FEAT_MEC := 2 91 RMMD_ENABLE_IDE_KEY_PROG := 1 92endif 93 94# The FVP platform depends on this macro to build with correct GIC driver. 95$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 96 97# Pass FVP_CLUSTER_COUNT to the build system. 98$(eval $(call add_define,FVP_CLUSTER_COUNT)) 99 100# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 101$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 102 103# Pass FVP_MAX_PE_PER_CPU to the build system. 104$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 105 106# Pass FVP_GICR_REGION_PROTECTION to the build system. 107$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 108 109# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 110$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 111 112# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 113# choose the CCI driver , else the CCN driver 114ifeq ($(FVP_CLUSTER_COUNT), 0) 115$(error "Incorrect cluster count specified for FVP port") 116else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 117FVP_INTERCONNECT_DRIVER := FVP_CCI 118else 119FVP_INTERCONNECT_DRIVER := FVP_CCN 120endif 121 122$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 123 124# Choose the GIC sources depending upon the how the FVP will be invoked 125ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 126USE_GIC_DRIVER := 3 127 128# The GIC model (GIC-600 or GIC-500) will be detected at runtime 129GICV3_SUPPORT_GIC600 := 1 130GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 131 132FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 133ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 134BL31_SOURCES += plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c 135endif 136 137ifeq (${HW_ASSISTED_COHERENCY}, 0) 138FVP_DT_PREFIX := fvp-base-gicv3-psci 139else 140FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 141endif 142else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV5) 143USE_GIC_DRIVER := 5 144ENABLE_FEAT_GCIE := 1 145BL31_SOURCES += plat/arm/board/fvp/fvp_gicv5.c 146FVP_DT_PREFIX := "FVP does not provide a GICv5 dts yet" 147else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 148USE_GIC_DRIVER := 2 149 150# No GICv4 extension 151GIC_ENABLE_V4_EXTN := 0 152$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 153 154FVP_DT_PREFIX := fvp-base-gicv2-psci 155else 156$(error "Incorrect GIC driver chosen on FVP port") 157endif 158 159ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 160FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 161else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 162FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 163 plat/arm/common/arm_ccn.c 164else 165$(error "Incorrect CCN driver chosen on FVP port") 166endif 167 168FVP_SECURITY_SOURCES += drivers/arm/tzc/tzc400.c \ 169 plat/arm/board/fvp/fvp_security.c \ 170 plat/arm/common/arm_tzc400.c 171 172 173PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 174 -Iinclude/lib/psa 175 176 177PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 178 179FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 180 181ifeq (${ARCH}, aarch64) 182 183# select a different set of CPU files, depending on whether we compile for 184# hardware assisted coherency cores or not 185ifeq (${HW_ASSISTED_COHERENCY}, 0) 186# Cores used without DSU 187 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 188 lib/cpus/aarch64/cortex_a53.S \ 189 lib/cpus/aarch64/cortex_a57.S \ 190 lib/cpus/aarch64/cortex_a72.S \ 191 lib/cpus/aarch64/cortex_a73.S 192else 193# Cores used with DSU only 194 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 195 # AArch64-only cores 196 # TODO: add all cores to the appropriate lists 197 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 198 lib/cpus/aarch64/cortex_a65ae.S \ 199 lib/cpus/aarch64/cortex_a76.S \ 200 lib/cpus/aarch64/cortex_a76ae.S \ 201 lib/cpus/aarch64/cortex_a77.S \ 202 lib/cpus/aarch64/cortex_a78.S \ 203 lib/cpus/aarch64/cortex_a78_ae.S \ 204 lib/cpus/aarch64/cortex_a78c.S \ 205 lib/cpus/aarch64/cortex_a710.S \ 206 lib/cpus/aarch64/cortex_a715.S \ 207 lib/cpus/aarch64/cortex_a720.S \ 208 lib/cpus/aarch64/cortex_a720_ae.S \ 209 lib/cpus/aarch64/neoverse_n1.S \ 210 lib/cpus/aarch64/neoverse_n2.S \ 211 lib/cpus/aarch64/neoverse_v1.S \ 212 lib/cpus/aarch64/neoverse_e1.S \ 213 lib/cpus/aarch64/cortex_x2.S \ 214 lib/cpus/aarch64/cortex_x4.S 215 endif 216 # AArch64/AArch32 cores 217 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 218 lib/cpus/aarch64/cortex_a75.S 219endif 220 221#Include all CPUs to build to support all-errata build. 222ifeq (${ENABLE_ERRATA_ALL},1) 223 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 224 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \ 225 lib/cpus/aarch64/cortex_a510.S \ 226 lib/cpus/aarch64/cortex_a520.S \ 227 lib/cpus/aarch64/cortex_a725.S \ 228 lib/cpus/aarch64/cortex_x1.S \ 229 lib/cpus/aarch64/cortex_x3.S \ 230 lib/cpus/aarch64/cortex_x925.S \ 231 lib/cpus/aarch64/neoverse_n3.S \ 232 lib/cpus/aarch64/neoverse_v2.S \ 233 lib/cpus/aarch64/neoverse_v3.S 234endif 235 236#Build AArch64-only CPUs with no FVP model yet. 237ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 238 # travis/gelas need these 239 FEAT_PABANDON := 1 240 ERRATA_SME_POWER_DOWN := 1 241 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_gelas.S \ 242 lib/cpus/aarch64/nevis.S \ 243 lib/cpus/aarch64/travis.S \ 244 lib/cpus/aarch64/cortex_alto.S 245endif 246 247else 248FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 249 lib/cpus/aarch32/cortex_a57.S \ 250 lib/cpus/aarch32/cortex_a53.S 251endif 252 253BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 254 drivers/arm/sp805/sp805.c \ 255 drivers/delay_timer/delay_timer.c \ 256 drivers/io/io_semihosting.c \ 257 lib/semihosting/semihosting.c \ 258 lib/semihosting/${ARCH}/semihosting_call.S \ 259 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 260 plat/arm/board/fvp/fvp_bl1_setup.c \ 261 plat/arm/board/fvp/fvp_cpu_pwr.c \ 262 plat/arm/board/fvp/fvp_err.c \ 263 plat/arm/board/fvp/fvp_io_storage.c \ 264 plat/arm/board/fvp/fvp_topology.c \ 265 ${FVP_CPU_LIBS} \ 266 ${FVP_INTERCONNECT_SOURCES} 267 268ifeq (${USE_SP804_TIMER},1) 269BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 270else 271BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 272endif 273 274 275BL2_SOURCES += drivers/arm/sp805/sp805.c \ 276 drivers/io/io_semihosting.c \ 277 lib/utils/mem_region.c \ 278 lib/semihosting/semihosting.c \ 279 lib/semihosting/${ARCH}/semihosting_call.S \ 280 plat/arm/board/fvp/fvp_bl2_setup.c \ 281 plat/arm/board/fvp/fvp_err.c \ 282 plat/arm/board/fvp/fvp_io_storage.c \ 283 plat/arm/common/arm_nor_psci_mem_protect.c \ 284 ${FVP_SECURITY_SOURCES} 285 286 287ifeq (${COT_DESC_IN_DTB},1) 288BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 289endif 290 291ifeq (${ENABLE_RME},1) 292BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 293 plat/arm/board/fvp/fvp_cpu_pwr.c 294 295BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 296 plat/arm/board/fvp/fvp_realm_attest_key.c \ 297 plat/arm/board/fvp/fvp_el3_token_sign.c \ 298 plat/arm/board/fvp/fvp_ide_keymgmt.c 299endif 300 301ifneq (${ENABLE_FEAT_RNG_TRAP},0) 302BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 303endif 304 305ifeq (${RESET_TO_BL2},1) 306BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 307 plat/arm/board/fvp/fvp_cpu_pwr.c \ 308 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 309 ${FVP_CPU_LIBS} \ 310 ${FVP_INTERCONNECT_SOURCES} 311endif 312 313ifeq (${USE_SP804_TIMER},1) 314BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 315endif 316 317BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 318 ${FVP_SECURITY_SOURCES} 319 320ifeq (${USE_SP804_TIMER},1) 321BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 322endif 323 324BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 325 drivers/arm/smmu/smmu_v3.c \ 326 drivers/delay_timer/delay_timer.c \ 327 drivers/cfi/v2m/v2m_flash.c \ 328 lib/utils/mem_region.c \ 329 plat/arm/board/fvp/fvp_bl31_setup.c \ 330 plat/arm/board/fvp/fvp_console.c \ 331 plat/arm/board/fvp/fvp_pm.c \ 332 plat/arm/board/fvp/fvp_topology.c \ 333 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 334 plat/arm/board/fvp/fvp_cpu_pwr.c \ 335 plat/arm/common/arm_nor_psci_mem_protect.c \ 336 ${FVP_CPU_LIBS} \ 337 ${FVP_INTERCONNECT_SOURCES} \ 338 ${FVP_SECURITY_SOURCES} 339 340# Support for fconf in BL31 341# Added separately from the above list for better readability 342ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 343BL31_SOURCES += lib/fconf/fconf.c \ 344 lib/fconf/fconf_dyn_cfg_getter.c \ 345 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 346 347BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 348 349ifeq (${SEC_INT_DESC_IN_FCONF},1) 350BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 351endif 352 353endif 354 355ifeq (${USE_SP804_TIMER},1) 356BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 357else 358BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 359endif 360 361# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 362FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 363 364FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 365$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 366HW_CONFIG := ${FVP_HW_CONFIG} 367 368# Allow hw_config's secondary-load-address in the DT to be changed 369FVP_HW_CONFIG_ADDR ?= 0x82000000 370DTC_CPPFLAGS += -DFVP_HW_CONFIG_ADDR=$(FVP_HW_CONFIG_ADDR) 371 372# Set default initrd base 128MiB offset of the default kernel address in FVP 373INITRD_BASE ?= 0x90000000 374 375# Kernel base address supports Linux kernels before v5.7 376# DTB base 1MiB before normal base kernel address in FVP (0x88000000) 377ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) 378 PRELOADED_BL33_BASE ?= 0x80080000 379 ifeq (${RESET_TO_BL31},1) 380 ARM_PRELOADED_DTB_BASE ?= 0x87F00000 381 endif 382endif 383 384ifeq (${TRANSFER_LIST}, 0) 385FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 386 ${PLAT}_fw_config.dts \ 387 ${PLAT}_tb_fw_config.dts \ 388 ${PLAT}_soc_fw_config.dts \ 389 ${PLAT}_nt_fw_config.dts \ 390 ) 391 392FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 393FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 394FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 395FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 396 397ifeq (${SPD},tspd) 398FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 399FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 400 401# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 402$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 403endif 404 405ifeq (${SPD},spmd) 406 407ifeq ($(ARM_SPMC_MANIFEST_DTS),) 408ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 409endif 410 411FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 412FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 413 414# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 415$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 416endif 417 418# Add the FW_CONFIG to FIP and specify the same to certtool 419$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 420# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 421$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 422# Add the NT_FW_CONFIG to FIP and specify the same to certtool 423$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 424# Add the TB_FW_CONFIG to FIP and specify the same to certtool 425$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 426endif 427 428# Add the HW_CONFIG to FIP and specify the same to certtool 429$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 430 431ifeq (${TRANSFER_LIST}, 1) 432 433ifeq ($(RESET_TO_BL31), 1) 434FW_HANDOFF_SIZE := 20000 435 436TRANSFER_LIST_DTB_OFFSET := 0x20 437$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 438endif 439endif 440 441ifeq (${HOB_LIST}, 1) 442include lib/hob/hob.mk 443endif 444 445# Enable dynamic mitigation support by default 446DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 447 448ifneq (${ENABLE_FEAT_AMU},0) 449BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 450 lib/cpus/aarch64/cpuamu_helpers.S 451 452ifeq (${HW_ASSISTED_COHERENCY}, 1) 453BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 454 lib/cpus/aarch64/neoverse_n1_pubsub.c 455endif 456endif 457 458ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 459 ifeq (${ENABLE_FEAT_RAS},1) 460 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 461 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 462 else 463 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 464 endif 465 else 466 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 467 endif 468endif 469 470ifneq (${ENABLE_STACK_PROTECTOR},0) 471PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 472endif 473 474# Enable the dynamic translation tables library. 475ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 476 ifeq (${ARCH},aarch32) 477 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 478 else # AArch64 479 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 480 endif 481endif 482 483ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 484 ifeq (${ARCH},aarch32) 485 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 486 else # AArch64 487 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 488 ifeq (${SPD},tspd) 489 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 490 endif 491 endif 492endif 493 494ifeq (${USE_DEBUGFS},1) 495 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 496endif 497 498# Add support for platform supplied linker script for BL31 build 499$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 500 501ifneq (${RESET_TO_BL2}, 0) 502 override BL1_SOURCES = 503endif 504 505include plat/arm/board/common/board_common.mk 506include plat/arm/common/arm_common.mk 507 508ifeq (${MEASURED_BOOT},1) 509BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 510 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 511 lib/psa/measured_boot.c 512 513BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 514 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 515 lib/psa/measured_boot.c 516endif 517 518ifeq (${DRTM_SUPPORT}, 1) 519BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 520 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 521 plat/arm/board/fvp/fvp_drtm_err.c \ 522 plat/arm/board/fvp/fvp_drtm_measurement.c \ 523 plat/arm/board/fvp/fvp_drtm_stub.c \ 524 plat/arm/common/arm_dyn_cfg.c \ 525 plat/arm/board/fvp/fvp_err.c 526endif 527 528ifeq (${TRUSTED_BOARD_BOOT}, 1) 529BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 530BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 531 532# FVP being a development platform, enable capability to disable Authentication 533# dynamically if TRUSTED_BOARD_BOOT is set. 534DYN_DISABLE_AUTH := 1 535endif 536 537ifeq (${SPMC_AT_EL3}, 1) 538PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 539endif 540 541PSCI_OS_INIT_MODE := 1 542 543ifeq (${SPD},spmd) 544BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 545endif 546 547# Test specific macros, keep them at bottom of this file 548$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 549ifeq (${PLATFORM_TEST_EA_FFH}, 1) 550 ifeq (${FFH_SUPPORT}, 0) 551 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 552 endif 553 554endif 555 556$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 557ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 558 ifeq (${ENABLE_FEAT_RAS}, 0) 559 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 560 endif 561 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 562 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 563 endif 564endif 565 566$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 567ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 568 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 569 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 570 endif 571 ifeq (${ENABLE_SPMD_LP}, 0) 572 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 573 endif 574 ifeq (${ENABLE_FEAT_RAS}, 0) 575 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 576 endif 577 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 578 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 579 endif 580endif 581 582ifeq (${ERRATA_ABI_SUPPORT}, 1) 583include plat/arm/board/fvp/fvp_cpu_errata.mk 584endif 585 586# Build macro necessary for running SPM tests on FVP platform 587$(eval $(call add_define,PLAT_TEST_SPM)) 588