1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch_def.h> 11 12 #define PLAT_PRIMARY_CPU (0x0) 13 14 #define MT_GIC_BASE (0x0C000000) 15 #define MCUCFG_BASE (0x0C530000) 16 #define MCUCFG_REG_SIZE (0x10000) 17 #define IO_PHYS (0x10000000) 18 19 /* Aggregate of all devices for MMU mapping */ 20 #define MTK_DEV_RNG0_BASE (MT_GIC_BASE) 21 #define MTK_DEV_RNG0_SIZE (0x600000) 22 #define MTK_DEV_RNG1_BASE (IO_PHYS) 23 #define MTK_DEV_RNG1_SIZE (0x10000000) 24 25 #define TOPCKGEN_BASE (IO_PHYS) 26 27 /******************************************************************************* 28 * GPIO related constants 29 ******************************************************************************/ 30 #define GPIO_BASE (IO_PHYS + 0x00005000) 31 #define IOCFG_LM_BASE (IO_PHYS + 0x01B50000) 32 #define IOCFG_RB0_BASE (IO_PHYS + 0x01C50000) 33 #define IOCFG_RB1_BASE (IO_PHYS + 0x01C60000) 34 #define IOCFG_BM0_BASE (IO_PHYS + 0x01D20000) 35 #define IOCFG_BM1_BASE (IO_PHYS + 0x01D30000) 36 #define IOCFG_BM2_BASE (IO_PHYS + 0x01D40000) 37 #define IOCFG_LT0_BASE (IO_PHYS + 0x01E20000) 38 #define IOCFG_LT1_BASE (IO_PHYS + 0x01E30000) 39 #define IOCFG_RT_BASE (IO_PHYS + 0x01F20000) 40 41 /******************************************************************************* 42 * UART related constants 43 ******************************************************************************/ 44 #define UART0_BASE (IO_PHYS + 0x01002000) 45 #define UART_BAUDRATE (115200) 46 47 /******************************************************************************* 48 * Infra IOMMU related constants 49 ******************************************************************************/ 50 #define PERICFG_AO_BASE (IO_PHYS + 0x01036000) 51 #define PERICFG_AO_REG_SIZE (0x1000) 52 53 /******************************************************************************* 54 * CIRQ related constants 55 ******************************************************************************/ 56 #define SYS_CIRQ_BASE (IO_PHYS + 204000) 57 #define MD_WDT_IRQ_BIT_ID (519) 58 #define CIRQ_REG_NUM (19) 59 #define CIRQ_SPI_START (128) 60 #define CIRQ_IRQ_NUM (598) 61 62 /******************************************************************************* 63 * MM IOMMU & SMI related constants 64 ******************************************************************************/ 65 #define SMI_LARB_0_BASE (IO_PHYS + 0x0401c000) 66 #define SMI_LARB_1_BASE (IO_PHYS + 0x0401d000) 67 #define SMI_LARB_2_BASE (IO_PHYS + 0x0f002000) 68 #define SMI_LARB_4_BASE (IO_PHYS + 0x0602e000) 69 #define SMI_LARB_7_BASE (IO_PHYS + 0x07010000) 70 #define SMI_LARB_9_BASE (IO_PHYS + 0x0502e000) 71 #define SMI_LARB_11_BASE (IO_PHYS + 0x0582e000) 72 #define SMI_LARB_13_BASE (IO_PHYS + 0x0a001000) 73 #define SMI_LARB_14_BASE (IO_PHYS + 0x0a002000) 74 #define SMI_LARB_16_BASE (IO_PHYS + 0x0a00f000) 75 #define SMI_LARB_17_BASE (IO_PHYS + 0x0a010000) 76 #define SMI_LARB_19_BASE (IO_PHYS + 0x0b10f000) 77 #define SMI_LARB_20_BASE (IO_PHYS + 0x0b00f000) 78 #define SMI_LARB_REG_RNG_SIZE (0x1000) 79 80 #define MM_IOMMU_BASE (IO_PHYS + 0x0e802000 + 0x4000) 81 #define APU_IOMMU_BASE (IO_PHYS + 0x09010000) 82 83 #define IOMMU_REG_RNG_SIZE (0x5000) 84 85 /******************************************************************************* 86 * System counter frequency related constants 87 ******************************************************************************/ 88 #define SYS_COUNTER_FREQ_IN_HZ (13000000) 89 #define SYS_COUNTER_FREQ_IN_MHZ (13) 90 91 /******************************************************************************* 92 * Platform binary types for linking 93 ******************************************************************************/ 94 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 95 #define PLATFORM_LINKER_ARCH aarch64 96 97 /******************************************************************************* 98 * Generic platform constants 99 ******************************************************************************/ 100 #define PLATFORM_STACK_SIZE (0x800) 101 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 102 #define SOC_CHIP_ID U(0x8189) 103 104 /******************************************************************************* 105 * Platform memory map related constants 106 ******************************************************************************/ 107 #define TZRAM_BASE (0x54600000) 108 #define TZRAM_SIZE (0x00200000) 109 110 /******************************************************************************* 111 * BL31 specific defines. 112 ******************************************************************************/ 113 /* 114 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 115 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 116 * little space for growth. 117 */ 118 #define BL31_BASE (TZRAM_BASE + 0x1000) 119 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 120 121 /******************************************************************************* 122 * GIC-600 & interrupt handling related constants 123 ******************************************************************************/ 124 /* Base MTK_platform compatible GIC memory map */ 125 #define BASE_GICD_BASE (MT_GIC_BASE) 126 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 127 #define DEV_IRQ_ID 300 128 129 #define PLAT_MTK_G1S_IRQ_PROPS(grp) \ 130 INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \ 131 GIC_INTR_CFG_LEVEL) 132 133 /******************************************************************************* 134 * Platform specific page table and MMU setup constants 135 ******************************************************************************/ 136 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 137 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 138 #define MAX_XLAT_TABLES (16) 139 #define MAX_MMAP_REGIONS (16) 140 141 /******************************************************************************* 142 * SYSTIMER related definitions 143 ******************************************************************************/ 144 #define SYSTIMER_BASE (IO_PHYS + 0x0CC10000) 145 146 /******************************************************************************* 147 * SPMI related definitions 148 ******************************************************************************/ 149 #define SPMI_MST_P_BASE (IO_PHYS + 0x0CC00000) 150 #define PMIF_SPMI_P_BASE (IO_PHYS + 0x0CC06000) 151 #define SPMI_MST_P_SIZE (0x1000) 152 153 /******************************************************************************* 154 * PWRAP related definitions 155 ******************************************************************************/ 156 #define PMICSPI_MST_BASE (IO_PHYS + 0x0c013000) 157 #define PMICSPI_MST_SIZE (0x1000) 158 #define PMIC_WRAP_BASE (IO_PHYS + 0x0CC04000) 159 #define PMIF_SPI_BASE (0x1CC04000) 160 #define PWRAP_REG_BASE (0x1C013000) 161 #define PWRAP_WRAP_EN (PWRAP_REG_BASE + 0x14) 162 163 /******************************************************************************* 164 * PMIC regsister related definitions 165 ******************************************************************************/ 166 #define PMIC_REG_BASE (0x0000) 167 #define PWRAP_SIZE (0x1000) 168 #define DEW_READ_TEST (PMIC_REG_BASE + 0x040e) 169 #define DEW_WRITE_TEST (PMIC_REG_BASE + 0x0410) 170 171 /******************************************************************************* 172 * Differentiate between 3G and 2.6G-related definitions 173 ******************************************************************************/ 174 #define EFUSEC_BASE (IO_PHYS + 0x01F10000) 175 #define CHIP_ID_REG (EFUSEC_BASE + 0x7A0) 176 #define CPU_SEG_ID_REG (EFUSEC_BASE + 0x7E0) 177 178 #define MTK_CPU_ID_MT8189 0x81890000 179 #define MTK_CPU_SEG_ID_MT8189G 0x20 180 #define MTK_CPU_SEG_ID_MT8189H 0x21 181 182 #endif /* PLATFORM_DEF_H */ 183