Merge changes I93de2db1,I880f88b1,I02e2fc75,I48908413,Ie7de9a9f, ... into integration

* changes:
feat(st-ddr): add STM32MP2 driver
refactor(st-ddr): create generic services
refactor(st-ddr): r

Merge changes I93de2db1,I880f88b1,I02e2fc75,I48908413,Ie7de9a9f, ... into integration

* changes:
feat(st-ddr): add STM32MP2 driver
refactor(st-ddr): create generic services
refactor(st-ddr): remove name from stm32mp_ddr_reg_desc
refactor(st-ddr): add definition for timeouts and delays
feat(st): add stm32mp_is_wakeup_from_standby()
feat(stm32mp2): add RETRAM map/unmap capability
feat(stm32mp2): add helper to get DDRDBG base address
feat(stm32mp2): handle DDR power supplies
feat(stm32mp1): handle DDR power supplies

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Merge changes from topic "nxp-clk/add_ddr_clk" into integration

* changes:
fix(nxp-clk): function parameter should not be modified
feat(nxp-clk): enable the DDR clock
feat(nxp-clk): add object

Merge changes from topic "nxp-clk/add_ddr_clk" into integration

* changes:
fix(nxp-clk): function parameter should not be modified
feat(nxp-clk): enable the DDR clock
feat(nxp-clk): add objects needed for DDR clock
feat(nxp-clk): setup the DDR PLL
feat(nxp-clk): add MC_ME utilities
feat(nxp-clk): add partition reset utilities
feat(nxp-clk): add partitions objects

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feat(st-ddr): add STM32MP2 driver

Add driver to support DDR on STM32MP2 platform. It drives the DDR PHY
and its firmware, as well as the DDR controller.

Signed-off-by: Nicolas Le Bayon <nicolas.le.

feat(st-ddr): add STM32MP2 driver

Add driver to support DDR on STM32MP2 platform. It drives the DDR PHY
and its firmware, as well as the DDR controller.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I93de2db1b9378d5654e76b3bf6f3407d80bc4ca5

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refactor(st-ddr): create generic services

Disabling AXI port, enabling host interface and both enabling/disabling
software self-refresh services are already present inside the driver
source code.
Fa

refactor(st-ddr): create generic services

Disabling AXI port, enabling host interface and both enabling/disabling
software self-refresh services are already present inside the driver
source code.
Factorize by gathering them as services inside the generic part,
and adapt driver to call these new functions.

Add services to manage quasi-dynamic registers. DDRCTRL contains
quasi-dynamic registers, which are dynamic only under some conditions
defined by the user guide (with 4 groups).
In our driver, out of reset state, only groups 3 and 4 are updated.
Group 4 needs only sw_done/sw_done_ack sequence, already available.
Group 3 sequence include more conditions, that are gathered in
specific services. stm32mp_ddr_disable_host_interface() has been added
to do this.

Add dedicated generic service to toggle rfshctl3.refresh_update_level
and wait for completion.

Manage AXI ports and HIF when updating QD3 registers. Quasi-dynamic
group 3 (QD3) registers are updated when DDR is not completely
initialized, i.e. when AXI ports are not enabled and possibly when
host interface (HIF) is not enabled too.
In that case, a specific mechanism is necessary to restore the same
conditions as before accessing QD3 registers.
Static functions have been added to get AXI ports and HIF states and
are used to determine the needed conditions to set/unset.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I880f88b1cb6fc76199ad9ea33e9d63a5c469aed4

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refactor(st-ddr): remove name from stm32mp_ddr_reg_desc

It was only used for an error trace, with little added value. This
allows some gains in DDR driver data size.

Signed-off-by: Yann Gautier <ya

refactor(st-ddr): remove name from stm32mp_ddr_reg_desc

It was only used for an error trace, with little added value. This
allows some gains in DDR driver data size.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I02e2fc75efd90ff188e62f39850b9bd4c3af1649

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refactor(st-ddr): add definition for timeouts and delays

Instead of using hard-coded number in DDR driver, use macros.
Modify TIMEOUT_US_1S to DDR_TIMEOUT_US_1S to align with other defines.

Signed-

refactor(st-ddr): add definition for timeouts and delays

Instead of using hard-coded number in DDR driver, use macros.
Modify TIMEOUT_US_1S to DDR_TIMEOUT_US_1S to align with other defines.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I489084132821774b0049a4a5d7fc30db24a7bb11

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feat(stm32mp1): handle DDR power supplies

Modify the DDR driver to handle the DDR power supplies when a PMIC
is present in the function stm32mp_board_ddr_power_init(), define
in the platform file.

feat(stm32mp1): handle DDR power supplies

Modify the DDR driver to handle the DDR power supplies when a PMIC
is present in the function stm32mp_board_ddr_power_init(), define
in the platform file.

This patch allows to easily modify the used DDR power supplies
for customer boards, when they don't use STPMIC1 PMU or when
the regulators are not connected as on the STMicroelectronics
boards.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I93ee6295ef7032ac20f03608d22cd460f7d87ef5

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refactor: digest sizes

The digest size in bytes for sha1/256/384/512 were defined in multiple
places. Refactor the macros into a common header file.

Change-Id: I84ef3561486ff70345ae8c871d5d6e156457

refactor: digest sizes

The digest size in bytes for sha1/256/384/512 were defined in multiple
places. Refactor the macros into a common header file.

Change-Id: I84ef3561486ff70345ae8c871d5d6e1564574ec2
Signed-off-by: Raghu Krishnamurthy <raghupathyk@nvidia.com>

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fix(nxp-clk): function parameter should not be modified

The function 'update_stack_depth' modifies the value of the 'depth'
parameter passed by reference. Typically, the caller recevies this
paramet

fix(nxp-clk): function parameter should not be modified

The function 'update_stack_depth' modifies the value of the 'depth'
parameter passed by reference. Typically, the caller recevies this
parameter by value, and it is then passed to 'update_stack_depth' by
reference. This violates MISRA 17.8 rule. To address this issue, a new
local variable is introduced to store the value of 'depth'.

Change-Id: Ia37f4ede9e6558f778bdda17b7b195f1f50d0c30
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): enable the DDR clock

Enable the DDR clock by setting up its reset block, the associated
partition and configuring the clock tree above the MC_CGM mux.

Change-Id: Idfed24b3e74a189df87

feat(nxp-clk): enable the DDR clock

Enable the DDR clock by setting up its reset block, the associated
partition and configuring the clock tree above the MC_CGM mux.

Change-Id: Idfed24b3e74a189df87f9782886a91b906cd2022
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add objects needed for DDR clock

The DDR clock can be powered by either a PLL or an oscillator. An MC_CGM
mux selects between these two clock sources. A reset block, part of
partition

feat(nxp-clk): add objects needed for DDR clock

The DDR clock can be powered by either a PLL or an oscillator. An MC_CGM
mux selects between these two clock sources. A reset block, part of
partition 0, is also connected to this IP block. Therefore, all the
dependencies mentioned above must be configured to have a working clock.

Change-Id: Ia841428db9acb95c59ea851b6afeb0b7ff9230a2
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): setup the DDR PLL

Add the DDR PLL instance and configure it to operate at its maximum
allowed frequency.

Change-Id: I96efd68687de78f70759f631d10a0f611c234c8d
Signed-off-by: Ghennadi

feat(nxp-clk): setup the DDR PLL

Add the DDR PLL instance and configure it to operate at its maximum
allowed frequency.

Change-Id: I96efd68687de78f70759f631d10a0f611c234c8d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add MC_ME utilities

MC_ME is one of the leading hardware blocks responsible for partitions'
transition to and from a reset state. Not being the only one involved in
this role, it must

feat(nxp-clk): add MC_ME utilities

MC_ME is one of the leading hardware blocks responsible for partitions'
transition to and from a reset state. Not being the only one involved in
this role, it must cooperate with some other modules (MC_RGM, RDC) to
successfully bring a peripheral out of the reset state. As a result, the
partition management is isolated into a dedicated file, as parts of it
will later contribute to peripheral reset control.

Change-Id: I6a9dbf28008b1677bc847bbafa474b489c999d05
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add partition reset utilities

MC_RGM is a hardware block involved in resetting peripherals and
partitions. Here, the accessories for partition reset are added.

Change-Id: If00755fe0e

feat(nxp-clk): add partition reset utilities

MC_RGM is a hardware block involved in resetting peripherals and
partitions. Here, the accessories for partition reset are added.

Change-Id: If00755fe0e93ba2e4841f95ed5ae3c87db20bebf
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(s32g274a): workaround for ERR051700 erratum

ERR051700 erratum is present on all S32CC-based SoCs and relates to
reset. Releasing multiple Software Resettable Domains (SRDs) from
reset simultaneo

fix(s32g274a): workaround for ERR051700 erratum

ERR051700 erratum is present on all S32CC-based SoCs and relates to
reset. Releasing multiple Software Resettable Domains (SRDs) from
reset simultaneously, may cause a false error in the fault control
unit.

The workaround is to clear the SRD resets sequentially instead of
simultaneously.

Change-Id: I883bc223bf6834907259e6964a5702d7186e4c7f
Signed-off-by: Alexandru-Catalin Ionita <alexandru-catalin.ionita@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "nxp-drivers/add-get-parent-callback" into integration

* changes:
feat(nxp-clk): refactor clock enablement
feat(nxp-clk): add get_parent callback
fix(nxp-clk): broken

Merge changes from topic "nxp-drivers/add-get-parent-callback" into integration

* changes:
feat(nxp-clk): refactor clock enablement
feat(nxp-clk): add get_parent callback
fix(nxp-clk): broken UART clock initalization

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Merge changes I14df5d21,I7f952205,I6f52ec2c,Ibe0cacf8 into integration

* changes:
feat(stm32mp2-fdts): describe stpmic2 power supplies
feat(stm32mp2-fdts): add I2C7 pin muxing
feat(stm32mp2-fd

Merge changes I14df5d21,I7f952205,I6f52ec2c,Ibe0cacf8 into integration

* changes:
feat(stm32mp2-fdts): describe stpmic2 power supplies
feat(stm32mp2-fdts): add I2C7 pin muxing
feat(stm32mp2-fdts): add UART and I2C nodes for STM32MP2
feat(st-pmic): add STPMIC2 driver

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Merge changes from topic "update-mbedtls-to-3.6.1" into integration

* changes:
refactor(mbedtls): remove hack in LIBMBEDTLS_CFLAGS
docs(prerequisites): update MbedTLS version to 3.6.1

feat(st-pmic): add STPMIC2 driver

The STPMIC2 embeds 15 regulators with various
properties, and is designed to supply the STM32MP2
SOC. This driver handles a minimal set of feature
to handle the boo

feat(st-pmic): add STPMIC2 driver

The STPMIC2 embeds 15 regulators with various
properties, and is designed to supply the STM32MP2
SOC. This driver handles a minimal set of feature
to handle the boot of a board.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Ibe0cacf8aec2871eb9a86ec16cbbd18d3745fe9e

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Merge changes Idf032b03,Id8e803b3 into integration

* changes:
feat(st-regulator): support regulator_set_voltage for fixed regulator
feat(st-regulator): add enable ramp-delay

feat(nxp-clk): refactor clock enablement

Simplify the clock enablement mechanism from a usage perspective. With
this new approach, enabling a clock cascades the turn-on sequence of all
its parent cl

feat(nxp-clk): refactor clock enablement

Simplify the clock enablement mechanism from a usage perspective. With
this new approach, enabling a clock cascades the turn-on sequence of all
its parent clocks in the clock tree. Therefore, enabling the A53 clock
will also turn on the A53 PLL and the oscillator that feeds it.

Change-Id: Ifc2bee3e9edbb4baced34f9e809a961562f7d0a6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_parent callback

Bring in the implementation for the struct clk_ops->get_parent callback
for the S32G clock driver. The parent is established depending on the
clock object type

feat(nxp-clk): add get_parent callback

Bring in the implementation for the struct clk_ops->get_parent callback
for the S32G clock driver. The parent is established depending on the
clock object type. Usually, this is determined based on the parent
field, but not always.

Change-Id: I76a3d2636dc23ba2d547d058b8650dd0e99fe1fa
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(nxp-clk): broken UART clock initalization

The UART clock initialization failed because the clock mux enablement
mechanism did not correctly recognize the PERIPH PLL mux. Therefore, it
was report

fix(nxp-clk): broken UART clock initalization

The UART clock initialization failed because the clock mux enablement
mechanism did not correctly recognize the PERIPH PLL mux. Therefore, it
was reported as an unknown mux ID.

Change-Id: I6cc72c87a8462a2ed2e7c360f59a74961bb2f3a1
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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refactor(mbedtls): use PSA API for auth_decrypt

This new version uses the multipart PSA AEAD API;
the authentication tag is verified via
a call to psa_aead_verify.

Change-Id: If4b7e6258223ae6fead17

refactor(mbedtls): use PSA API for auth_decrypt

This new version uses the multipart PSA AEAD API;
the authentication tag is verified via
a call to psa_aead_verify.

Change-Id: If4b7e6258223ae6fead1794d3e8d0004f0f387b3
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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refactor(mbedtls): remove hack in LIBMBEDTLS_CFLAGS

MbedTLS 3.6.1 fixed the issue which previously
produced this warning, so this hack is no longer
necessary.

Change-Id: I934adefbf2fed16e16b9d98bc8

refactor(mbedtls): remove hack in LIBMBEDTLS_CFLAGS

MbedTLS 3.6.1 fixed the issue which previously
produced this warning, so this hack is no longer
necessary.

Change-Id: I934adefbf2fed16e16b9d98bc8674125b70b08fc
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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