| 22966106 | 22-Sep-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
GIC: Add helpers to set interrupt configuration
The helpers perform read-modify-write on GIC*_ICFGR registers, but don't
serialise callers. Any serialisation must be taken care of by the
callers.
C
GIC: Add helpers to set interrupt configuration
The helpers perform read-modify-write on GIC*_ICFGR registers, but don't
serialise callers. Any serialisation must be taken care of by the
callers.
Change-Id: I71995f82ff2c7f70d37af0ede30d6ee18682fd3f
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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|
| d55a4450 | 22-Sep-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
GIC: Add API to set priority mask
API documentation updated.
Change-Id: I40feec1fe67a960d035061b54dd55610bc34ce1d
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
| a2816a16 | 22-Sep-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
GIC: Add API to set/clear interrupt pending
API documentation updated.
Change-Id: I14e33cfc7dfa93257c82d76fae186b17a1b6d266
Co-authored-by: Yousuf A <yousuf.sait@arm.com>
Signed-off-by: Jeenu Viswa
GIC: Add API to set/clear interrupt pending
API documentation updated.
Change-Id: I14e33cfc7dfa93257c82d76fae186b17a1b6d266
Co-authored-by: Yousuf A <yousuf.sait@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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|
| fc529fee | 22-Sep-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
GIC: Add API to set interrupt routing
SPIs can be routed to either a specific PE, or to any one of all
available PEs.
API documentation updated.
Change-Id: I28675f634568aaf4ea1aa8aa7ebf25b419a963e
GIC: Add API to set interrupt routing
SPIs can be routed to either a specific PE, or to any one of all
available PEs.
API documentation updated.
Change-Id: I28675f634568aaf4ea1aa8aa7ebf25b419a963ed
Co-authored-by: Yousuf A <yousuf.sait@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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|
| 8db978b5 | 22-Sep-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
GIC: Add API to raise secure SGI
API documentation updated.
Change-Id: I129725059299af6cc612bafa8d74817f779d7c4f
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
| 74dce7fa | 22-Sep-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
GIC: Add APIs to set interrupt type and query support
The back end GIC driver converts and assigns the interrupt type to
suitable group.
For GICv2, a build option GICV2_G0_FOR_EL3 is introduced, wh
GIC: Add APIs to set interrupt type and query support
The back end GIC driver converts and assigns the interrupt type to
suitable group.
For GICv2, a build option GICV2_G0_FOR_EL3 is introduced, which
determines to which type Group 0 interrupts maps to.
- When the build option is set 0 (the default), Group 0 interrupts are
meant for Secure EL1. This is presently the case.
- Otherwise, Group 0 interrupts are meant for EL3. This means the SPD
will have to synchronously hand over the interrupt to Secure EL1.
The query API allows the platform to query whether the platform supports
interrupts of a given type.
API documentation updated.
Change-Id: I60fdb4053ffe0bd006b3b20914914ebd311fc858
Co-authored-by: Yousuf A <yousuf.sait@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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|
| f3a86600 | 22-Sep-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
GIC: Add API to set interrupt priority
API documentation updated.
Change-Id: Ib700eb1b8ca65503aeed0ac4ce0e7b934df67ff9
Co-authored-by: Yousuf A <yousuf.sait@arm.com>
Signed-off-by: Jeenu Viswambhar
GIC: Add API to set interrupt priority
API documentation updated.
Change-Id: Ib700eb1b8ca65503aeed0ac4ce0e7b934df67ff9
Co-authored-by: Yousuf A <yousuf.sait@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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|
| 979225f4 | 22-Sep-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
GIC: Add APIs to enable and disable interrupt
API documentation updated.
Change-Id: Ice7511f8df5356851001d2f7dc2a46cfe318f9ba
Co-authored-by: Yousuf A <yousuf.sait@arm.com>
Signed-off-by: Jeenu Vis
GIC: Add APIs to enable and disable interrupt
API documentation updated.
Change-Id: Ice7511f8df5356851001d2f7dc2a46cfe318f9ba
Co-authored-by: Yousuf A <yousuf.sait@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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|
| cbd3f370 | 22-Sep-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
GIC: Add API to get interrupt active status
API documentation updated.
Change-Id: I6d61785af0d5330930c709de971a904dc7c3516c
Co-authored-by: Yousuf A <yousuf.sait@arm.com>
Signed-off-by: Jeenu Viswa
GIC: Add API to get interrupt active status
API documentation updated.
Change-Id: I6d61785af0d5330930c709de971a904dc7c3516c
Co-authored-by: Yousuf A <yousuf.sait@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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|
| fa9db423 | 22-Sep-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
GICv2: Add driver API to set PE target mask
The PE target mask is used to translate linear PE index (returned by
platform core position) to a bit mask used when targeting interrupts to
a PE, viz. wh
GICv2: Add driver API to set PE target mask
The PE target mask is used to translate linear PE index (returned by
platform core position) to a bit mask used when targeting interrupts to
a PE, viz. when raising SGIs and routing SPIs.
The platform shall:
- Populate the driver data with a pointer to array that's to contain
per-PE target masks.
- Invoke the new driver API 'gicv2_set_pe_target_mask()' during
per-CPU initialization so that the driver populates the target mask
for that CPU.
Platforms that don't intend to target interrupts or raise SGIs need not
populate this.
Change-Id: Ic0db54da86915e9dccd82fff51479bc3c1fdc968
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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|
| eb68ea9b | 22-Sep-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
GIC: Add API to get running priority
Document the API in separate platform interrupt controller API document.
Change-Id: If18f208e10a8a243f5c59d226fcf48e985941949
Co-authored-by: Yousuf A <yousuf.s
GIC: Add API to get running priority
Document the API in separate platform interrupt controller API document.
Change-Id: If18f208e10a8a243f5c59d226fcf48e985941949
Co-authored-by: Yousuf A <yousuf.sait@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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|
| c1bbeb5f | 06-Oct-2017 |
Soby Mathew <soby.mathew@arm.com> |
Fix assertion in GIC ITS helper
This patch fixes an assertion check in the GICv3 ITS helper function.
Change-Id: I75f50d7bf6d87c12c6e24a07c9a9889e5facf4a5
Signed-off-by: Soby Mathew <soby.mathew@ar
Fix assertion in GIC ITS helper
This patch fixes an assertion check in the GICv3 ITS helper function.
Change-Id: I75f50d7bf6d87c12c6e24a07c9a9889e5facf4a5
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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|
| b258278e | 18-Jul-2017 |
Soby Mathew <soby.mathew@arm.com> |
GICv3: ITS architectural save and restore helpers
This patch adds functions to save and restore GICv3 ITS registers during
system suspend. Please note that the power management of GIC ITS is
impleme
GICv3: ITS architectural save and restore helpers
This patch adds functions to save and restore GICv3 ITS registers during
system suspend. Please note that the power management of GIC ITS is
implementation defined. These functions only implements the
architectural part of the ITS power management and they do not restore
memory structures or register content required to support ITS. Even if
the ITS implementation stores structures in memory, an implementation
defined power down sequence is likely to be required to flush some
internal ITS caches to memory. If such implementation defined sequence
is not followed, the platform must ensure that the ITS is not power
gated during system suspend.
Change-Id: I5f31e5541975aa7dcaab69b0b7f67583c0e27678
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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|
| ebf1ca10 | 13-Jul-2017 |
Soby Mathew <soby.mathew@arm.com> |
GICv3: add functions for save and restore
During system suspend, the GICv3 Distributor and Redistributor context
can be lost due to power gating of the system power domain. This means
that the GICv3
GICv3: add functions for save and restore
During system suspend, the GICv3 Distributor and Redistributor context
can be lost due to power gating of the system power domain. This means
that the GICv3 context needs to be saved prior to system suspend and
restored on wakeup. Currently the consensus is that the Firmware should
be in charge of this. See tf-issues#464 for more details.
This patch introduces helper APIs in the GICv3 driver to save and
restore the Distributor and Redistributor contexts. The GICv3 ITS
context is not considered in this patch because the specification says
that the details of ITS power management is implementation-defined.
These APIs are expected to be appropriately invoked by the platform
layer during system suspend.
Fixes ARM-software/tf-issues#464
Change-Id: Iebb9c6770ab8c4d522546f161fa402d2fe02ec00
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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|
| a64b4e62 | 26-Jul-2017 |
Douglas Raillard <douglas.raillard@arm.com> |
GICv3: turn some macros into inline functions
Tidy up the code a bit by turning some macros into inline functions
which allows to remove the do/while(0) idiom and backslashes at the end
of the line.
GICv3: turn some macros into inline functions
Tidy up the code a bit by turning some macros into inline functions
which allows to remove the do/while(0) idiom and backslashes at the end
of the line.
Change-Id: Ie41a4ea4a4da507f7b925247b53e85019101d717
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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|
| b50bdcea | 03-Aug-2017 |
Douglas Raillard <douglas.raillard@arm.com> |
GICv3: Fix gic600.c indentation
Reindent the file using tabs as the mix of spaces and tabs confuses some
editors and leads them to use spaces instead of tabs for new code
although the coding style m
GICv3: Fix gic600.c indentation
Reindent the file using tabs as the mix of spaces and tabs confuses some
editors and leads them to use spaces instead of tabs for new code
although the coding style mandates tabs.
Change-Id: I87fa4a5d368a048340054b9b3622325f3f7befba
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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|
| b8fa2ed5 | 02-Oct-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1107 from geesun/qx/add_ecdsa_support
Add support for TBBR using ECDSA keys in ARM platforms |
| dcbf3932 | 24-Aug-2017 |
Qixiang Xu <qixiang.xu@arm.com> |
Dynamic selection of ECDSA or RSA
Add new option rsa+ecdsa for TF_MBEDTLS_KEY_ALG, which selects
rsa or ecdsa depending on the certificate used.
Change-Id: I08d9e99bdbba361ed2ec5624248dc382c750ad47
Dynamic selection of ECDSA or RSA
Add new option rsa+ecdsa for TF_MBEDTLS_KEY_ALG, which selects
rsa or ecdsa depending on the certificate used.
Change-Id: I08d9e99bdbba361ed2ec5624248dc382c750ad47
Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
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|
| 9db9c65a | 24-Aug-2017 |
Qixiang Xu <qixiang.xu@arm.com> |
Add support for TBBR using ECDSA keys in ARM platforms
- fixed compile error when KEY_ALG=ecdsa
- add new option ecdsa for TF_MBEDTLS_KEY_ALG
- add new option devel_ecdsa for ARM_ROTPK_L
Add support for TBBR using ECDSA keys in ARM platforms
- fixed compile error when KEY_ALG=ecdsa
- add new option ecdsa for TF_MBEDTLS_KEY_ALG
- add new option devel_ecdsa for ARM_ROTPK_LOCATION
- add ecdsa key at plat/arm/board/common/rotpk/
- reduce the mbedtls heap memory size to 13k
Change-Id: I3f7a6170af93fdbaaa7bf2fffb4680a9f6113c13
Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
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|
| e47ac1fd | 14-Sep-2017 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Fix type of `unsigned long` constants
The type `unsigned long` is 32 bit wide in AArch32, but 64 bit wide in
AArch64. This is inconsistent and that's why we avoid using it as per
the Coding Guidelin
Fix type of `unsigned long` constants
The type `unsigned long` is 32 bit wide in AArch32, but 64 bit wide in
AArch64. This is inconsistent and that's why we avoid using it as per
the Coding Guidelines. This patch changes all `UL` occurrences to `U`
or `ULL` depending on the context so that the size of the constant is
clear.
This problem affected the macro `BIT(nr)`. As long as this macro is used
to fill fields of registers, that's not a problem, since all registers
are 32 bit wide in AArch32 and 64 bit wide in AArch64. However, if the
macro is used to fill the fields of a 64-bit integer, it won't be able
to set the upper 32 bits in AArch32.
By changing the type of this macro to `unsigned long long` the behaviour
is always the same regardless of the architecture, as this type is
64-bit wide in both cases.
Some Tegra platform files have been modified by this patch.
Change-Id: I918264c03e7d691a931f0d1018df25a2796cc221
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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|
| a8eb286a | 31-Aug-2017 |
Soby Mathew <soby.mathew@arm.com> |
cert_tool: Support for legacy RSA PKCS#1 v1.5
This patch enables choice of RSA version at run time to be used for
generating signatures by the cert_tool. The RSA PSS as defined in
PKCS#1 v2.1 become
cert_tool: Support for legacy RSA PKCS#1 v1.5
This patch enables choice of RSA version at run time to be used for
generating signatures by the cert_tool. The RSA PSS as defined in
PKCS#1 v2.1 becomes the default version and this patch enables to specify
the RSA PKCS#1 v1.5 algorithm to `cert_create` through the command line
-a option. Also, the build option `KEY_ALG` can be used to pass this
option from the build system. Please note that RSA PSS is mandated
by Trusted Board Boot requirements (TBBR) and legacy RSA support is
being added for compatibility reasons.
Fixes ARM-Software/tf-issues#499
Change-Id: Ifaa3f2f7c9b43f3d7b3effe2cde76bf6745a5d73
Co-Authored-By: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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|
| 2091755c | 31-Aug-2017 |
Soby Mathew <soby.mathew@arm.com> |
Export KEY_ALG as a user build option
The `KEY_ALG` variable is used to select the algorithm for key
generation by `cert_create` tool for signing the certificates. This
variable was previously undoc
Export KEY_ALG as a user build option
The `KEY_ALG` variable is used to select the algorithm for key
generation by `cert_create` tool for signing the certificates. This
variable was previously undocumented and did not have a global default
value. This patch corrects this and also adds changes to derive the
value of `TF_MBEDTLS_KEY_ALG` based on `KEY_ALG` if it not set by the
platform. The corresponding assignment of these variables are also now
removed from the `arm_common.mk` makefile.
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I78e2d6f4fc04ed5ad35ce2266118afb63127a5a4
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|
| 1a52aca5 | 14-Aug-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1040 from sliai/support-opteed-header
Support opteed header |
| 71fb3964 | 20-Apr-2017 |
Summer Qin <summer.qin@arm.com> |
Support Trusted OS firmware extra images in TF tools
Since Trusted OS firmware may have extra images, need to
assign new uuid and image id for them.
The TBBR chain of trust has been extended to add
Support Trusted OS firmware extra images in TF tools
Since Trusted OS firmware may have extra images, need to
assign new uuid and image id for them.
The TBBR chain of trust has been extended to add support
for the new images within the existing Trusted OS firmware
content certificate.
Change-Id: I678dac7ba1137e85c5779b05e0c4331134c10e06
Signed-off-by: Summer Qin <summer.qin@arm.com>
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|
| 1154586b | 26-May-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
Add SMMUv3 driver
The driver has only one API: to initialize an SMMUv3 device. This
operates on a device that implements secure state, by invalidating
secure caches and TLBs.
Change-Id: Ief32800419
Add SMMUv3 driver
The driver has only one API: to initialize an SMMUv3 device. This
operates on a device that implements secure state, by invalidating
secure caches and TLBs.
Change-Id: Ief32800419ddf0f1fe38c8f0da8f5ba75c72c826
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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|