1# 2# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# The AArch32 Secure Payload to be built as BL32 image 14AARCH32_SP := none 15 16# The Target build architecture. Supported values are: aarch64, aarch32. 17ARCH := aarch64 18 19# ARM Architecture major and minor versions: 8.0 by default. 20ARM_ARCH_MAJOR := 8 21ARM_ARCH_MINOR := 0 22 23# Determine the version of ARM GIC architecture to use for interrupt management 24# in EL3. The platform port can change this value if needed. 25ARM_GIC_ARCH := 2 26 27# Base commit to perform code check on 28BASE_COMMIT := origin/master 29 30# By default, consider that the platform may release several CPUs out of reset. 31# The platform Makefile is free to override this value. 32COLD_BOOT_SINGLE_CPU := 0 33 34# Flag to compile in coreboot support code. Exclude by default. The coreboot 35# Makefile system will set this when compiling TF as part of a coreboot image. 36COREBOOT := 0 37 38# For Chain of Trust 39CREATE_KEYS := 1 40 41# Build flag to include AArch32 registers in cpu context save and restore during 42# world switch. This flag must be set to 0 for AArch64-only platforms. 43CTX_INCLUDE_AARCH32_REGS := 1 44 45# Include FP registers in cpu context 46CTX_INCLUDE_FPREGS := 0 47 48# Debug build 49DEBUG := 0 50 51# Build platform 52DEFAULT_PLAT := fvp 53 54# Flag to enable Performance Measurement Framework 55ENABLE_PMF := 0 56 57# Flag to enable PSCI STATs functionality 58ENABLE_PSCI_STAT := 0 59 60# Flag to enable runtime instrumentation using PMF 61ENABLE_RUNTIME_INSTRUMENTATION := 0 62 63# Flag to enable stack corruption protection 64ENABLE_STACK_PROTECTOR := 0 65 66# Flag to enable exception handling in EL3 67EL3_EXCEPTION_HANDLING := 0 68 69# Build flag to treat usage of deprecated platform and framework APIs as error. 70ERROR_DEPRECATED := 0 71 72# Byte alignment that each component in FIP is aligned to 73FIP_ALIGN := 0 74 75# Default FIP file name 76FIP_NAME := fip.bin 77 78# Default FWU_FIP file name 79FWU_FIP_NAME := fwu_fip.bin 80 81# For Chain of Trust 82GENERATE_COT := 0 83 84# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 85# default, they are for Secure EL1. 86GICV2_G0_FOR_EL3 := 0 87 88# Whether system coherency is managed in hardware, without explicit software 89# operations. 90HW_ASSISTED_COHERENCY := 0 91 92# Set the default algorithm for the generation of Trusted Board Boot keys 93KEY_ALG := rsa 94 95# Flag to enable new version of image loading 96LOAD_IMAGE_V2 := 0 97 98# Use the new console API that allows registering more than one console instance 99# at once. Use = instead of := to dynamically default to ERROR_DEPRECATED. 100MULTI_CONSOLE_API = $(ERROR_DEPRECATED) 101 102# NS timer register save and restore 103NS_TIMER_SWITCH := 0 104 105# Build PL011 UART driver in minimal generic UART mode 106PL011_GENERIC_UART := 0 107 108# By default, consider that the platform's reset address is not programmable. 109# The platform Makefile is free to override this value. 110PROGRAMMABLE_RESET_ADDRESS := 0 111 112# Flag used to choose the power state format viz Extended State-ID or the 113# Original format. 114PSCI_EXTENDED_STATE_ID := 0 115 116# By default, BL1 acts as the reset handler, not BL31 117RESET_TO_BL31 := 0 118 119# For Chain of Trust 120SAVE_KEYS := 0 121 122# Software Delegated Exception support 123SDEI_SUPPORT := 0 124 125# Whether code and read-only data should be put on separate memory pages. The 126# platform Makefile is free to override this value. 127SEPARATE_CODE_AND_RODATA := 0 128 129# SPD choice 130SPD := none 131 132# For including the Secure Partition Manager 133ENABLE_SPM := 0 134 135# Flag to introduce an infinite loop in BL1 just before it exits into the next 136# image. This is meant to help debugging the post-BL2 phase. 137SPIN_ON_BL1_EXIT := 0 138 139# Flags to build TF with Trusted Boot support 140TRUSTED_BOARD_BOOT := 0 141 142# Build option to choose whether Trusted firmware uses Coherent memory or not. 143USE_COHERENT_MEM := 1 144 145# Use tbbr_oid.h instead of platform_oid.h 146USE_TBBR_DEFS = $(ERROR_DEPRECATED) 147 148# Build verbosity 149V := 0 150 151# Whether to enable D-Cache early during warm boot. This is usually 152# applicable for platforms wherein interconnect programming is not 153# required to enable cache coherency after warm reset (eg: single cluster 154# platforms). 155WARMBOOT_ENABLE_DCACHE_EARLY := 0 156 157# Build option to enable/disable the Statistical Profiling Extensions 158ENABLE_SPE_FOR_LOWER_ELS := 1 159 160# SPE is only supported on AArch64 so disable it on AArch32. 161ifeq (${ARCH},aarch32) 162 override ENABLE_SPE_FOR_LOWER_ELS := 0 163endif 164 165ENABLE_AMU := 0 166 167# By default, enable Scalable Vector Extension if implemented for Non-secure 168# lower ELs 169# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 170ifneq (${ARCH},aarch32) 171 ENABLE_SVE_FOR_NS := 1 172else 173 override ENABLE_SVE_FOR_NS := 0 174endif 175