1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arm_gic.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <coreboot.h> 12 #include <debug.h> 13 #include <generic_delay_timer.h> 14 #include <mmio.h> 15 #include <plat_private.h> 16 #include <platform.h> 17 #include <platform_def.h> 18 #include <uart_16550.h> 19 20 /******************************************************************************* 21 * Declarations of linker defined symbols which will help us find the layout 22 * of trusted SRAM 23 ******************************************************************************/ 24 unsigned long __RO_START__; 25 unsigned long __RO_END__; 26 27 /* 28 * The next 2 constants identify the extents of the code & RO data region. 29 * These addresses are used by the MMU setup code and therefore they must be 30 * page-aligned. It is the responsibility of the linker script to ensure that 31 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 32 */ 33 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 34 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 35 36 static entry_point_info_t bl32_ep_info; 37 static entry_point_info_t bl33_ep_info; 38 39 /******************************************************************************* 40 * Return a pointer to the 'entry_point_info' structure of the next image for 41 * the security state specified. BL33 corresponds to the non-secure image type 42 * while BL32 corresponds to the secure image type. A NULL pointer is returned 43 * if the image does not exist. 44 ******************************************************************************/ 45 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 46 { 47 entry_point_info_t *next_image_info; 48 49 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 50 51 /* None of the images on this platform can have 0x0 as the entrypoint */ 52 if (next_image_info->pc) 53 return next_image_info; 54 else 55 return NULL; 56 } 57 58 #pragma weak params_early_setup 59 void params_early_setup(void *plat_param_from_bl2) 60 { 61 } 62 63 /******************************************************************************* 64 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 65 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 66 * are lost (potentially). This needs to be done before the MMU is initialized 67 * so that the memory layout can be used while creating page tables. 68 * BL2 has flushed this information to memory, so we are guaranteed to pick up 69 * good data. 70 ******************************************************************************/ 71 void bl31_early_platform_setup(bl31_params_t *from_bl2, 72 void *plat_params_from_bl2) 73 { 74 static console_16550_t console; 75 76 params_early_setup(plat_params_from_bl2); 77 78 #if COREBOOT 79 if (coreboot_serial.type) 80 console_16550_register(coreboot_serial.baseaddr, 81 coreboot_serial.input_hertz, 82 coreboot_serial.baud, 83 &console); 84 #else 85 console_16550_register(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK, 86 PLAT_RK_UART_BAUDRATE, &console); 87 #endif 88 89 VERBOSE("bl31_setup\n"); 90 91 /* Passing a NULL context is a critical programming error */ 92 assert(from_bl2); 93 94 assert(from_bl2->h.type == PARAM_BL31); 95 assert(from_bl2->h.version >= VERSION_1); 96 97 bl32_ep_info = *from_bl2->bl32_ep_info; 98 bl33_ep_info = *from_bl2->bl33_ep_info; 99 } 100 101 /******************************************************************************* 102 * Perform any BL3-1 platform setup code 103 ******************************************************************************/ 104 void bl31_platform_setup(void) 105 { 106 generic_delay_timer_init(); 107 plat_rockchip_soc_init(); 108 109 /* Initialize the gic cpu and distributor interfaces */ 110 plat_rockchip_gic_driver_init(); 111 plat_rockchip_gic_init(); 112 plat_rockchip_pmu_init(); 113 } 114 115 /******************************************************************************* 116 * Perform the very early platform specific architectural setup here. At the 117 * moment this is only intializes the mmu in a quick and dirty way. 118 ******************************************************************************/ 119 void bl31_plat_arch_setup(void) 120 { 121 plat_cci_init(); 122 plat_cci_enable(); 123 plat_configure_mmu_el3(BL31_RO_BASE, 124 BL_COHERENT_RAM_END - BL31_RO_BASE, 125 BL31_RO_BASE, 126 BL31_RO_LIMIT, 127 BL_COHERENT_RAM_BASE, 128 BL_COHERENT_RAM_END); 129 } 130