fix(drivers/marvell/comphy-3700): configure phy selector also for PCIe

The mvebu_a3700_comphy_pcie_power_on() function does not configure the
PHY selector explicitly, it relies on the register defau

fix(drivers/marvell/comphy-3700): configure phy selector also for PCIe

The mvebu_a3700_comphy_pcie_power_on() function does not configure the
PHY selector explicitly, it relies on the register default value.

Configure the PHY selector just in case someone changed the default
value.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I54048b4bb7a5eced36f7fe6592ebe108f978fff0

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fix(drivers/marvell/comphy-cp110): fix error code in pcie power on

Function polling_with_timeout() returns last value from polled register
on failure and zero on success. So set "ret" variable to er

fix(drivers/marvell/comphy-cp110): fix error code in pcie power on

Function polling_with_timeout() returns last value from polled register
on failure and zero on success. So set "ret" variable to error code
-ETIMEDOUT on error like it is done in other functions.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I16cac81bbcbe2113e139722dc0e8fc2b85428d1b

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fix(drivers/marvell/comphy-3700): handle failures in power functions

Subroutines in power functions may fail. So propagate failures from
subroutines back to the caller of power function with appropr

fix(drivers/marvell/comphy-3700): handle failures in power functions

Subroutines in power functions may fail. So propagate failures from
subroutines back to the caller of power function with appropriate error
code in return value.

Function polling_with_timeout() returns last value from polled register
on failure and zero on success. So return -ETIMEDOUT on error from power
functions like it is doing Marvell comphy-cp110 driver.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I6c709c0c9616ab26829616a42a85b713f314b201

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fix(drivers/marvell/comphy-3700): fix address overflow

Physical address has to be stored in 64-bit data type as Armada 3720 is
64-bit platform. Driver already uses uintptr_t type for this purpise.

fix(drivers/marvell/comphy-3700): fix address overflow

Physical address has to be stored in 64-bit data type as Armada 3720 is
64-bit platform. Driver already uses uintptr_t type for this purpise.

Change type of 'offset' variables in mvebu_a3700_comphy_usb3_power_on()
and mvebu_a3700_comphy_sgmii_power_on() / off() functions to uintptr_t
as in this variable is stored physical address of registers.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I69581714f8899d21cc1a27005747708f0f1cd933

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refactor(drivers/marvell/comphy-3700): simplify usage of comphy_sgmii_phy_init()

Parameter 'comphy_index' is not used and parameter 'mode' is used only
to check if speed is 1 Gbps or not.

Remove pa

refactor(drivers/marvell/comphy-3700): simplify usage of comphy_sgmii_phy_init()

Parameter 'comphy_index' is not used and parameter 'mode' is used only
to check if speed is 1 Gbps or not.

Remove parameter 'comphy_index' and instead of 32-bit variable 'mode',
pass only boolean value which represents 1 Gbps speed.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I018d158f689ddf7d1f57003717d709c00d988fba

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refactor(drivers/marvell/comphy-3700): simplify usage of indirect access on lane2

For code cleanup add two helper functions comphy_sata_set_indirect() and
comphy_usb_set_indirect() for SATA and USB

refactor(drivers/marvell/comphy-3700): simplify usage of indirect access on lane2

For code cleanup add two helper functions comphy_sata_set_indirect() and
comphy_usb_set_indirect() for SATA and USB 3.0 modes and remove additional
'mode' argument which is not needed anymore.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I23146f569db318dbaed5d411d7d175abf6efff85

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refactor(drivers/marvell/comphy-3700): simplify usage of sata power off

Function mvebu_a3700_comphy_sata_power_off() uses comphy_mode parameter
only for extracting mode bits. Mode is always COMPHY_S

refactor(drivers/marvell/comphy-3700): simplify usage of sata power off

Function mvebu_a3700_comphy_sata_power_off() uses comphy_mode parameter
only for extracting mode bits. Mode is always COMPHY_SATA_MODE, so
there is no need to pass comphy_mode parameter to this function. Use
directly COMPHY_SATA_MODE in mvebu_a3700_comphy_sata_power_off().

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ib6b7c2bf62c1ef4d8a6af240c08696d5cd506b14

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fix(drivers/marvell/comphy): fix name of 3.125G SerDes mode

There is no support for 2.5/3.125G SGMII. This 3.125G SerDes mode is not
SGMII. It is just plain 1000Base-X (as defined in IEEE 802.3z sta

fix(drivers/marvell/comphy): fix name of 3.125G SerDes mode

There is no support for 2.5/3.125G SGMII. This 3.125G SerDes mode is not
SGMII. It is just plain 1000Base-X (as defined in IEEE 802.3z standard)
but upclocked 2.5x. This mode is commonly known under name 2500Base-X.

So remove incorrect SGMII keyword from names and comments and replace it
by more adequate 2500Base-X keyword.

There is no functional change in code, just renaming macros and updating
comments.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: If79aec16cc233f4896aafd75bfbbebb3f172a197

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Merge "fix(plat/marvell/armada): select correct pcie reference clock source" into integration

fix(plat/marvell/a3720/uart): fix UART parent clock rate determination

The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal cl

fix(plat/marvell/a3720/uart): fix UART parent clock rate determination

The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal clock can also run
at 40 MHz (this is board specific).

The frequency of the xtal clock is determined by a value on a strapping
pin during SOC reset. The code to determine this frequency is already in
A3K's comphy driver.

Move the get_ref_clk() function from the comphy driver to a separate
file and use it for UART parent clock rate determination.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e

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fix(plat/marvell/armada): select correct pcie reference clock source

when comphy is in pcie mode, correct reference clock need be
selected according to SAR register that reflect the CPx_MPP boot
str

fix(plat/marvell/armada): select correct pcie reference clock source

when comphy is in pcie mode, correct reference clock need be
selected according to SAR register that reflect the CPx_MPP boot
strapping pins. Either from external or from internal

Signed-off-by: Guo Yi <yguo@cavium.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Change-Id: I99ed64a141e85174cc0f8e9dab5886ab2506efa1

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drivers: marvell: comphy: add rx training on 10G port

This patch forces rx training on 10G ports
as part of comphy_smc call from Linux.

Signed-off-by: Alex Evraev <alexev@marvell.com>
Change-Id: Ie

drivers: marvell: comphy: add rx training on 10G port

This patch forces rx training on 10G ports
as part of comphy_smc call from Linux.

Signed-off-by: Alex Evraev <alexev@marvell.com>
Change-Id: Iebe6ea7c8b21cbdce5c466c8a69b92e9d7c8a8ca
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30763
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>

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plat/marvell/armada: allow builds without MSS support

Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2
definition.
Images build with MSS_SUPPORT=0 will not include service CPUs
FW and w

plat/marvell/armada: allow builds without MSS support

Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2
definition.
Images build with MSS_SUPPORT=0 will not include service CPUs
FW and will not support PM, FC and other features implemented
in these FW images.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Idf301ebd218ce65a60f277f3876d0aeb6c72f105
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/37769
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>

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drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization

Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
Initialization says that TXDCLK_2X_SEL bit need

drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization

Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe
Root Complex mode. Both U-Boot and Linux kernel support only Root Complex
mode. Set this bit.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Id2a538c379b911b62597f9463b4842b7b5c24df7

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drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call

The third argument of the reg_set() function has name 'mask', which
indicates that it is a mask applied to the register valu

drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call

The third argument of the reg_set() function has name 'mask', which
indicates that it is a mask applied to the register value which is
going to be updated. But the implementation of this function uses
this argument to clear prior value of the register, i.e. instead of
new_val = (old_val & ~mask) | (data & mask);
it does
new_val = (new_val & ~mask) | data;

(The more proper name for this function should be reg_clrsetbits(),
since internally it calls mmio_clrsetbits_32().)

To make code more readable set 'mask' argument to real mask, i.e. bits
of register values which are going to be updated.

This patch does not make any functional change, only cosmetic, due to
how 'mask' is interpreted.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ifa0339e79c07d1994c7971b65d966b92cb735f65

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drivers: marvell: comphy-a3700: Fix configuring polarity invert bits

TXD_INVERT_BIT or RXD_INVERT_BIT needs to be set only in case when
appropriate polarity is inverted. Otherwise these bits should

drivers: marvell: comphy-a3700: Fix configuring polarity invert bits

TXD_INVERT_BIT or RXD_INVERT_BIT needs to be set only in case when
appropriate polarity is inverted. Otherwise these bits should be
cleared.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8b09fab883a7b995fd72a7d8ae6233f0fa07011b

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marvell: comphy: cp110: add support for USB comphy polarity invert

The polarity inversion for USB was not tested due to lack of hw design
which requires it. Currently all supported boards doesn't re

marvell: comphy: cp110: add support for USB comphy polarity invert

The polarity inversion for USB was not tested due to lack of hw design
which requires it. Currently all supported boards doesn't require USB
phy polarity inversion, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards. Enable the option for the ones that need it.

Change-Id: Ia5f2ee313a93962e94963e2dd8a759ef6d9da369
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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marvell: comphy: cp110: add support for SATA comphy polarity invert

The cp110 comphy has ability to invert RX and/or TX polarity. Polarity
depends on board design. Currently all supported boards doe

marvell: comphy: cp110: add support for SATA comphy polarity invert

The cp110 comphy has ability to invert RX and/or TX polarity. Polarity
depends on board design. Currently all supported boards doesn't require
SATA phy polarity invert, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards.

Change-Id: Ifd0bc6aaf8a76a0928132b197422f3193cf020d5
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353

According to erratum IPCE_COMPHY-1353 the TX_IDLE bit should
be toggled in addition to the XFI/SFI PHY reset.

Change-Id: Idd2c2abfcb2f960c

marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353

According to erratum IPCE_COMPHY-1353 the TX_IDLE bit should
be toggled in addition to the XFI/SFI PHY reset.

Change-Id: Idd2c2abfcb2f960caa01e6d69db524c2e4734f50
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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drivers: marvell: mg_conf_cm3: pass comphy lane number to AP FW

Since the AP process can be enabled on different setups, the information
about used comphy lane should be passed to AP FW. For instanc

drivers: marvell: mg_conf_cm3: pass comphy lane number to AP FW

Since the AP process can be enabled on different setups, the information
about used comphy lane should be passed to AP FW. For instance:
- A8K development board uses comphy lane 2 for eth 0
- cn913x development board uses comphy lane 4 for eth 0

Change-Id: Icf001fb3eea4d9c24c09384e49844ecaf8655ad2
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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marvell: comphy: start AP FW when comphy AP mode selected

After configuring comphy to AP mode also start AP FW.

Change-Id: Ib28977d7ee643575a818ba17f69dea0b7e8e0df4
Signed-off-by: Grzegorz Jaszczyk

marvell: comphy: start AP FW when comphy AP mode selected

After configuring comphy to AP mode also start AP FW.

Change-Id: Ib28977d7ee643575a818ba17f69dea0b7e8e0df4
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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marvell: comphy: initialize common phy selector for AP mode

Configuring common phy selector which was missing for AP mode.

Change-Id: I15be1ba50b8aafe9094734abec139d72c18bb224
Signed-off-by: Grzego

marvell: comphy: initialize common phy selector for AP mode

Configuring common phy selector which was missing for AP mode.

Change-Id: I15be1ba50b8aafe9094734abec139d72c18bb224
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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marvell: comphy: update rx_training procedure

1) Relay only on rx training, remove parts responsible for tx training
(trx training).
2) Add extra steps e.g. preconfigure FFE before starting training

marvell: comphy: update rx_training procedure

1) Relay only on rx training, remove parts responsible for tx training
(trx training).
2) Add extra steps e.g. preconfigure FFE before starting training.
3) Remove some unnecessary steps like RRBS31 loopback setting which
shouldn't be relevant for tx_training.

Change-Id: Ib1e8567714f9ce33578186a262c339aa4b1c51f2
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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marvell: armada: add extra level in marvell platform hierarchy

This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
pla

marvell: armada: add extra level in marvell platform hierarchy

This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
plat, include/plat) are moved to the new "armada" sub-folder.

Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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