| b2a68f88 | 16-Feb-2018 |
Soby Mathew <soby.mathew@arm.com> |
Docs: Update design guide for dynamic config
This patch updates the `firmware-design.rst` document for
changes in ARM-TF for supporting dynamic configuration features
as presented in `Secure Firmwar
Docs: Update design guide for dynamic config
This patch updates the `firmware-design.rst` document for
changes in ARM-TF for supporting dynamic configuration features
as presented in `Secure Firmware BoF SFO'17`[1].
The patch also updates the user-guide for 2 build options for FVP
pertaining to dynamic config.
[1] https://www.slideshare.net/linaroorg/bof-device-tree-and-secure-firmware-bof-sfo17310
Change-Id: Ic099cf41e7f1a98718c39854e6286d884011d445
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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| bf35944b | 08-Mar-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1277 from hzhuang1/testing/bl2_el3_v0.6
hikey: migrate to BL2_EL3 |
| dbf9f283 | 07-Mar-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1239 from arve-android/trusty-fixes
Trusty fixes |
| 0e9c7f27 | 05-Mar-2018 |
Arve Hjønnevåg <arve@android.com> |
trusty: Add boot parameter documentation
Change-Id: Ibfb75145e3a31ae2106eedfbe4a91c2e31bb9f2a |
| d2128731 | 25-Jan-2018 |
Haojian Zhuang <haojian.zhuang@linaro.org> |
hikey960: migrate to bl2_el3
Since non-TF ROM is used in HiKey960 platform (Hisilicon Hi3660 SoC),
replace BL1 by BL2_EL3 in normal boot mode.
When flush images in recovery mode, keep to use BL1.
hikey960: migrate to bl2_el3
Since non-TF ROM is used in HiKey960 platform (Hisilicon Hi3660 SoC),
replace BL1 by BL2_EL3 in normal boot mode.
When flush images in recovery mode, keep to use BL1.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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| a628b1ab | 25-Jan-2018 |
Haojian Zhuang <haojian.zhuang@linaro.org> |
hikey: migrate to bl2_el3
Since non-TF ROM is used in HiKey platform (Hisilicon Hi6220 SoC),
replace BL1 by BL2_EL3 in normal boot mode.
When we recovery images in recovery mode, keep to use BL1.
hikey: migrate to bl2_el3
Since non-TF ROM is used in HiKey platform (Hisilicon Hi6220 SoC),
replace BL1 by BL2_EL3 in normal boot mode.
When we recovery images in recovery mode, keep to use BL1.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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| fe7210cd | 31-Jan-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
FVP: Allow building for DynamIQ systems
FVPs that model DynamIQ configuration implements all CPUs in a single
cluster. I.e., such models have a single cluster with more than 4 CPUs.
This differs fro
FVP: Allow building for DynamIQ systems
FVPs that model DynamIQ configuration implements all CPUs in a single
cluster. I.e., such models have a single cluster with more than 4 CPUs.
This differs from existing default build configuration for FVP where up
to 4 CPUs are assumed per cluster.
To allow building for DynamIQ configuration, promote the macro
FVP_MAX_CPUS_PER_CLUSTER as a build option to have it set from the build
command line. The value of the build option defaults to 4.
Change-Id: Idc3853bc95f680869b434b011c2dbd733e40c6ce
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| bd8e6a99 | 28-Feb-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1287 from davidcunado-arm/dc/fix_misra
Update ULL() macro and instances of ull to comply with MISRA |
| b39d2896 | 27-Feb-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1283 from jeenu-arm/sdei-fixes
SDEI fixes |
| 5724481f | 16-Feb-2018 |
David Cunado <david.cunado@arm.com> |
Update ULL() macro and instances of ull to comply with MISRA
MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes.
This patch resolves this for the ULL() macro by usin
Update ULL() macro and instances of ull to comply with MISRA
MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes.
This patch resolves this for the ULL() macro by using ULL suffix instead
of the ull suffix.
Change-Id: Ia8183c399e74677e676956e8653e82375d0e0a01
Signed-off-by: David Cunado <david.cunado@arm.com>
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| f2928f5b | 16-Jan-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
SDEI: Add prioritisation clarification
To make exception handling amongst Secure components, require that SDEI
exception priorities must be assigned the lowest among Secure
priorities. Clarify docum
SDEI: Add prioritisation clarification
To make exception handling amongst Secure components, require that SDEI
exception priorities must be assigned the lowest among Secure
priorities. Clarify documentation to this effect.
Change-Id: I92524b7b7e9b3fa06a10c86372bc3c4dd18c00ad
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 101d01e2 | 10-Jan-2018 |
Soby Mathew <soby.mathew@arm.com> |
BL1: Deprecate the `bl1_init_bl2_mem_layout()` API
The `bl1_init_bl2_mem_layout()` API is now deprecated. The default weak
implementation of `bl1_plat_handle_post_image_load()` calculates the
BL2 me
BL1: Deprecate the `bl1_init_bl2_mem_layout()` API
The `bl1_init_bl2_mem_layout()` API is now deprecated. The default weak
implementation of `bl1_plat_handle_post_image_load()` calculates the
BL2 memory layout and populates the same in x1(r1). This ensures
compatibility for the deprecated API.
Change-Id: Id44bdc1f572dc42ee6ceef4036b3a46803689315
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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| 566034fc | 08-Feb-2018 |
Soby Mathew <soby.mathew@arm.com> |
Add image_id to bl1_plat_handle_post/pre_image_load()
This patch adds an argument to bl1_plat_post/pre_image_load() APIs
to make it more future proof. The default implementation of
these are moved t
Add image_id to bl1_plat_handle_post/pre_image_load()
This patch adds an argument to bl1_plat_post/pre_image_load() APIs
to make it more future proof. The default implementation of
these are moved to `plat_bl1_common.c` file.
These APIs are now invoked appropriately in the FWU code path prior
to or post image loading by BL1 and are not restricted
to LOAD_IMAGE_V2.
The patch also reorganizes some common platform files. The previous
`plat_bl2_el3_common.c` and `platform_helpers_default.c` files are
merged into a new `plat_bl_common.c` file.
NOTE: The addition of an argument to the above mentioned platform APIs
is not expected to have a great impact because these APIs were only
recently added and are unlikely to be used.
Change-Id: I0519caaee0f774dd33638ff63a2e597ea178c453
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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| 38d96de6 | 23-Feb-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Fix Foundation FVP instructions in User Guide
The Arm Trusted Firmware is built by default for ARMv8-A version 8.0.
However, the Foundation FVP runs by default in the highest version of
the architec
Fix Foundation FVP instructions in User Guide
The Arm Trusted Firmware is built by default for ARMv8-A version 8.0.
However, the Foundation FVP runs by default in the highest version of
the architecture it supports. This causes problems when trying to run
the Arm Trusted Firmware on it.
This patch adds a note to the User Guide about this problem.
Change-Id: I0220fe1a9c66c2292149ad4a7ffe5e27ba08ab28
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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|
| 15e59585 | 12-Feb-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1256 from jeenu-arm/tsp-ehf
TSP changes for EHF |
| fb750ee1 | 10-Jan-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
interrupt-framework-design.rst: Cosmetic changes
Change-Id: Id2e2800af59ca35fc0c4cfdddd9f5c5afd56a4db
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
| 6027796f | 11-Jan-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
TSPD: Require NS preemption along with EL3 exception handling
At present, the build option TSP_NS_INTR_ASYNC_PREEMPT controls how
Non-secure interrupt affects TSPs execution. When TSP is executing:
TSPD: Require NS preemption along with EL3 exception handling
At present, the build option TSP_NS_INTR_ASYNC_PREEMPT controls how
Non-secure interrupt affects TSPs execution. When TSP is executing:
1. When TSP_NS_INTR_ASYNC_PREEMPT=0, Non-secure interrupts are received
at the TSP's exception vector, and TSP voluntarily preempts itself.
2. When TSP_NS_INTR_ASYNC_PREEMPT=1, Non-secure interrupts causes a
trap to EL3, which preempts TSP execution.
When EL3 exception handling is in place (i.e.,
EL3_EXCEPTION_HANDLING=1), FIQs are always trapped to EL3. On a system
with GICv3, pending NS interrupts while TSP is executing will be
signalled as FIQ (which traps to EL3). This situation necessitates the
same treatment applied to case (2) above.
Therefore, when EL3 exception handling is in place, additionally
require that TSP_NS_INTR_ASYNC_PREEMPT is set to one 1.
Strictly speaking, this is not required on a system with GICv2, but the
same model is uniformly followed regardless, for simplicity.
Relevant documentation updated.
Change-Id: I928a8ed081fb0ac96e8b1dfe9375c98384da1ccd
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 26ea3908 | 10-Jan-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
Deprecate one EL3 interrupt routing model with EL3 exception handling
When ARM Trusted Firmware is built with EL3_EXCEPTION_HANDLING=1,
EL3 interrupts (INTR_TYPE_EL3) will always preempt both Non-se
Deprecate one EL3 interrupt routing model with EL3 exception handling
When ARM Trusted Firmware is built with EL3_EXCEPTION_HANDLING=1,
EL3 interrupts (INTR_TYPE_EL3) will always preempt both Non-secure and
secure execution.
The interrupt management framework currently treats EL3 interrupt
routing as valid. For the above reason, this patch makes them invalid
when EL3_EXCEPTION_HANDLING is in effect.
Change-Id: I95bca8f5dc8df8eb0ff6f305cfba098611522a39
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 11f001cb | 01-Feb-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
bl1: add bl1_plat_handle_{pre,post}_image_load()
Just like bl2_, add pre/post image load handlers for BL1. No argument
is needed since BL2 is the only image loaded by BL1.
Signed-off-by: Masahiro
bl1: add bl1_plat_handle_{pre,post}_image_load()
Just like bl2_, add pre/post image load handlers for BL1. No argument
is needed since BL2 is the only image loaded by BL1.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| ba68ef55 | 01-Feb-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
bl2: add bl2_plat_handle_pre_image_load()
There are cases where we need to manipulate image information before
the load. For example, for decompressing data, we cannot load the
compressed images to
bl2: add bl2_plat_handle_pre_image_load()
There are cases where we need to manipulate image information before
the load. For example, for decompressing data, we cannot load the
compressed images to their final destination. Instead, we need to
load them to the temporary buffer for the decompressor.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| aca8a490 | 29-Jan-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1246 from sandrine-bailleux-arm/topics/sb/fix-cnp-doc
Fix documentation for CnP bit |
| 7c0a843f | 29-Jan-2018 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Fix documentation for CnP bit
The CnP bit documentation in the Firmware Design Guide incorrectly
used the term "Page Entries" instead of "Processing Elements".
Fix that.
Change-Id: Ie44ee99c281b7b1
Fix documentation for CnP bit
The CnP bit documentation in the Firmware Design Guide incorrectly
used the term "Page Entries" instead of "Processing Elements".
Fix that.
Change-Id: Ie44ee99c281b7b1a9ad90fba2c7d109f12425507
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| 1b9e79e8 | 29-Jan-2018 |
Andreas Färber <afaerber@suse.de> |
docs: hikey: Fix typo
The correct name of the manufacturer is LeMaker.
Signed-off-by: Andreas Färber <afaerber@suse.de> |
| f478253d | 25-Jan-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1232 from masahir0y/uniphier
uniphier: migrate to BL2-AT-EL3 |
| 040f1e69 | 24-Jan-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1193 from jwerner-chromium/JW_coreboot
New console API and coreboot support [v4] |