1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <delay_timer.h> 13 #include <desc_image_load.h> 14 #include <dw_ufs.h> 15 #include <errno.h> 16 #include <generic_delay_timer.h> 17 #include <hi3660.h> 18 #include <mmio.h> 19 #ifdef SPD_opteed 20 #include <optee_utils.h> 21 #endif 22 #include <platform_def.h> 23 #include <string.h> 24 #include <ufs.h> 25 26 #include "hikey960_def.h" 27 #include "hikey960_private.h" 28 29 /* 30 * The next 2 constants identify the extents of the code & RO data region. 31 * These addresses are used by the MMU setup code and therefore they must be 32 * page-aligned. It is the responsibility of the linker script to ensure that 33 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 34 */ 35 #define BL2_RO_BASE (unsigned long)(&__RO_START__) 36 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) 37 38 #define BL2_RW_BASE (BL2_RO_LIMIT) 39 40 /* 41 * The next 2 constants identify the extents of the coherent memory region. 42 * These addresses are used by the MMU setup code and therefore they must be 43 * page-aligned. It is the responsibility of the linker script to ensure that 44 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 45 * page-aligned addresses. 46 */ 47 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 48 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 49 50 static meminfo_t bl2_el3_tzram_layout; 51 extern int load_lpm3(void); 52 53 enum { 54 BOOT_MODE_RECOVERY = 0, 55 BOOT_MODE_NORMAL, 56 BOOT_MODE_MASK = 1, 57 }; 58 59 /******************************************************************************* 60 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. 61 * Return 0 on success, -1 otherwise. 62 ******************************************************************************/ 63 int plat_hikey960_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) 64 { 65 int i; 66 int *buf; 67 68 assert(scp_bl2_image_info->image_size < SCP_BL2_SIZE); 69 70 INFO("BL2: Initiating SCP_BL2 transfer to SCP\n"); 71 72 INFO("BL2: SCP_BL2: 0x%lx@0x%x\n", 73 scp_bl2_image_info->image_base, 74 scp_bl2_image_info->image_size); 75 76 buf = (int *)scp_bl2_image_info->image_base; 77 78 INFO("BL2: SCP_BL2 HEAD:\n"); 79 for (i = 0; i < 64; i += 4) 80 INFO("BL2: SCP_BL2 0x%x 0x%x 0x%x 0x%x\n", 81 buf[i], buf[i+1], buf[i+2], buf[i+3]); 82 83 buf = (int *)(scp_bl2_image_info->image_base + 84 scp_bl2_image_info->image_size - 256); 85 86 INFO("BL2: SCP_BL2 TAIL:\n"); 87 for (i = 0; i < 64; i += 4) 88 INFO("BL2: SCP_BL2 0x%x 0x%x 0x%x 0x%x\n", 89 buf[i], buf[i+1], buf[i+2], buf[i+3]); 90 91 INFO("BL2: SCP_BL2 transferred to SCP\n"); 92 93 load_lpm3(); 94 (void)buf; 95 96 return 0; 97 } 98 99 static void hikey960_ufs_reset(void) 100 { 101 unsigned int data, mask; 102 103 mmio_write_32(CRG_PERDIS7_REG, 1 << 14); 104 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 105 do { 106 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 107 } while (data & BIT_SYSCTRL_REF_CLOCK_EN); 108 /* use abb clk */ 109 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); 110 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); 111 mmio_write_32(PCTRL_PERI_CTRL3_REG, (1 << 0) | (1 << 16)); 112 mdelay(1); 113 mmio_write_32(CRG_PEREN7_REG, 1 << 14); 114 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 115 116 mmio_write_32(CRG_PERRSTEN3_REG, PERI_UFS_BIT); 117 do { 118 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 119 } while ((data & PERI_UFS_BIT) == 0); 120 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); 121 mdelay(1); 122 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); 123 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 124 MASK_UFS_DEVICE_RESET); 125 /* clear SC_DIV_UFS_PERIBUS */ 126 mask = SC_DIV_UFS_PERIBUS << 16; 127 mmio_write_32(CRG_CLKDIV17_REG, mask); 128 /* set SC_DIV_UFSPHY_CFG(3) */ 129 mask = SC_DIV_UFSPHY_CFG_MASK << 16; 130 data = SC_DIV_UFSPHY_CFG(3); 131 mmio_write_32(CRG_CLKDIV16_REG, mask | data); 132 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 133 data &= ~MASK_SYSCTRL_CFG_CLOCK_FREQ; 134 data |= 0x39; 135 mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); 136 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); 137 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, 138 MASK_UFS_CLK_GATE_BYPASS); 139 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); 140 141 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); 142 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); 143 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); 144 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); 145 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_ARST_UFS_BIT); 146 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); 147 mdelay(1); 148 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 149 MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET); 150 mdelay(20); 151 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 152 0x03300330); 153 154 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_UFS_BIT); 155 do { 156 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 157 } while (data & PERI_UFS_BIT); 158 } 159 160 void hikey960_init_ufs(void) 161 { 162 dw_ufs_params_t ufs_params; 163 164 memset(&ufs_params, 0, sizeof(ufs_params_t)); 165 ufs_params.reg_base = UFS_REG_BASE; 166 ufs_params.desc_base = HIKEY960_UFS_DESC_BASE; 167 ufs_params.desc_size = HIKEY960_UFS_DESC_SIZE; 168 hikey960_ufs_reset(); 169 dw_ufs_init(&ufs_params); 170 } 171 172 /******************************************************************************* 173 * Gets SPSR for BL32 entry 174 ******************************************************************************/ 175 uint32_t hikey960_get_spsr_for_bl32_entry(void) 176 { 177 /* 178 * The Secure Payload Dispatcher service is responsible for 179 * setting the SPSR prior to entry into the BL3-2 image. 180 */ 181 return 0; 182 } 183 184 /******************************************************************************* 185 * Gets SPSR for BL33 entry 186 ******************************************************************************/ 187 #ifndef AARCH32 188 uint32_t hikey960_get_spsr_for_bl33_entry(void) 189 { 190 unsigned int mode; 191 uint32_t spsr; 192 193 /* Figure out what mode we enter the non-secure world in */ 194 mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1; 195 196 /* 197 * TODO: Consider the possibility of specifying the SPSR in 198 * the FIP ToC and allowing the platform to have a say as 199 * well. 200 */ 201 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 202 return spsr; 203 } 204 #else 205 uint32_t hikey960_get_spsr_for_bl33_entry(void) 206 { 207 unsigned int hyp_status, mode, spsr; 208 209 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 210 211 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 212 213 /* 214 * TODO: Consider the possibility of specifying the SPSR in 215 * the FIP ToC and allowing the platform to have a say as 216 * well. 217 */ 218 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 219 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 220 return spsr; 221 } 222 #endif /* AARCH32 */ 223 224 int hikey960_bl2_handle_post_image_load(unsigned int image_id) 225 { 226 int err = 0; 227 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 228 #ifdef SPD_opteed 229 bl_mem_params_node_t *pager_mem_params = NULL; 230 bl_mem_params_node_t *paged_mem_params = NULL; 231 #endif 232 assert(bl_mem_params); 233 234 switch (image_id) { 235 #ifdef AARCH64 236 case BL32_IMAGE_ID: 237 #ifdef SPD_opteed 238 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 239 assert(pager_mem_params); 240 241 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 242 assert(paged_mem_params); 243 244 err = parse_optee_header(&bl_mem_params->ep_info, 245 &pager_mem_params->image_info, 246 &paged_mem_params->image_info); 247 if (err != 0) { 248 WARN("OPTEE header parse error.\n"); 249 } 250 #endif 251 bl_mem_params->ep_info.spsr = hikey960_get_spsr_for_bl32_entry(); 252 break; 253 #endif 254 255 case BL33_IMAGE_ID: 256 /* BL33 expects to receive the primary CPU MPID (through r0) */ 257 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 258 bl_mem_params->ep_info.spsr = hikey960_get_spsr_for_bl33_entry(); 259 break; 260 261 #ifdef SCP_BL2_BASE 262 case SCP_BL2_IMAGE_ID: 263 /* The subsequent handling of SCP_BL2 is platform specific */ 264 err = plat_hikey960_bl2_handle_scp_bl2(&bl_mem_params->image_info); 265 if (err) { 266 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 267 } 268 break; 269 #endif 270 } 271 272 return err; 273 } 274 275 static void hikey960_clk_init(void) 276 { 277 /* change ldi0 sel to ppll2 */ 278 mmio_write_32(0xfff350b4, 0xf0002000); 279 /* ldi0 20' */ 280 mmio_write_32(0xfff350bc, 0xfc004c00); 281 } 282 283 static void hikey960_pmu_init(void) 284 { 285 /* clear np_xo_abb_dig_START bit in PMIC_CLK_TOP_CTRL7 register */ 286 mmio_clrbits_32(PMU_SSI0_CLK_TOP_CTRL7_REG, NP_XO_ABB_DIG); 287 } 288 289 static void hikey960_enable_ppll3(void) 290 { 291 /* enable ppll3 */ 292 mmio_write_32(PMC_PPLL3_CTRL0_REG, 0x4904305); 293 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x2300000); 294 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x6300000); 295 } 296 297 static void bus_idle_clear(unsigned int value) 298 { 299 unsigned int pmc_value, value1, value2; 300 int timeout = 100; 301 302 pmc_value = value << 16; 303 pmc_value &= ~value; 304 mmio_write_32(PMC_NOC_POWER_IDLEREQ_REG, pmc_value); 305 306 for (;;) { 307 value1 = (unsigned int)mmio_read_32(PMC_NOC_POWER_IDLEACK_REG); 308 value2 = (unsigned int)mmio_read_32(PMC_NOC_POWER_IDLE_REG); 309 if (((value1 & value) == 0) && ((value2 & value) == 0)) 310 break; 311 udelay(1); 312 timeout--; 313 if (timeout <= 0) { 314 WARN("%s timeout\n", __func__); 315 break; 316 } 317 } 318 } 319 320 static void set_vivobus_power_up(void) 321 { 322 /* clk enable */ 323 mmio_write_32(CRG_CLKDIV20_REG, 0x00020002); 324 mmio_write_32(CRG_PEREN0_REG, 0x00001000); 325 } 326 327 static void set_dss_power_up(void) 328 { 329 /* set edc0 133MHz = 1600MHz / 12 */ 330 mmio_write_32(CRG_CLKDIV5_REG, 0x003f000b); 331 /* set ldi0 ppl0 */ 332 mmio_write_32(CRG_CLKDIV3_REG, 0xf0001000); 333 /* set ldi0 133MHz, 1600MHz / 12 */ 334 mmio_write_32(CRG_CLKDIV5_REG, 0xfc002c00); 335 /* mtcmos on */ 336 mmio_write_32(CRG_PERPWREN_REG, 0x00000020); 337 udelay(100); 338 /* DISP CRG */ 339 mmio_write_32(CRG_PERRSTDIS4_REG, 0x00000010); 340 /* clk enable */ 341 mmio_write_32(CRG_CLKDIV18_REG, 0x01400140); 342 mmio_write_32(CRG_PEREN0_REG, 0x00002000); 343 mmio_write_32(CRG_PEREN3_REG, 0x0003b000); 344 udelay(1); 345 /* clk disable */ 346 mmio_write_32(CRG_PERDIS3_REG, 0x0003b000); 347 mmio_write_32(CRG_PERDIS0_REG, 0x00002000); 348 mmio_write_32(CRG_CLKDIV18_REG, 0x01400000); 349 udelay(1); 350 /* iso disable */ 351 mmio_write_32(CRG_ISODIS_REG, 0x00000040); 352 /* unreset */ 353 mmio_write_32(CRG_PERRSTDIS4_REG, 0x00000006); 354 mmio_write_32(CRG_PERRSTDIS3_REG, 0x00000c00); 355 /* clk enable */ 356 mmio_write_32(CRG_CLKDIV18_REG, 0x01400140); 357 mmio_write_32(CRG_PEREN0_REG, 0x00002000); 358 mmio_write_32(CRG_PEREN3_REG, 0x0003b000); 359 /* bus idle clear */ 360 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_DSS); 361 /* set edc0 400MHz for 2K 1600MHz / 4 */ 362 mmio_write_32(CRG_CLKDIV5_REG, 0x003f0003); 363 /* set ldi 266MHz, 1600MHz / 6 */ 364 mmio_write_32(CRG_CLKDIV5_REG, 0xfc001400); 365 } 366 367 static void set_vcodec_power_up(void) 368 { 369 /* clk enable */ 370 mmio_write_32(CRG_CLKDIV20_REG, 0x00040004); 371 mmio_write_32(CRG_PEREN0_REG, 0x00000060); 372 mmio_write_32(CRG_PEREN2_REG, 0x10000000); 373 /* unreset */ 374 mmio_write_32(CRG_PERRSTDIS0_REG, 0x00000018); 375 /* bus idle clear */ 376 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_VCODEC); 377 } 378 379 static void set_vdec_power_up(void) 380 { 381 /* mtcmos on */ 382 mmio_write_32(CRG_PERPWREN_REG, 0x00000004); 383 udelay(100); 384 /* clk enable */ 385 mmio_write_32(CRG_CLKDIV18_REG, 0x80008000); 386 mmio_write_32(CRG_PEREN2_REG, 0x20080000); 387 mmio_write_32(CRG_PEREN3_REG, 0x00000800); 388 udelay(1); 389 /* clk disable */ 390 mmio_write_32(CRG_PERDIS3_REG, 0x00000800); 391 mmio_write_32(CRG_PERDIS2_REG, 0x20080000); 392 mmio_write_32(CRG_CLKDIV18_REG, 0x80000000); 393 udelay(1); 394 /* iso disable */ 395 mmio_write_32(CRG_ISODIS_REG, 0x00000004); 396 /* unreset */ 397 mmio_write_32(CRG_PERRSTDIS3_REG, 0x00000200); 398 /* clk enable */ 399 mmio_write_32(CRG_CLKDIV18_REG, 0x80008000); 400 mmio_write_32(CRG_PEREN2_REG, 0x20080000); 401 mmio_write_32(CRG_PEREN3_REG, 0x00000800); 402 /* bus idle clear */ 403 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_VDEC); 404 } 405 406 static void set_venc_power_up(void) 407 { 408 /* set venc ppll3 */ 409 mmio_write_32(CRG_CLKDIV8_REG, 0x18001000); 410 /* set venc 258MHz, 1290MHz / 5 */ 411 mmio_write_32(CRG_CLKDIV8_REG, 0x07c00100); 412 /* mtcmos on */ 413 mmio_write_32(CRG_PERPWREN_REG, 0x00000002); 414 udelay(100); 415 /* clk enable */ 416 mmio_write_32(CRG_CLKDIV19_REG, 0x00010001); 417 mmio_write_32(CRG_PEREN2_REG, 0x40000100); 418 mmio_write_32(CRG_PEREN3_REG, 0x00000400); 419 udelay(1); 420 /* clk disable */ 421 mmio_write_32(CRG_PERDIS3_REG, 0x00000400); 422 mmio_write_32(CRG_PERDIS2_REG, 0x40000100); 423 mmio_write_32(CRG_CLKDIV19_REG, 0x00010000); 424 udelay(1); 425 /* iso disable */ 426 mmio_write_32(CRG_ISODIS_REG, 0x00000002); 427 /* unreset */ 428 mmio_write_32(CRG_PERRSTDIS3_REG, 0x00000100); 429 /* clk enable */ 430 mmio_write_32(CRG_CLKDIV19_REG, 0x00010001); 431 mmio_write_32(CRG_PEREN2_REG, 0x40000100); 432 mmio_write_32(CRG_PEREN3_REG, 0x00000400); 433 /* bus idle clear */ 434 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_VENC); 435 /* set venc 645MHz, 1290MHz / 2 */ 436 mmio_write_32(CRG_CLKDIV8_REG, 0x07c00040); 437 } 438 439 static void set_isp_power_up(void) 440 { 441 /* mtcmos on */ 442 mmio_write_32(CRG_PERPWREN_REG, 0x00000001); 443 udelay(100); 444 /* clk enable */ 445 mmio_write_32(CRG_CLKDIV18_REG, 0x70007000); 446 mmio_write_32(CRG_CLKDIV20_REG, 0x00100010); 447 mmio_write_32(CRG_PEREN5_REG, 0x01000010); 448 mmio_write_32(CRG_PEREN3_REG, 0x0bf00000); 449 udelay(1); 450 /* clk disable */ 451 mmio_write_32(CRG_PERDIS5_REG, 0x01000010); 452 mmio_write_32(CRG_PERDIS3_REG, 0x0bf00000); 453 mmio_write_32(CRG_CLKDIV18_REG, 0x70000000); 454 mmio_write_32(CRG_CLKDIV20_REG, 0x00100000); 455 udelay(1); 456 /* iso disable */ 457 mmio_write_32(CRG_ISODIS_REG, 0x00000001); 458 /* unreset */ 459 mmio_write_32(CRG_ISP_SEC_RSTDIS_REG, 0x0000002f); 460 /* clk enable */ 461 mmio_write_32(CRG_CLKDIV18_REG, 0x70007000); 462 mmio_write_32(CRG_CLKDIV20_REG, 0x00100010); 463 mmio_write_32(CRG_PEREN5_REG, 0x01000010); 464 mmio_write_32(CRG_PEREN3_REG, 0x0bf00000); 465 /* bus idle clear */ 466 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_ISP); 467 /* csi clk enable */ 468 mmio_write_32(CRG_PEREN3_REG, 0x00700000); 469 } 470 471 static void set_ivp_power_up(void) 472 { 473 /* set ivp ppll0 */ 474 mmio_write_32(CRG_CLKDIV0_REG, 0xc0000000); 475 /* set ivp 267MHz, 1600MHz / 6 */ 476 mmio_write_32(CRG_CLKDIV0_REG, 0x3c001400); 477 /* mtcmos on */ 478 mmio_write_32(CRG_PERPWREN_REG, 0x00200000); 479 udelay(100); 480 /* IVP CRG unreset */ 481 mmio_write_32(CRG_IVP_SEC_RSTDIS_REG, 0x00000001); 482 /* clk enable */ 483 mmio_write_32(CRG_CLKDIV20_REG, 0x02000200); 484 mmio_write_32(CRG_PEREN4_REG, 0x000000a8); 485 udelay(1); 486 /* clk disable */ 487 mmio_write_32(CRG_PERDIS4_REG, 0x000000a8); 488 mmio_write_32(CRG_CLKDIV20_REG, 0x02000000); 489 udelay(1); 490 /* iso disable */ 491 mmio_write_32(CRG_ISODIS_REG, 0x01000000); 492 /* unreset */ 493 mmio_write_32(CRG_IVP_SEC_RSTDIS_REG, 0x00000002); 494 /* clk enable */ 495 mmio_write_32(CRG_CLKDIV20_REG, 0x02000200); 496 mmio_write_32(CRG_PEREN4_REG, 0x000000a8); 497 /* bus idle clear */ 498 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_IVP); 499 /* set ivp 533MHz, 1600MHz / 3 */ 500 mmio_write_32(CRG_CLKDIV0_REG, 0x3c000800); 501 } 502 503 static void set_audio_power_up(void) 504 { 505 unsigned int ret; 506 int timeout = 100; 507 /* mtcmos on */ 508 mmio_write_32(SCTRL_SCPWREN_REG, 0x00000001); 509 udelay(100); 510 /* clk enable */ 511 mmio_write_32(CRG_CLKDIV19_REG, 0x80108010); 512 mmio_write_32(SCTRL_SCCLKDIV2_REG, 0x00010001); 513 mmio_write_32(SCTRL_SCPEREN0_REG, 0x0c000000); 514 mmio_write_32(CRG_PEREN0_REG, 0x04000000); 515 mmio_write_32(CRG_PEREN5_REG, 0x00000080); 516 mmio_write_32(SCTRL_SCPEREN1_REG, 0x0000000f); 517 udelay(1); 518 /* clk disable */ 519 mmio_write_32(SCTRL_SCPERDIS1_REG, 0x0000000f); 520 mmio_write_32(SCTRL_SCPERDIS0_REG, 0x0c000000); 521 mmio_write_32(CRG_PERDIS5_REG, 0x00000080); 522 mmio_write_32(CRG_PERDIS0_REG, 0x04000000); 523 mmio_write_32(SCTRL_SCCLKDIV2_REG, 0x00010000); 524 mmio_write_32(CRG_CLKDIV19_REG, 0x80100000); 525 udelay(1); 526 /* iso disable */ 527 mmio_write_32(SCTRL_SCISODIS_REG, 0x00000001); 528 udelay(1); 529 /* unreset */ 530 mmio_write_32(SCTRL_PERRSTDIS1_SEC_REG, 0x00000001); 531 mmio_write_32(SCTRL_SCPERRSTDIS0_REG, 0x00000780); 532 /* clk enable */ 533 mmio_write_32(CRG_CLKDIV19_REG, 0x80108010); 534 mmio_write_32(SCTRL_SCCLKDIV2_REG, 0x00010001); 535 mmio_write_32(SCTRL_SCPEREN0_REG, 0x0c000000); 536 mmio_write_32(CRG_PEREN0_REG, 0x04000000); 537 mmio_write_32(CRG_PEREN5_REG, 0x00000080); 538 mmio_write_32(SCTRL_SCPEREN1_REG, 0x0000000f); 539 /* bus idle clear */ 540 mmio_write_32(SCTRL_SCPERCTRL7_REG, 0x00040000); 541 for (;;) { 542 ret = mmio_read_32(SCTRL_SCPERSTAT6_REG); 543 if (((ret & (1 << 5)) == 0) && ((ret & (1 << 8)) == 0)) 544 break; 545 udelay(1); 546 timeout--; 547 if (timeout <= 0) { 548 WARN("%s timeout\n", __func__); 549 break; 550 } 551 } 552 mmio_write_32(ASP_CFG_MMBUF_CTRL_REG, 0x00ff0000); 553 } 554 555 static void set_pcie_power_up(void) 556 { 557 /* mtcmos on */ 558 mmio_write_32(SCTRL_SCPWREN_REG, 0x00000010); 559 udelay(100); 560 /* clk enable */ 561 mmio_write_32(SCTRL_SCCLKDIV6_REG, 0x08000800); 562 mmio_write_32(SCTRL_SCPEREN2_REG, 0x00104000); 563 mmio_write_32(CRG_PEREN7_REG, 0x000003a0); 564 udelay(1); 565 /* clk disable */ 566 mmio_write_32(SCTRL_SCPERDIS2_REG, 0x00104000); 567 mmio_write_32(CRG_PERDIS7_REG, 0x000003a0); 568 mmio_write_32(SCTRL_SCCLKDIV6_REG, 0x08000000); 569 udelay(1); 570 /* iso disable */ 571 mmio_write_32(SCTRL_SCISODIS_REG, 0x00000030); 572 /* unreset */ 573 mmio_write_32(CRG_PERRSTDIS3_REG, 0x8c000000); 574 /* clk enable */ 575 mmio_write_32(SCTRL_SCCLKDIV6_REG, 0x08000800); 576 mmio_write_32(SCTRL_SCPEREN2_REG, 0x00104000); 577 mmio_write_32(CRG_PEREN7_REG, 0x000003a0); 578 } 579 580 static void ispfunc_enable(void) 581 { 582 /* enable ispfunc. Otherwise powerup isp_srt causes exception. */ 583 mmio_write_32(0xfff35000, 0x00000008); 584 mmio_write_32(0xfff35460, 0xc004ffff); 585 mmio_write_32(0xfff35030, 0x02000000); 586 mdelay(10); 587 } 588 589 static void isps_control_clock(int flag) 590 { 591 unsigned int ret; 592 593 /* flag: 0 -- disable clock, 1 -- enable clock */ 594 if (flag) { 595 ret = mmio_read_32(0xe8420364); 596 ret |= 1; 597 mmio_write_32(0xe8420364, ret); 598 } else { 599 ret = mmio_read_32(0xe8420364); 600 ret &= ~1; 601 mmio_write_32(0xe8420364, ret); 602 } 603 } 604 605 static void set_isp_srt_power_up(void) 606 { 607 unsigned int ret; 608 609 ispfunc_enable(); 610 /* reset */ 611 mmio_write_32(0xe8420374, 0x00000001); 612 mmio_write_32(0xe8420350, 0x00000000); 613 mmio_write_32(0xe8420358, 0x00000000); 614 /* mtcmos on */ 615 mmio_write_32(0xfff35150, 0x00400000); 616 udelay(100); 617 /* clk enable */ 618 isps_control_clock(1); 619 udelay(1); 620 isps_control_clock(0); 621 udelay(1); 622 /* iso disable */ 623 mmio_write_32(0xfff35148, 0x08000000); 624 /* unreset */ 625 ret = mmio_read_32(0xe8420374); 626 ret &= ~0x1; 627 mmio_write_32(0xe8420374, ret); 628 /* clk enable */ 629 isps_control_clock(1); 630 /* enable clock gating for accessing csi registers */ 631 mmio_write_32(0xe8420010, ~0); 632 } 633 634 static void hikey960_regulator_enable(void) 635 { 636 set_vivobus_power_up(); 637 hikey960_enable_ppll3(); 638 set_dss_power_up(); 639 set_vcodec_power_up(); 640 set_vdec_power_up(); 641 set_venc_power_up(); 642 set_isp_power_up(); 643 set_ivp_power_up(); 644 set_audio_power_up(); 645 set_pcie_power_up(); 646 set_isp_srt_power_up(); 647 } 648 649 static void hikey960_tzc_init(void) 650 { 651 mmio_write_32(TZC_EN0_REG, 0x7fbff066); 652 mmio_write_32(TZC_EN1_REG, 0xfffff5fc); 653 mmio_write_32(TZC_EN2_REG, 0x0007005c); 654 mmio_write_32(TZC_EN3_REG, 0x37030700); 655 mmio_write_32(TZC_EN4_REG, 0xf63fefae); 656 mmio_write_32(TZC_EN5_REG, 0x000410fd); 657 mmio_write_32(TZC_EN6_REG, 0x0063ff68); 658 mmio_write_32(TZC_EN7_REG, 0x030000f3); 659 mmio_write_32(TZC_EN8_REG, 0x00000007); 660 } 661 662 static void hikey960_peri_init(void) 663 { 664 /* unreset */ 665 mmio_setbits_32(CRG_PERRSTDIS4_REG, 1); 666 } 667 668 static void hikey960_pinmux_init(void) 669 { 670 unsigned int id; 671 672 hikey960_read_boardid(&id); 673 if (id == 5301) { 674 /* hikey960 hardware v2 */ 675 /* GPIO150: LED */ 676 mmio_write_32(IOMG_FIX_006_REG, 0); 677 /* GPIO151: LED */ 678 mmio_write_32(IOMG_FIX_007_REG, 0); 679 /* GPIO189: LED */ 680 mmio_write_32(IOMG_AO_011_REG, 0); 681 /* GPIO190: LED */ 682 mmio_write_32(IOMG_AO_012_REG, 0); 683 /* GPIO46 */ 684 mmio_write_32(IOMG_044_REG, 0); 685 /* GPIO202 */ 686 mmio_write_32(IOMG_AO_023_REG, 0); 687 /* GPIO206 */ 688 mmio_write_32(IOMG_AO_026_REG, 0); 689 /* GPIO219 - PD pullup */ 690 mmio_write_32(IOMG_AO_039_REG, 0); 691 mmio_write_32(IOCG_AO_043_REG, 1 << 0); 692 } 693 /* GPIO005 - PMU SSI, 10mA */ 694 mmio_write_32(IOCG_006_REG, 2 << 4); 695 } 696 697 /******************************************************************************* 698 * This function can be used by the platforms to update/use image 699 * information for given `image_id`. 700 ******************************************************************************/ 701 int bl2_plat_handle_post_image_load(unsigned int image_id) 702 { 703 return hikey960_bl2_handle_post_image_load(image_id); 704 } 705 706 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 707 u_register_t arg3, u_register_t arg4) 708 { 709 unsigned int id, uart_base; 710 711 generic_delay_timer_init(); 712 hikey960_read_boardid(&id); 713 if (id == 5300) 714 uart_base = PL011_UART5_BASE; 715 else 716 uart_base = PL011_UART6_BASE; 717 /* Initialize the console to provide early debug support */ 718 console_init(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 719 /* 720 * Allow BL2 to see the whole Trusted RAM. 721 */ 722 bl2_el3_tzram_layout.total_base = BL2_RW_BASE; 723 bl2_el3_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE; 724 } 725 726 void bl2_el3_plat_arch_setup(void) 727 { 728 hikey960_init_mmu_el3(bl2_el3_tzram_layout.total_base, 729 bl2_el3_tzram_layout.total_size, 730 BL2_RO_BASE, 731 BL2_RO_LIMIT, 732 BL2_COHERENT_RAM_BASE, 733 BL2_COHERENT_RAM_LIMIT); 734 } 735 736 void bl2_platform_setup(void) 737 { 738 /* disable WDT0 */ 739 if (mmio_read_32(WDT0_REG_BASE + WDT_LOCK_OFFSET) == WDT_LOCKED) { 740 mmio_write_32(WDT0_REG_BASE + WDT_LOCK_OFFSET, WDT_UNLOCK); 741 mmio_write_32(WDT0_REG_BASE + WDT_CONTROL_OFFSET, 0); 742 mmio_write_32(WDT0_REG_BASE + WDT_LOCK_OFFSET, 0); 743 } 744 hikey960_clk_init(); 745 hikey960_pmu_init(); 746 hikey960_regulator_enable(); 747 hikey960_tzc_init(); 748 hikey960_peri_init(); 749 hikey960_pinmux_init(); 750 } 751