1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <desc_image_load.h> 13 #include <dw_mmc.h> 14 #include <emmc.h> 15 #include <errno.h> 16 #include <gpio.h> 17 #include <hi6220.h> 18 #include <hi6553.h> 19 #include <hisi_mcu.h> 20 #include <hisi_sram_map.h> 21 #include <mmio.h> 22 #ifdef SPD_opteed 23 #include <optee_utils.h> 24 #endif 25 #include <pl061_gpio.h> 26 #include <platform.h> 27 #include <platform_def.h> 28 #include <sp804_delay_timer.h> 29 #include <string.h> 30 31 #include "hikey_def.h" 32 #include "hikey_private.h" 33 34 /* 35 * The next 2 constants identify the extents of the code & RO data region. 36 * These addresses are used by the MMU setup code and therefore they must be 37 * page-aligned. It is the responsibility of the linker script to ensure that 38 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 39 */ 40 #define BL2_RO_BASE (unsigned long)(&__RO_START__) 41 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) 42 43 #define BL2_RW_BASE (BL2_RO_LIMIT) 44 45 /* 46 * The next 2 constants identify the extents of the coherent memory region. 47 * These addresses are used by the MMU setup code and therefore they must be 48 * page-aligned. It is the responsibility of the linker script to ensure that 49 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 50 * page-aligned addresses. 51 */ 52 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 53 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 54 55 static meminfo_t bl2_el3_tzram_layout; 56 57 enum { 58 BOOT_MODE_RECOVERY = 0, 59 BOOT_MODE_NORMAL, 60 BOOT_MODE_MASK = 1, 61 }; 62 63 /******************************************************************************* 64 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. 65 * Return 0 on success, -1 otherwise. 66 ******************************************************************************/ 67 int plat_hikey_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) 68 { 69 /* Enable MCU SRAM */ 70 hisi_mcu_enable_sram(); 71 72 /* Load MCU binary into SRAM */ 73 hisi_mcu_load_image(scp_bl2_image_info->image_base, 74 scp_bl2_image_info->image_size); 75 /* Let MCU running */ 76 hisi_mcu_start_run(); 77 78 INFO("%s: MCU PC is at 0x%x\n", 79 __func__, mmio_read_32(AO_SC_MCU_SUBSYS_STAT2)); 80 INFO("%s: AO_SC_PERIPH_CLKSTAT4 is 0x%x\n", 81 __func__, mmio_read_32(AO_SC_PERIPH_CLKSTAT4)); 82 return 0; 83 } 84 85 /******************************************************************************* 86 * Gets SPSR for BL32 entry 87 ******************************************************************************/ 88 uint32_t hikey_get_spsr_for_bl32_entry(void) 89 { 90 /* 91 * The Secure Payload Dispatcher service is responsible for 92 * setting the SPSR prior to entry into the BL3-2 image. 93 */ 94 return 0; 95 } 96 97 /******************************************************************************* 98 * Gets SPSR for BL33 entry 99 ******************************************************************************/ 100 #ifndef AARCH32 101 uint32_t hikey_get_spsr_for_bl33_entry(void) 102 { 103 unsigned int mode; 104 uint32_t spsr; 105 106 /* Figure out what mode we enter the non-secure world in */ 107 mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1; 108 109 /* 110 * TODO: Consider the possibility of specifying the SPSR in 111 * the FIP ToC and allowing the platform to have a say as 112 * well. 113 */ 114 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 115 return spsr; 116 } 117 #else 118 uint32_t hikey_get_spsr_for_bl33_entry(void) 119 { 120 unsigned int hyp_status, mode, spsr; 121 122 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 123 124 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 125 126 /* 127 * TODO: Consider the possibility of specifying the SPSR in 128 * the FIP ToC and allowing the platform to have a say as 129 * well. 130 */ 131 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 132 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 133 return spsr; 134 } 135 #endif /* AARCH32 */ 136 137 int hikey_bl2_handle_post_image_load(unsigned int image_id) 138 { 139 int err = 0; 140 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 141 #ifdef SPD_opteed 142 bl_mem_params_node_t *pager_mem_params = NULL; 143 bl_mem_params_node_t *paged_mem_params = NULL; 144 #endif 145 assert(bl_mem_params); 146 147 switch (image_id) { 148 #ifdef AARCH64 149 case BL32_IMAGE_ID: 150 #ifdef SPD_opteed 151 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 152 assert(pager_mem_params); 153 154 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 155 assert(paged_mem_params); 156 157 err = parse_optee_header(&bl_mem_params->ep_info, 158 &pager_mem_params->image_info, 159 &paged_mem_params->image_info); 160 if (err != 0) { 161 WARN("OPTEE header parse error.\n"); 162 } 163 #endif 164 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl32_entry(); 165 break; 166 #endif 167 168 case BL33_IMAGE_ID: 169 /* BL33 expects to receive the primary CPU MPID (through r0) */ 170 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 171 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl33_entry(); 172 break; 173 174 #ifdef SCP_BL2_BASE 175 case SCP_BL2_IMAGE_ID: 176 /* The subsequent handling of SCP_BL2 is platform specific */ 177 err = plat_hikey_bl2_handle_scp_bl2(&bl_mem_params->image_info); 178 if (err) { 179 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 180 } 181 break; 182 #endif 183 } 184 185 return err; 186 } 187 188 /******************************************************************************* 189 * This function can be used by the platforms to update/use image 190 * information for given `image_id`. 191 ******************************************************************************/ 192 int bl2_plat_handle_post_image_load(unsigned int image_id) 193 { 194 return hikey_bl2_handle_post_image_load(image_id); 195 } 196 197 static void reset_dwmmc_clk(void) 198 { 199 unsigned int data; 200 201 /* disable mmc0 bus clock */ 202 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0); 203 do { 204 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 205 } while (data & PERI_CLK0_MMC0); 206 /* enable mmc0 bus clock */ 207 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0); 208 do { 209 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 210 } while (!(data & PERI_CLK0_MMC0)); 211 /* reset mmc0 clock domain */ 212 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0); 213 214 /* bypass mmc0 clock phase */ 215 data = mmio_read_32(PERI_SC_PERIPH_CTRL2); 216 data |= 3; 217 mmio_write_32(PERI_SC_PERIPH_CTRL2, data); 218 219 /* disable low power */ 220 data = mmio_read_32(PERI_SC_PERIPH_CTRL13); 221 data |= 1 << 3; 222 mmio_write_32(PERI_SC_PERIPH_CTRL13, data); 223 do { 224 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 225 } while (!(data & PERI_RST0_MMC0)); 226 227 /* unreset mmc0 clock domain */ 228 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0); 229 do { 230 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 231 } while (data & PERI_RST0_MMC0); 232 } 233 234 static void hikey_boardid_init(void) 235 { 236 u_register_t midr; 237 238 midr = read_midr(); 239 mmio_write_32(MEMORY_AXI_CHIP_ADDR, midr); 240 INFO("[BDID] [%x] midr: 0x%x\n", MEMORY_AXI_CHIP_ADDR, 241 (unsigned int)midr); 242 243 mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR, 0); 244 mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR, 0x2b); 245 246 mmio_write_32(ACPU_ARM64_FLAGA, 0x1234); 247 mmio_write_32(ACPU_ARM64_FLAGB, 0x5678); 248 } 249 250 static void hikey_sd_init(void) 251 { 252 /* switch pinmux to SD */ 253 mmio_write_32(IOMG_SD_CLK, IOMG_MUX_FUNC0); 254 mmio_write_32(IOMG_SD_CMD, IOMG_MUX_FUNC0); 255 mmio_write_32(IOMG_SD_DATA0, IOMG_MUX_FUNC0); 256 mmio_write_32(IOMG_SD_DATA1, IOMG_MUX_FUNC0); 257 mmio_write_32(IOMG_SD_DATA2, IOMG_MUX_FUNC0); 258 mmio_write_32(IOMG_SD_DATA3, IOMG_MUX_FUNC0); 259 260 mmio_write_32(IOCG_SD_CLK, IOCG_INPUT_16MA); 261 mmio_write_32(IOCG_SD_CMD, IOCG_INPUT_12MA); 262 mmio_write_32(IOCG_SD_DATA0, IOCG_INPUT_12MA); 263 mmio_write_32(IOCG_SD_DATA1, IOCG_INPUT_12MA); 264 mmio_write_32(IOCG_SD_DATA2, IOCG_INPUT_12MA); 265 mmio_write_32(IOCG_SD_DATA3, IOCG_INPUT_12MA); 266 267 /* set SD Card detect as nopull */ 268 mmio_write_32(IOCG_GPIO8, 0); 269 } 270 271 static void hikey_jumper_init(void) 272 { 273 /* set jumper detect as nopull */ 274 mmio_write_32(IOCG_GPIO24, 0); 275 /* set jumper detect as GPIO */ 276 mmio_write_32(IOMG_GPIO24, IOMG_MUX_FUNC0); 277 } 278 279 static void hikey_sp804_init(void) 280 { 281 uint32_t data; 282 283 /* select the clock of dual timer0 */ 284 data = mmio_read_32(AO_SC_TIMER_EN0); 285 while (data & 3) { 286 data &= ~3; 287 data |= 3 << 16; 288 mmio_write_32(AO_SC_TIMER_EN0, data); 289 data = mmio_read_32(AO_SC_TIMER_EN0); 290 } 291 /* enable the pclk of dual timer0 */ 292 data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4); 293 while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0)) { 294 mmio_write_32(AO_SC_PERIPH_CLKEN4, PCLK_TIMER1 | PCLK_TIMER0); 295 data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4); 296 } 297 /* reset dual timer0 */ 298 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); 299 mmio_write_32(AO_SC_PERIPH_RSTEN4, PCLK_TIMER1 | PCLK_TIMER0); 300 do { 301 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); 302 } while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0)); 303 /* unreset dual timer0 */ 304 mmio_write_32(AO_SC_PERIPH_RSTDIS4, PCLK_TIMER1 | PCLK_TIMER0); 305 do { 306 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); 307 } while ((data & PCLK_TIMER1) || (data & PCLK_TIMER0)); 308 309 sp804_timer_init(SP804_TIMER0_BASE, 10, 192); 310 } 311 312 static void hikey_gpio_init(void) 313 { 314 pl061_gpio_init(); 315 pl061_gpio_register(GPIO0_BASE, 0); 316 pl061_gpio_register(GPIO1_BASE, 1); 317 pl061_gpio_register(GPIO2_BASE, 2); 318 pl061_gpio_register(GPIO3_BASE, 3); 319 pl061_gpio_register(GPIO4_BASE, 4); 320 pl061_gpio_register(GPIO5_BASE, 5); 321 pl061_gpio_register(GPIO6_BASE, 6); 322 pl061_gpio_register(GPIO7_BASE, 7); 323 pl061_gpio_register(GPIO8_BASE, 8); 324 pl061_gpio_register(GPIO9_BASE, 9); 325 pl061_gpio_register(GPIO10_BASE, 10); 326 pl061_gpio_register(GPIO11_BASE, 11); 327 pl061_gpio_register(GPIO12_BASE, 12); 328 pl061_gpio_register(GPIO13_BASE, 13); 329 pl061_gpio_register(GPIO14_BASE, 14); 330 pl061_gpio_register(GPIO15_BASE, 15); 331 pl061_gpio_register(GPIO16_BASE, 16); 332 pl061_gpio_register(GPIO17_BASE, 17); 333 pl061_gpio_register(GPIO18_BASE, 18); 334 pl061_gpio_register(GPIO19_BASE, 19); 335 336 /* Power on indicator LED (USER_LED1). */ 337 gpio_set_direction(32, GPIO_DIR_OUT); /* LED1 */ 338 gpio_set_value(32, GPIO_LEVEL_HIGH); 339 gpio_set_direction(33, GPIO_DIR_OUT); /* LED2 */ 340 gpio_set_value(33, GPIO_LEVEL_LOW); 341 gpio_set_direction(34, GPIO_DIR_OUT); /* LED3 */ 342 gpio_set_direction(35, GPIO_DIR_OUT); /* LED4 */ 343 } 344 345 static void hikey_pmussi_init(void) 346 { 347 uint32_t data; 348 349 /* Initialize PWR_HOLD GPIO */ 350 gpio_set_direction(0, GPIO_DIR_OUT); 351 gpio_set_value(0, GPIO_LEVEL_LOW); 352 353 /* 354 * After reset, PMUSSI stays in reset mode. 355 * Now make it out of reset. 356 */ 357 mmio_write_32(AO_SC_PERIPH_RSTDIS4, 358 AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N); 359 do { 360 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); 361 } while (data & AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N); 362 363 /* Set PMUSSI clock latency for read operation. */ 364 data = mmio_read_32(AO_SC_MCU_SUBSYS_CTRL3); 365 data &= ~AO_SC_MCU_SUBSYS_CTRL3_RCLK_MASK; 366 data |= AO_SC_MCU_SUBSYS_CTRL3_RCLK_3; 367 mmio_write_32(AO_SC_MCU_SUBSYS_CTRL3, data); 368 369 /* enable PMUSSI clock */ 370 data = AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_CCPU | 371 AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_MCU; 372 mmio_write_32(AO_SC_PERIPH_CLKEN5, data); 373 data = AO_SC_PERIPH_CLKEN4_PCLK_PMUSSI; 374 mmio_write_32(AO_SC_PERIPH_CLKEN4, data); 375 376 gpio_set_value(0, GPIO_LEVEL_HIGH); 377 } 378 379 static void hikey_hi6553_init(void) 380 { 381 uint8_t data; 382 383 mmio_write_8(HI6553_PERI_EN_MARK, 0x1e); 384 mmio_write_8(HI6553_NP_REG_ADJ1, 0); 385 data = DISABLE6_XO_CLK_CONN | DISABLE6_XO_CLK_NFC | 386 DISABLE6_XO_CLK_RF1 | DISABLE6_XO_CLK_RF2; 387 mmio_write_8(HI6553_DISABLE6_XO_CLK, data); 388 389 /* configure BUCK0 & BUCK1 */ 390 mmio_write_8(HI6553_BUCK01_CTRL2, 0x5e); 391 mmio_write_8(HI6553_BUCK0_CTRL7, 0x10); 392 mmio_write_8(HI6553_BUCK1_CTRL7, 0x10); 393 mmio_write_8(HI6553_BUCK0_CTRL5, 0x1e); 394 mmio_write_8(HI6553_BUCK1_CTRL5, 0x1e); 395 mmio_write_8(HI6553_BUCK0_CTRL1, 0xfc); 396 mmio_write_8(HI6553_BUCK1_CTRL1, 0xfc); 397 398 /* configure BUCK2 */ 399 mmio_write_8(HI6553_BUCK2_REG1, 0x4f); 400 mmio_write_8(HI6553_BUCK2_REG5, 0x99); 401 mmio_write_8(HI6553_BUCK2_REG6, 0x45); 402 mdelay(1); 403 mmio_write_8(HI6553_VSET_BUCK2_ADJ, 0x22); 404 mdelay(1); 405 406 /* configure BUCK3 */ 407 mmio_write_8(HI6553_BUCK3_REG3, 0x02); 408 mmio_write_8(HI6553_BUCK3_REG5, 0x99); 409 mmio_write_8(HI6553_BUCK3_REG6, 0x41); 410 mmio_write_8(HI6553_VSET_BUCK3_ADJ, 0x02); 411 mdelay(1); 412 413 /* configure BUCK4 */ 414 mmio_write_8(HI6553_BUCK4_REG2, 0x9a); 415 mmio_write_8(HI6553_BUCK4_REG5, 0x99); 416 mmio_write_8(HI6553_BUCK4_REG6, 0x45); 417 418 /* configure LDO20 */ 419 mmio_write_8(HI6553_LDO20_REG_ADJ, 0x50); 420 421 mmio_write_8(HI6553_NP_REG_CHG, 0x0f); 422 mmio_write_8(HI6553_CLK_TOP0, 0x06); 423 mmio_write_8(HI6553_CLK_TOP3, 0xc0); 424 mmio_write_8(HI6553_CLK_TOP4, 0x00); 425 426 /* configure LDO7 & LDO10 for SD slot */ 427 /* enable LDO7 */ 428 data = mmio_read_8(HI6553_LDO7_REG_ADJ); 429 data = (data & 0xf8) | 0x2; 430 mmio_write_8(HI6553_LDO7_REG_ADJ, data); 431 mdelay(5); 432 mmio_write_8(HI6553_ENABLE2_LDO1_8, 1 << 6); 433 mdelay(5); 434 /* enable LDO10 */ 435 data = mmio_read_8(HI6553_LDO10_REG_ADJ); 436 data = (data & 0xf8) | 0x5; 437 mmio_write_8(HI6553_LDO10_REG_ADJ, data); 438 mdelay(5); 439 mmio_write_8(HI6553_ENABLE3_LDO9_16, 1 << 1); 440 mdelay(5); 441 /* enable LDO15 */ 442 data = mmio_read_8(HI6553_LDO15_REG_ADJ); 443 data = (data & 0xf8) | 0x4; 444 mmio_write_8(HI6553_LDO15_REG_ADJ, data); 445 mmio_write_8(HI6553_ENABLE3_LDO9_16, 1 << 6); 446 mdelay(5); 447 /* enable LDO19 */ 448 data = mmio_read_8(HI6553_LDO19_REG_ADJ); 449 data |= 0x7; 450 mmio_write_8(HI6553_LDO19_REG_ADJ, data); 451 mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 2); 452 mdelay(5); 453 /* enable LDO21 */ 454 data = mmio_read_8(HI6553_LDO21_REG_ADJ); 455 data = (data & 0xf8) | 0x3; 456 mmio_write_8(HI6553_LDO21_REG_ADJ, data); 457 mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 4); 458 mdelay(5); 459 /* enable LDO22 */ 460 data = mmio_read_8(HI6553_LDO22_REG_ADJ); 461 data = (data & 0xf8) | 0x7; 462 mmio_write_8(HI6553_LDO22_REG_ADJ, data); 463 mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 5); 464 mdelay(5); 465 466 /* select 32.764KHz */ 467 mmio_write_8(HI6553_CLK19M2_600_586_EN, 0x01); 468 469 /* Disable vbus_det interrupts */ 470 data = mmio_read_8(HI6553_IRQ2_MASK); 471 data = data | 0x3; 472 mmio_write_8(HI6553_IRQ2_MASK, data); 473 } 474 475 static void init_mmc0_pll(void) 476 { 477 unsigned int data; 478 479 /* select SYSPLL as the source of MMC0 */ 480 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */ 481 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 5 | 1 << 21); 482 do { 483 data = mmio_read_32(PERI_SC_CLK_SEL0); 484 } while (!(data & (1 << 5))); 485 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */ 486 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 29); 487 do { 488 data = mmio_read_32(PERI_SC_CLK_SEL0); 489 } while (data & (1 << 13)); 490 491 mmio_write_32(PERI_SC_PERIPH_CLKEN0, (1 << 0)); 492 do { 493 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 494 } while (!(data & (1 << 0))); 495 496 data = mmio_read_32(PERI_SC_PERIPH_CLKEN12); 497 data |= 1 << 1; 498 mmio_write_32(PERI_SC_PERIPH_CLKEN12, data); 499 500 do { 501 mmio_write_32(PERI_SC_CLKCFG8BIT1, (1 << 7) | 0xb); 502 data = mmio_read_32(PERI_SC_CLKCFG8BIT1); 503 } while ((data & 0xb) != 0xb); 504 } 505 506 static void reset_mmc0_clk(void) 507 { 508 unsigned int data; 509 510 /* disable mmc0 bus clock */ 511 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0); 512 do { 513 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 514 } while (data & PERI_CLK0_MMC0); 515 /* enable mmc0 bus clock */ 516 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0); 517 do { 518 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 519 } while (!(data & PERI_CLK0_MMC0)); 520 /* reset mmc0 clock domain */ 521 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0); 522 523 /* bypass mmc0 clock phase */ 524 data = mmio_read_32(PERI_SC_PERIPH_CTRL2); 525 data |= 3; 526 mmio_write_32(PERI_SC_PERIPH_CTRL2, data); 527 528 /* disable low power */ 529 data = mmio_read_32(PERI_SC_PERIPH_CTRL13); 530 data |= 1 << 3; 531 mmio_write_32(PERI_SC_PERIPH_CTRL13, data); 532 do { 533 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 534 } while (!(data & PERI_RST0_MMC0)); 535 536 /* unreset mmc0 clock domain */ 537 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0); 538 do { 539 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 540 } while (data & PERI_RST0_MMC0); 541 } 542 543 static void init_media_clk(void) 544 { 545 unsigned int data, value; 546 547 data = mmio_read_32(PMCTRL_MEDPLLCTRL); 548 data |= 1; 549 mmio_write_32(PMCTRL_MEDPLLCTRL, data); 550 551 for (;;) { 552 data = mmio_read_32(PMCTRL_MEDPLLCTRL); 553 value = 1 << 28; 554 if ((data & value) == value) 555 break; 556 } 557 558 data = mmio_read_32(PERI_SC_PERIPH_CLKEN12); 559 data = 1 << 10; 560 mmio_write_32(PERI_SC_PERIPH_CLKEN12, data); 561 } 562 563 static void init_mmc1_pll(void) 564 { 565 uint32_t data; 566 567 /* select SYSPLL as the source of MMC1 */ 568 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */ 569 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 11 | 1 << 27); 570 do { 571 data = mmio_read_32(PERI_SC_CLK_SEL0); 572 } while (!(data & (1 << 11))); 573 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */ 574 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 30); 575 do { 576 data = mmio_read_32(PERI_SC_CLK_SEL0); 577 } while (data & (1 << 14)); 578 579 mmio_write_32(PERI_SC_PERIPH_CLKEN0, (1 << 1)); 580 do { 581 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 582 } while (!(data & (1 << 1))); 583 584 data = mmio_read_32(PERI_SC_PERIPH_CLKEN12); 585 data |= 1 << 2; 586 mmio_write_32(PERI_SC_PERIPH_CLKEN12, data); 587 588 do { 589 /* 1.2GHz / 50 = 24MHz */ 590 mmio_write_32(PERI_SC_CLKCFG8BIT2, 0x31 | (1 << 7)); 591 data = mmio_read_32(PERI_SC_CLKCFG8BIT2); 592 } while ((data & 0x31) != 0x31); 593 } 594 595 static void reset_mmc1_clk(void) 596 { 597 unsigned int data; 598 599 /* disable mmc1 bus clock */ 600 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC1); 601 do { 602 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 603 } while (data & PERI_CLK0_MMC1); 604 /* enable mmc1 bus clock */ 605 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC1); 606 do { 607 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 608 } while (!(data & PERI_CLK0_MMC1)); 609 /* reset mmc1 clock domain */ 610 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC1); 611 612 /* bypass mmc1 clock phase */ 613 data = mmio_read_32(PERI_SC_PERIPH_CTRL2); 614 data |= 3 << 2; 615 mmio_write_32(PERI_SC_PERIPH_CTRL2, data); 616 617 /* disable low power */ 618 data = mmio_read_32(PERI_SC_PERIPH_CTRL13); 619 data |= 1 << 4; 620 mmio_write_32(PERI_SC_PERIPH_CTRL13, data); 621 do { 622 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 623 } while (!(data & PERI_RST0_MMC1)); 624 625 /* unreset mmc0 clock domain */ 626 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC1); 627 do { 628 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 629 } while (data & PERI_RST0_MMC1); 630 } 631 632 /* Initialize PLL of both eMMC and SD controllers. */ 633 static void hikey_mmc_pll_init(void) 634 { 635 init_mmc0_pll(); 636 reset_mmc0_clk(); 637 init_media_clk(); 638 639 dsb(); 640 641 init_mmc1_pll(); 642 reset_mmc1_clk(); 643 } 644 645 static void hikey_rtc_init(void) 646 { 647 uint32_t data; 648 649 data = mmio_read_32(AO_SC_PERIPH_CLKEN4); 650 data |= AO_SC_PERIPH_RSTDIS4_RESET_RTC0_N; 651 mmio_write_32(AO_SC_PERIPH_CLKEN4, data); 652 } 653 654 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 655 u_register_t arg3, u_register_t arg4) 656 { 657 /* Initialize the console to provide early debug support */ 658 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 659 /* 660 * Allow BL2 to see the whole Trusted RAM. 661 */ 662 bl2_el3_tzram_layout.total_base = BL2_RW_BASE; 663 bl2_el3_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE; 664 } 665 666 void bl2_el3_plat_arch_setup(void) 667 { 668 hikey_init_mmu_el3(bl2_el3_tzram_layout.total_base, 669 bl2_el3_tzram_layout.total_size, 670 BL2_RO_BASE, 671 BL2_RO_LIMIT, 672 BL2_COHERENT_RAM_BASE, 673 BL2_COHERENT_RAM_LIMIT); 674 } 675 676 void bl2_platform_setup(void) 677 { 678 dw_mmc_params_t params; 679 680 hikey_sp804_init(); 681 hikey_gpio_init(); 682 hikey_pmussi_init(); 683 hikey_hi6553_init(); 684 685 dsb(); 686 hikey_ddr_init(); 687 hikey_security_setup(); 688 689 /* Clear SRAM since it'll be used by MCU right now. */ 690 memset((void *)SRAM_BASE, 0, SRAM_SIZE); 691 clean_dcache_range(SRAM_BASE, SRAM_SIZE); 692 693 hikey_boardid_init(); 694 init_acpu_dvfs(); 695 hikey_rtc_init(); 696 hikey_sd_init(); 697 hikey_jumper_init(); 698 699 hikey_mmc_pll_init(); 700 701 reset_dwmmc_clk(); 702 memset(¶ms, 0, sizeof(dw_mmc_params_t)); 703 params.reg_base = DWMMC0_BASE; 704 params.desc_base = HIKEY_MMC_DESC_BASE; 705 params.desc_size = 1 << 20; 706 params.clk_rate = 24 * 1000 * 1000; 707 params.bus_width = EMMC_BUS_WIDTH_8; 708 params.flags = EMMC_FLAG_CMD23; 709 dw_mmc_init(¶ms); 710 711 hikey_io_setup(); 712 } 713