1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <dw_mmc.h> 13 #include <emmc.h> 14 #include <errno.h> 15 #include <gpio.h> 16 #include <hi6220.h> 17 #include <hi6553.h> 18 #include <mmio.h> 19 #include <pl061_gpio.h> 20 #include <platform.h> 21 #include <platform_def.h> 22 #include <sp804_delay_timer.h> 23 #include <string.h> 24 #include <tbbr/tbbr_img_desc.h> 25 26 #include "../../bl1/bl1_private.h" 27 #include "hikey_def.h" 28 #include "hikey_private.h" 29 30 /* 31 * Declarations of linker defined symbols which will help us find the layout 32 * of trusted RAM 33 */ 34 extern unsigned long __COHERENT_RAM_START__; 35 extern unsigned long __COHERENT_RAM_END__; 36 37 /* 38 * The next 2 constants identify the extents of the coherent memory region. 39 * These addresses are used by the MMU setup code and therefore they must be 40 * page-aligned. It is the responsibility of the linker script to ensure that 41 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 42 * page-aligned addresses. 43 */ 44 #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 45 #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 46 47 /* Data structure which holds the extents of the trusted RAM for BL1 */ 48 static meminfo_t bl1_tzram_layout; 49 50 enum { 51 BOOT_NORMAL = 0, 52 BOOT_USB_DOWNLOAD, 53 BOOT_UART_DOWNLOAD, 54 }; 55 56 meminfo_t *bl1_plat_sec_mem_layout(void) 57 { 58 return &bl1_tzram_layout; 59 } 60 61 /******************************************************************************* 62 * Function that takes a memory layout into which BL2 has been loaded and 63 * populates a new memory layout for BL2 that ensures that BL1's data sections 64 * resident in secure RAM are not visible to BL2. 65 ******************************************************************************/ 66 void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, 67 meminfo_t *bl2_mem_layout) 68 { 69 70 assert(bl1_mem_layout != NULL); 71 assert(bl2_mem_layout != NULL); 72 73 /* 74 * Cannot remove BL1 RW data from the scope of memory visible to BL2 75 * like arm platforms because they overlap in hikey 76 */ 77 bl2_mem_layout->total_base = BL2_BASE; 78 bl2_mem_layout->total_size = BL32_SRAM_LIMIT - BL2_BASE; 79 80 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); 81 } 82 83 /* 84 * Perform any BL1 specific platform actions. 85 */ 86 void bl1_early_platform_setup(void) 87 { 88 /* Initialize the console to provide early debug support */ 89 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 90 91 /* Allow BL1 to see the whole Trusted RAM */ 92 bl1_tzram_layout.total_base = BL1_RW_BASE; 93 bl1_tzram_layout.total_size = BL1_RW_SIZE; 94 95 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 96 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */ 97 } 98 99 /* 100 * Perform the very early platform specific architecture setup here. At the 101 * moment this only does basic initialization. Later architectural setup 102 * (bl1_arch_setup()) does not do anything platform specific. 103 */ 104 void bl1_plat_arch_setup(void) 105 { 106 hikey_init_mmu_el3(bl1_tzram_layout.total_base, 107 bl1_tzram_layout.total_size, 108 BL1_RO_BASE, 109 BL1_RO_LIMIT, 110 BL1_COHERENT_RAM_BASE, 111 BL1_COHERENT_RAM_LIMIT); 112 } 113 114 static void hikey_sp804_init(void) 115 { 116 uint32_t data; 117 118 /* select the clock of dual timer0 */ 119 data = mmio_read_32(AO_SC_TIMER_EN0); 120 while (data & 3) { 121 data &= ~3; 122 data |= 3 << 16; 123 mmio_write_32(AO_SC_TIMER_EN0, data); 124 data = mmio_read_32(AO_SC_TIMER_EN0); 125 } 126 /* enable the pclk of dual timer0 */ 127 data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4); 128 while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0)) { 129 mmio_write_32(AO_SC_PERIPH_CLKEN4, PCLK_TIMER1 | PCLK_TIMER0); 130 data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4); 131 } 132 /* reset dual timer0 */ 133 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); 134 mmio_write_32(AO_SC_PERIPH_RSTEN4, PCLK_TIMER1 | PCLK_TIMER0); 135 do { 136 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); 137 } while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0)); 138 /* unreset dual timer0 */ 139 mmio_write_32(AO_SC_PERIPH_RSTDIS4, PCLK_TIMER1 | PCLK_TIMER0); 140 do { 141 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); 142 } while ((data & PCLK_TIMER1) || (data & PCLK_TIMER0)); 143 144 sp804_timer_init(SP804_TIMER0_BASE, 10, 192); 145 } 146 147 static void hikey_gpio_init(void) 148 { 149 pl061_gpio_init(); 150 pl061_gpio_register(GPIO0_BASE, 0); 151 pl061_gpio_register(GPIO1_BASE, 1); 152 pl061_gpio_register(GPIO2_BASE, 2); 153 pl061_gpio_register(GPIO3_BASE, 3); 154 pl061_gpio_register(GPIO4_BASE, 4); 155 pl061_gpio_register(GPIO5_BASE, 5); 156 pl061_gpio_register(GPIO6_BASE, 6); 157 pl061_gpio_register(GPIO7_BASE, 7); 158 pl061_gpio_register(GPIO8_BASE, 8); 159 pl061_gpio_register(GPIO9_BASE, 9); 160 pl061_gpio_register(GPIO10_BASE, 10); 161 pl061_gpio_register(GPIO11_BASE, 11); 162 pl061_gpio_register(GPIO12_BASE, 12); 163 pl061_gpio_register(GPIO13_BASE, 13); 164 pl061_gpio_register(GPIO14_BASE, 14); 165 pl061_gpio_register(GPIO15_BASE, 15); 166 pl061_gpio_register(GPIO16_BASE, 16); 167 pl061_gpio_register(GPIO17_BASE, 17); 168 pl061_gpio_register(GPIO18_BASE, 18); 169 pl061_gpio_register(GPIO19_BASE, 19); 170 171 /* Power on indicator LED (USER_LED1). */ 172 gpio_set_direction(32, GPIO_DIR_OUT); /* LED1 */ 173 gpio_set_value(32, GPIO_LEVEL_HIGH); 174 gpio_set_direction(33, GPIO_DIR_OUT); /* LED2 */ 175 gpio_set_value(33, GPIO_LEVEL_LOW); 176 gpio_set_direction(34, GPIO_DIR_OUT); /* LED3 */ 177 gpio_set_direction(35, GPIO_DIR_OUT); /* LED4 */ 178 } 179 180 static void hikey_pmussi_init(void) 181 { 182 uint32_t data; 183 184 /* Initialize PWR_HOLD GPIO */ 185 gpio_set_direction(0, GPIO_DIR_OUT); 186 gpio_set_value(0, GPIO_LEVEL_LOW); 187 188 /* 189 * After reset, PMUSSI stays in reset mode. 190 * Now make it out of reset. 191 */ 192 mmio_write_32(AO_SC_PERIPH_RSTDIS4, 193 AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N); 194 do { 195 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); 196 } while (data & AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N); 197 198 /* Set PMUSSI clock latency for read operation. */ 199 data = mmio_read_32(AO_SC_MCU_SUBSYS_CTRL3); 200 data &= ~AO_SC_MCU_SUBSYS_CTRL3_RCLK_MASK; 201 data |= AO_SC_MCU_SUBSYS_CTRL3_RCLK_3; 202 mmio_write_32(AO_SC_MCU_SUBSYS_CTRL3, data); 203 204 /* enable PMUSSI clock */ 205 data = AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_CCPU | 206 AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_MCU; 207 mmio_write_32(AO_SC_PERIPH_CLKEN5, data); 208 data = AO_SC_PERIPH_CLKEN4_PCLK_PMUSSI; 209 mmio_write_32(AO_SC_PERIPH_CLKEN4, data); 210 211 gpio_set_value(0, GPIO_LEVEL_HIGH); 212 } 213 214 static void hikey_hi6553_init(void) 215 { 216 uint8_t data; 217 218 mmio_write_8(HI6553_PERI_EN_MARK, 0x1e); 219 mmio_write_8(HI6553_NP_REG_ADJ1, 0); 220 data = DISABLE6_XO_CLK_CONN | DISABLE6_XO_CLK_NFC | 221 DISABLE6_XO_CLK_RF1 | DISABLE6_XO_CLK_RF2; 222 mmio_write_8(HI6553_DISABLE6_XO_CLK, data); 223 224 /* configure BUCK0 & BUCK1 */ 225 mmio_write_8(HI6553_BUCK01_CTRL2, 0x5e); 226 mmio_write_8(HI6553_BUCK0_CTRL7, 0x10); 227 mmio_write_8(HI6553_BUCK1_CTRL7, 0x10); 228 mmio_write_8(HI6553_BUCK0_CTRL5, 0x1e); 229 mmio_write_8(HI6553_BUCK1_CTRL5, 0x1e); 230 mmio_write_8(HI6553_BUCK0_CTRL1, 0xfc); 231 mmio_write_8(HI6553_BUCK1_CTRL1, 0xfc); 232 233 /* configure BUCK2 */ 234 mmio_write_8(HI6553_BUCK2_REG1, 0x4f); 235 mmio_write_8(HI6553_BUCK2_REG5, 0x99); 236 mmio_write_8(HI6553_BUCK2_REG6, 0x45); 237 mdelay(1); 238 mmio_write_8(HI6553_VSET_BUCK2_ADJ, 0x22); 239 mdelay(1); 240 241 /* configure BUCK3 */ 242 mmio_write_8(HI6553_BUCK3_REG3, 0x02); 243 mmio_write_8(HI6553_BUCK3_REG5, 0x99); 244 mmio_write_8(HI6553_BUCK3_REG6, 0x41); 245 mmio_write_8(HI6553_VSET_BUCK3_ADJ, 0x02); 246 mdelay(1); 247 248 /* configure BUCK4 */ 249 mmio_write_8(HI6553_BUCK4_REG2, 0x9a); 250 mmio_write_8(HI6553_BUCK4_REG5, 0x99); 251 mmio_write_8(HI6553_BUCK4_REG6, 0x45); 252 253 /* configure LDO20 */ 254 mmio_write_8(HI6553_LDO20_REG_ADJ, 0x50); 255 256 mmio_write_8(HI6553_NP_REG_CHG, 0x0f); 257 mmio_write_8(HI6553_CLK_TOP0, 0x06); 258 mmio_write_8(HI6553_CLK_TOP3, 0xc0); 259 mmio_write_8(HI6553_CLK_TOP4, 0x00); 260 261 /* configure LDO7 & LDO10 for SD slot */ 262 /* enable LDO7 */ 263 data = mmio_read_8(HI6553_LDO7_REG_ADJ); 264 data = (data & 0xf8) | 0x2; 265 mmio_write_8(HI6553_LDO7_REG_ADJ, data); 266 mdelay(5); 267 mmio_write_8(HI6553_ENABLE2_LDO1_8, 1 << 6); 268 mdelay(5); 269 /* enable LDO10 */ 270 data = mmio_read_8(HI6553_LDO10_REG_ADJ); 271 data = (data & 0xf8) | 0x5; 272 mmio_write_8(HI6553_LDO10_REG_ADJ, data); 273 mdelay(5); 274 mmio_write_8(HI6553_ENABLE3_LDO9_16, 1 << 1); 275 mdelay(5); 276 /* enable LDO15 */ 277 data = mmio_read_8(HI6553_LDO15_REG_ADJ); 278 data = (data & 0xf8) | 0x4; 279 mmio_write_8(HI6553_LDO15_REG_ADJ, data); 280 mmio_write_8(HI6553_ENABLE3_LDO9_16, 1 << 6); 281 mdelay(5); 282 /* enable LDO19 */ 283 data = mmio_read_8(HI6553_LDO19_REG_ADJ); 284 data |= 0x7; 285 mmio_write_8(HI6553_LDO19_REG_ADJ, data); 286 mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 2); 287 mdelay(5); 288 /* enable LDO21 */ 289 data = mmio_read_8(HI6553_LDO21_REG_ADJ); 290 data = (data & 0xf8) | 0x3; 291 mmio_write_8(HI6553_LDO21_REG_ADJ, data); 292 mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 4); 293 mdelay(5); 294 /* enable LDO22 */ 295 data = mmio_read_8(HI6553_LDO22_REG_ADJ); 296 data = (data & 0xf8) | 0x7; 297 mmio_write_8(HI6553_LDO22_REG_ADJ, data); 298 mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 5); 299 mdelay(5); 300 301 /* select 32.764KHz */ 302 mmio_write_8(HI6553_CLK19M2_600_586_EN, 0x01); 303 304 /* Disable vbus_det interrupts */ 305 data = mmio_read_8(HI6553_IRQ2_MASK); 306 data = data | 0x3; 307 mmio_write_8(HI6553_IRQ2_MASK, data); 308 } 309 310 static void init_mmc0_pll(void) 311 { 312 unsigned int data; 313 314 /* select SYSPLL as the source of MMC0 */ 315 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */ 316 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 5 | 1 << 21); 317 do { 318 data = mmio_read_32(PERI_SC_CLK_SEL0); 319 } while (!(data & (1 << 5))); 320 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */ 321 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 29); 322 do { 323 data = mmio_read_32(PERI_SC_CLK_SEL0); 324 } while (data & (1 << 13)); 325 326 mmio_write_32(PERI_SC_PERIPH_CLKEN0, (1 << 0)); 327 do { 328 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 329 } while (!(data & (1 << 0))); 330 331 data = mmio_read_32(PERI_SC_PERIPH_CLKEN12); 332 data |= 1 << 1; 333 mmio_write_32(PERI_SC_PERIPH_CLKEN12, data); 334 335 do { 336 mmio_write_32(PERI_SC_CLKCFG8BIT1, (1 << 7) | 0xb); 337 data = mmio_read_32(PERI_SC_CLKCFG8BIT1); 338 } while ((data & 0xb) != 0xb); 339 } 340 341 static void reset_mmc0_clk(void) 342 { 343 unsigned int data; 344 345 /* disable mmc0 bus clock */ 346 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0); 347 do { 348 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 349 } while (data & PERI_CLK0_MMC0); 350 /* enable mmc0 bus clock */ 351 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0); 352 do { 353 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 354 } while (!(data & PERI_CLK0_MMC0)); 355 /* reset mmc0 clock domain */ 356 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0); 357 358 /* bypass mmc0 clock phase */ 359 data = mmio_read_32(PERI_SC_PERIPH_CTRL2); 360 data |= 3; 361 mmio_write_32(PERI_SC_PERIPH_CTRL2, data); 362 363 /* disable low power */ 364 data = mmio_read_32(PERI_SC_PERIPH_CTRL13); 365 data |= 1 << 3; 366 mmio_write_32(PERI_SC_PERIPH_CTRL13, data); 367 do { 368 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 369 } while (!(data & PERI_RST0_MMC0)); 370 371 /* unreset mmc0 clock domain */ 372 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0); 373 do { 374 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 375 } while (data & PERI_RST0_MMC0); 376 } 377 378 static void init_media_clk(void) 379 { 380 unsigned int data, value; 381 382 data = mmio_read_32(PMCTRL_MEDPLLCTRL); 383 data |= 1; 384 mmio_write_32(PMCTRL_MEDPLLCTRL, data); 385 386 for (;;) { 387 data = mmio_read_32(PMCTRL_MEDPLLCTRL); 388 value = 1 << 28; 389 if ((data & value) == value) 390 break; 391 } 392 393 data = mmio_read_32(PERI_SC_PERIPH_CLKEN12); 394 data = 1 << 10; 395 mmio_write_32(PERI_SC_PERIPH_CLKEN12, data); 396 } 397 398 static void init_mmc1_pll(void) 399 { 400 uint32_t data; 401 402 /* select SYSPLL as the source of MMC1 */ 403 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */ 404 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 11 | 1 << 27); 405 do { 406 data = mmio_read_32(PERI_SC_CLK_SEL0); 407 } while (!(data & (1 << 11))); 408 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */ 409 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 30); 410 do { 411 data = mmio_read_32(PERI_SC_CLK_SEL0); 412 } while (data & (1 << 14)); 413 414 mmio_write_32(PERI_SC_PERIPH_CLKEN0, (1 << 1)); 415 do { 416 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 417 } while (!(data & (1 << 1))); 418 419 data = mmio_read_32(PERI_SC_PERIPH_CLKEN12); 420 data |= 1 << 2; 421 mmio_write_32(PERI_SC_PERIPH_CLKEN12, data); 422 423 do { 424 /* 1.2GHz / 50 = 24MHz */ 425 mmio_write_32(PERI_SC_CLKCFG8BIT2, 0x31 | (1 << 7)); 426 data = mmio_read_32(PERI_SC_CLKCFG8BIT2); 427 } while ((data & 0x31) != 0x31); 428 } 429 430 static void reset_mmc1_clk(void) 431 { 432 unsigned int data; 433 434 /* disable mmc1 bus clock */ 435 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC1); 436 do { 437 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 438 } while (data & PERI_CLK0_MMC1); 439 /* enable mmc1 bus clock */ 440 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC1); 441 do { 442 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 443 } while (!(data & PERI_CLK0_MMC1)); 444 /* reset mmc1 clock domain */ 445 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC1); 446 447 /* bypass mmc1 clock phase */ 448 data = mmio_read_32(PERI_SC_PERIPH_CTRL2); 449 data |= 3 << 2; 450 mmio_write_32(PERI_SC_PERIPH_CTRL2, data); 451 452 /* disable low power */ 453 data = mmio_read_32(PERI_SC_PERIPH_CTRL13); 454 data |= 1 << 4; 455 mmio_write_32(PERI_SC_PERIPH_CTRL13, data); 456 do { 457 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 458 } while (!(data & PERI_RST0_MMC1)); 459 460 /* unreset mmc0 clock domain */ 461 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC1); 462 do { 463 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 464 } while (data & PERI_RST0_MMC1); 465 } 466 467 /* Initialize PLL of both eMMC and SD controllers. */ 468 static void hikey_mmc_pll_init(void) 469 { 470 init_mmc0_pll(); 471 reset_mmc0_clk(); 472 init_media_clk(); 473 474 dsb(); 475 476 init_mmc1_pll(); 477 reset_mmc1_clk(); 478 } 479 480 static void hikey_rtc_init(void) 481 { 482 uint32_t data; 483 484 data = mmio_read_32(AO_SC_PERIPH_CLKEN4); 485 data |= AO_SC_PERIPH_RSTDIS4_RESET_RTC0_N; 486 mmio_write_32(AO_SC_PERIPH_CLKEN4, data); 487 } 488 489 /* 490 * Function which will perform any remaining platform-specific setup that can 491 * occur after the MMU and data cache have been enabled. 492 */ 493 void bl1_platform_setup(void) 494 { 495 dw_mmc_params_t params; 496 497 assert((HIKEY_BL1_MMC_DESC_BASE >= SRAM_BASE) && 498 ((SRAM_BASE + SRAM_SIZE) >= 499 (HIKEY_BL1_MMC_DATA_BASE + HIKEY_BL1_MMC_DATA_SIZE))); 500 hikey_sp804_init(); 501 hikey_gpio_init(); 502 hikey_pmussi_init(); 503 hikey_hi6553_init(); 504 505 hikey_rtc_init(); 506 507 hikey_mmc_pll_init(); 508 509 memset(¶ms, 0, sizeof(dw_mmc_params_t)); 510 params.reg_base = DWMMC0_BASE; 511 params.desc_base = HIKEY_BL1_MMC_DESC_BASE; 512 params.desc_size = 1 << 20; 513 params.clk_rate = 24 * 1000 * 1000; 514 params.bus_width = EMMC_BUS_WIDTH_8; 515 params.flags = EMMC_FLAG_CMD23; 516 dw_mmc_init(¶ms); 517 518 hikey_io_setup(); 519 } 520 521 /* 522 * The following function checks if Firmware update is needed, 523 * by checking if TOC in FIP image is valid or not. 524 */ 525 unsigned int bl1_plat_get_next_image_id(void) 526 { 527 int32_t boot_mode; 528 unsigned int ret; 529 530 boot_mode = mmio_read_32(ONCHIPROM_PARAM_BASE); 531 switch (boot_mode) { 532 case BOOT_USB_DOWNLOAD: 533 case BOOT_UART_DOWNLOAD: 534 ret = NS_BL1U_IMAGE_ID; 535 break; 536 default: 537 WARN("Invalid boot mode is found:%d\n", boot_mode); 538 panic(); 539 } 540 return ret; 541 } 542 543 image_desc_t *bl1_plat_get_image_desc(unsigned int image_id) 544 { 545 unsigned int index = 0; 546 547 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) { 548 if (bl1_tbbr_image_descs[index].image_id == image_id) 549 return &bl1_tbbr_image_descs[index]; 550 551 index++; 552 } 553 554 return NULL; 555 } 556 557 void bl1_plat_set_ep_info(unsigned int image_id, 558 entry_point_info_t *ep_info) 559 { 560 unsigned int data = 0; 561 562 if (image_id == BL2_IMAGE_ID) 563 panic(); 564 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE); 565 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data)); 566 do { 567 data |= 3 << 20; 568 __asm__ volatile ("msr cpacr_el1, %0" : : "r"(data)); 569 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data)); 570 } while ((data & (3 << 20)) != (3 << 20)); 571 INFO("cpacr_el1:0x%x\n", data); 572 573 ep_info->args.arg0 = 0xffff & read_mpidr(); 574 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 575 DISABLE_ALL_EXCEPTIONS); 576 } 577