1ARM Trusted Firmware Porting Guide 2================================== 3 4 5.. section-numbering:: 6 :suffix: . 7 8.. contents:: 9 10-------------- 11 12Introduction 13------------ 14 15Please note that this document has been updated for the new platform API 16as required by the PSCI v1.0 implementation. Please refer to the 17`Migration Guide`_ for the previous platform API. 18 19Porting the ARM Trusted Firmware to a new platform involves making some 20mandatory and optional modifications for both the cold and warm boot paths. 21Modifications consist of: 22 23- Implementing a platform-specific function or variable, 24- Setting up the execution context in a certain way, or 25- Defining certain constants (for example #defines). 26 27The platform-specific functions and variables are declared in 28`include/plat/common/platform.h`_. The firmware provides a default implementation 29of variables and functions to fulfill the optional requirements. These 30implementations are all weakly defined; they are provided to ease the porting 31effort. Each platform port can override them with its own implementation if the 32default implementation is inadequate. 33 34Platform ports that want to be aligned with standard ARM platforms (for example 35FVP and Juno) may also use `include/plat/arm/common/plat\_arm.h`_ and the 36corresponding source files in ``plat/arm/common/``. These provide standard 37implementations for some of the required platform porting functions. However, 38using these functions requires the platform port to implement additional 39ARM standard platform porting functions. These additional functions are not 40documented here. 41 42Some modifications are common to all Boot Loader (BL) stages. Section 2 43discusses these in detail. The subsequent sections discuss the remaining 44modifications for each BL stage in detail. 45 46This document should be read in conjunction with the ARM Trusted Firmware 47`User Guide`_. 48 49Common modifications 50-------------------- 51 52This section covers the modifications that should be made by the platform for 53each BL stage to correctly port the firmware stack. They are categorized as 54either mandatory or optional. 55 56Common mandatory modifications 57------------------------------ 58 59A platform port must enable the Memory Management Unit (MMU) as well as the 60instruction and data caches for each BL stage. Setting up the translation 61tables is the responsibility of the platform port because memory maps differ 62across platforms. A memory translation library (see ``lib/xlat_tables/``) is 63provided to help in this setup. 64 65Note that although this library supports non-identity mappings, this is intended 66only for re-mapping peripheral physical addresses and allows platforms with high 67I/O addresses to reduce their virtual address space. All other addresses 68corresponding to code and data must currently use an identity mapping. 69 70Also, the only translation granule size supported in Trusted Firmware is 4KB, as 71various parts of the code assume that is the case. It is not possible to switch 72to 16 KB or 64 KB granule sizes at the moment. 73 74In ARM standard platforms, each BL stage configures the MMU in the 75platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 76an identity mapping for all addresses. 77 78If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 79block of identity mapped secure memory with Device-nGnRE attributes aligned to 80page boundary (4K) for each BL stage. All sections which allocate coherent 81memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a 82section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its 83possible for the firmware to place variables in it using the following C code 84directive: 85 86:: 87 88 __section("bakery_lock") 89 90Or alternatively the following assembler code directive: 91 92:: 93 94 .section bakery_lock 95 96The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are 97used to allocate any data structures that are accessed both when a CPU is 98executing with its MMU and caches enabled, and when it's running with its MMU 99and caches disabled. Examples are given below. 100 101The following variables, functions and constants must be defined by the platform 102for the firmware to work correctly. 103 104File : platform\_def.h [mandatory] 105~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 106 107Each platform must ensure that a header file of this name is in the system 108include path with the following constants defined. This may require updating the 109list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. In the ARM development 110platforms, this file is found in ``plat/arm/board/<plat_name>/include/``. 111 112Platform ports may optionally use the file `include/plat/common/common\_def.h`_, 113which provides typical values for some of the constants below. These values are 114likely to be suitable for all platform ports. 115 116Platform ports that want to be aligned with standard ARM platforms (for example 117FVP and Juno) may also use `include/plat/arm/common/arm\_def.h`_, which provides 118standard values for some of the constants below. However, this requires the 119platform port to define additional platform porting constants in 120``platform_def.h``. These additional constants are not documented here. 121 122- **#define : PLATFORM\_LINKER\_FORMAT** 123 124 Defines the linker format used by the platform, for example 125 ``elf64-littleaarch64``. 126 127- **#define : PLATFORM\_LINKER\_ARCH** 128 129 Defines the processor architecture for the linker by the platform, for 130 example ``aarch64``. 131 132- **#define : PLATFORM\_STACK\_SIZE** 133 134 Defines the normal stack memory available to each CPU. This constant is used 135 by `plat/common/aarch64/platform\_mp\_stack.S`_ and 136 `plat/common/aarch64/platform\_up\_stack.S`_. 137 138- **define : CACHE\_WRITEBACK\_GRANULE** 139 140 Defines the size in bits of the largest cache line across all the cache 141 levels in the platform. 142 143- **#define : FIRMWARE\_WELCOME\_STR** 144 145 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 146 function. 147 148- **#define : PLATFORM\_CORE\_COUNT** 149 150 Defines the total number of CPUs implemented by the platform across all 151 clusters in the system. 152 153- **#define : PLAT\_NUM\_PWR\_DOMAINS** 154 155 Defines the total number of nodes in the power domain topology 156 tree at all the power domain levels used by the platform. 157 This macro is used by the PSCI implementation to allocate 158 data structures to represent power domain topology. 159 160- **#define : PLAT\_MAX\_PWR\_LVL** 161 162 Defines the maximum power domain level that the power management operations 163 should apply to. More often, but not always, the power domain level 164 corresponds to affinity level. This macro allows the PSCI implementation 165 to know the highest power domain level that it should consider for power 166 management operations in the system that the platform implements. For 167 example, the Base AEM FVP implements two clusters with a configurable 168 number of CPUs and it reports the maximum power domain level as 1. 169 170- **#define : PLAT\_MAX\_OFF\_STATE** 171 172 Defines the local power state corresponding to the deepest power down 173 possible at every power domain level in the platform. The local power 174 states for each level may be sparsely allocated between 0 and this value 175 with 0 being reserved for the RUN state. The PSCI implementation uses this 176 value to initialize the local power states of the power domain nodes and 177 to specify the requested power state for a PSCI\_CPU\_OFF call. 178 179- **#define : PLAT\_MAX\_RET\_STATE** 180 181 Defines the local power state corresponding to the deepest retention state 182 possible at every power domain level in the platform. This macro should be 183 a value less than PLAT\_MAX\_OFF\_STATE and greater than 0. It is used by the 184 PSCI implementation to distinguish between retention and power down local 185 power states within PSCI\_CPU\_SUSPEND call. 186 187- **#define : PLAT\_MAX\_PWR\_LVL\_STATES** 188 189 Defines the maximum number of local power states per power domain level 190 that the platform supports. The default value of this macro is 2 since 191 most platforms just support a maximum of two local power states at each 192 power domain level (power-down and retention). If the platform needs to 193 account for more local power states, then it must redefine this macro. 194 195 Currently, this macro is used by the Generic PSCI implementation to size 196 the array used for PSCI\_STAT\_COUNT/RESIDENCY accounting. 197 198- **#define : BL1\_RO\_BASE** 199 200 Defines the base address in secure ROM where BL1 originally lives. Must be 201 aligned on a page-size boundary. 202 203- **#define : BL1\_RO\_LIMIT** 204 205 Defines the maximum address in secure ROM that BL1's actual content (i.e. 206 excluding any data section allocated at runtime) can occupy. 207 208- **#define : BL1\_RW\_BASE** 209 210 Defines the base address in secure RAM where BL1's read-write data will live 211 at runtime. Must be aligned on a page-size boundary. 212 213- **#define : BL1\_RW\_LIMIT** 214 215 Defines the maximum address in secure RAM that BL1's read-write data can 216 occupy at runtime. 217 218- **#define : BL2\_BASE** 219 220 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 221 Must be aligned on a page-size boundary. 222 223- **#define : BL2\_LIMIT** 224 225 Defines the maximum address in secure RAM that the BL2 image can occupy. 226 227- **#define : BL31\_BASE** 228 229 Defines the base address in secure RAM where BL2 loads the BL31 binary 230 image. Must be aligned on a page-size boundary. 231 232- **#define : BL31\_LIMIT** 233 234 Defines the maximum address in secure RAM that the BL31 image can occupy. 235 236For every image, the platform must define individual identifiers that will be 237used by BL1 or BL2 to load the corresponding image into memory from non-volatile 238storage. For the sake of performance, integer numbers will be used as 239identifiers. The platform will use those identifiers to return the relevant 240information about the image to be loaded (file handler, load address, 241authentication information, etc.). The following image identifiers are 242mandatory: 243 244- **#define : BL2\_IMAGE\_ID** 245 246 BL2 image identifier, used by BL1 to load BL2. 247 248- **#define : BL31\_IMAGE\_ID** 249 250 BL31 image identifier, used by BL2 to load BL31. 251 252- **#define : BL33\_IMAGE\_ID** 253 254 BL33 image identifier, used by BL2 to load BL33. 255 256If Trusted Board Boot is enabled, the following certificate identifiers must 257also be defined: 258 259- **#define : TRUSTED\_BOOT\_FW\_CERT\_ID** 260 261 BL2 content certificate identifier, used by BL1 to load the BL2 content 262 certificate. 263 264- **#define : TRUSTED\_KEY\_CERT\_ID** 265 266 Trusted key certificate identifier, used by BL2 to load the trusted key 267 certificate. 268 269- **#define : SOC\_FW\_KEY\_CERT\_ID** 270 271 BL31 key certificate identifier, used by BL2 to load the BL31 key 272 certificate. 273 274- **#define : SOC\_FW\_CONTENT\_CERT\_ID** 275 276 BL31 content certificate identifier, used by BL2 to load the BL31 content 277 certificate. 278 279- **#define : NON\_TRUSTED\_FW\_KEY\_CERT\_ID** 280 281 BL33 key certificate identifier, used by BL2 to load the BL33 key 282 certificate. 283 284- **#define : NON\_TRUSTED\_FW\_CONTENT\_CERT\_ID** 285 286 BL33 content certificate identifier, used by BL2 to load the BL33 content 287 certificate. 288 289- **#define : FWU\_CERT\_ID** 290 291 Firmware Update (FWU) certificate identifier, used by NS\_BL1U to load the 292 FWU content certificate. 293 294- **#define : PLAT\_CRYPTOCELL\_BASE** 295 296 This defines the base address of ARM® TrustZone® CryptoCell and must be 297 defined if CryptoCell crypto driver is used for Trusted Board Boot. For 298 capable ARM platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is 299 set. 300 301If the AP Firmware Updater Configuration image, BL2U is used, the following 302must also be defined: 303 304- **#define : BL2U\_BASE** 305 306 Defines the base address in secure memory where BL1 copies the BL2U binary 307 image. Must be aligned on a page-size boundary. 308 309- **#define : BL2U\_LIMIT** 310 311 Defines the maximum address in secure memory that the BL2U image can occupy. 312 313- **#define : BL2U\_IMAGE\_ID** 314 315 BL2U image identifier, used by BL1 to fetch an image descriptor 316 corresponding to BL2U. 317 318If the SCP Firmware Update Configuration Image, SCP\_BL2U is used, the following 319must also be defined: 320 321- **#define : SCP\_BL2U\_IMAGE\_ID** 322 323 SCP\_BL2U image identifier, used by BL1 to fetch an image descriptor 324 corresponding to SCP\_BL2U. 325 NOTE: TF does not provide source code for this image. 326 327If the Non-Secure Firmware Updater ROM, NS\_BL1U is used, the following must 328also be defined: 329 330- **#define : NS\_BL1U\_BASE** 331 332 Defines the base address in non-secure ROM where NS\_BL1U executes. 333 Must be aligned on a page-size boundary. 334 NOTE: TF does not provide source code for this image. 335 336- **#define : NS\_BL1U\_IMAGE\_ID** 337 338 NS\_BL1U image identifier, used by BL1 to fetch an image descriptor 339 corresponding to NS\_BL1U. 340 341If the Non-Secure Firmware Updater, NS\_BL2U is used, the following must also 342be defined: 343 344- **#define : NS\_BL2U\_BASE** 345 346 Defines the base address in non-secure memory where NS\_BL2U executes. 347 Must be aligned on a page-size boundary. 348 NOTE: TF does not provide source code for this image. 349 350- **#define : NS\_BL2U\_IMAGE\_ID** 351 352 NS\_BL2U image identifier, used by BL1 to fetch an image descriptor 353 corresponding to NS\_BL2U. 354 355For the the Firmware update capability of TRUSTED BOARD BOOT, the following 356macros may also be defined: 357 358- **#define : PLAT\_FWU\_MAX\_SIMULTANEOUS\_IMAGES** 359 360 Total number of images that can be loaded simultaneously. If the platform 361 doesn't specify any value, it defaults to 10. 362 363If a SCP\_BL2 image is supported by the platform, the following constants must 364also be defined: 365 366- **#define : SCP\_BL2\_IMAGE\_ID** 367 368 SCP\_BL2 image identifier, used by BL2 to load SCP\_BL2 into secure memory 369 from platform storage before being transfered to the SCP. 370 371- **#define : SCP\_FW\_KEY\_CERT\_ID** 372 373 SCP\_BL2 key certificate identifier, used by BL2 to load the SCP\_BL2 key 374 certificate (mandatory when Trusted Board Boot is enabled). 375 376- **#define : SCP\_FW\_CONTENT\_CERT\_ID** 377 378 SCP\_BL2 content certificate identifier, used by BL2 to load the SCP\_BL2 379 content certificate (mandatory when Trusted Board Boot is enabled). 380 381If a BL32 image is supported by the platform, the following constants must 382also be defined: 383 384- **#define : BL32\_IMAGE\_ID** 385 386 BL32 image identifier, used by BL2 to load BL32. 387 388- **#define : TRUSTED\_OS\_FW\_KEY\_CERT\_ID** 389 390 BL32 key certificate identifier, used by BL2 to load the BL32 key 391 certificate (mandatory when Trusted Board Boot is enabled). 392 393- **#define : TRUSTED\_OS\_FW\_CONTENT\_CERT\_ID** 394 395 BL32 content certificate identifier, used by BL2 to load the BL32 content 396 certificate (mandatory when Trusted Board Boot is enabled). 397 398- **#define : BL32\_BASE** 399 400 Defines the base address in secure memory where BL2 loads the BL32 binary 401 image. Must be aligned on a page-size boundary. 402 403- **#define : BL32\_LIMIT** 404 405 Defines the maximum address that the BL32 image can occupy. 406 407If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 408platform, the following constants must also be defined: 409 410- **#define : TSP\_SEC\_MEM\_BASE** 411 412 Defines the base address of the secure memory used by the TSP image on the 413 platform. This must be at the same address or below ``BL32_BASE``. 414 415- **#define : TSP\_SEC\_MEM\_SIZE** 416 417 Defines the size of the secure memory used by the BL32 image on the 418 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully accomodate 419 the memory required by the BL32 image, defined by ``BL32_BASE`` and 420 ``BL32_LIMIT``. 421 422- **#define : TSP\_IRQ\_SEC\_PHY\_TIMER** 423 424 Defines the ID of the secure physical generic timer interrupt used by the 425 TSP's interrupt handling code. 426 427If the platform port uses the translation table library code, the following 428constants must also be defined: 429 430- **#define : PLAT\_XLAT\_TABLES\_DYNAMIC** 431 432 Optional flag that can be set per-image to enable the dynamic allocation of 433 regions even when the MMU is enabled. If not defined, only static 434 functionality will be available, if defined and set to 1 it will also 435 include the dynamic functionality. 436 437- **#define : MAX\_XLAT\_TABLES** 438 439 Defines the maximum number of translation tables that are allocated by the 440 translation table library code. To minimize the amount of runtime memory 441 used, choose the smallest value needed to map the required virtual addresses 442 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 443 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 444 as well. 445 446- **#define : MAX\_MMAP\_REGIONS** 447 448 Defines the maximum number of regions that are allocated by the translation 449 table library code. A region consists of physical base address, virtual base 450 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 451 defined in the ``mmap_region_t`` structure. The platform defines the regions 452 that should be mapped. Then, the translation table library will create the 453 corresponding tables and descriptors at runtime. To minimize the amount of 454 runtime memory used, choose the smallest value needed to register the 455 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 456 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 457 the dynamic regions as well. 458 459- **#define : ADDR\_SPACE\_SIZE** 460 461 Defines the total size of the address space in bytes. For example, for a 32 462 bit address space, this value should be ``(1ULL << 32)``. This definition is 463 now deprecated, platforms should use ``PLAT_PHY_ADDR_SPACE_SIZE`` and 464 ``PLAT_VIRT_ADDR_SPACE_SIZE`` instead. 465 466- **#define : PLAT\_VIRT\_ADDR\_SPACE\_SIZE** 467 468 Defines the total size of the virtual address space in bytes. For example, 469 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. 470 471- **#define : PLAT\_PHY\_ADDR\_SPACE\_SIZE** 472 473 Defines the total size of the physical address space in bytes. For example, 474 for a 32 bit physical address space, this value should be ``(1ULL << 32)``. 475 476If the platform port uses the IO storage framework, the following constants 477must also be defined: 478 479- **#define : MAX\_IO\_DEVICES** 480 481 Defines the maximum number of registered IO devices. Attempting to register 482 more devices than this value using ``io_register_device()`` will fail with 483 -ENOMEM. 484 485- **#define : MAX\_IO\_HANDLES** 486 487 Defines the maximum number of open IO handles. Attempting to open more IO 488 entities than this value using ``io_open()`` will fail with -ENOMEM. 489 490- **#define : MAX\_IO\_BLOCK\_DEVICES** 491 492 Defines the maximum number of registered IO block devices. Attempting to 493 register more devices this value using ``io_dev_open()`` will fail 494 with -ENOMEM. MAX\_IO\_BLOCK\_DEVICES should be less than MAX\_IO\_DEVICES. 495 With this macro, multiple block devices could be supported at the same 496 time. 497 498If the platform needs to allocate data within the per-cpu data framework in 499BL31, it should define the following macro. Currently this is only required if 500the platform decides not to use the coherent memory section by undefining the 501``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 502required memory within the the per-cpu data to minimize wastage. 503 504- **#define : PLAT\_PCPU\_DATA\_SIZE** 505 506 Defines the memory (in bytes) to be reserved within the per-cpu data 507 structure for use by the platform layer. 508 509The following constants are optional. They should be defined when the platform 510memory layout implies some image overlaying like in ARM standard platforms. 511 512- **#define : BL31\_PROGBITS\_LIMIT** 513 514 Defines the maximum address in secure RAM that the BL31's progbits sections 515 can occupy. 516 517- **#define : TSP\_PROGBITS\_LIMIT** 518 519 Defines the maximum address that the TSP's progbits sections can occupy. 520 521If the platform port uses the PL061 GPIO driver, the following constant may 522optionally be defined: 523 524- **PLAT\_PL061\_MAX\_GPIOS** 525 Maximum number of GPIOs required by the platform. This allows control how 526 much memory is allocated for PL061 GPIO controllers. The default value is 527 528 #. $(eval $(call add\_define,PLAT\_PL061\_MAX\_GPIOS)) 529 530If the platform port uses the partition driver, the following constant may 531optionally be defined: 532 533- **PLAT\_PARTITION\_MAX\_ENTRIES** 534 Maximum number of partition entries required by the platform. This allows 535 control how much memory is allocated for partition entries. The default 536 value is 128. 537 `For example, define the build flag in platform.mk`_: 538 PLAT\_PARTITION\_MAX\_ENTRIES := 12 539 $(eval $(call add\_define,PLAT\_PARTITION\_MAX\_ENTRIES)) 540 541The following constant is optional. It should be defined to override the default 542behaviour of the ``assert()`` function (for example, to save memory). 543 544- **PLAT\_LOG\_LEVEL\_ASSERT** 545 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 546 ``assert()`` prints the name of the file, the line number and the asserted 547 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 548 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 549 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 550 defined, it defaults to ``LOG_LEVEL``. 551 552If the platform port uses the Activity Monitor Unit, the following constants 553may be defined: 554 555- **PLAT\_AMU\_GROUP1\_COUNTERS\_MASK** 556 This mask reflects the set of group counters that should be enabled. The 557 maximum number of group 1 counters supported by AMUv1 is 16 so the mask 558 can be at most 0xffff. If the platform does not define this mask, no group 1 559 counters are enabled. If the platform defines this mask, the following 560 constant needs to also be defined. 561 562- **PLAT\_AMU\_GROUP1\_NR\_COUNTERS** 563 This value is used to allocate an array to save and restore the counters 564 specified by ``PLAT_AMU_GROUP1_COUNTERS_MASK`` on CPU suspend. 565 This value should be equal to the highest bit position set in the 566 mask, plus 1. The maximum number of group 1 counters in AMUv1 is 16. 567 568File : plat\_macros.S [mandatory] 569~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 570 571Each platform must ensure a file of this name is in the system include path with 572the following macro defined. In the ARM development platforms, this file is 573found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 574 575- **Macro : plat\_crash\_print\_regs** 576 577 This macro allows the crash reporting routine to print relevant platform 578 registers in case of an unhandled exception in BL31. This aids in debugging 579 and this macro can be defined to be empty in case register reporting is not 580 desired. 581 582 For instance, GIC or interconnect registers may be helpful for 583 troubleshooting. 584 585Handling Reset 586-------------- 587 588BL1 by default implements the reset vector where execution starts from a cold 589or warm boot. BL31 can be optionally set as a reset vector using the 590``RESET_TO_BL31`` make variable. 591 592For each CPU, the reset vector code is responsible for the following tasks: 593 594#. Distinguishing between a cold boot and a warm boot. 595 596#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 597 the CPU is placed in a platform-specific state until the primary CPU 598 performs the necessary steps to remove it from this state. 599 600#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 601 specific address in the BL31 image in the same processor mode as it was 602 when released from reset. 603 604The following functions need to be implemented by the platform port to enable 605reset vector code to perform the above tasks. 606 607Function : plat\_get\_my\_entrypoint() [mandatory when PROGRAMMABLE\_RESET\_ADDRESS == 0] 608~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 609 610:: 611 612 Argument : void 613 Return : uintptr_t 614 615This function is called with the MMU and caches disabled 616(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 617distinguishing between a warm and cold reset for the current CPU using 618platform-specific means. If it's a warm reset, then it returns the warm 619reset entrypoint point provided to ``plat_setup_psci_ops()`` during 620BL31 initialization. If it's a cold reset then this function must return zero. 621 622This function does not follow the Procedure Call Standard used by the 623Application Binary Interface for the ARM 64-bit architecture. The caller should 624not assume that callee saved registers are preserved across a call to this 625function. 626 627This function fulfills requirement 1 and 3 listed above. 628 629Note that for platforms that support programming the reset address, it is 630expected that a CPU will start executing code directly at the right address, 631both on a cold and warm reset. In this case, there is no need to identify the 632type of reset nor to query the warm reset entrypoint. Therefore, implementing 633this function is not required on such platforms. 634 635Function : plat\_secondary\_cold\_boot\_setup() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0] 636~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 637 638:: 639 640 Argument : void 641 642This function is called with the MMU and data caches disabled. It is responsible 643for placing the executing secondary CPU in a platform-specific state until the 644primary CPU performs the necessary actions to bring it out of that state and 645allow entry into the OS. This function must not return. 646 647In the ARM FVP port, when using the normal boot flow, each secondary CPU powers 648itself off. The primary CPU is responsible for powering up the secondary CPUs 649when normal world software requires them. When booting an EL3 payload instead, 650they stay powered on and are put in a holding pen until their mailbox gets 651populated. 652 653This function fulfills requirement 2 above. 654 655Note that for platforms that can't release secondary CPUs out of reset, only the 656primary CPU will execute the cold boot code. Therefore, implementing this 657function is not required on such platforms. 658 659Function : plat\_is\_my\_cpu\_primary() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0] 660~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 661 662:: 663 664 Argument : void 665 Return : unsigned int 666 667This function identifies whether the current CPU is the primary CPU or a 668secondary CPU. A return value of zero indicates that the CPU is not the 669primary CPU, while a non-zero return value indicates that the CPU is the 670primary CPU. 671 672Note that for platforms that can't release secondary CPUs out of reset, only the 673primary CPU will execute the cold boot code. Therefore, there is no need to 674distinguish between primary and secondary CPUs and implementing this function is 675not required. 676 677Function : platform\_mem\_init() [mandatory] 678~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 679 680:: 681 682 Argument : void 683 Return : void 684 685This function is called before any access to data is made by the firmware, in 686order to carry out any essential memory initialization. 687 688Function: plat\_get\_rotpk\_info() 689~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 690 691:: 692 693 Argument : void *, void **, unsigned int *, unsigned int * 694 Return : int 695 696This function is mandatory when Trusted Board Boot is enabled. It returns a 697pointer to the ROTPK stored in the platform (or a hash of it) and its length. 698The ROTPK must be encoded in DER format according to the following ASN.1 699structure: 700 701:: 702 703 AlgorithmIdentifier ::= SEQUENCE { 704 algorithm OBJECT IDENTIFIER, 705 parameters ANY DEFINED BY algorithm OPTIONAL 706 } 707 708 SubjectPublicKeyInfo ::= SEQUENCE { 709 algorithm AlgorithmIdentifier, 710 subjectPublicKey BIT STRING 711 } 712 713In case the function returns a hash of the key: 714 715:: 716 717 DigestInfo ::= SEQUENCE { 718 digestAlgorithm AlgorithmIdentifier, 719 digest OCTET STRING 720 } 721 722The function returns 0 on success. Any other value is treated as error by the 723Trusted Board Boot. The function also reports extra information related 724to the ROTPK in the flags parameter: 725 726:: 727 728 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 729 hash. 730 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 731 verification while the platform ROTPK is not deployed. 732 When this flag is set, the function does not need to 733 return a platform ROTPK, and the authentication 734 framework uses the ROTPK in the certificate without 735 verifying it against the platform value. This flag 736 must not be used in a deployed production environment. 737 738Function: plat\_get\_nv\_ctr() 739~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 740 741:: 742 743 Argument : void *, unsigned int * 744 Return : int 745 746This function is mandatory when Trusted Board Boot is enabled. It returns the 747non-volatile counter value stored in the platform in the second argument. The 748cookie in the first argument may be used to select the counter in case the 749platform provides more than one (for example, on platforms that use the default 750TBBR CoT, the cookie will correspond to the OID values defined in 751TRUSTED\_FW\_NVCOUNTER\_OID or NON\_TRUSTED\_FW\_NVCOUNTER\_OID). 752 753The function returns 0 on success. Any other value means the counter value could 754not be retrieved from the platform. 755 756Function: plat\_set\_nv\_ctr() 757~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 758 759:: 760 761 Argument : void *, unsigned int 762 Return : int 763 764This function is mandatory when Trusted Board Boot is enabled. It sets a new 765counter value in the platform. The cookie in the first argument may be used to 766select the counter (as explained in plat\_get\_nv\_ctr()). The second argument is 767the updated counter value to be written to the NV counter. 768 769The function returns 0 on success. Any other value means the counter value could 770not be updated. 771 772Function: plat\_set\_nv\_ctr2() 773~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 774 775:: 776 777 Argument : void *, const auth_img_desc_t *, unsigned int 778 Return : int 779 780This function is optional when Trusted Board Boot is enabled. If this 781interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 782first argument passed is a cookie and is typically used to 783differentiate between a Non Trusted NV Counter and a Trusted NV 784Counter. The second argument is a pointer to an authentication image 785descriptor and may be used to decide if the counter is allowed to be 786updated or not. The third argument is the updated counter value to 787be written to the NV counter. 788 789The function returns 0 on success. Any other value means the counter value 790either could not be updated or the authentication image descriptor indicates 791that it is not allowed to be updated. 792 793Common mandatory function modifications 794--------------------------------------- 795 796The following functions are mandatory functions which need to be implemented 797by the platform port. 798 799Function : plat\_my\_core\_pos() 800~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 801 802:: 803 804 Argument : void 805 Return : unsigned int 806 807This funtion returns the index of the calling CPU which is used as a 808CPU-specific linear index into blocks of memory (for example while allocating 809per-CPU stacks). This function will be invoked very early in the 810initialization sequence which mandates that this function should be 811implemented in assembly and should not rely on the avalability of a C 812runtime environment. This function can clobber x0 - x8 and must preserve 813x9 - x29. 814 815This function plays a crucial role in the power domain topology framework in 816PSCI and details of this can be found in `Power Domain Topology Design`_. 817 818Function : plat\_core\_pos\_by\_mpidr() 819~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 820 821:: 822 823 Argument : u_register_t 824 Return : int 825 826This function validates the ``MPIDR`` of a CPU and converts it to an index, 827which can be used as a CPU-specific linear index into blocks of memory. In 828case the ``MPIDR`` is invalid, this function returns -1. This function will only 829be invoked by BL31 after the power domain topology is initialized and can 830utilize the C runtime environment. For further details about how ARM Trusted 831Firmware represents the power domain topology and how this relates to the 832linear CPU index, please refer `Power Domain Topology Design`_. 833 834Common optional modifications 835----------------------------- 836 837The following are helper functions implemented by the firmware that perform 838common platform-specific tasks. A platform may choose to override these 839definitions. 840 841Function : plat\_set\_my\_stack() 842~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 843 844:: 845 846 Argument : void 847 Return : void 848 849This function sets the current stack pointer to the normal memory stack that 850has been allocated for the current CPU. For BL images that only require a 851stack for the primary CPU, the UP version of the function is used. The size 852of the stack allocated to each CPU is specified by the platform defined 853constant ``PLATFORM_STACK_SIZE``. 854 855Common implementations of this function for the UP and MP BL images are 856provided in `plat/common/aarch64/platform\_up\_stack.S`_ and 857`plat/common/aarch64/platform\_mp\_stack.S`_ 858 859Function : plat\_get\_my\_stack() 860~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 861 862:: 863 864 Argument : void 865 Return : uintptr_t 866 867This function returns the base address of the normal memory stack that 868has been allocated for the current CPU. For BL images that only require a 869stack for the primary CPU, the UP version of the function is used. The size 870of the stack allocated to each CPU is specified by the platform defined 871constant ``PLATFORM_STACK_SIZE``. 872 873Common implementations of this function for the UP and MP BL images are 874provided in `plat/common/aarch64/platform\_up\_stack.S`_ and 875`plat/common/aarch64/platform\_mp\_stack.S`_ 876 877Function : plat\_report\_exception() 878~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 879 880:: 881 882 Argument : unsigned int 883 Return : void 884 885A platform may need to report various information about its status when an 886exception is taken, for example the current exception level, the CPU security 887state (secure/non-secure), the exception type, and so on. This function is 888called in the following circumstances: 889 890- In BL1, whenever an exception is taken. 891- In BL2, whenever an exception is taken. 892 893The default implementation doesn't do anything, to avoid making assumptions 894about the way the platform displays its status information. 895 896For AArch64, this function receives the exception type as its argument. 897Possible values for exceptions types are listed in the 898`include/common/bl\_common.h`_ header file. Note that these constants are not 899related to any architectural exception code; they are just an ARM Trusted 900Firmware convention. 901 902For AArch32, this function receives the exception mode as its argument. 903Possible values for exception modes are listed in the 904`include/lib/aarch32/arch.h`_ header file. 905 906Function : plat\_reset\_handler() 907~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 908 909:: 910 911 Argument : void 912 Return : void 913 914A platform may need to do additional initialization after reset. This function 915allows the platform to do the platform specific intializations. Platform 916specific errata workarounds could also be implemented here. The api should 917preserve the values of callee saved registers x19 to x29. 918 919The default implementation doesn't do anything. If a platform needs to override 920the default implementation, refer to the `Firmware Design`_ for general 921guidelines. 922 923Function : plat\_disable\_acp() 924~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 925 926:: 927 928 Argument : void 929 Return : void 930 931This api allows a platform to disable the Accelerator Coherency Port (if 932present) during a cluster power down sequence. The default weak implementation 933doesn't do anything. Since this api is called during the power down sequence, 934it has restrictions for stack usage and it can use the registers x0 - x17 as 935scratch registers. It should preserve the value in x18 register as it is used 936by the caller to store the return address. 937 938Function : plat\_error\_handler() 939~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 940 941:: 942 943 Argument : int 944 Return : void 945 946This API is called when the generic code encounters an error situation from 947which it cannot continue. It allows the platform to perform error reporting or 948recovery actions (for example, reset the system). This function must not return. 949 950The parameter indicates the type of error using standard codes from ``errno.h``. 951Possible errors reported by the generic code are: 952 953- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 954 Board Boot is enabled) 955- ``-ENOENT``: the requested image or certificate could not be found or an IO 956 error was detected 957- ``-ENOMEM``: resources exhausted. Trusted Firmware does not use dynamic 958 memory, so this error is usually an indication of an incorrect array size 959 960The default implementation simply spins. 961 962Function : plat\_panic\_handler() 963~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 964 965:: 966 967 Argument : void 968 Return : void 969 970This API is called when the generic code encounters an unexpected error 971situation from which it cannot recover. This function must not return, 972and must be implemented in assembly because it may be called before the C 973environment is initialized. 974 975Note: The address from where it was called is stored in x30 (Link Register). 976The default implementation simply spins. 977 978Function : plat\_get\_bl\_image\_load\_info() 979~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 980 981:: 982 983 Argument : void 984 Return : bl_load_info_t * 985 986This function returns pointer to the list of images that the platform has 987populated to load. This function is currently invoked in BL2 to load the 988BL3xx images, when LOAD\_IMAGE\_V2 is enabled. 989 990Function : plat\_get\_next\_bl\_params() 991~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 992 993:: 994 995 Argument : void 996 Return : bl_params_t * 997 998This function returns a pointer to the shared memory that the platform has 999kept aside to pass trusted firmware related information that next BL image 1000needs. This function is currently invoked in BL2 to pass this information to 1001the next BL image, when LOAD\_IMAGE\_V2 is enabled. 1002 1003Function : plat\_get\_stack\_protector\_canary() 1004~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1005 1006:: 1007 1008 Argument : void 1009 Return : u_register_t 1010 1011This function returns a random value that is used to initialize the canary used 1012when the stack protector is enabled with ENABLE\_STACK\_PROTECTOR. A predictable 1013value will weaken the protection as the attacker could easily write the right 1014value as part of the attack most of the time. Therefore, it should return a 1015true random number. 1016 1017Note: For the protection to be effective, the global data need to be placed at 1018a lower address than the stack bases. Failure to do so would allow an attacker 1019to overwrite the canary as part of the stack buffer overflow attack. 1020 1021Function : plat\_flush\_next\_bl\_params() 1022~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1023 1024:: 1025 1026 Argument : void 1027 Return : void 1028 1029This function flushes to main memory all the image params that are passed to 1030next image. This function is currently invoked in BL2 to flush this information 1031to the next BL image, when LOAD\_IMAGE\_V2 is enabled. 1032 1033Function : plat\_log\_get\_prefix() 1034~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1035 1036:: 1037 1038 Argument : unsigned int 1039 Return : const char * 1040 1041This function defines the prefix string corresponding to the `log_level` to be 1042prepended to all the log output from ARM Trusted Firmware. The `log_level` 1043(argument) will correspond to one of the standard log levels defined in 1044debug.h. The platform can override the common implementation to define a 1045different prefix string for the log output. The implementation should be 1046robust to future changes that increase the number of log levels. 1047 1048Modifications specific to a Boot Loader stage 1049--------------------------------------------- 1050 1051Boot Loader Stage 1 (BL1) 1052------------------------- 1053 1054BL1 implements the reset vector where execution starts from after a cold or 1055warm boot. For each CPU, BL1 is responsible for the following tasks: 1056 1057#. Handling the reset as described in section 2.2 1058 1059#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1060 only this CPU executes the remaining BL1 code, including loading and passing 1061 control to the BL2 stage. 1062 1063#. Identifying and starting the Firmware Update process (if required). 1064 1065#. Loading the BL2 image from non-volatile storage into secure memory at the 1066 address specified by the platform defined constant ``BL2_BASE``. 1067 1068#. Populating a ``meminfo`` structure with the following information in memory, 1069 accessible by BL2 immediately upon entry. 1070 1071 :: 1072 1073 meminfo.total_base = Base address of secure RAM visible to BL2 1074 meminfo.total_size = Size of secure RAM visible to BL2 1075 meminfo.free_base = Base address of secure RAM available for 1076 allocation to BL2 1077 meminfo.free_size = Size of secure RAM available for allocation to BL2 1078 1079 By default, BL1 places this ``meminfo`` structure at the beginning of the 1080 free memory available for its use. Since BL1 cannot allocate memory 1081 dynamically at the moment, its free memory will be available for BL2's use 1082 as-is. However, this means that BL2 must read the ``meminfo`` structure 1083 before it starts using its free memory (this is discussed in Section 3.2). 1084 1085 It is possible for the platform to decide where it wants to place the 1086 ``meminfo`` structure for BL2 or restrict the amount of memory visible to 1087 BL2 by overriding the weak default implementation of 1088 ``bl1_plat_handle_post_image_load`` API. 1089 1090The following functions need to be implemented by the platform port to enable 1091BL1 to perform the above tasks. 1092 1093Function : bl1\_early\_platform\_setup() [mandatory] 1094~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1095 1096:: 1097 1098 Argument : void 1099 Return : void 1100 1101This function executes with the MMU and data caches disabled. It is only called 1102by the primary CPU. 1103 1104On ARM standard platforms, this function: 1105 1106- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1107 1108- Initializes a UART (PL011 console), which enables access to the ``printf`` 1109 family of functions in BL1. 1110 1111- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1112 the CCI slave interface corresponding to the cluster that includes the 1113 primary CPU. 1114 1115Function : bl1\_plat\_arch\_setup() [mandatory] 1116~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1117 1118:: 1119 1120 Argument : void 1121 Return : void 1122 1123This function performs any platform-specific and architectural setup that the 1124platform requires. Platform-specific setup might include configuration of 1125memory controllers and the interconnect. 1126 1127In ARM standard platforms, this function enables the MMU. 1128 1129This function helps fulfill requirement 2 above. 1130 1131Function : bl1\_platform\_setup() [mandatory] 1132~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1133 1134:: 1135 1136 Argument : void 1137 Return : void 1138 1139This function executes with the MMU and data caches enabled. It is responsible 1140for performing any remaining platform-specific setup that can occur after the 1141MMU and data cache have been enabled. 1142 1143if support for multiple boot sources is required, it initializes the boot 1144sequence used by plat\_try\_next\_boot\_source(). 1145 1146In ARM standard platforms, this function initializes the storage abstraction 1147layer used to load the next bootloader image. 1148 1149This function helps fulfill requirement 4 above. 1150 1151Function : bl1\_plat\_sec\_mem\_layout() [mandatory] 1152~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1153 1154:: 1155 1156 Argument : void 1157 Return : meminfo * 1158 1159This function should only be called on the cold boot path. It executes with the 1160MMU and data caches enabled. The pointer returned by this function must point to 1161a ``meminfo`` structure containing the extents and availability of secure RAM for 1162the BL1 stage. 1163 1164:: 1165 1166 meminfo.total_base = Base address of secure RAM visible to BL1 1167 meminfo.total_size = Size of secure RAM visible to BL1 1168 meminfo.free_base = Base address of secure RAM available for allocation 1169 to BL1 1170 meminfo.free_size = Size of secure RAM available for allocation to BL1 1171 1172This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1173populates a similar structure to tell BL2 the extents of memory available for 1174its own use. 1175 1176This function helps fulfill requirements 4 and 5 above. 1177 1178Function : bl1\_plat\_prepare\_exit() [optional] 1179~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1180 1181:: 1182 1183 Argument : entry_point_info_t * 1184 Return : void 1185 1186This function is called prior to exiting BL1 in response to the 1187``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1188platform specific clean up or bookkeeping operations before transferring 1189control to the next image. It receives the address of the ``entry_point_info_t`` 1190structure passed from BL2. This function runs with MMU disabled. 1191 1192Function : bl1\_plat\_set\_ep\_info() [optional] 1193~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1194 1195:: 1196 1197 Argument : unsigned int image_id, entry_point_info_t *ep_info 1198 Return : void 1199 1200This function allows platforms to override ``ep_info`` for the given ``image_id``. 1201 1202The default implementation just returns. 1203 1204Function : bl1\_plat\_get\_next\_image\_id() [optional] 1205~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1206 1207:: 1208 1209 Argument : void 1210 Return : unsigned int 1211 1212This and the following function must be overridden to enable the FWU feature. 1213 1214BL1 calls this function after platform setup to identify the next image to be 1215loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1216with the normal boot sequence, which loads and executes BL2. If the platform 1217returns a different image id, BL1 assumes that Firmware Update is required. 1218 1219The default implementation always returns ``BL2_IMAGE_ID``. The ARM development 1220platforms override this function to detect if firmware update is required, and 1221if so, return the first image in the firmware update process. 1222 1223Function : bl1\_plat\_get\_image\_desc() [optional] 1224~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1225 1226:: 1227 1228 Argument : unsigned int image_id 1229 Return : image_desc_t * 1230 1231BL1 calls this function to get the image descriptor information ``image_desc_t`` 1232for the provided ``image_id`` from the platform. 1233 1234The default implementation always returns a common BL2 image descriptor. ARM 1235standard platforms return an image descriptor corresponding to BL2 or one of 1236the firmware update images defined in the Trusted Board Boot Requirements 1237specification. 1238 1239Function : bl1\_plat\_handle\_pre\_image\_load() [optional] 1240~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1241 1242:: 1243 1244 Argument : unsigned int image_id 1245 Return : int 1246 1247This function can be used by the platforms to update/use image information 1248corresponding to ``image_id``. This function is invoked in BL1, both in cold 1249boot and FWU code path, before loading the image. 1250 1251Function : bl1\_plat\_handle\_post\_image\_load() [optional] 1252~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1253 1254:: 1255 1256 Argument : unsigned int image_id 1257 Return : int 1258 1259This function can be used by the platforms to update/use image information 1260corresponding to ``image_id``. This function is invoked in BL1, both in cold 1261boot and FWU code path, after loading and authenticating the image. 1262 1263The default weak implementation of this function calculates the amount of 1264Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` 1265structure at the beginning of this free memory and populates it. The address 1266of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint 1267information to BL2. 1268 1269Function : bl1\_plat\_fwu\_done() [optional] 1270~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1271 1272:: 1273 1274 Argument : unsigned int image_id, uintptr_t image_src, 1275 unsigned int image_size 1276 Return : void 1277 1278BL1 calls this function when the FWU process is complete. It must not return. 1279The platform may override this function to take platform specific action, for 1280example to initiate the normal boot flow. 1281 1282The default implementation spins forever. 1283 1284Function : bl1\_plat\_mem\_check() [mandatory] 1285~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1286 1287:: 1288 1289 Argument : uintptr_t mem_base, unsigned int mem_size, 1290 unsigned int flags 1291 Return : int 1292 1293BL1 calls this function while handling FWU related SMCs, more specifically when 1294copying or authenticating an image. Its responsibility is to ensure that the 1295region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1296that this memory corresponds to either a secure or non-secure memory region as 1297indicated by the security state of the ``flags`` argument. 1298 1299This function can safely assume that the value resulting from the addition of 1300``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1301overflow. 1302 1303This function must return 0 on success, a non-null error code otherwise. 1304 1305The default implementation of this function asserts therefore platforms must 1306override it when using the FWU feature. 1307 1308Boot Loader Stage 2 (BL2) 1309------------------------- 1310 1311The BL2 stage is executed only by the primary CPU, which is determined in BL1 1312using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1313``BL2_BASE``. BL2 executes in Secure EL1 and is responsible for: 1314 1315#. (Optional) Loading the SCP\_BL2 binary image (if present) from platform 1316 provided non-volatile storage. To load the SCP\_BL2 image, BL2 makes use of 1317 the ``meminfo`` returned by the ``bl2_plat_get_scp_bl2_meminfo()`` function. 1318 The platform also defines the address in memory where SCP\_BL2 is loaded 1319 through the optional constant ``SCP_BL2_BASE``. BL2 uses this information 1320 to determine if there is enough memory to load the SCP\_BL2 image. 1321 Subsequent handling of the SCP\_BL2 image is platform-specific and is 1322 implemented in the ``bl2_plat_handle_scp_bl2()`` function. 1323 If ``SCP_BL2_BASE`` is not defined then this step is not performed. 1324 1325#. Loading the BL31 binary image into secure RAM from non-volatile storage. To 1326 load the BL31 image, BL2 makes use of the ``meminfo`` structure passed to it 1327 by BL1. This structure allows BL2 to calculate how much secure RAM is 1328 available for its use. The platform also defines the address in secure RAM 1329 where BL31 is loaded through the constant ``BL31_BASE``. BL2 uses this 1330 information to determine if there is enough memory to load the BL31 image. 1331 1332#. (Optional) Loading the BL32 binary image (if present) from platform 1333 provided non-volatile storage. To load the BL32 image, BL2 makes use of 1334 the ``meminfo`` returned by the ``bl2_plat_get_bl32_meminfo()`` function. 1335 The platform also defines the address in memory where BL32 is loaded 1336 through the optional constant ``BL32_BASE``. BL2 uses this information 1337 to determine if there is enough memory to load the BL32 image. 1338 If ``BL32_BASE`` is not defined then this and the next step is not performed. 1339 1340#. (Optional) Arranging to pass control to the BL32 image (if present) that 1341 has been pre-loaded at ``BL32_BASE``. BL2 populates an ``entry_point_info`` 1342 structure in memory provided by the platform with information about how 1343 BL31 should pass control to the BL32 image. 1344 1345#. (Optional) Loading the normal world BL33 binary image (if not loaded by 1346 other means) into non-secure DRAM from platform storage and arranging for 1347 BL31 to pass control to this image. This address is determined using the 1348 ``plat_get_ns_image_entrypoint()`` function described below. 1349 1350#. BL2 populates an ``entry_point_info`` structure in memory provided by the 1351 platform with information about how BL31 should pass control to the 1352 other BL images. 1353 1354The following functions must be implemented by the platform port to enable BL2 1355to perform the above tasks. 1356 1357Function : bl2\_early\_platform\_setup() [mandatory] 1358~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1359 1360:: 1361 1362 Argument : meminfo * 1363 Return : void 1364 1365This function executes with the MMU and data caches disabled. It is only called 1366by the primary CPU. The arguments to this function is the address of the 1367``meminfo`` structure populated by BL1. 1368 1369The platform may copy the contents of the ``meminfo`` structure into a private 1370variable as the original memory may be subsequently overwritten by BL2. The 1371copied structure is made available to all BL2 code through the 1372``bl2_plat_sec_mem_layout()`` function. 1373 1374On ARM standard platforms, this function also: 1375 1376- Initializes a UART (PL011 console), which enables access to the ``printf`` 1377 family of functions in BL2. 1378 1379- Initializes the storage abstraction layer used to load further bootloader 1380 images. It is necessary to do this early on platforms with a SCP\_BL2 image, 1381 since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded. 1382 1383Function : bl2\_plat\_arch\_setup() [mandatory] 1384~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1385 1386:: 1387 1388 Argument : void 1389 Return : void 1390 1391This function executes with the MMU and data caches disabled. It is only called 1392by the primary CPU. 1393 1394The purpose of this function is to perform any architectural initialization 1395that varies across platforms. 1396 1397On ARM standard platforms, this function enables the MMU. 1398 1399Function : bl2\_platform\_setup() [mandatory] 1400~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1401 1402:: 1403 1404 Argument : void 1405 Return : void 1406 1407This function may execute with the MMU and data caches enabled if the platform 1408port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1409called by the primary CPU. 1410 1411The purpose of this function is to perform any platform initialization 1412specific to BL2. 1413 1414In ARM standard platforms, this function performs security setup, including 1415configuration of the TrustZone controller to allow non-secure masters access 1416to most of DRAM. Part of DRAM is reserved for secure world use. 1417 1418Function : bl2\_plat\_sec\_mem\_layout() [mandatory] 1419~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1420 1421:: 1422 1423 Argument : void 1424 Return : meminfo * 1425 1426This function should only be called on the cold boot path. It may execute with 1427the MMU and data caches enabled if the platform port does the necessary 1428initialization in ``bl2_plat_arch_setup()``. It is only called by the primary CPU. 1429 1430The purpose of this function is to return a pointer to a ``meminfo`` structure 1431populated with the extents of secure RAM available for BL2 to use. See 1432``bl2_early_platform_setup()`` above. 1433 1434Following functions are optionally used only when LOAD\_IMAGE\_V2 is enabled. 1435 1436Function : bl2\_plat\_handle\_pre\_image\_load() [optional] 1437~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1438 1439:: 1440 1441 Argument : unsigned int 1442 Return : int 1443 1444This function can be used by the platforms to update/use image information 1445for given ``image_id``. This function is currently invoked in BL2 before 1446loading each image, when LOAD\_IMAGE\_V2 is enabled. 1447 1448Function : bl2\_plat\_handle\_post\_image\_load() [optional] 1449~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1450 1451:: 1452 1453 Argument : unsigned int 1454 Return : int 1455 1456This function can be used by the platforms to update/use image information 1457for given ``image_id``. This function is currently invoked in BL2 after 1458loading each image, when LOAD\_IMAGE\_V2 is enabled. 1459 1460Following functions are required only when LOAD\_IMAGE\_V2 is disabled. 1461 1462Function : bl2\_plat\_get\_scp\_bl2\_meminfo() [mandatory] 1463~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1464 1465:: 1466 1467 Argument : meminfo * 1468 Return : void 1469 1470This function is used to get the memory limits where BL2 can load the 1471SCP\_BL2 image. The meminfo provided by this is used by load\_image() to 1472validate whether the SCP\_BL2 image can be loaded within the given 1473memory from the given base. 1474 1475Function : bl2\_plat\_handle\_scp\_bl2() [mandatory] 1476~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1477 1478:: 1479 1480 Argument : image_info * 1481 Return : int 1482 1483This function is called after loading SCP\_BL2 image and it is used to perform 1484any platform-specific actions required to handle the SCP firmware. Typically it 1485transfers the image into SCP memory using a platform-specific protocol and waits 1486until SCP executes it and signals to the Application Processor (AP) for BL2 1487execution to continue. 1488 1489This function returns 0 on success, a negative error code otherwise. 1490 1491Function : bl2\_plat\_get\_bl31\_params() [mandatory] 1492~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1493 1494:: 1495 1496 Argument : void 1497 Return : bl31_params * 1498 1499BL2 platform code needs to return a pointer to a ``bl31_params`` structure it 1500will use for passing information to BL31. The ``bl31_params`` structure carries 1501the following information. 1502- Header describing the version information for interpreting the bl31\_param 1503structure 1504- Information about executing the BL33 image in the ``bl33_ep_info`` field 1505- Information about executing the BL32 image in the ``bl32_ep_info`` field 1506- Information about the type and extents of BL31 image in the 1507``bl31_image_info`` field 1508- Information about the type and extents of BL32 image in the 1509``bl32_image_info`` field 1510- Information about the type and extents of BL33 image in the 1511``bl33_image_info`` field 1512 1513The memory pointed by this structure and its sub-structures should be 1514accessible from BL31 initialisation code. BL31 might choose to copy the 1515necessary content, or maintain the structures until BL33 is initialised. 1516 1517Funtion : bl2\_plat\_get\_bl31\_ep\_info() [mandatory] 1518~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1519 1520:: 1521 1522 Argument : void 1523 Return : entry_point_info * 1524 1525BL2 platform code returns a pointer which is used to populate the entry point 1526information for BL31 entry point. The location pointed by it should be 1527accessible from BL1 while processing the synchronous exception to run to BL31. 1528 1529In ARM standard platforms this is allocated inside a bl2\_to\_bl31\_params\_mem 1530structure in BL2 memory. 1531 1532Function : bl2\_plat\_set\_bl31\_ep\_info() [mandatory] 1533~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1534 1535:: 1536 1537 Argument : image_info *, entry_point_info * 1538 Return : void 1539 1540In the normal boot flow, this function is called after loading BL31 image and 1541it can be used to overwrite the entry point set by loader and also set the 1542security state and SPSR which represents the entry point system state for BL31. 1543 1544When booting an EL3 payload instead, this function is called after populating 1545its entry point address and can be used for the same purpose for the payload 1546image. It receives a null pointer as its first argument in this case. 1547 1548Function : bl2\_plat\_set\_bl32\_ep\_info() [mandatory] 1549~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1550 1551:: 1552 1553 Argument : image_info *, entry_point_info * 1554 Return : void 1555 1556This function is called after loading BL32 image and it can be used to 1557overwrite the entry point set by loader and also set the security state 1558and SPSR which represents the entry point system state for BL32. 1559 1560Function : bl2\_plat\_set\_bl33\_ep\_info() [mandatory] 1561~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1562 1563:: 1564 1565 Argument : image_info *, entry_point_info * 1566 Return : void 1567 1568This function is called after loading BL33 image and it can be used to 1569overwrite the entry point set by loader and also set the security state 1570and SPSR which represents the entry point system state for BL33. 1571 1572In the preloaded BL33 alternative boot flow, this function is called after 1573populating its entry point address. It is passed a null pointer as its first 1574argument in this case. 1575 1576Function : bl2\_plat\_get\_bl32\_meminfo() [mandatory] 1577~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1578 1579:: 1580 1581 Argument : meminfo * 1582 Return : void 1583 1584This function is used to get the memory limits where BL2 can load the 1585BL32 image. The meminfo provided by this is used by load\_image() to 1586validate whether the BL32 image can be loaded with in the given 1587memory from the given base. 1588 1589Function : bl2\_plat\_get\_bl33\_meminfo() [mandatory] 1590~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1591 1592:: 1593 1594 Argument : meminfo * 1595 Return : void 1596 1597This function is used to get the memory limits where BL2 can load the 1598BL33 image. The meminfo provided by this is used by load\_image() to 1599validate whether the BL33 image can be loaded with in the given 1600memory from the given base. 1601 1602This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE`` 1603build options are used. 1604 1605Function : bl2\_plat\_flush\_bl31\_params() [mandatory] 1606~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1607 1608:: 1609 1610 Argument : void 1611 Return : void 1612 1613Once BL2 has populated all the structures that needs to be read by BL1 1614and BL31 including the bl31\_params structures and its sub-structures, 1615the bl31\_ep\_info structure and any platform specific data. It flushes 1616all these data to the main memory so that it is available when we jump to 1617later Bootloader stages with MMU off 1618 1619Function : plat\_get\_ns\_image\_entrypoint() [mandatory] 1620~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1621 1622:: 1623 1624 Argument : void 1625 Return : uintptr_t 1626 1627As previously described, BL2 is responsible for arranging for control to be 1628passed to a normal world BL image through BL31. This function returns the 1629entrypoint of that image, which BL31 uses to jump to it. 1630 1631BL2 is responsible for loading the normal world BL33 image (e.g. UEFI). 1632 1633This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE`` 1634build options are used. 1635 1636Function : bl2\_plat\_preload\_setup [optional] 1637~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1638 1639:: 1640 Argument : void 1641 Return : void 1642 1643This optional function performs any BL2 platform initialization 1644required before image loading, that is not done later in 1645bl2\_platform\_setup(). Specifically, if support for multiple 1646boot sources is required, it initializes the boot sequence used by 1647plat\_try\_next\_boot\_source(). 1648 1649Function : plat\_try\_next\_boot\_source() [optional] 1650~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1651 1652:: 1653 Argument : void 1654 Return : int 1655 1656This optional function passes to the next boot source in the redundancy 1657sequence. 1658 1659This function moves the current boot redundancy source to the next 1660element in the boot sequence. If there are no more boot sources then it 1661must return 0, otherwise it must return 1. The default implementation 1662of this always returns 0. 1663 1664Boot Loader Stage 2 (BL2) at EL3 1665-------------------------------- 1666 1667When the platform has a non-TF Boot ROM it is desirable to jump 1668directly to BL2 instead of TF BL1. In this case BL2 is expected to 1669execute at EL3 instead of executing at EL1. Refer to the `Firmware 1670Design`_ for more information. 1671 1672All mandatory functions of BL2 must be implemented, except the functions 1673bl2\_early\_platform\_setup and bl2\_el3\_plat\_arch\_setup, because 1674their work is done now by bl2\_el3\_early\_platform\_setup and 1675bl2\_el3\_plat\_arch\_setup. These functions should generally implement 1676the bl1\_plat\_xxx() and bl2\_plat\_xxx() functionality combined. 1677 1678 1679Function : bl2\_el3\_early\_platform\_setup() [mandatory] 1680~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1681 1682:: 1683 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1684 Return : void 1685 1686This function executes with the MMU and data caches disabled. It is only called 1687by the primary CPU. This function receives four parameters which can be used 1688by the platform to pass any needed information from the Boot ROM to BL2. 1689 1690On ARM standard platforms, this function does the following: 1691 1692- Initializes a UART (PL011 console), which enables access to the ``printf`` 1693 family of functions in BL2. 1694 1695- Initializes the storage abstraction layer used to load further bootloader 1696 images. It is necessary to do this early on platforms with a SCP\_BL2 image, 1697 since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded. 1698 1699- Initializes the private variables that define the memory layout used. 1700 1701Function : bl2\_el3\_plat\_arch\_setup() [mandatory] 1702~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1703 1704:: 1705 Argument : void 1706 Return : void 1707 1708This function executes with the MMU and data caches disabled. It is only called 1709by the primary CPU. 1710 1711The purpose of this function is to perform any architectural initialization 1712that varies across platforms. 1713 1714On ARM standard platforms, this function enables the MMU. 1715 1716Function : bl2\_el3\_plat\_prepare\_exit() [optional] 1717~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1718 1719:: 1720 Argument : void 1721 Return : void 1722 1723This function is called prior to exiting BL2 and run the next image. 1724It should be used to perform platform specific clean up or bookkeeping 1725operations before transferring control to the next image. This function 1726runs with MMU disabled. 1727 1728FWU Boot Loader Stage 2 (BL2U) 1729------------------------------ 1730 1731The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 1732process and is executed only by the primary CPU. BL1 passes control to BL2U at 1733``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 1734 1735#. (Optional) Transfering the optional SCP\_BL2U binary image from AP secure 1736 memory to SCP RAM. BL2U uses the SCP\_BL2U ``image_info`` passed by BL1. 1737 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP\_BL2U 1738 should be copied from. Subsequent handling of the SCP\_BL2U image is 1739 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 1740 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 1741 1742#. Any platform specific setup required to perform the FWU process. For 1743 example, ARM standard platforms initialize the TZC controller so that the 1744 normal world can access DDR memory. 1745 1746The following functions must be implemented by the platform port to enable 1747BL2U to perform the tasks mentioned above. 1748 1749Function : bl2u\_early\_platform\_setup() [mandatory] 1750~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1751 1752:: 1753 1754 Argument : meminfo *mem_info, void *plat_info 1755 Return : void 1756 1757This function executes with the MMU and data caches disabled. It is only 1758called by the primary CPU. The arguments to this function is the address 1759of the ``meminfo`` structure and platform specific info provided by BL1. 1760 1761The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 1762private storage as the original memory may be subsequently overwritten by BL2U. 1763 1764On ARM CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 1765to extract SCP\_BL2U image information, which is then copied into a private 1766variable. 1767 1768Function : bl2u\_plat\_arch\_setup() [mandatory] 1769~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1770 1771:: 1772 1773 Argument : void 1774 Return : void 1775 1776This function executes with the MMU and data caches disabled. It is only 1777called by the primary CPU. 1778 1779The purpose of this function is to perform any architectural initialization 1780that varies across platforms, for example enabling the MMU (since the memory 1781map differs across platforms). 1782 1783Function : bl2u\_platform\_setup() [mandatory] 1784~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1785 1786:: 1787 1788 Argument : void 1789 Return : void 1790 1791This function may execute with the MMU and data caches enabled if the platform 1792port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 1793called by the primary CPU. 1794 1795The purpose of this function is to perform any platform initialization 1796specific to BL2U. 1797 1798In ARM standard platforms, this function performs security setup, including 1799configuration of the TrustZone controller to allow non-secure masters access 1800to most of DRAM. Part of DRAM is reserved for secure world use. 1801 1802Function : bl2u\_plat\_handle\_scp\_bl2u() [optional] 1803~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1804 1805:: 1806 1807 Argument : void 1808 Return : int 1809 1810This function is used to perform any platform-specific actions required to 1811handle the SCP firmware. Typically it transfers the image into SCP memory using 1812a platform-specific protocol and waits until SCP executes it and signals to the 1813Application Processor (AP) for BL2U execution to continue. 1814 1815This function returns 0 on success, a negative error code otherwise. 1816This function is included if SCP\_BL2U\_BASE is defined. 1817 1818Boot Loader Stage 3-1 (BL31) 1819---------------------------- 1820 1821During cold boot, the BL31 stage is executed only by the primary CPU. This is 1822determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 1823control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 1824CPUs. BL31 executes at EL3 and is responsible for: 1825 1826#. Re-initializing all architectural and platform state. Although BL1 performs 1827 some of this initialization, BL31 remains resident in EL3 and must ensure 1828 that EL3 architectural and platform state is completely initialized. It 1829 should make no assumptions about the system state when it receives control. 1830 1831#. Passing control to a normal world BL image, pre-loaded at a platform- 1832 specific address by BL2. BL31 uses the ``entry_point_info`` structure that BL2 1833 populated in memory to do this. 1834 1835#. Providing runtime firmware services. Currently, BL31 only implements a 1836 subset of the Power State Coordination Interface (PSCI) API as a runtime 1837 service. See Section 3.3 below for details of porting the PSCI 1838 implementation. 1839 1840#. Optionally passing control to the BL32 image, pre-loaded at a platform- 1841 specific address by BL2. BL31 exports a set of apis that allow runtime 1842 services to specify the security state in which the next image should be 1843 executed and run the corresponding image. BL31 uses the ``entry_point_info`` 1844 structure populated by BL2 to do this. 1845 1846If BL31 is a reset vector, It also needs to handle the reset as specified in 1847section 2.2 before the tasks described above. 1848 1849The following functions must be implemented by the platform port to enable BL31 1850to perform the above tasks. 1851 1852Function : bl31\_early\_platform\_setup() [mandatory] 1853~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1854 1855:: 1856 1857 Argument : bl31_params *, void * 1858 Return : void 1859 1860This function executes with the MMU and data caches disabled. It is only called 1861by the primary CPU. The arguments to this function are: 1862 1863- The address of the ``bl31_params`` structure populated by BL2. 1864- An opaque pointer that the platform may use as needed. 1865 1866The platform can copy the contents of the ``bl31_params`` structure and its 1867sub-structures into private variables if the original memory may be 1868subsequently overwritten by BL31 and similarly the ``void *`` pointing 1869to the platform data also needs to be saved. 1870 1871In ARM standard platforms, BL2 passes a pointer to a ``bl31_params`` structure 1872in BL2 memory. BL31 copies the information in this pointer to internal data 1873structures. It also performs the following: 1874 1875- Initialize a UART (PL011 console), which enables access to the ``printf`` 1876 family of functions in BL31. 1877 1878- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 1879 CCI slave interface corresponding to the cluster that includes the primary 1880 CPU. 1881 1882Function : bl31\_plat\_arch\_setup() [mandatory] 1883~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1884 1885:: 1886 1887 Argument : void 1888 Return : void 1889 1890This function executes with the MMU and data caches disabled. It is only called 1891by the primary CPU. 1892 1893The purpose of this function is to perform any architectural initialization 1894that varies across platforms. 1895 1896On ARM standard platforms, this function enables the MMU. 1897 1898Function : bl31\_platform\_setup() [mandatory] 1899~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1900 1901:: 1902 1903 Argument : void 1904 Return : void 1905 1906This function may execute with the MMU and data caches enabled if the platform 1907port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 1908called by the primary CPU. 1909 1910The purpose of this function is to complete platform initialization so that both 1911BL31 runtime services and normal world software can function correctly. 1912 1913On ARM standard platforms, this function does the following: 1914 1915- Initialize the generic interrupt controller. 1916 1917 Depending on the GIC driver selected by the platform, the appropriate GICv2 1918 or GICv3 initialization will be done, which mainly consists of: 1919 1920 - Enable secure interrupts in the GIC CPU interface. 1921 - Disable the legacy interrupt bypass mechanism. 1922 - Configure the priority mask register to allow interrupts of all priorities 1923 to be signaled to the CPU interface. 1924 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 1925 - Target all secure SPIs to CPU0. 1926 - Enable these secure interrupts in the GIC distributor. 1927 - Configure all other interrupts as non-secure. 1928 - Enable signaling of secure interrupts in the GIC distributor. 1929 1930- Enable system-level implementation of the generic timer counter through the 1931 memory mapped interface. 1932 1933- Grant access to the system counter timer module 1934 1935- Initialize the power controller device. 1936 1937 In particular, initialise the locks that prevent concurrent accesses to the 1938 power controller device. 1939 1940Function : bl31\_plat\_runtime\_setup() [optional] 1941~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1942 1943:: 1944 1945 Argument : void 1946 Return : void 1947 1948The purpose of this function is allow the platform to perform any BL31 runtime 1949setup just prior to BL31 exit during cold boot. The default weak 1950implementation of this function will invoke ``console_switch_state()`` to switch 1951console output to consoles marked for use in the ``runtime`` state. 1952 1953Function : bl31\_get\_next\_image\_info() [mandatory] 1954~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1955 1956:: 1957 1958 Argument : unsigned int 1959 Return : entry_point_info * 1960 1961This function may execute with the MMU and data caches enabled if the platform 1962port does the necessary initializations in ``bl31_plat_arch_setup()``. 1963 1964This function is called by ``bl31_main()`` to retrieve information provided by 1965BL2 for the next image in the security state specified by the argument. BL31 1966uses this information to pass control to that image in the specified security 1967state. This function must return a pointer to the ``entry_point_info`` structure 1968(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 1969should return NULL otherwise. 1970 1971Function : plat\_get\_syscnt\_freq2() [mandatory] 1972~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1973 1974:: 1975 1976 Argument : void 1977 Return : unsigned int 1978 1979This function is used by the architecture setup code to retrieve the counter 1980frequency for the CPU's generic timer. This value will be programmed into the 1981``CNTFRQ_EL0`` register. In ARM standard platforms, it returns the base frequency 1982of the system counter, which is retrieved from the first entry in the frequency 1983modes table. 1984 1985#define : PLAT\_PERCPU\_BAKERY\_LOCK\_SIZE [optional] 1986~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1987 1988When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 1989bytes) aligned to the cache line boundary that should be allocated per-cpu to 1990accommodate all the bakery locks. 1991 1992If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 1993calculates the size of the ``bakery_lock`` input section, aligns it to the 1994nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 1995and stores the result in a linker symbol. This constant prevents a platform 1996from relying on the linker and provide a more efficient mechanism for 1997accessing per-cpu bakery lock information. 1998 1999If this constant is defined and its value is not equal to the value 2000calculated by the linker then a link time assertion is raised. A compile time 2001assertion is raised if the value of the constant is not aligned to the cache 2002line boundary. 2003 2004SDEI porting requirements 2005~~~~~~~~~~~~~~~~~~~~~~~~~ 2006 2007The SDEI dispatcher requires the platform to provide the following macros 2008and functions, of which some are optional, and some others mandatory. 2009 2010Macros 2011...... 2012 2013Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 2014^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2015 2016This macro must be defined to the EL3 exception priority level associated with 2017Normal SDEI events on the platform. This must have a higher value (therefore of 2018lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 2019 2020Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 2021^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2022 2023This macro must be defined to the EL3 exception priority level associated with 2024Critical SDEI events on the platform. This must have a lower value (therefore of 2025higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 2026 2027**Note**: SDEI exception priorities must be the lowest among Secure priorities. 2028Among the SDEI exceptions, Critical SDEI priority must be higher than Normal 2029SDEI priority. 2030 2031Functions 2032......... 2033 2034Function: int plat_sdei_validate_entry_point(uintptr_t ep) [optional] 2035^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2036 2037:: 2038 2039 Argument: uintptr_t 2040 Return: int 2041 2042This function validates the address of client entry points provided for both 2043event registration and *Complete and Resume* SDEI calls. The function takes one 2044argument, which is the address of the handler the SDEI client requested to 2045register. The function must return ``0`` for successful validation, or ``-1`` 2046upon failure. 2047 2048The default implementation always returns ``0``. On ARM platforms, this function 2049is implemented to translate the entry point to physical address, and further to 2050ensure that the address is located in Non-secure DRAM. 2051 2052Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 2053^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2054 2055:: 2056 2057 Argument: uint64_t 2058 Argument: unsigned int 2059 Return: void 2060 2061SDEI specification requires that a PE comes out of reset with the events masked. 2062The client therefore is expected to call ``PE_UNMASK`` to unmask SDEI events on 2063the PE. No SDEI events can be dispatched until such time. 2064 2065Should a PE receive an interrupt that was bound to an SDEI event while the 2066events are masked on the PE, the dispatcher implementation invokes the function 2067``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 2068interrupt and the interrupt ID are passed as parameters. 2069 2070The default implementation only prints out a warning message. 2071 2072Power State Coordination Interface (in BL31) 2073-------------------------------------------- 2074 2075The ARM Trusted Firmware's implementation of the PSCI API is based around the 2076concept of a *power domain*. A *power domain* is a CPU or a logical group of 2077CPUs which share some state on which power management operations can be 2078performed as specified by `PSCI`_. Each CPU in the system is assigned a cpu 2079index which is a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. 2080The *power domains* are arranged in a hierarchical tree structure and 2081each *power domain* can be identified in a system by the cpu index of any CPU 2082that is part of that domain and a *power domain level*. A processing element 2083(for example, a CPU) is at level 0. If the *power domain* node above a CPU is 2084a logical grouping of CPUs that share some state, then level 1 is that group 2085of CPUs (for example, a cluster), and level 2 is a group of clusters 2086(for example, the system). More details on the power domain topology and its 2087organization can be found in `Power Domain Topology Design`_. 2088 2089BL31's platform initialization code exports a pointer to the platform-specific 2090power management operations required for the PSCI implementation to function 2091correctly. This information is populated in the ``plat_psci_ops`` structure. The 2092PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 2093power management operations on the power domains. For example, the target 2094CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 2095handler (if present) is called for the CPU power domain. 2096 2097The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 2098describe composite power states specific to a platform. The PSCI implementation 2099defines a generic representation of the power-state parameter viz which is an 2100array of local power states where each index corresponds to a power domain 2101level. Each entry contains the local power state the power domain at that power 2102level could enter. It depends on the ``validate_power_state()`` handler to 2103convert the power-state parameter (possibly encoding a composite power state) 2104passed in a PSCI ``CPU_SUSPEND`` call to this representation. 2105 2106The following functions form part of platform port of PSCI functionality. 2107 2108Function : plat\_psci\_stat\_accounting\_start() [optional] 2109~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2110 2111:: 2112 2113 Argument : const psci_power_state_t * 2114 Return : void 2115 2116This is an optional hook that platforms can implement for residency statistics 2117accounting before entering a low power state. The ``pwr_domain_state`` field of 2118``state_info`` (first argument) can be inspected if stat accounting is done 2119differently at CPU level versus higher levels. As an example, if the element at 2120index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2121state, special hardware logic may be programmed in order to keep track of the 2122residency statistics. For higher levels (array indices > 0), the residency 2123statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2124default implementation will use PMF to capture timestamps. 2125 2126Function : plat\_psci\_stat\_accounting\_stop() [optional] 2127~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2128 2129:: 2130 2131 Argument : const psci_power_state_t * 2132 Return : void 2133 2134This is an optional hook that platforms can implement for residency statistics 2135accounting after exiting from a low power state. The ``pwr_domain_state`` field 2136of ``state_info`` (first argument) can be inspected if stat accounting is done 2137differently at CPU level versus higher levels. As an example, if the element at 2138index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2139state, special hardware logic may be programmed in order to keep track of the 2140residency statistics. For higher levels (array indices > 0), the residency 2141statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2142default implementation will use PMF to capture timestamps. 2143 2144Function : plat\_psci\_stat\_get\_residency() [optional] 2145~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2146 2147:: 2148 2149 Argument : unsigned int, const psci_power_state_t *, int 2150 Return : u_register_t 2151 2152This is an optional interface that is is invoked after resuming from a low power 2153state and provides the time spent resident in that low power state by the power 2154domain at a particular power domain level. When a CPU wakes up from suspend, 2155all its parent power domain levels are also woken up. The generic PSCI code 2156invokes this function for each parent power domain that is resumed and it 2157identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 2158argument) describes the low power state that the power domain has resumed from. 2159The current CPU is the first CPU in the power domain to resume from the low 2160power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2161CPU in the power domain to suspend and may be needed to calculate the residency 2162for that power domain. 2163 2164Function : plat\_get\_target\_pwr\_state() [optional] 2165~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2166 2167:: 2168 2169 Argument : unsigned int, const plat_local_state_t *, unsigned int 2170 Return : plat_local_state_t 2171 2172The PSCI generic code uses this function to let the platform participate in 2173state coordination during a power management operation. The function is passed 2174a pointer to an array of platform specific local power state ``states`` (second 2175argument) which contains the requested power state for each CPU at a particular 2176power domain level ``lvl`` (first argument) within the power domain. The function 2177is expected to traverse this array of upto ``ncpus`` (third argument) and return 2178a coordinated target power state by the comparing all the requested power 2179states. The target power state should not be deeper than any of the requested 2180power states. 2181 2182A weak definition of this API is provided by default wherein it assumes 2183that the platform assigns a local state value in order of increasing depth 2184of the power state i.e. for two power states X & Y, if X < Y 2185then X represents a shallower power state than Y. As a result, the 2186coordinated target local power state for a power domain will be the minimum 2187of the requested local power state values. 2188 2189Function : plat\_get\_power\_domain\_tree\_desc() [mandatory] 2190~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2191 2192:: 2193 2194 Argument : void 2195 Return : const unsigned char * 2196 2197This function returns a pointer to the byte array containing the power domain 2198topology tree description. The format and method to construct this array are 2199described in `Power Domain Topology Design`_. The BL31 PSCI initilization code 2200requires this array to be described by the platform, either statically or 2201dynamically, to initialize the power domain topology tree. In case the array 2202is populated dynamically, then plat\_core\_pos\_by\_mpidr() and 2203plat\_my\_core\_pos() should also be implemented suitably so that the topology 2204tree description matches the CPU indices returned by these APIs. These APIs 2205together form the platform interface for the PSCI topology framework. 2206 2207Function : plat\_setup\_psci\_ops() [mandatory] 2208~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2209 2210:: 2211 2212 Argument : uintptr_t, const plat_psci_ops ** 2213 Return : int 2214 2215This function may execute with the MMU and data caches enabled if the platform 2216port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 2217called by the primary CPU. 2218 2219This function is called by PSCI initialization code. Its purpose is to let 2220the platform layer know about the warm boot entrypoint through the 2221``sec_entrypoint`` (first argument) and to export handler routines for 2222platform-specific psci power management actions by populating the passed 2223pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 2224 2225A description of each member of this structure is given below. Please refer to 2226the ARM FVP specific implementation of these handlers in 2227`plat/arm/board/fvp/fvp\_pm.c`_ as an example. For each PSCI function that the 2228platform wants to support, the associated operation or operations in this 2229structure must be provided and implemented (Refer section 4 of 2230`Firmware Design`_ for the PSCI API supported in Trusted Firmware). To disable 2231a PSCI function in a platform port, the operation should be removed from this 2232structure instead of providing an empty implementation. 2233 2234plat\_psci\_ops.cpu\_standby() 2235.............................. 2236 2237Perform the platform-specific actions to enter the standby state for a cpu 2238indicated by the passed argument. This provides a fast path for CPU standby 2239wherein overheads of PSCI state management and lock acquistion is avoided. 2240For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 2241the suspend state type specified in the ``power-state`` parameter should be 2242STANDBY and the target power domain level specified should be the CPU. The 2243handler should put the CPU into a low power retention state (usually by 2244issuing a wfi instruction) and ensure that it can be woken up from that 2245state by a normal interrupt. The generic code expects the handler to succeed. 2246 2247plat\_psci\_ops.pwr\_domain\_on() 2248................................. 2249 2250Perform the platform specific actions to power on a CPU, specified 2251by the ``MPIDR`` (first argument). The generic code expects the platform to 2252return PSCI\_E\_SUCCESS on success or PSCI\_E\_INTERN\_FAIL for any failure. 2253 2254plat\_psci\_ops.pwr\_domain\_off() 2255.................................. 2256 2257Perform the platform specific actions to prepare to power off the calling CPU 2258and its higher parent power domain levels as indicated by the ``target_state`` 2259(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 2260 2261The ``target_state`` encodes the platform coordinated target local power states 2262for the CPU power domain and its parent power domain levels. The handler 2263needs to perform power management operation corresponding to the local state 2264at each power level. 2265 2266For this handler, the local power state for the CPU power domain will be a 2267power down state where as it could be either power down, retention or run state 2268for the higher power domain levels depending on the result of state 2269coordination. The generic code expects the handler to succeed. 2270 2271plat\_psci\_ops.pwr\_domain\_suspend\_pwrdown\_early() [optional] 2272................................................................. 2273 2274This optional function may be used as a performance optimization to replace 2275or complement pwr_domain_suspend() on some platforms. Its calling semantics 2276are identical to pwr_domain_suspend(), except the PSCI implementation only 2277calls this function when suspending to a power down state, and it guarantees 2278that data caches are enabled. 2279 2280When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 2281before calling pwr_domain_suspend(). If the target_state corresponds to a 2282power down state and it is safe to perform some or all of the platform 2283specific actions in that function with data caches enabled, it may be more 2284efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 2285= 1, data caches remain enabled throughout, and so there is no advantage to 2286moving platform specific actions to this function. 2287 2288plat\_psci\_ops.pwr\_domain\_suspend() 2289...................................... 2290 2291Perform the platform specific actions to prepare to suspend the calling 2292CPU and its higher parent power domain levels as indicated by the 2293``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 2294API implementation. 2295 2296The ``target_state`` has a similar meaning as described in 2297the ``pwr_domain_off()`` operation. It encodes the platform coordinated 2298target local power states for the CPU power domain and its parent 2299power domain levels. The handler needs to perform power management operation 2300corresponding to the local state at each power level. The generic code 2301expects the handler to succeed. 2302 2303The difference between turning a power domain off versus suspending it is that 2304in the former case, the power domain is expected to re-initialize its state 2305when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 2306case, the power domain is expected to save enough state so that it can resume 2307execution by restoring this state when its powered on (see 2308``pwr_domain_suspend_finish()``). 2309 2310When suspending a core, the platform can also choose to power off the GICv3 2311Redistributor and ITS through an implementation-defined sequence. To achieve 2312this safely, the ITS context must be saved first. The architectural part is 2313implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 2314sequence is implementation defined and it is therefore the responsibility of 2315the platform code to implement the necessary sequence. Then the GIC 2316Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 2317Powering off the Redistributor requires the implementation to support it and it 2318is the responsibility of the platform code to execute the right implementation 2319defined sequence. 2320 2321When a system suspend is requested, the platform can also make use of the 2322``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 2323it has saved the context of the Redistributors and ITS of all the cores in the 2324system. The context of the Distributor can be large and may require it to be 2325allocated in a special area if it cannot fit in the platform's global static 2326data, for example in DRAM. The Distributor can then be powered down using an 2327implementation-defined sequence. 2328 2329plat\_psci\_ops.pwr\_domain\_pwr\_down\_wfi() 2330............................................. 2331 2332This is an optional function and, if implemented, is expected to perform 2333platform specific actions including the ``wfi`` invocation which allows the 2334CPU to powerdown. Since this function is invoked outside the PSCI locks, 2335the actions performed in this hook must be local to the CPU or the platform 2336must ensure that races between multiple CPUs cannot occur. 2337 2338The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 2339operation and it encodes the platform coordinated target local power states for 2340the CPU power domain and its parent power domain levels. This function must 2341not return back to the caller. 2342 2343If this function is not implemented by the platform, PSCI generic 2344implementation invokes ``psci_power_down_wfi()`` for power down. 2345 2346plat\_psci\_ops.pwr\_domain\_on\_finish() 2347......................................... 2348 2349This function is called by the PSCI implementation after the calling CPU is 2350powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 2351It performs the platform-specific setup required to initialize enough state for 2352this CPU to enter the normal world and also provide secure runtime firmware 2353services. 2354 2355The ``target_state`` (first argument) is the prior state of the power domains 2356immediately before the CPU was turned on. It indicates which power domains 2357above the CPU might require initialization due to having previously been in 2358low power states. The generic code expects the handler to succeed. 2359 2360plat\_psci\_ops.pwr\_domain\_suspend\_finish() 2361.............................................. 2362 2363This function is called by the PSCI implementation after the calling CPU is 2364powered on and released from reset in response to an asynchronous wakeup 2365event, for example a timer interrupt that was programmed by the CPU during the 2366``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 2367setup required to restore the saved state for this CPU to resume execution 2368in the normal world and also provide secure runtime firmware services. 2369 2370The ``target_state`` (first argument) has a similar meaning as described in 2371the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 2372to succeed. 2373 2374If the Distributor, Redistributors or ITS have been powered off as part of a 2375suspend, their context must be restored in this function in the reverse order 2376to how they were saved during suspend sequence. 2377 2378plat\_psci\_ops.system\_off() 2379............................. 2380 2381This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 2382call. It performs the platform-specific system poweroff sequence after 2383notifying the Secure Payload Dispatcher. 2384 2385plat\_psci\_ops.system\_reset() 2386............................... 2387 2388This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 2389call. It performs the platform-specific system reset sequence after 2390notifying the Secure Payload Dispatcher. 2391 2392plat\_psci\_ops.validate\_power\_state() 2393........................................ 2394 2395This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 2396call to validate the ``power_state`` parameter of the PSCI API and if valid, 2397populate it in ``req_state`` (second argument) array as power domain level 2398specific local states. If the ``power_state`` is invalid, the platform must 2399return PSCI\_E\_INVALID\_PARAMS as error, which is propagated back to the 2400normal world PSCI client. 2401 2402plat\_psci\_ops.validate\_ns\_entrypoint() 2403.......................................... 2404 2405This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 2406``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 2407parameter passed by the normal world. If the ``entry_point`` is invalid, 2408the platform must return PSCI\_E\_INVALID\_ADDRESS as error, which is 2409propagated back to the normal world PSCI client. 2410 2411plat\_psci\_ops.get\_sys\_suspend\_power\_state() 2412................................................. 2413 2414This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 2415call to get the ``req_state`` parameter from platform which encodes the power 2416domain level specific local states to suspend to system affinity level. The 2417``req_state`` will be utilized to do the PSCI state coordination and 2418``pwr_domain_suspend()`` will be invoked with the coordinated target state to 2419enter system suspend. 2420 2421plat\_psci\_ops.get\_pwr\_lvl\_state\_idx() 2422........................................... 2423 2424This is an optional function and, if implemented, is invoked by the PSCI 2425implementation to convert the ``local_state`` (first argument) at a specified 2426``pwr_lvl`` (second argument) to an index between 0 and 2427``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 2428supports more than two local power states at each power domain level, that is 2429``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 2430local power states. 2431 2432plat\_psci\_ops.translate\_power\_state\_by\_mpidr() 2433.................................................... 2434 2435This is an optional function and, if implemented, verifies the ``power_state`` 2436(second argument) parameter of the PSCI API corresponding to a target power 2437domain. The target power domain is identified by using both ``MPIDR`` (first 2438argument) and the power domain level encoded in ``power_state``. The power domain 2439level specific local states are to be extracted from ``power_state`` and be 2440populated in the ``output_state`` (third argument) array. The functionality 2441is similar to the ``validate_power_state`` function described above and is 2442envisaged to be used in case the validity of ``power_state`` depend on the 2443targeted power domain. If the ``power_state`` is invalid for the targeted power 2444domain, the platform must return PSCI\_E\_INVALID\_PARAMS as error. If this 2445function is not implemented, then the generic implementation relies on 2446``validate_power_state`` function to translate the ``power_state``. 2447 2448This function can also be used in case the platform wants to support local 2449power state encoding for ``power_state`` parameter of PSCI\_STAT\_COUNT/RESIDENCY 2450APIs as described in Section 5.18 of `PSCI`_. 2451 2452plat\_psci\_ops.get\_node\_hw\_state() 2453...................................... 2454 2455This is an optional function. If implemented this function is intended to return 2456the power state of a node (identified by the first parameter, the ``MPIDR``) in 2457the power domain topology (identified by the second parameter, ``power_level``), 2458as retrieved from a power controller or equivalent component on the platform. 2459Upon successful completion, the implementation must map and return the final 2460status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 2461must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 2462appropriate. 2463 2464Implementations are not expected to handle ``power_levels`` greater than 2465``PLAT_MAX_PWR_LVL``. 2466 2467plat\_psci\_ops.system\_reset2() 2468................................ 2469 2470This is an optional function. If implemented this function is 2471called during the ``SYSTEM_RESET2`` call to perform a reset 2472based on the first parameter ``reset_type`` as specified in 2473`PSCI`_. The parameter ``cookie`` can be used to pass additional 2474reset information. If the ``reset_type`` is not supported, the 2475function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 2476resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 2477and vendor reset can return other PSCI error codes as defined 2478in `PSCI`_. On success this function will not return. 2479 2480plat\_psci\_ops.write\_mem\_protect() 2481.................................... 2482 2483This is an optional function. If implemented it enables or disables the 2484``MEM_PROTECT`` functionality based on the value of ``val``. 2485A non-zero value enables ``MEM_PROTECT`` and a value of zero 2486disables it. Upon encountering failures it must return a negative value 2487and on success it must return 0. 2488 2489plat\_psci\_ops.read\_mem\_protect() 2490..................................... 2491 2492This is an optional function. If implemented it returns the current 2493state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 2494failures it must return a negative value and on success it must 2495return 0. 2496 2497plat\_psci\_ops.mem\_protect\_chk() 2498................................... 2499 2500This is an optional function. If implemented it checks if a memory 2501region defined by a base address ``base`` and with a size of ``length`` 2502bytes is protected by ``MEM_PROTECT``. If the region is protected 2503then it must return 0, otherwise it must return a negative number. 2504 2505Interrupt Management framework (in BL31) 2506---------------------------------------- 2507 2508BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 2509generated in either security state and targeted to EL1 or EL2 in the non-secure 2510state or EL3/S-EL1 in the secure state. The design of this framework is 2511described in the `IMF Design Guide`_ 2512 2513A platform should export the following APIs to support the IMF. The following 2514text briefly describes each api and its implementation in ARM standard 2515platforms. The API implementation depends upon the type of interrupt controller 2516present in the platform. ARM standard platform layer supports both 2517`ARM Generic Interrupt Controller version 2.0 (GICv2)`_ 2518and `3.0 (GICv3)`_. Juno builds the ARM 2519Standard layer to use GICv2 and the FVP can be configured to use either GICv2 or 2520GICv3 depending on the build flag ``FVP_USE_GIC_DRIVER`` (See FVP platform 2521specific build options in `User Guide`_ for more details). 2522 2523See also: `Interrupt Controller Abstraction APIs`__. 2524 2525.. __: platform-interrupt-controller-API.rst 2526 2527Function : plat\_interrupt\_type\_to\_line() [mandatory] 2528~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2529 2530:: 2531 2532 Argument : uint32_t, uint32_t 2533 Return : uint32_t 2534 2535The ARM processor signals an interrupt exception either through the IRQ or FIQ 2536interrupt line. The specific line that is signaled depends on how the interrupt 2537controller (IC) reports different interrupt types from an execution context in 2538either security state. The IMF uses this API to determine which interrupt line 2539the platform IC uses to signal each type of interrupt supported by the framework 2540from a given security state. This API must be invoked at EL3. 2541 2542The first parameter will be one of the ``INTR_TYPE_*`` values (see 2543`IMF Design Guide`_) indicating the target type of the interrupt, the second parameter is the 2544security state of the originating execution context. The return result is the 2545bit position in the ``SCR_EL3`` register of the respective interrupt trap: IRQ=1, 2546FIQ=2. 2547 2548In the case of ARM standard platforms using GICv2, S-EL1 interrupts are 2549configured as FIQs and Non-secure interrupts as IRQs from either security 2550state. 2551 2552In the case of ARM standard platforms using GICv3, the interrupt line to be 2553configured depends on the security state of the execution context when the 2554interrupt is signalled and are as follows: 2555 2556- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 2557 NS-EL0/1/2 context. 2558- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 2559 in the NS-EL0/1/2 context. 2560- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 2561 context. 2562 2563Function : plat\_ic\_get\_pending\_interrupt\_type() [mandatory] 2564~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2565 2566:: 2567 2568 Argument : void 2569 Return : uint32_t 2570 2571This API returns the type of the highest priority pending interrupt at the 2572platform IC. The IMF uses the interrupt type to retrieve the corresponding 2573handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 2574pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 2575``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 2576 2577In the case of ARM standard platforms using GICv2, the *Highest Priority 2578Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 2579the pending interrupt. The type of interrupt depends upon the id value as 2580follows. 2581 2582#. id < 1022 is reported as a S-EL1 interrupt 2583#. id = 1022 is reported as a Non-secure interrupt. 2584#. id = 1023 is reported as an invalid interrupt type. 2585 2586In the case of ARM standard platforms using GICv3, the system register 2587``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 2588is read to determine the id of the pending interrupt. The type of interrupt 2589depends upon the id value as follows. 2590 2591#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 2592#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 2593#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 2594#. All other interrupt id's are reported as EL3 interrupt. 2595 2596Function : plat\_ic\_get\_pending\_interrupt\_id() [mandatory] 2597~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2598 2599:: 2600 2601 Argument : void 2602 Return : uint32_t 2603 2604This API returns the id of the highest priority pending interrupt at the 2605platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 2606pending. 2607 2608In the case of ARM standard platforms using GICv2, the *Highest Priority 2609Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 2610pending interrupt. The id that is returned by API depends upon the value of 2611the id read from the interrupt controller as follows. 2612 2613#. id < 1022. id is returned as is. 2614#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 2615 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 2616 This id is returned by the API. 2617#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 2618 2619In the case of ARM standard platforms using GICv3, if the API is invoked from 2620EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 2621group 0 Register*, is read to determine the id of the pending interrupt. The id 2622that is returned by API depends upon the value of the id read from the 2623interrupt controller as follows. 2624 2625#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 2626#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 2627 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 2628 Register* is read to determine the id of the group 1 interrupt. This id 2629 is returned by the API as long as it is a valid interrupt id 2630#. If the id is any of the special interrupt identifiers, 2631 ``INTR_ID_UNAVAILABLE`` is returned. 2632 2633When the API invoked from S-EL1 for GICv3 systems, the id read from system 2634register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 2635Register*, is returned if is not equal to GIC\_SPURIOUS\_INTERRUPT (1023) else 2636``INTR_ID_UNAVAILABLE`` is returned. 2637 2638Function : plat\_ic\_acknowledge\_interrupt() [mandatory] 2639~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2640 2641:: 2642 2643 Argument : void 2644 Return : uint32_t 2645 2646This API is used by the CPU to indicate to the platform IC that processing of 2647the highest pending interrupt has begun. It should return the raw, unmodified 2648value obtained from the interrupt controller when acknowledging an interrupt. 2649The actual interrupt number shall be extracted from this raw value using the API 2650`plat_ic_get_interrupt_id()`__. 2651 2652.. __: platform-interrupt-controller-API.rst#function-unsigned-int-plat-ic-get-interrupt-id-unsigned-int-raw-optional 2653 2654This function in ARM standard platforms using GICv2, reads the *Interrupt 2655Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 2656priority pending interrupt from pending to active in the interrupt controller. 2657It returns the value read from the ``GICC_IAR``, unmodified. 2658 2659In the case of ARM standard platforms using GICv3, if the API is invoked 2660from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 2661Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 2662reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 2663group 1*. The read changes the state of the highest pending interrupt from 2664pending to active in the interrupt controller. The value read is returned 2665unmodified. 2666 2667The TSP uses this API to start processing of the secure physical timer 2668interrupt. 2669 2670Function : plat\_ic\_end\_of\_interrupt() [mandatory] 2671~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2672 2673:: 2674 2675 Argument : uint32_t 2676 Return : void 2677 2678This API is used by the CPU to indicate to the platform IC that processing of 2679the interrupt corresponding to the id (passed as the parameter) has 2680finished. The id should be the same as the id returned by the 2681``plat_ic_acknowledge_interrupt()`` API. 2682 2683ARM standard platforms write the id to the *End of Interrupt Register* 2684(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 2685system register in case of GICv3 depending on where the API is invoked from, 2686EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 2687controller. 2688 2689The TSP uses this API to finish processing of the secure physical timer 2690interrupt. 2691 2692Function : plat\_ic\_get\_interrupt\_type() [mandatory] 2693~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2694 2695:: 2696 2697 Argument : uint32_t 2698 Return : uint32_t 2699 2700This API returns the type of the interrupt id passed as the parameter. 2701``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 2702interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 2703returned depending upon how the interrupt has been configured by the platform 2704IC. This API must be invoked at EL3. 2705 2706ARM standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 2707and Non-secure interrupts as Group1 interrupts. It reads the group value 2708corresponding to the interrupt id from the relevant *Interrupt Group Register* 2709(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 2710 2711In the case of ARM standard platforms using GICv3, both the *Interrupt Group 2712Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 2713(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 2714as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 2715 2716Crash Reporting mechanism (in BL31) 2717----------------------------------- 2718 2719NOTE: This section assumes that your platform is enabling the MULTI_CONSOLE_API 2720flag in its platform.mk. Not using this flag is deprecated for new platforms. 2721 2722BL31 implements a crash reporting mechanism which prints the various registers 2723of the CPU to enable quick crash analysis and debugging. By default, the 2724definitions in ``plat/common/aarch64/platform\_helpers.S`` will cause the crash 2725output to be routed over the normal console infrastructure and get printed on 2726consoles configured to output in crash state. ``console_set_scope()`` can be 2727used to control whether a console is used for crash output. 2728 2729In some cases (such as debugging very early crashes that happen before the 2730normal boot console can be set up), platforms may want to control crash output 2731more explicitly. For these, the following functions can be overridden by 2732platform code. They are executed outside of a C environment and without a stack. 2733 2734Function : plat\_crash\_console\_init 2735~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2736 2737:: 2738 2739 Argument : void 2740 Return : int 2741 2742This API is used by the crash reporting mechanism to initialize the crash 2743console. It must only use the general purpose registers x0 through x7 to do the 2744initialization and returns 1 on success. 2745 2746If you are trying to debug crashes before the console driver would normally get 2747registered, you can use this to register a driver from assembly with hardcoded 2748parameters. For example, you could register the 16550 driver like this: 2749 2750:: 2751 2752 .section .data.crash_console /* Reserve space for console structure */ 2753 crash_console: 2754 .zero 6 * 8 /* console_16550_t has 6 8-byte words */ 2755 func plat_crash_console_init 2756 ldr x0, =YOUR_16550_BASE_ADDR 2757 ldr x1, =YOUR_16550_SRCCLK_IN_HZ 2758 ldr x2, =YOUR_16550_TARGET_BAUD_RATE 2759 adrp x3, crash_console 2760 add x3, x3, :lo12:crash_console 2761 b console_16550_register /* tail call, returns 1 on success */ 2762 endfunc plat_crash_console_init 2763 2764If you're trying to debug crashes in BL1, you can call the console_xxx_core_init 2765function exported by some console drivers from here. 2766 2767Function : plat\_crash\_console\_putc 2768~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2769 2770:: 2771 2772 Argument : int 2773 Return : int 2774 2775This API is used by the crash reporting mechanism to print a character on the 2776designated crash console. It must only use general purpose registers x1 and 2777x2 to do its work. The parameter and the return value are in general purpose 2778register x0. 2779 2780If you have registered a normal console driver in ``plat_crash_console_init``, 2781you can keep the default implementation here (which calls ``console_putc()``). 2782 2783If you're trying to debug crashes in BL1, you can call the console_xxx_core_putc 2784function exported by some console drivers from here. 2785 2786Function : plat\_crash\_console\_flush 2787~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2788 2789:: 2790 2791 Argument : void 2792 Return : int 2793 2794This API is used by the crash reporting mechanism to force write of all buffered 2795data on the designated crash console. It should only use general purpose 2796registers x0 through x5 to do its work. The return value is 0 on successful 2797completion; otherwise the return value is -1. 2798 2799If you have registered a normal console driver in ``plat_crash_console_init``, 2800you can keep the default implementation here (which calls ``console_flush()``). 2801 2802If you're trying to debug crashes in BL1, you can call the console_xx_core_flush 2803function exported by some console drivers from here. 2804 2805Build flags 2806----------- 2807 2808- **ENABLE\_PLAT\_COMPAT** 2809 All the platforms ports conforming to this API specification should define 2810 the build flag ``ENABLE_PLAT_COMPAT`` to 0 as the compatibility layer should 2811 be disabled. For more details on compatibility layer, refer 2812 `Migration Guide`_. 2813 2814There are some build flags which can be defined by the platform to control 2815inclusion or exclusion of certain BL stages from the FIP image. These flags 2816need to be defined in the platform makefile which will get included by the 2817build system. 2818 2819- **NEED\_BL33** 2820 By default, this flag is defined ``yes`` by the build system and ``BL33`` 2821 build option should be supplied as a build option. The platform has the 2822 option of excluding the BL33 image in the ``fip`` image by defining this flag 2823 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 2824 are used, this flag will be set to ``no`` automatically. 2825 2826C Library 2827--------- 2828 2829To avoid subtle toolchain behavioral dependencies, the header files provided 2830by the compiler are not used. The software is built with the ``-nostdinc`` flag 2831to ensure no headers are included from the toolchain inadvertently. Instead the 2832required headers are included in the ARM Trusted Firmware source tree. The 2833library only contains those C library definitions required by the local 2834implementation. If more functionality is required, the needed library functions 2835will need to be added to the local implementation. 2836 2837Versions of `FreeBSD`_ headers can be found in ``include/lib/stdlib``. Some of 2838these headers have been cut down in order to simplify the implementation. In 2839order to minimize changes to the header files, the `FreeBSD`_ layout has been 2840maintained. The generic C library definitions can be found in 2841``include/lib/stdlib`` with more system and machine specific declarations in 2842``include/lib/stdlib/sys`` and ``include/lib/stdlib/machine``. 2843 2844The local C library implementations can be found in ``lib/stdlib``. In order to 2845extend the C library these files may need to be modified. It is recommended to 2846use a release version of `FreeBSD`_ as a starting point. 2847 2848The C library header files in the `FreeBSD`_ source tree are located in the 2849``include`` and ``sys/sys`` directories. `FreeBSD`_ machine specific definitions 2850can be found in the ``sys/<machine-type>`` directories. These files define things 2851like 'the size of a pointer' and 'the range of an integer'. Since an AArch64 2852port for `FreeBSD`_ does not yet exist, the machine specific definitions are 2853based on existing machine types with similar properties (for example SPARC64). 2854 2855Where possible, C library function implementations were taken from `FreeBSD`_ 2856as found in the ``lib/libc`` directory. 2857 2858A copy of the `FreeBSD`_ sources can be downloaded with ``git``. 2859 2860:: 2861 2862 git clone git://github.com/freebsd/freebsd.git -b origin/release/9.2.0 2863 2864Storage abstraction layer 2865------------------------- 2866 2867In order to improve platform independence and portability an storage abstraction 2868layer is used to load data from non-volatile platform storage. 2869 2870Each platform should register devices and their drivers via the Storage layer. 2871These drivers then need to be initialized by bootloader phases as 2872required in their respective ``blx_platform_setup()`` functions. Currently 2873storage access is only required by BL1 and BL2 phases. The ``load_image()`` 2874function uses the storage layer to access non-volatile platform storage. 2875 2876It is mandatory to implement at least one storage driver. For the ARM 2877development platforms the Firmware Image Package (FIP) driver is provided as 2878the default means to load data from storage (see the "Firmware Image Package" 2879section in the `User Guide`_). The storage layer is described in the header file 2880``include/drivers/io/io_storage.h``. The implementation of the common library 2881is in ``drivers/io/io_storage.c`` and the driver files are located in 2882``drivers/io/``. 2883 2884Each IO driver must provide ``io_dev_*`` structures, as described in 2885``drivers/io/io_driver.h``. These are returned via a mandatory registration 2886function that is called on platform initialization. The semi-hosting driver 2887implementation in ``io_semihosting.c`` can be used as an example. 2888 2889The Storage layer provides mechanisms to initialize storage devices before 2890IO operations are called. The basic operations supported by the layer 2891include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 2892Drivers do not have to implement all operations, but each platform must 2893provide at least one driver for a device capable of supporting generic 2894operations such as loading a bootloader image. 2895 2896The current implementation only allows for known images to be loaded by the 2897firmware. These images are specified by using their identifiers, as defined in 2898[include/plat/common/platform\_def.h] (or a separate header file included from 2899there). The platform layer (``plat_get_image_source()``) then returns a reference 2900to a device and a driver-specific ``spec`` which will be understood by the driver 2901to allow access to the image data. 2902 2903The layer is designed in such a way that is it possible to chain drivers with 2904other drivers. For example, file-system drivers may be implemented on top of 2905physical block devices, both represented by IO devices with corresponding 2906drivers. In such a case, the file-system "binding" with the block device may 2907be deferred until the file-system device is initialised. 2908 2909The abstraction currently depends on structures being statically allocated 2910by the drivers and callers, as the system does not yet provide a means of 2911dynamically allocating memory. This may also have the affect of limiting the 2912amount of open resources per driver. 2913 2914-------------- 2915 2916*Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.* 2917 2918.. _Migration Guide: platform-migration-guide.rst 2919.. _include/plat/common/platform.h: ../include/plat/common/platform.h 2920.. _include/plat/arm/common/plat\_arm.h: ../include/plat/arm/common/plat_arm.h%5D 2921.. _User Guide: user-guide.rst 2922.. _include/plat/common/common\_def.h: ../include/plat/common/common_def.h 2923.. _include/plat/arm/common/arm\_def.h: ../include/plat/arm/common/arm_def.h 2924.. _plat/common/aarch64/platform\_mp\_stack.S: ../plat/common/aarch64/platform_mp_stack.S 2925.. _plat/common/aarch64/platform\_up\_stack.S: ../plat/common/aarch64/platform_up_stack.S 2926.. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160 2927.. _Power Domain Topology Design: psci-pd-tree.rst 2928.. _include/common/bl\_common.h: ../include/common/bl_common.h 2929.. _include/lib/aarch32/arch.h: ../include/lib/aarch32/arch.h 2930.. _Firmware Design: firmware-design.rst 2931.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf 2932.. _plat/arm/board/fvp/fvp\_pm.c: ../plat/arm/board/fvp/fvp_pm.c 2933.. _IMF Design Guide: interrupt-framework-design.rst 2934.. _ARM Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 2935.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 2936.. _FreeBSD: http://www.freebsd.org 2937