1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_gic.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <delay_timer.h> 14 #include <dw_ufs.h> 15 #include <errno.h> 16 #include <generic_delay_timer.h> 17 #include <gicv2.h> 18 #include <hi3660.h> 19 #include <mmio.h> 20 #include <platform.h> 21 #include <platform_def.h> 22 #include <string.h> 23 #include <tbbr/tbbr_img_desc.h> 24 #include <ufs.h> 25 26 #include "../../bl1/bl1_private.h" 27 #include "hikey960_def.h" 28 #include "hikey960_private.h" 29 30 enum { 31 BOOT_MODE_RECOVERY = 0, 32 BOOT_MODE_NORMAL, 33 BOOT_MODE_MASK = 1, 34 }; 35 36 /* 37 * Declarations of linker defined symbols which will help us find the layout 38 * of trusted RAM 39 */ 40 extern unsigned long __COHERENT_RAM_START__; 41 extern unsigned long __COHERENT_RAM_END__; 42 43 /* 44 * The next 2 constants identify the extents of the coherent memory region. 45 * These addresses are used by the MMU setup code and therefore they must be 46 * page-aligned. It is the responsibility of the linker script to ensure that 47 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 48 * page-aligned addresses. 49 */ 50 #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 51 #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 52 53 /* Data structure which holds the extents of the trusted RAM for BL1 */ 54 static meminfo_t bl1_tzram_layout; 55 56 /****************************************************************************** 57 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 58 * interrupts. 59 *****************************************************************************/ 60 const unsigned int g0_interrupt_array[] = { 61 IRQ_SEC_PHY_TIMER, 62 IRQ_SEC_SGI_0 63 }; 64 65 const gicv2_driver_data_t hikey960_gic_data = { 66 .gicd_base = GICD_REG_BASE, 67 .gicc_base = GICC_REG_BASE, 68 .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), 69 .g0_interrupt_array = g0_interrupt_array, 70 }; 71 72 meminfo_t *bl1_plat_sec_mem_layout(void) 73 { 74 return &bl1_tzram_layout; 75 } 76 77 /******************************************************************************* 78 * Function that takes a memory layout into which BL2 has been loaded and 79 * populates a new memory layout for BL2 that ensures that BL1's data sections 80 * resident in secure RAM are not visible to BL2. 81 ******************************************************************************/ 82 void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, 83 meminfo_t *bl2_mem_layout) 84 { 85 86 assert(bl1_mem_layout != NULL); 87 assert(bl2_mem_layout != NULL); 88 89 /* 90 * Cannot remove BL1 RW data from the scope of memory visible to BL2 91 * like arm platforms because they overlap in hikey960 92 */ 93 bl2_mem_layout->total_base = BL2_BASE; 94 bl2_mem_layout->total_size = NS_BL1U_LIMIT - BL2_BASE; 95 96 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); 97 } 98 99 /* 100 * Perform any BL1 specific platform actions. 101 */ 102 void bl1_early_platform_setup(void) 103 { 104 unsigned int id, uart_base; 105 106 generic_delay_timer_init(); 107 hikey960_read_boardid(&id); 108 if (id == 5300) 109 uart_base = PL011_UART5_BASE; 110 else 111 uart_base = PL011_UART6_BASE; 112 /* Initialize the console to provide early debug support */ 113 console_init(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 114 115 /* Allow BL1 to see the whole Trusted RAM */ 116 bl1_tzram_layout.total_base = BL1_RW_BASE; 117 bl1_tzram_layout.total_size = BL1_RW_SIZE; 118 119 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 120 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */ 121 } 122 123 /* 124 * Perform the very early platform specific architecture setup here. At the 125 * moment this only does basic initialization. Later architectural setup 126 * (bl1_arch_setup()) does not do anything platform specific. 127 */ 128 void bl1_plat_arch_setup(void) 129 { 130 hikey960_init_mmu_el3(bl1_tzram_layout.total_base, 131 bl1_tzram_layout.total_size, 132 BL1_RO_BASE, 133 BL1_RO_LIMIT, 134 BL1_COHERENT_RAM_BASE, 135 BL1_COHERENT_RAM_LIMIT); 136 } 137 138 static void hikey960_clk_init(void) 139 { 140 /* change ldi0 sel to ppll2 */ 141 mmio_write_32(0xfff350b4, 0xf0002000); 142 /* ldi0 20' */ 143 mmio_write_32(0xfff350bc, 0xfc004c00); 144 } 145 146 static void hikey960_pmu_init(void) 147 { 148 /* clear np_xo_abb_dig_START bit in PMIC_CLK_TOP_CTRL7 register */ 149 mmio_clrbits_32(PMU_SSI0_CLK_TOP_CTRL7_REG, NP_XO_ABB_DIG); 150 } 151 152 static void hikey960_enable_ppll3(void) 153 { 154 /* enable ppll3 */ 155 mmio_write_32(PMC_PPLL3_CTRL0_REG, 0x4904305); 156 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x2300000); 157 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x6300000); 158 } 159 160 static void bus_idle_clear(unsigned int value) 161 { 162 unsigned int pmc_value, value1, value2; 163 int timeout = 100; 164 165 pmc_value = value << 16; 166 pmc_value &= ~value; 167 mmio_write_32(PMC_NOC_POWER_IDLEREQ_REG, pmc_value); 168 169 for (;;) { 170 value1 = (unsigned int)mmio_read_32(PMC_NOC_POWER_IDLEACK_REG); 171 value2 = (unsigned int)mmio_read_32(PMC_NOC_POWER_IDLE_REG); 172 if (((value1 & value) == 0) && ((value2 & value) == 0)) 173 break; 174 udelay(1); 175 timeout--; 176 if (timeout <= 0) { 177 WARN("%s timeout\n", __func__); 178 break; 179 } 180 } 181 } 182 183 static void set_vivobus_power_up(void) 184 { 185 /* clk enable */ 186 mmio_write_32(CRG_CLKDIV20_REG, 0x00020002); 187 mmio_write_32(CRG_PEREN0_REG, 0x00001000); 188 } 189 190 static void set_dss_power_up(void) 191 { 192 /* set edc0 133MHz = 1600MHz / 12 */ 193 mmio_write_32(CRG_CLKDIV5_REG, 0x003f000b); 194 /* set ldi0 ppl0 */ 195 mmio_write_32(CRG_CLKDIV3_REG, 0xf0001000); 196 /* set ldi0 133MHz, 1600MHz / 12 */ 197 mmio_write_32(CRG_CLKDIV5_REG, 0xfc002c00); 198 /* mtcmos on */ 199 mmio_write_32(CRG_PERPWREN_REG, 0x00000020); 200 udelay(100); 201 /* DISP CRG */ 202 mmio_write_32(CRG_PERRSTDIS4_REG, 0x00000010); 203 /* clk enable */ 204 mmio_write_32(CRG_CLKDIV18_REG, 0x01400140); 205 mmio_write_32(CRG_PEREN0_REG, 0x00002000); 206 mmio_write_32(CRG_PEREN3_REG, 0x0003b000); 207 udelay(1); 208 /* clk disable */ 209 mmio_write_32(CRG_PERDIS3_REG, 0x0003b000); 210 mmio_write_32(CRG_PERDIS0_REG, 0x00002000); 211 mmio_write_32(CRG_CLKDIV18_REG, 0x01400000); 212 udelay(1); 213 /* iso disable */ 214 mmio_write_32(CRG_ISODIS_REG, 0x00000040); 215 /* unreset */ 216 mmio_write_32(CRG_PERRSTDIS4_REG, 0x00000006); 217 mmio_write_32(CRG_PERRSTDIS3_REG, 0x00000c00); 218 /* clk enable */ 219 mmio_write_32(CRG_CLKDIV18_REG, 0x01400140); 220 mmio_write_32(CRG_PEREN0_REG, 0x00002000); 221 mmio_write_32(CRG_PEREN3_REG, 0x0003b000); 222 /* bus idle clear */ 223 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_DSS); 224 /* set edc0 400MHz for 2K 1600MHz / 4 */ 225 mmio_write_32(CRG_CLKDIV5_REG, 0x003f0003); 226 /* set ldi 266MHz, 1600MHz / 6 */ 227 mmio_write_32(CRG_CLKDIV5_REG, 0xfc001400); 228 } 229 230 static void set_vcodec_power_up(void) 231 { 232 /* clk enable */ 233 mmio_write_32(CRG_CLKDIV20_REG, 0x00040004); 234 mmio_write_32(CRG_PEREN0_REG, 0x00000060); 235 mmio_write_32(CRG_PEREN2_REG, 0x10000000); 236 /* unreset */ 237 mmio_write_32(CRG_PERRSTDIS0_REG, 0x00000018); 238 /* bus idle clear */ 239 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_VCODEC); 240 } 241 242 static void set_vdec_power_up(void) 243 { 244 /* mtcmos on */ 245 mmio_write_32(CRG_PERPWREN_REG, 0x00000004); 246 udelay(100); 247 /* clk enable */ 248 mmio_write_32(CRG_CLKDIV18_REG, 0x80008000); 249 mmio_write_32(CRG_PEREN2_REG, 0x20080000); 250 mmio_write_32(CRG_PEREN3_REG, 0x00000800); 251 udelay(1); 252 /* clk disable */ 253 mmio_write_32(CRG_PERDIS3_REG, 0x00000800); 254 mmio_write_32(CRG_PERDIS2_REG, 0x20080000); 255 mmio_write_32(CRG_CLKDIV18_REG, 0x80000000); 256 udelay(1); 257 /* iso disable */ 258 mmio_write_32(CRG_ISODIS_REG, 0x00000004); 259 /* unreset */ 260 mmio_write_32(CRG_PERRSTDIS3_REG, 0x00000200); 261 /* clk enable */ 262 mmio_write_32(CRG_CLKDIV18_REG, 0x80008000); 263 mmio_write_32(CRG_PEREN2_REG, 0x20080000); 264 mmio_write_32(CRG_PEREN3_REG, 0x00000800); 265 /* bus idle clear */ 266 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_VDEC); 267 } 268 269 static void set_venc_power_up(void) 270 { 271 /* set venc ppll3 */ 272 mmio_write_32(CRG_CLKDIV8_REG, 0x18001000); 273 /* set venc 258MHz, 1290MHz / 5 */ 274 mmio_write_32(CRG_CLKDIV8_REG, 0x07c00100); 275 /* mtcmos on */ 276 mmio_write_32(CRG_PERPWREN_REG, 0x00000002); 277 udelay(100); 278 /* clk enable */ 279 mmio_write_32(CRG_CLKDIV19_REG, 0x00010001); 280 mmio_write_32(CRG_PEREN2_REG, 0x40000100); 281 mmio_write_32(CRG_PEREN3_REG, 0x00000400); 282 udelay(1); 283 /* clk disable */ 284 mmio_write_32(CRG_PERDIS3_REG, 0x00000400); 285 mmio_write_32(CRG_PERDIS2_REG, 0x40000100); 286 mmio_write_32(CRG_CLKDIV19_REG, 0x00010000); 287 udelay(1); 288 /* iso disable */ 289 mmio_write_32(CRG_ISODIS_REG, 0x00000002); 290 /* unreset */ 291 mmio_write_32(CRG_PERRSTDIS3_REG, 0x00000100); 292 /* clk enable */ 293 mmio_write_32(CRG_CLKDIV19_REG, 0x00010001); 294 mmio_write_32(CRG_PEREN2_REG, 0x40000100); 295 mmio_write_32(CRG_PEREN3_REG, 0x00000400); 296 /* bus idle clear */ 297 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_VENC); 298 /* set venc 645MHz, 1290MHz / 2 */ 299 mmio_write_32(CRG_CLKDIV8_REG, 0x07c00040); 300 } 301 302 static void set_isp_power_up(void) 303 { 304 /* mtcmos on */ 305 mmio_write_32(CRG_PERPWREN_REG, 0x00000001); 306 udelay(100); 307 /* clk enable */ 308 mmio_write_32(CRG_CLKDIV18_REG, 0x70007000); 309 mmio_write_32(CRG_CLKDIV20_REG, 0x00100010); 310 mmio_write_32(CRG_PEREN5_REG, 0x01000010); 311 mmio_write_32(CRG_PEREN3_REG, 0x0bf00000); 312 udelay(1); 313 /* clk disable */ 314 mmio_write_32(CRG_PERDIS5_REG, 0x01000010); 315 mmio_write_32(CRG_PERDIS3_REG, 0x0bf00000); 316 mmio_write_32(CRG_CLKDIV18_REG, 0x70000000); 317 mmio_write_32(CRG_CLKDIV20_REG, 0x00100000); 318 udelay(1); 319 /* iso disable */ 320 mmio_write_32(CRG_ISODIS_REG, 0x00000001); 321 /* unreset */ 322 mmio_write_32(CRG_ISP_SEC_RSTDIS_REG, 0x0000002f); 323 /* clk enable */ 324 mmio_write_32(CRG_CLKDIV18_REG, 0x70007000); 325 mmio_write_32(CRG_CLKDIV20_REG, 0x00100010); 326 mmio_write_32(CRG_PEREN5_REG, 0x01000010); 327 mmio_write_32(CRG_PEREN3_REG, 0x0bf00000); 328 /* bus idle clear */ 329 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_ISP); 330 /* csi clk enable */ 331 mmio_write_32(CRG_PEREN3_REG, 0x00700000); 332 } 333 334 static void set_ivp_power_up(void) 335 { 336 /* set ivp ppll0 */ 337 mmio_write_32(CRG_CLKDIV0_REG, 0xc0000000); 338 /* set ivp 267MHz, 1600MHz / 6 */ 339 mmio_write_32(CRG_CLKDIV0_REG, 0x3c001400); 340 /* mtcmos on */ 341 mmio_write_32(CRG_PERPWREN_REG, 0x00200000); 342 udelay(100); 343 /* IVP CRG unreset */ 344 mmio_write_32(CRG_IVP_SEC_RSTDIS_REG, 0x00000001); 345 /* clk enable */ 346 mmio_write_32(CRG_CLKDIV20_REG, 0x02000200); 347 mmio_write_32(CRG_PEREN4_REG, 0x000000a8); 348 udelay(1); 349 /* clk disable */ 350 mmio_write_32(CRG_PERDIS4_REG, 0x000000a8); 351 mmio_write_32(CRG_CLKDIV20_REG, 0x02000000); 352 udelay(1); 353 /* iso disable */ 354 mmio_write_32(CRG_ISODIS_REG, 0x01000000); 355 /* unreset */ 356 mmio_write_32(CRG_IVP_SEC_RSTDIS_REG, 0x00000002); 357 /* clk enable */ 358 mmio_write_32(CRG_CLKDIV20_REG, 0x02000200); 359 mmio_write_32(CRG_PEREN4_REG, 0x000000a8); 360 /* bus idle clear */ 361 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_IVP); 362 /* set ivp 533MHz, 1600MHz / 3 */ 363 mmio_write_32(CRG_CLKDIV0_REG, 0x3c000800); 364 } 365 366 static void set_audio_power_up(void) 367 { 368 unsigned int ret; 369 int timeout = 100; 370 /* mtcmos on */ 371 mmio_write_32(SCTRL_SCPWREN_REG, 0x00000001); 372 udelay(100); 373 /* clk enable */ 374 mmio_write_32(CRG_CLKDIV19_REG, 0x80108010); 375 mmio_write_32(SCTRL_SCCLKDIV2_REG, 0x00010001); 376 mmio_write_32(SCTRL_SCPEREN0_REG, 0x0c000000); 377 mmio_write_32(CRG_PEREN0_REG, 0x04000000); 378 mmio_write_32(CRG_PEREN5_REG, 0x00000080); 379 mmio_write_32(SCTRL_SCPEREN1_REG, 0x0000000f); 380 udelay(1); 381 /* clk disable */ 382 mmio_write_32(SCTRL_SCPERDIS1_REG, 0x0000000f); 383 mmio_write_32(SCTRL_SCPERDIS0_REG, 0x0c000000); 384 mmio_write_32(CRG_PERDIS5_REG, 0x00000080); 385 mmio_write_32(CRG_PERDIS0_REG, 0x04000000); 386 mmio_write_32(SCTRL_SCCLKDIV2_REG, 0x00010000); 387 mmio_write_32(CRG_CLKDIV19_REG, 0x80100000); 388 udelay(1); 389 /* iso disable */ 390 mmio_write_32(SCTRL_SCISODIS_REG, 0x00000001); 391 udelay(1); 392 /* unreset */ 393 mmio_write_32(SCTRL_PERRSTDIS1_SEC_REG, 0x00000001); 394 mmio_write_32(SCTRL_SCPERRSTDIS0_REG, 0x00000780); 395 /* clk enable */ 396 mmio_write_32(CRG_CLKDIV19_REG, 0x80108010); 397 mmio_write_32(SCTRL_SCCLKDIV2_REG, 0x00010001); 398 mmio_write_32(SCTRL_SCPEREN0_REG, 0x0c000000); 399 mmio_write_32(CRG_PEREN0_REG, 0x04000000); 400 mmio_write_32(CRG_PEREN5_REG, 0x00000080); 401 mmio_write_32(SCTRL_SCPEREN1_REG, 0x0000000f); 402 /* bus idle clear */ 403 mmio_write_32(SCTRL_SCPERCTRL7_REG, 0x00040000); 404 for (;;) { 405 ret = mmio_read_32(SCTRL_SCPERSTAT6_REG); 406 if (((ret & (1 << 5)) == 0) && ((ret & (1 << 8)) == 0)) 407 break; 408 udelay(1); 409 timeout--; 410 if (timeout <= 0) { 411 WARN("%s timeout\n", __func__); 412 break; 413 } 414 } 415 mmio_write_32(ASP_CFG_MMBUF_CTRL_REG, 0x00ff0000); 416 } 417 418 static void set_pcie_power_up(void) 419 { 420 /* mtcmos on */ 421 mmio_write_32(SCTRL_SCPWREN_REG, 0x00000010); 422 udelay(100); 423 /* clk enable */ 424 mmio_write_32(SCTRL_SCCLKDIV6_REG, 0x08000800); 425 mmio_write_32(SCTRL_SCPEREN2_REG, 0x00104000); 426 mmio_write_32(CRG_PEREN7_REG, 0x000003a0); 427 udelay(1); 428 /* clk disable */ 429 mmio_write_32(SCTRL_SCPERDIS2_REG, 0x00104000); 430 mmio_write_32(CRG_PERDIS7_REG, 0x000003a0); 431 mmio_write_32(SCTRL_SCCLKDIV6_REG, 0x08000000); 432 udelay(1); 433 /* iso disable */ 434 mmio_write_32(SCTRL_SCISODIS_REG, 0x00000030); 435 /* unreset */ 436 mmio_write_32(CRG_PERRSTDIS3_REG, 0x8c000000); 437 /* clk enable */ 438 mmio_write_32(SCTRL_SCCLKDIV6_REG, 0x08000800); 439 mmio_write_32(SCTRL_SCPEREN2_REG, 0x00104000); 440 mmio_write_32(CRG_PEREN7_REG, 0x000003a0); 441 } 442 443 static void ispfunc_enable(void) 444 { 445 /* enable ispfunc. Otherwise powerup isp_srt causes exception. */ 446 mmio_write_32(0xfff35000, 0x00000008); 447 mmio_write_32(0xfff35460, 0xc004ffff); 448 mmio_write_32(0xfff35030, 0x02000000); 449 mdelay(10); 450 } 451 452 static void isps_control_clock(int flag) 453 { 454 unsigned int ret; 455 456 /* flag: 0 -- disable clock, 1 -- enable clock */ 457 if (flag) { 458 ret = mmio_read_32(0xe8420364); 459 ret |= 1; 460 mmio_write_32(0xe8420364, ret); 461 } else { 462 ret = mmio_read_32(0xe8420364); 463 ret &= ~1; 464 mmio_write_32(0xe8420364, ret); 465 } 466 } 467 468 static void set_isp_srt_power_up(void) 469 { 470 unsigned int ret; 471 472 ispfunc_enable(); 473 /* reset */ 474 mmio_write_32(0xe8420374, 0x00000001); 475 mmio_write_32(0xe8420350, 0x00000000); 476 mmio_write_32(0xe8420358, 0x00000000); 477 /* mtcmos on */ 478 mmio_write_32(0xfff35150, 0x00400000); 479 udelay(100); 480 /* clk enable */ 481 isps_control_clock(1); 482 udelay(1); 483 isps_control_clock(0); 484 udelay(1); 485 /* iso disable */ 486 mmio_write_32(0xfff35148, 0x08000000); 487 /* unreset */ 488 ret = mmio_read_32(0xe8420374); 489 ret &= ~0x1; 490 mmio_write_32(0xe8420374, ret); 491 /* clk enable */ 492 isps_control_clock(1); 493 /* enable clock gating for accessing csi registers */ 494 mmio_write_32(0xe8420010, ~0); 495 } 496 497 static void hikey960_regulator_enable(void) 498 { 499 set_vivobus_power_up(); 500 hikey960_enable_ppll3(); 501 set_dss_power_up(); 502 set_vcodec_power_up(); 503 set_vdec_power_up(); 504 set_venc_power_up(); 505 set_isp_power_up(); 506 set_ivp_power_up(); 507 set_audio_power_up(); 508 set_pcie_power_up(); 509 set_isp_srt_power_up(); 510 511 /* set ISP_CORE_CTRL_S to unsecure mode */ 512 mmio_write_32(0xe8583800, 0x7); 513 /* set ISP_SUB_CTRL_S to unsecure mode */ 514 mmio_write_32(0xe8583804, 0xf); 515 } 516 517 static void hikey960_ufs_reset(void) 518 { 519 unsigned int data, mask; 520 521 mmio_write_32(CRG_PERDIS7_REG, 1 << 14); 522 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 523 do { 524 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 525 } while (data & BIT_SYSCTRL_REF_CLOCK_EN); 526 /* use abb clk */ 527 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); 528 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); 529 mmio_write_32(PCTRL_PERI_CTRL3_REG, (1 << 0) | (1 << 16)); 530 mdelay(1); 531 mmio_write_32(CRG_PEREN7_REG, 1 << 14); 532 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 533 534 mmio_write_32(CRG_PERRSTEN3_REG, PERI_UFS_BIT); 535 do { 536 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 537 } while ((data & PERI_UFS_BIT) == 0); 538 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); 539 mdelay(1); 540 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); 541 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 542 MASK_UFS_DEVICE_RESET); 543 /* clear SC_DIV_UFS_PERIBUS */ 544 mask = SC_DIV_UFS_PERIBUS << 16; 545 mmio_write_32(CRG_CLKDIV17_REG, mask); 546 /* set SC_DIV_UFSPHY_CFG(3) */ 547 mask = SC_DIV_UFSPHY_CFG_MASK << 16; 548 data = SC_DIV_UFSPHY_CFG(3); 549 mmio_write_32(CRG_CLKDIV16_REG, mask | data); 550 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 551 data &= ~MASK_SYSCTRL_CFG_CLOCK_FREQ; 552 data |= 0x39; 553 mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); 554 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); 555 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, 556 MASK_UFS_CLK_GATE_BYPASS); 557 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); 558 559 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); 560 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); 561 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); 562 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); 563 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_ARST_UFS_BIT); 564 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); 565 mdelay(1); 566 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 567 MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET); 568 mdelay(20); 569 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 570 0x03300330); 571 572 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_UFS_BIT); 573 do { 574 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 575 } while (data & PERI_UFS_BIT); 576 } 577 578 static void hikey960_ufs_init(void) 579 { 580 dw_ufs_params_t ufs_params; 581 582 memset(&ufs_params, 0, sizeof(ufs_params)); 583 ufs_params.reg_base = UFS_REG_BASE; 584 ufs_params.desc_base = HIKEY960_UFS_DESC_BASE; 585 ufs_params.desc_size = HIKEY960_UFS_DESC_SIZE; 586 587 if ((ufs_params.flags & UFS_FLAGS_SKIPINIT) == 0) 588 hikey960_ufs_reset(); 589 dw_ufs_init(&ufs_params); 590 } 591 592 static void hikey960_tzc_init(void) 593 { 594 mmio_write_32(TZC_EN0_REG, 0x7fbff066); 595 mmio_write_32(TZC_EN1_REG, 0xfffff5fc); 596 mmio_write_32(TZC_EN2_REG, 0x0007005c); 597 mmio_write_32(TZC_EN3_REG, 0x37030700); 598 mmio_write_32(TZC_EN4_REG, 0xf63fefae); 599 mmio_write_32(TZC_EN5_REG, 0x000410fd); 600 mmio_write_32(TZC_EN6_REG, 0x0063ff68); 601 mmio_write_32(TZC_EN7_REG, 0x030000f3); 602 mmio_write_32(TZC_EN8_REG, 0x00000007); 603 } 604 605 static void hikey960_peri_init(void) 606 { 607 /* unreset */ 608 mmio_setbits_32(CRG_PERRSTDIS4_REG, 1); 609 } 610 611 static void hikey960_pinmux_init(void) 612 { 613 unsigned int id; 614 615 hikey960_read_boardid(&id); 616 if (id == 5301) { 617 /* hikey960 hardware v2 */ 618 /* GPIO150: LED */ 619 mmio_write_32(IOMG_FIX_006_REG, 0); 620 /* GPIO151: LED */ 621 mmio_write_32(IOMG_FIX_007_REG, 0); 622 /* GPIO189: LED */ 623 mmio_write_32(IOMG_AO_011_REG, 0); 624 /* GPIO190: LED */ 625 mmio_write_32(IOMG_AO_012_REG, 0); 626 /* GPIO46 */ 627 mmio_write_32(IOMG_044_REG, 0); 628 /* GPIO202 */ 629 mmio_write_32(IOMG_AO_023_REG, 0); 630 /* GPIO206 */ 631 mmio_write_32(IOMG_AO_026_REG, 0); 632 /* GPIO219 - PD pullup */ 633 mmio_write_32(IOMG_AO_039_REG, 0); 634 mmio_write_32(IOCG_AO_043_REG, 1 << 0); 635 } 636 /* GPIO005 - PMU SSI, 10mA */ 637 mmio_write_32(IOCG_006_REG, 2 << 4); 638 /* GPIO213 - PCIE_CLKREQ_N */ 639 mmio_write_32(IOMG_AO_033_REG, 1); 640 } 641 642 /* 643 * Function which will perform any remaining platform-specific setup that can 644 * occur after the MMU and data cache have been enabled. 645 */ 646 void bl1_platform_setup(void) 647 { 648 hikey960_clk_init(); 649 hikey960_pmu_init(); 650 hikey960_regulator_enable(); 651 hikey960_tzc_init(); 652 hikey960_peri_init(); 653 hikey960_ufs_init(); 654 hikey960_pinmux_init(); 655 hikey960_io_setup(); 656 } 657 658 /* 659 * The following function checks if Firmware update is needed, 660 * by checking if TOC in FIP image is valid or not. 661 */ 662 unsigned int bl1_plat_get_next_image_id(void) 663 { 664 unsigned int mode, ret; 665 666 mode = mmio_read_32(SCTRL_BAK_DATA0_REG); 667 switch (mode & BOOT_MODE_MASK) { 668 case BOOT_MODE_RECOVERY: 669 ret = NS_BL1U_IMAGE_ID; 670 break; 671 default: 672 WARN("Invalid boot mode is found:%d\n", mode); 673 panic(); 674 } 675 return ret; 676 } 677 678 image_desc_t *bl1_plat_get_image_desc(unsigned int image_id) 679 { 680 unsigned int index = 0; 681 682 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) { 683 if (bl1_tbbr_image_descs[index].image_id == image_id) 684 return &bl1_tbbr_image_descs[index]; 685 index++; 686 } 687 688 return NULL; 689 } 690 691 void bl1_plat_set_ep_info(unsigned int image_id, 692 entry_point_info_t *ep_info) 693 { 694 unsigned int data = 0; 695 uintptr_t tmp = HIKEY960_NS_TMP_OFFSET; 696 697 if (image_id != NS_BL1U_IMAGE_ID) 698 panic(); 699 /* Copy NS BL1U from 0x1AC1_8000 to 0x1AC9_8000 */ 700 memcpy((void *)tmp, (void *)HIKEY960_NS_IMAGE_OFFSET, 701 NS_BL1U_SIZE); 702 memcpy((void *)NS_BL1U_BASE, (void *)tmp, NS_BL1U_SIZE); 703 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE); 704 /* Initialize the GIC driver, cpu and distributor interfaces */ 705 gicv2_driver_init(&hikey960_gic_data); 706 gicv2_distif_init(); 707 gicv2_pcpu_distif_init(); 708 gicv2_cpuif_enable(); 709 /* CNTFRQ is read-only in EL1 */ 710 write_cntfrq_el0(plat_get_syscnt_freq2()); 711 data = read_cpacr_el1(); 712 do { 713 data |= 3 << 20; 714 write_cpacr_el1(data); 715 data = read_cpacr_el1(); 716 } while ((data & (3 << 20)) != (3 << 20)); 717 INFO("cpacr_el1:0x%x\n", data); 718 719 ep_info->args.arg0 = 0xffff & read_mpidr(); 720 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 721 DISABLE_ALL_EXCEPTIONS); 722 } 723