Add Raghu Krishnamurthy as a TF-A maintainer

Change-Id: I3726f42f8f3de0cd88bd77a0f9d92a710649d18c
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Prevent RAS register access from lower ELs

This patch adds a build config 'RAS_TRAP_LOWER_EL_ERR_ACCESS' to set
SCR_EL3.TERR during CPU boot. This bit enables trapping RAS register
accesses from EL1

Prevent RAS register access from lower ELs

This patch adds a build config 'RAS_TRAP_LOWER_EL_ERR_ACCESS' to set
SCR_EL3.TERR during CPU boot. This bit enables trapping RAS register
accesses from EL1 or EL2 to EL3.

RAS_TRAP_LOWER_EL_ERR_ACCESS is disabled by default.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ifb0fb0afedea7dd2a29a0b0491a1161ecd241438

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Merge "GICv3: GIC-600: Detect GIC-600 at runtime" into integration

plat/fvp: Add support for dynamic description of secure interrupts

Using the fconf framework, the Group 0 and Group 1 secure interrupt
descriptors are moved to device tree and retrieved in runtime.

plat/fvp: Add support for dynamic description of secure interrupts

Using the fconf framework, the Group 0 and Group 1 secure interrupt
descriptors are moved to device tree and retrieved in runtime. This
feature is enabled by the build flag SEC_INT_DESC_IN_FCONF.

Change-Id: I360c63a83286c7ecc2426cd1ff1b4746d61e633c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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GICv3: GIC-600: Detect GIC-600 at runtime

The only difference between GIC-500 and GIC-600 relevant to TF-A is the
differing power management sequence.
A certain GIC implementation is detectable at r

GICv3: GIC-600: Detect GIC-600 at runtime

The only difference between GIC-500 and GIC-600 relevant to TF-A is the
differing power management sequence.
A certain GIC implementation is detectable at runtime, for instance by
checking the IIDR register. Let's add that test before initiating the
GIC-600 specific sequence, so the code can be used on both GIC-600 and
GIC-500 chips alike, without deciding on a GIC chip at compile time.

This means that the GIC-500 "driver" is now redundant. To allow minimal
platform support, add a switch to disable GIC-600 support.

Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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ddr: a80x0: add DDR 32-bit mode support

This commit introduces 32-bit DDR topology map initialization.
For that purpose a new DDR32 build flag is added, with
according documentation update.

Change-

ddr: a80x0: add DDR 32-bit mode support

This commit introduces 32-bit DDR topology map initialization.
For that purpose a new DDR32 build flag is added, with
according documentation update.

Change-Id: I169ff358c2923afd984e27bc126dc551dcaefc01
Signed-off-by: Alex Leibovich <alexl@marvell.com>

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marvell: armada: add extra level in marvell platform hierarchy

This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
pla

marvell: armada: add extra level in marvell platform hierarchy

This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
plat, include/plat) are moved to the new "armada" sub-folder.

Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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Rename Cortex-Hercules to Cortex-A78

Change-Id: I89b90cbdfc8f2aa898b4f3676a4764f060f8e138
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

Add new maintainers for the project

As per the trustedfirmware.org Project Maintenance Process [1], the
current maintainers of the TF-A project have nominated some contributors
to become maintainers

Add new maintainers for the project

As per the trustedfirmware.org Project Maintenance Process [1], the
current maintainers of the TF-A project have nominated some contributors
to become maintainers themselves. List them in the maintainers.rst file
to make this official.

[1] https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/

Change-Id: Id4e3cfd12a9074f4e255087fa5dd6fa5f902845f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Merge "doc: Update the list of code owners" into integration

doc: Update the list of code owners

Extend the list of modules and assign code owners to each of them.

Change-Id: I267b87d8e239c7eff143b4c7e6ce9712fcf7101e
Signed-off-by: Sandrine Bailleux <sandrin

doc: Update the list of code owners

Extend the list of modules and assign code owners to each of them.

Change-Id: I267b87d8e239c7eff143b4c7e6ce9712fcf7101e
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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plat/arm: Introduce TC0 platform

This patch adds support for Total Compute (TC0) platform. It is an
initial port and additional features are expected to be added later.

TC0 has a SCP which brings t

plat/arm: Introduce TC0 platform

This patch adds support for Total Compute (TC0) platform. It is an
initial port and additional features are expected to be added later.

TC0 has a SCP which brings the primary Cortex-A out of reset
which starts executing BL1. TF-A optionally authenticates the SCP
ram-fw available in FIP and makes it available for SCP to copy.

Some of the major features included and tested in this platform
port include TBBR, PSCI, MHUv2 and DVFS.

Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef
Signed-off-by: Usama Arif <usama.arif@arm.com>

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Merge "plat: imx8mn: Add imx8mn basic support" into integration

Merge "Cleanup the code for TBBR CoT descriptors" into integration

Merge "doc: Fix plat_sdei_validate_entry_point() documentation" into integration

doc: Fix plat_sdei_validate_entry_point() documentation

Document the second argument of the function.
Minor rewording.

Change-Id: I190794b8cc74c99db4cfe6efc225217c32dd0774
Signed-off-by: Sandrine B

doc: Fix plat_sdei_validate_entry_point() documentation

Document the second argument of the function.
Minor rewording.

Change-Id: I190794b8cc74c99db4cfe6efc225217c32dd0774
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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doc: Fixes in PSA FF-A binding document

- Fix possible run-time ELs value and xlat-granule size.
- Remove mandatory field for stream-ids.
- Define interrupts attributes to <u32>.
- Remove mem-manage

doc: Fixes in PSA FF-A binding document

- Fix possible run-time ELs value and xlat-granule size.
- Remove mandatory field for stream-ids.
- Define interrupts attributes to <u32>.
- Remove mem-manage field.
- Add description for memory/device region attributes.

Co-authored-by: Manish Pandey <manish.pandey2@arm.com>
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I71cf4406c78eaf894fa6532f83467a6f4110b344

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SPCI is now called PSA FF-A

SPCI is renamed as PSA FF-A which stands for Platform Security
Architecture Firmware Framework for A class processors.
This patch replaces the occurrence of SPCI with PSA

SPCI is now called PSA FF-A

SPCI is renamed as PSA FF-A which stands for Platform Security
Architecture Firmware Framework for A class processors.
This patch replaces the occurrence of SPCI with PSA FF-A(in documents)
or simply FFA(in code).

Change-Id: I4ab10adb9ffeef1ff784641dfafd99f515133760
Signed-off-by: J-Alves <joao.alves@arm.com>

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plat: imx8mn: Add imx8mn basic support

Add imx8mn basic support

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ibdfcc87700bfaf980e429f3a5fa08515218ae78d

Enable v8.6 WFE trap delays

This patch enables the v8.6 extension to add a delay before WFE traps
are taken. A weak hook plat_arm_set_twedel_scr_el3 has been added in
plat/common/aarch64/plat_common

Enable v8.6 WFE trap delays

This patch enables the v8.6 extension to add a delay before WFE traps
are taken. A weak hook plat_arm_set_twedel_scr_el3 has been added in
plat/common/aarch64/plat_common.c that disables this feature by default
but platform-specific code can override it when needed.

The only hook provided sets the TWED fields in SCR_EL3, there are similar
fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to control WFE trap delays in
lower ELs but these should be configured by code running at EL2 and/or EL1
depending on the platform configuration and is outside the scope of TF-A.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I0a9bb814205efeab693a3d0a0623e62144abba2d

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Cleanup the code for TBBR CoT descriptors

CoT used for BL1 and BL2 are moved to tbbr_cot_bl1.c
and tbbr_cot_bl2.c respectively.
Common CoT used across BL1 and BL2 are moved to
tbbr_cot_common.c.

Si

Cleanup the code for TBBR CoT descriptors

CoT used for BL1 and BL2 are moved to tbbr_cot_bl1.c
and tbbr_cot_bl2.c respectively.
Common CoT used across BL1 and BL2 are moved to
tbbr_cot_common.c.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I2252ac8a6960b3431bcaafdb3ea4fb2d01b79cf5

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plat/arm/fvp: Support performing SDEI platform setup in runtime

This patch introduces dynamic configuration for SDEI setup and is supported
when the new build flag SDEI_IN_FCONF is enabled. Instead

plat/arm/fvp: Support performing SDEI platform setup in runtime

This patch introduces dynamic configuration for SDEI setup and is supported
when the new build flag SDEI_IN_FCONF is enabled. Instead of using C arrays
and processing the configuration at compile time, the config is moved to
dts files. It will be retrieved at runtime during SDEI init, using the fconf
layer.

Change-Id: If5c35a7517ba00a9f258d7f3e7c8c20cee169a31
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Co-authored-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Implement workaround for AT speculative behaviour

During context switching from higher EL (EL2 or higher)
to lower EL can cause incorrect translation in TLB due to
speculative execution of AT instru

Implement workaround for AT speculative behaviour

During context switching from higher EL (EL2 or higher)
to lower EL can cause incorrect translation in TLB due to
speculative execution of AT instruction using out-of-context
translation regime.

Workaround is implemented as below during EL's (EL1 or EL2)
"context_restore" operation:
1. Disable page table walk using SCTLR.M and TCR.EPD0 & EPD1
bits for EL1 or EL2 (stage1 and stage2 disabled)
2. Save all system registers except TCR and SCTLR (for EL1 and EL2)
3. Do memory barrier operation (isb) to ensure all
system register writes are done.
4. Restore TCR and SCTLR registers (for EL1 and EL2)

Errata details are available for various CPUs as below:
Cortex-A76: 1165522
Cortex-A72: 1319367
Cortex-A57: 1319537
Cortex-A55: 1530923
Cortex-A53: 1530924

More details can be found in mail-chain:
https://lists.trustedfirmware.org/pipermail/tf-a/2020-April/000445.html

Currently, Workaround is implemented as build option which is default
disabled.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: If8545e61f782cb0c2dda7ffbaf50681c825bd2f0

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doc: Reorganize maintainers.rst file

The maintainers.rst file provides the list of all TF-A modules and their
code owners. As there are quite a lot of modules (and more to come) in
TF-A, it is somet

doc: Reorganize maintainers.rst file

The maintainers.rst file provides the list of all TF-A modules and their
code owners. As there are quite a lot of modules (and more to come) in
TF-A, it is sometimes hard to find the information.

Introduce categories (core code, drivers/libraries/framework, ...) and
classify each module in the right one.

Note that the core code category is pretty much empty right now but the
plan would be to expand it with further modules (e.g. PSCI, SDEI, TBBR,
...) in a future patch.

Change-Id: Id68a2dd79a8f6b68af5364bbf1c59b20c05f8fe7
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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doc: Update various process documents

Most of the changes consist in using the new code owners terminology
(from [1]).

[1] https://developer.trustedfirmware.org/w/collaboration/project-maintenance-

doc: Update various process documents

Most of the changes consist in using the new code owners terminology
(from [1]).

[1] https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/

Change-Id: Icead20e9335af12aa47d3f1ac5d04ca157b20c82
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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