1# 2# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Use the GICv3 driver on the FVP by default 8FVP_USE_GIC_DRIVER := FVP_GICV3 9 10# Use the SP804 timer instead of the generic one 11FVP_USE_SP804_TIMER := 0 12 13# Default cluster count for FVP 14FVP_CLUSTER_COUNT := 2 15 16# Default number of CPUs per cluster on FVP 17FVP_MAX_CPUS_PER_CLUSTER := 4 18 19# Default number of threads per CPU on FVP 20FVP_MAX_PE_PER_CPU := 1 21 22FVP_DT_PREFIX := fvp-base-gicv3-psci 23 24$(eval $(call assert_boolean,FVP_USE_SP804_TIMER)) 25$(eval $(call add_define,FVP_USE_SP804_TIMER)) 26 27# The FVP platform depends on this macro to build with correct GIC driver. 28$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 29 30# Pass FVP_CLUSTER_COUNT to the build system. 31$(eval $(call add_define,FVP_CLUSTER_COUNT)) 32 33# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 34$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 35 36# Pass FVP_MAX_PE_PER_CPU to the build system. 37$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 38 39# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 40# choose the CCI driver , else the CCN driver 41ifeq ($(FVP_CLUSTER_COUNT), 0) 42$(error "Incorrect cluster count specified for FVP port") 43else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 44FVP_INTERCONNECT_DRIVER := FVP_CCI 45else 46FVP_INTERCONNECT_DRIVER := FVP_CCN 47endif 48 49$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 50 51# Choose the GIC sources depending upon the how the FVP will be invoked 52ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 53 54# The GIC model (GIC-600 or GIC-500) will be detected at runtime 55GICV3_SUPPORT_GIC600 := 1 56GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 57 58# Include GICv3 driver files 59include drivers/arm/gic/v3/gicv3.mk 60 61FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 62 plat/common/plat_gicv3.c \ 63 plat/arm/common/arm_gicv3.c 64 65 ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 66 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 67 endif 68 69else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 70 71# No GICv4 extension 72GIC_ENABLE_V4_EXTN := 0 73$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 74 75# No support for extended PPI and SPI range 76GIC_EXT_INTID := 0 77$(eval $(call add_define,GIC_EXT_INTID)) 78 79FVP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ 80 drivers/arm/gic/v2/gicv2_main.c \ 81 drivers/arm/gic/v2/gicv2_helpers.c \ 82 plat/common/plat_gicv2.c \ 83 plat/arm/common/arm_gicv2.c 84 85FVP_DT_PREFIX := fvp-base-gicv2-psci 86else 87$(error "Incorrect GIC driver chosen on FVP port") 88endif 89 90ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 91FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 92else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 93FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 94 plat/arm/common/arm_ccn.c 95else 96$(error "Incorrect CCN driver chosen on FVP port") 97endif 98 99FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 100 plat/arm/board/fvp/fvp_security.c \ 101 plat/arm/common/arm_tzc400.c 102 103 104PLAT_INCLUDES := -Iplat/arm/board/fvp/include 105 106 107PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 108 109FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 110 111ifeq (${ARCH}, aarch64) 112 113# select a different set of CPU files, depending on whether we compile for 114# hardware assisted coherency cores or not 115ifeq (${HW_ASSISTED_COHERENCY}, 0) 116# Cores used without DSU 117 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 118 lib/cpus/aarch64/cortex_a53.S \ 119 lib/cpus/aarch64/cortex_a57.S \ 120 lib/cpus/aarch64/cortex_a72.S \ 121 lib/cpus/aarch64/cortex_a73.S 122else 123# Cores used with DSU only 124 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 125 # AArch64-only cores 126 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ 127 lib/cpus/aarch64/cortex_a76ae.S \ 128 lib/cpus/aarch64/cortex_a77.S \ 129 lib/cpus/aarch64/cortex_a78.S \ 130 lib/cpus/aarch64/neoverse_n1.S \ 131 lib/cpus/aarch64/neoverse_e1.S \ 132 lib/cpus/aarch64/neoverse_zeus.S \ 133 lib/cpus/aarch64/cortex_hercules_ae.S \ 134 lib/cpus/aarch64/cortex_klein.S \ 135 lib/cpus/aarch64/cortex_matterhorn.S \ 136 lib/cpus/aarch64/cortex_a65.S \ 137 lib/cpus/aarch64/cortex_a65ae.S 138 endif 139 # AArch64/AArch32 cores 140 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 141 lib/cpus/aarch64/cortex_a75.S 142endif 143 144else 145FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S 146endif 147 148BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 149 drivers/arm/sp805/sp805.c \ 150 drivers/delay_timer/delay_timer.c \ 151 drivers/io/io_semihosting.c \ 152 lib/semihosting/semihosting.c \ 153 lib/semihosting/${ARCH}/semihosting_call.S \ 154 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 155 plat/arm/board/fvp/fvp_bl1_setup.c \ 156 plat/arm/board/fvp/fvp_err.c \ 157 plat/arm/board/fvp/fvp_io_storage.c \ 158 ${FVP_CPU_LIBS} \ 159 ${FVP_INTERCONNECT_SOURCES} 160 161ifeq (${FVP_USE_SP804_TIMER},1) 162BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 163else 164BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 165endif 166 167 168BL2_SOURCES += drivers/arm/sp805/sp805.c \ 169 drivers/io/io_semihosting.c \ 170 lib/utils/mem_region.c \ 171 lib/semihosting/semihosting.c \ 172 lib/semihosting/${ARCH}/semihosting_call.S \ 173 plat/arm/board/fvp/fvp_bl2_setup.c \ 174 plat/arm/board/fvp/fvp_err.c \ 175 plat/arm/board/fvp/fvp_io_storage.c \ 176 plat/arm/common/arm_nor_psci_mem_protect.c \ 177 ${FVP_SECURITY_SOURCES} 178 179 180 181ifeq (${BL2_AT_EL3},1) 182BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 183 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 184 ${FVP_CPU_LIBS} \ 185 ${FVP_INTERCONNECT_SOURCES} 186endif 187 188ifeq (${FVP_USE_SP804_TIMER},1) 189BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 190endif 191 192BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 193 ${FVP_SECURITY_SOURCES} 194 195ifeq (${FVP_USE_SP804_TIMER},1) 196BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 197endif 198 199BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 200 drivers/arm/smmu/smmu_v3.c \ 201 drivers/delay_timer/delay_timer.c \ 202 drivers/cfi/v2m/v2m_flash.c \ 203 lib/utils/mem_region.c \ 204 plat/arm/board/fvp/fvp_bl31_setup.c \ 205 plat/arm/board/fvp/fvp_console.c \ 206 plat/arm/board/fvp/fvp_pm.c \ 207 plat/arm/board/fvp/fvp_topology.c \ 208 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 209 plat/arm/common/arm_nor_psci_mem_protect.c \ 210 ${FVP_CPU_LIBS} \ 211 ${FVP_GIC_SOURCES} \ 212 ${FVP_INTERCONNECT_SOURCES} \ 213 ${FVP_SECURITY_SOURCES} 214 215# Support for fconf in BL31 216# Added separately from the above list for better readability 217ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_BL31}),) 218BL31_SOURCES += common/fdt_wrappers.c \ 219 lib/fconf/fconf.c \ 220 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 221endif 222 223ifeq (${FVP_USE_SP804_TIMER},1) 224BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 225else 226BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 227endif 228 229# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 230ifdef UNIX_MK 231FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 232FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 233 ${PLAT}_fw_config.dts \ 234 ${PLAT}_soc_fw_config.dts \ 235 ${PLAT}_nt_fw_config.dts \ 236 ) 237 238FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 239FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 240FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 241 242ifeq (${SPD},tspd) 243FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 244FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 245 246# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 247$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config)) 248endif 249 250ifeq (${SPD},spmd) 251FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 252FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_spmc_manifest.dtb 253 254# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 255$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config)) 256endif 257 258# Add the TB_FW_CONFIG to FIP and specify the same to certtool 259$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config)) 260# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 261$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config)) 262# Add the NT_FW_CONFIG to FIP and specify the same to certtool 263$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config)) 264 265FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 266$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 267 268# Add the HW_CONFIG to FIP and specify the same to certtool 269$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config)) 270endif 271 272# Enable Activity Monitor Unit extensions by default 273ENABLE_AMU := 1 274 275# Enable dynamic mitigation support by default 276DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 277 278# Enable reclaiming of BL31 initialisation code for secondary cores 279# stacks for FVP. However, don't enable reclaiming for clang. 280ifneq (${RESET_TO_BL31},1) 281ifeq ($(findstring clang,$(notdir $(CC))),) 282RECLAIM_INIT_CODE := 1 283endif 284endif 285 286ifeq (${ENABLE_AMU},1) 287BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 288 lib/cpus/aarch64/cpuamu_helpers.S 289 290ifeq (${HW_ASSISTED_COHERENCY}, 1) 291BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 292 lib/cpus/aarch64/neoverse_n1_pubsub.c 293endif 294endif 295 296ifeq (${RAS_EXTENSION},1) 297BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 298endif 299 300ifneq (${ENABLE_STACK_PROTECTOR},0) 301PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 302endif 303 304ifeq (${ARCH},aarch32) 305 NEED_BL32 := yes 306endif 307 308# Enable the dynamic translation tables library. 309ifeq (${ARCH},aarch32) 310 ifeq (${RESET_TO_SP_MIN},1) 311 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 312 endif 313else # AArch64 314 ifeq (${RESET_TO_BL31},1) 315 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 316 endif 317 ifeq (${SPD},trusty) 318 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 319 endif 320endif 321 322ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 323 ifeq (${ARCH},aarch32) 324 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 325 else # AArch64 326 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 327 ifeq (${SPD},tspd) 328 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 329 endif 330 endif 331endif 332 333ifeq (${USE_DEBUGFS},1) 334 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 335endif 336 337# Add support for platform supplied linker script for BL31 build 338$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 339 340ifneq (${BL2_AT_EL3}, 0) 341 override BL1_SOURCES = 342endif 343 344include plat/arm/board/common/board_common.mk 345include plat/arm/common/arm_common.mk 346 347ifeq (${TRUSTED_BOARD_BOOT}, 1) 348BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 349BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 350# FVP being a development platform, enable capability to disable Authentication 351# dynamically if TRUSTED_BOARD_BOOT is set. 352DYN_DISABLE_AUTH := 1 353endif 354