| 70311692 | 26-Jan-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "Fix documentation typos and misspellings" into integration |
| 1cea0213 | 26-Jan-2021 |
Pali Rohár <pali@kernel.org> |
docs: marvell: Update mv-ddr-marvell and A3700-utils-marvell branches
Marvell finally started providing the latest version of mv-ddr-marvell and
A3700-utils-marvell code in master branch of their gi
docs: marvell: Update mv-ddr-marvell and A3700-utils-marvell branches
Marvell finally started providing the latest version of mv-ddr-marvell and
A3700-utils-marvell code in master branch of their git repositories.
Reflect this in build instructions.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I08d1189dac60eb2a28335c68f611c1da634106f6
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| 49e4a5fc | 24-Jan-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs: marvell: armada: Update MARVELL_PLATFORM list and build instructions" into integration |
| 47147013 | 21-Jan-2021 |
David Horstmann <david.horstmann@arm.com> |
Fix documentation typos and misspellings
Fix some typos and misspellings in TF-A documentation.
Signed-off-by: David Horstmann <david.horstmann@arm.com>
Change-Id: Id72553ce7b2f0bed9821604fbc8df4d4
Fix documentation typos and misspellings
Fix some typos and misspellings in TF-A documentation.
Signed-off-by: David Horstmann <david.horstmann@arm.com>
Change-Id: Id72553ce7b2f0bed9821604fbc8df4d4949909fa
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| 6047a105 | 15-Jan-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I3c0a402f,I9ce5b9df,I08719015,If541278f,I99f1a697 into integration
* changes:
doc: renesas: Update code owner for Renesas platforms
doc: renesas: Document platforms based on RZ/G2
Merge changes I3c0a402f,I9ce5b9df,I08719015,If541278f,I99f1a697 into integration
* changes:
doc: renesas: Update code owner for Renesas platforms
doc: renesas: Document platforms based on RZ/G2 SoC's
renesas: rzg: Add PFC support for RZ/G2M
renesas: rzg: Add QoS support for RZ/G2M
renesas: rzg: Add support for DRAM initialization
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| d0b367b7 | 14-Jan-2021 |
Luka Kovacic <luka.kovacic@sartura.hr> |
docs: marvell: armada: Update MARVELL_PLATFORM list and build instructions
The supported MARVELL_PLATFORM list is updated to include the recently added
a80x0_puzzle platform (IEI Puzzle-M801).
Addi
docs: marvell: armada: Update MARVELL_PLATFORM list and build instructions
The supported MARVELL_PLATFORM list is updated to include the recently added
a80x0_puzzle platform (IEI Puzzle-M801).
Additionally building instructions are added for the GST ESPRESSObin-Ultra
board (1 GB, DDR4 RAM variant), which has been tested successfully and booted
TF-A on the board.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Change-Id: Ie5724df27c1ee2e8f6a52664520579e872471e93
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| 2bc48585 | 07-Dec-2020 |
Biju Das <biju.das.jz@bp.renesas.com> |
doc: renesas: Document platforms based on RZ/G2 SoC's
Document the platforms based on RZ/G2 SoC's.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev
doc: renesas: Document platforms based on RZ/G2 SoC's
Document the platforms based on RZ/G2 SoC's.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I9ce5b9df3573b1198c5c7be79b5471d54573609a
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| 06ea86fe | 13-Jan-2021 |
Aditya Angadi <aditya.angadi@arm.com> |
docs: update fvp version to be used for rdv1 platform
Move RD-V1 platform to use version of FVP_RD_Daniel from 11.10 build 36
to 11.13 build 10
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
docs: update fvp version to be used for rdv1 platform
Move RD-V1 platform to use version of FVP_RD_Daniel from 11.10 build 36
to 11.13 build 10
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I9622c03d342bb780234dec8ffe4ab11d8069acab
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| fde125cb | 06-Jan-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor" into integration |
| d9243f26 | 05-Jan-2021 |
Marek Behún <marek.behun@nic.cz> |
plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor
Introduce a new build option CM3_SYSTEM_RESET for A3700 platform, which,
when enabled, adds code to the PSCI reset h
plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor
Introduce a new build option CM3_SYSTEM_RESET for A3700 platform, which,
when enabled, adds code to the PSCI reset handler to try to do system
reset by the WTMI firmware running on the Cortex-M3 secure coprocessor.
(This function is exposed via the mailbox interface.)
The reason is that the Turris MOX board has a HW bug which causes reset
to hang unpredictably. This issue can be solved by putting the board in
a specific state before reset.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I3f60b9f244f334adcd33d6db6a361fbc8b8d209f
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| be3a3bc7 | 08-Dec-2020 |
Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
docs: arm: Add OPTEE_SP_FW_CONFIG
This adds documentation for device tree build flag OPTEE_SP_FW_CONFIG.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ie45f075cf04
docs: arm: Add OPTEE_SP_FW_CONFIG
This adds documentation for device tree build flag OPTEE_SP_FW_CONFIG.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ie45f075cf04182701007f87aa0c8912cd567157a
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| 7b24e48a | 08-Dec-2020 |
Aditya Angadi <aditya.angadi@arm.com> |
doc: Update list of supported FVP platforms
Updated the list of supported FVP platforms with support for RD-N2 FVP.
Change-Id: I861bbb6d520c20e718f072e118c66dab61fe1386
Signed-off-by: Aditya Angadi
doc: Update list of supported FVP platforms
Updated the list of supported FVP platforms with support for RD-N2 FVP.
Change-Id: I861bbb6d520c20e718f072e118c66dab61fe1386
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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| f20cb7e5 | 29-Oct-2020 |
Pali Rohár <pali@kernel.org> |
docs: marvell: Update build documentation to reflect mrvl_bootimage and mrvl_flash changes
Also add example how to build TF-A for A3720 Turris MOX board and also fix
style/indentation issues and inf
docs: marvell: Update build documentation to reflect mrvl_bootimage and mrvl_flash changes
Also add example how to build TF-A for A3720 Turris MOX board and also fix
style/indentation issues and information about default values.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2dc957307b1b627b403a8d960e85f5ac9e15aee5
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| 95fca110 | 24-Oct-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Merge "docs: marvell: update ddr3 build instructions" into integration |
| 63544012 | 13-Oct-2020 |
Yann Gautier <yann.gautier@st.com> |
docs: update STM32MP1 with versions details
After introducing the new STM32MP1 SoC versions in patch [1], the
document describing STM32MP1 platform is updated with the information
given in the patch
docs: update STM32MP1 with versions details
After introducing the new STM32MP1 SoC versions in patch [1], the
document describing STM32MP1 platform is updated with the information
given in the patch commit message.
[1]: stm32mp1: add support for new SoC profiles
Change-Id: I6d7ce1a3c29678ddac78a6685f5d5daf28c3c3a1
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 583079ae | 07-Oct-2020 |
Pali Rohár <pali@kernel.org> |
docs: marvell: update ddr3 build instructions
Add information about 2GB variant of EspressoBin V5 and use Marvell git
branches which contain required fixes for EspressoBin.
Signed-off-by: Pali Rohá
docs: marvell: update ddr3 build instructions
Add information about 2GB variant of EspressoBin V5 and use Marvell git
branches which contain required fixes for EspressoBin.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I1db510f1576f4762259ad7b0c10024b8ab434a59
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| 3fad9960 | 06-Oct-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "doc: Update list of supported FVP platforms" into integration |
| eeb77da6 | 06-Oct-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I959d1343,I6992df1a,I687e35cb,Ia5f2ee31,Ifd0bc6aa, ... into integration
* changes:
docs: marvell: update mv_ddr branch
plat: marvell: armada: a3k: rename the UART images archive
Merge changes I959d1343,I6992df1a,I687e35cb,Ia5f2ee31,Ifd0bc6aa, ... into integration
* changes:
docs: marvell: update mv_ddr branch
plat: marvell: armada: a3k: rename the UART images archive
plat: marvell: armada: a3k: allow image load to RAM address 0
marvell: comphy: cp110: add support for USB comphy polarity invert
marvell: comphy: cp110: add support for SATA comphy polarity invert
marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353
drivers: marvell: mochi: Update AP incoming masters secure level
plat: marvell: armada: add ccu window for workaround errata-id 3033912
plat: marvell: ap806: implement workaround for errata-id FE-4265711
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| 5ecfd890 | 04-Oct-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "doc: stm32mp1: Improve OP-TEE related documentation" into integration |
| 1d935a1b | 04-Oct-2020 |
Marcin Wojtas <mw@semihalf.com> |
docs: marvell: update mv_ddr branch
Now that the BLE image sources (mv_ddr) are updated, reflect
the proper branch in the Armada build howto.
Change-Id: I959d1343d0dfdd681c7e39bdcaed9b36aaddfca1
Si
docs: marvell: update mv_ddr branch
Now that the BLE image sources (mv_ddr) are updated, reflect
the proper branch in the Armada build howto.
Change-Id: I959d1343d0dfdd681c7e39bdcaed9b36aaddfca1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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| 8445253e | 01-Oct-2020 |
Chandni Cherukuri <chandni.cherukuri@arm.com> |
morello: Add Morello platform documentation
Morello platform has a SCP which brings the primary Rainier CPU
out of reset which starts executing at BL31.
This patch provides documentation support fo
morello: Add Morello platform documentation
Morello platform has a SCP which brings the primary Rainier CPU
out of reset which starts executing at BL31.
This patch provides documentation support for Morello platform.
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I38f596668e2b14862d543fabc04549ff34bfb8a2
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| ccf220ad | 02-Oct-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
doc: Update list of supported FVP platforms
Updated the list of supported FVP platform as per latest
FVP platform release.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I45e
doc: Update list of supported FVP platforms
Updated the list of supported FVP platform as per latest
FVP platform release.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I45ef79aff147ed598a3a92ab6f6b277f7f70604a
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| 219e45cd | 02-Oct-2020 |
Jan Kiszka <jan.kiszka@siemens.com> |
doc: stm32mp1: Improve OP-TEE related documentation
stm32mp15_optee_defconfig has been dropped from U-Boot as it became
identical to stm32mp15_trusted_defconfig.
Furthermore give a hint how OP-TEE
doc: stm32mp1: Improve OP-TEE related documentation
stm32mp15_optee_defconfig has been dropped from U-Boot as it became
identical to stm32mp15_trusted_defconfig.
Furthermore give a hint how OP-TEE is supposed to be installed.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: Id8f0bd84a87e3a62072dd4405aadddcdd3511213
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| 2173b3e0 | 30-Sep-2020 |
André Przywara <andre.przywara@arm.com> |
Merge changes from topic "fpga_generic" into integration
* changes:
arm_fpga: Add platform documentation
arm_fpga: Add post-build linker script
arm_fpga: Add ROM trampoline
arm_fpga: Add dev
Merge changes from topic "fpga_generic" into integration
* changes:
arm_fpga: Add platform documentation
arm_fpga: Add post-build linker script
arm_fpga: Add ROM trampoline
arm_fpga: Add devicetree file
arm_fpga: Remove SPE PMU DT node if SPE is not available
arm_fpga: Adjust GICR size in DT to match number of cores
fdt: Add function to adjust GICv3 redistributor size
drivers: arm: gicv3: Allow detecting number of cores
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| a6c07e0d | 27-Aug-2020 |
Andre Przywara <andre.przywara@arm.com> |
arm_fpga: Add platform documentation
As the Arm Ltd. FPGA port is now working for all existing images, add
some documentation file.
Change-Id: I9e2c532ed15bbc121bb54b3dfc1bdfee8f1443a6
Signed-off-b
arm_fpga: Add platform documentation
As the Arm Ltd. FPGA port is now working for all existing images, add
some documentation file.
Change-Id: I9e2c532ed15bbc121bb54b3dfc1bdfee8f1443a6
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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