1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 26 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 27 ``aarch64``. 28 29- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 30 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 31 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 32 :ref:`Firmware Design`. 33 34- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 35 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 36 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 37 38- ``BL2``: This is an optional build option which specifies the path to BL2 39 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 40 built. 41 42- ``BL2U``: This is an optional build option which specifies the path to 43 BL2U image. In this case, the BL2U in TF-A will not be built. 44 45- ``BL2_AT_EL3``: This is an optional build option that enables the use of 46 BL2 at EL3 execution level. 47 48- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 49 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 50 the RW sections in RAM, while leaving the RO sections in place. This option 51 enable this use-case. For now, this option is only supported when BL2_AT_EL3 52 is set to '1'. 53 54- ``BL31``: This is an optional build option which specifies the path to 55 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 56 be built. 57 58- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 59 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, 60 this file name will be used to save the key. 61 62- ``BL32``: This is an optional build option which specifies the path to 63 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 64 be built. 65 66- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 67 Trusted OS Extra1 image for the ``fip`` target. 68 69- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 70 Trusted OS Extra2 image for the ``fip`` target. 71 72- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 73 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, 74 this file name will be used to save the key. 75 76- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 77 ``fip`` target in case TF-A BL2 is used. 78 79- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 80 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, 81 this file name will be used to save the key. 82 83- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 84 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 85 If enabled, it is needed to use a compiler that supports the option 86 ``-mbranch-protection``. Selects the branch protection features to use: 87- 0: Default value turns off all types of branch protection 88- 1: Enables all types of branch protection features 89- 2: Return address signing to its standard level 90- 3: Extend the signing to include leaf functions 91- 4: Turn on branch target identification mechanism 92 93 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 94 and resulting PAuth/BTI features. 95 96 +-------+--------------+-------+-----+ 97 | Value | GCC option | PAuth | BTI | 98 +=======+==============+=======+=====+ 99 | 0 | none | N | N | 100 +-------+--------------+-------+-----+ 101 | 1 | standard | Y | Y | 102 +-------+--------------+-------+-----+ 103 | 2 | pac-ret | Y | N | 104 +-------+--------------+-------+-----+ 105 | 3 | pac-ret+leaf | Y | N | 106 +-------+--------------+-------+-----+ 107 | 4 | bti | N | Y | 108 +-------+--------------+-------+-----+ 109 110 This option defaults to 0 and this is an experimental feature. 111 Note that Pointer Authentication is enabled for Non-secure world 112 irrespective of the value of this option if the CPU supports it. 113 114- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 115 compilation of each build. It must be set to a C string (including quotes 116 where applicable). Defaults to a string that contains the time and date of 117 the compilation. 118 119- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 120 build to be uniquely identified. Defaults to the current git commit id. 121 122- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 123 124- ``CFLAGS``: Extra user options appended on the compiler's command line in 125 addition to the options set by the build system. 126 127- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 128 release several CPUs out of reset. It can take either 0 (several CPUs may be 129 brought up) or 1 (only one CPU will ever be brought up during cold reset). 130 Default is 0. If the platform always brings up a single CPU, there is no 131 need to distinguish between primary and secondary CPUs and the boot path can 132 be optimised. The ``plat_is_my_cpu_primary()`` and 133 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 134 to be implemented in this case. 135 136- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 137 Defaults to ``tbbr``. 138 139- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 140 register state when an unexpected exception occurs during execution of 141 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 142 this is only enabled for a debug build of the firmware. 143 144- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 145 certificate generation tool to create new keys in case no valid keys are 146 present or specified. Allowed options are '0' or '1'. Default is '1'. 147 148- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 149 the AArch32 system registers to be included when saving and restoring the 150 CPU context. The option must be set to 0 for AArch64-only platforms (that 151 is on hardware that does not implement AArch32, or at least not at EL1 and 152 higher ELs). Default value is 1. 153 154- ``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore 155 operations when entering/exiting an EL2 execution context. This is of primary 156 interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled). 157 This option must be equal to 1 (enabled) when ``SPD=spmd`` and 158 ``SPMD_SPM_AT_SEL2`` is set. 159 160- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 161 registers to be included when saving and restoring the CPU context. Default 162 is 0. 163 164- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables 165 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth 166 registers to be included when saving and restoring the CPU context as 167 part of world switch. Default value is 0 and this is an experimental feature. 168 Note that Pointer Authentication is enabled for Non-secure world irrespective 169 of the value of this flag if the CPU supports it. 170 171- ``DEBUG``: Chooses between a debug and release build. It can take either 0 172 (release) or 1 (debug) as values. 0 is the default. 173 174- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 175 authenticated decryption algorithm to be used to decrypt firmware/s during 176 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 177 this flag is ``none`` to disable firmware decryption which is an optional 178 feature as per TBBR. Also, it is an experimental feature. 179 180- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 181 of the binary image. If set to 1, then only the ELF image is built. 182 0 is the default. 183 184- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 185 Board Boot authentication at runtime. This option is meant to be enabled only 186 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 187 flag has to be enabled. 0 is the default. 188 189- ``E``: Boolean option to make warnings into errors. Default is 1. 190 191- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 192 the normal boot flow. It must specify the entry point address of the EL3 193 payload. Please refer to the "Booting an EL3 payload" section for more 194 details. 195 196- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. 197 This is an optional architectural feature available on v8.4 onwards. Some 198 v8.2 implementations also implement an AMU and this option can be used to 199 enable this feature on those systems as well. Default is 0. 200 201- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 202 are compiled out. For debug builds, this option defaults to 1, and calls to 203 ``assert()`` are left in place. For release builds, this option defaults to 0 204 and calls to ``assert()`` function are compiled out. This option can be set 205 independently of ``DEBUG``. It can also be used to hide any auxiliary code 206 that is only required for the assertion and does not fit in the assertion 207 itself. 208 209- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 210 dumps or not. It is supported in both AArch64 and AArch32. However, in 211 AArch32 the format of the frame records are not defined in the AAPCS and they 212 are defined by the implementation. This implementation of backtrace only 213 supports the format used by GCC when T32 interworking is disabled. For this 214 reason enabling this option in AArch32 will force the compiler to only 215 generate A32 code. This option is enabled by default only in AArch64 debug 216 builds, but this behaviour can be overridden in each platform's Makefile or 217 in the build command line. 218 219- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 220 support in GCC for TF-A. This option is currently only supported for 221 AArch64. Default is 0. 222 223- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM 224 feature. MPAM is an optional Armv8.4 extension that enables various memory 225 system components and resources to define partitions; software running at 226 various ELs can assign themselves to desired partition to control their 227 performance aspects. 228 229 When this option is set to ``1``, EL3 allows lower ELs to access their own 230 MPAM registers without trapping into EL3. This option doesn't make use of 231 partitioning in EL3, however. Platform initialisation code should configure 232 and use partitions in EL3 as required. This option defaults to ``0``. 233 234- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 235 support within generic code in TF-A. This option is currently only supported 236 in BL2_AT_EL3, BL31, and BL32 (TSP). Default is 0. 237 238- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 239 Measurement Framework(PMF). Default is 0. 240 241- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 242 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 243 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 244 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 245 software. 246 247- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 248 instrumentation which injects timestamp collection points into TF-A to 249 allow runtime performance to be measured. Currently, only PSCI is 250 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 251 as well. Default is 0. 252 253- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling 254 extensions. This is an optional architectural feature for AArch64. 255 The default is 1 but is automatically disabled when the target architecture 256 is AArch32. 257 258- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension 259 (SVE) for the Non-secure world only. SVE is an optional architectural feature 260 for AArch64. Note that when SVE is enabled for the Non-secure world, access 261 to SIMD and floating-point functionality from the Secure world is disabled. 262 This is to avoid corruption of the Non-secure world data in the Z-registers 263 which are aliased by the SIMD and FP registers. The build option is not 264 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 265 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to 266 1. The default is 1 but is automatically disabled when the target 267 architecture is AArch32. 268 269- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 270 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 271 default value is set to "none". "strong" is the recommended stack protection 272 level if this feature is desired. "none" disables the stack protection. For 273 all values other than "none", the ``plat_get_stack_protector_canary()`` 274 platform hook needs to be implemented. The value is passed as the last 275 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 276 277- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 278 flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 279 experimental. 280 281- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 282 This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 283 experimental. 284 285- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 286 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 287 on ``DECRYPTION_SUPPORT`` build flag which is marked as experimental. 288 289- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 290 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 291 build flag which is marked as experimental. 292 293- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 294 deprecated platform APIs, helper functions or drivers within Trusted 295 Firmware as error. It can take the value 1 (flag the use of deprecated 296 APIs as error) or 0. The default is 0. 297 298- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 299 targeted at EL3. When set ``0`` (default), no exceptions are expected or 300 handled at EL3, and a panic will result. This is supported only for AArch64 301 builds. 302 303- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 304 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 305 Default value is 40 (LOG_LEVEL_INFO). 306 307- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 308 injection from lower ELs, and this build option enables lower ELs to use 309 Error Records accessed via System Registers to inject faults. This is 310 applicable only to AArch64 builds. 311 312 This feature is intended for testing purposes only, and is advisable to keep 313 disabled for production images. 314 315- ``FIP_NAME``: This is an optional build option which specifies the FIP 316 filename for the ``fip`` target. Default is ``fip.bin``. 317 318- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 319 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 320 321- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 322 323 :: 324 325 0: Encryption is done with Secret Symmetric Key (SSK) which is common 326 for a class of devices. 327 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 328 unique per device. 329 330 This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 331 experimental. 332 333- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 334 tool to create certificates as per the Chain of Trust described in 335 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 336 include the certificates in the FIP and FWU_FIP. Default value is '0'. 337 338 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 339 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 340 the corresponding certificates, and to include those certificates in the 341 FIP and FWU_FIP. 342 343 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 344 images will not include support for Trusted Board Boot. The FIP will still 345 include the corresponding certificates. This FIP can be used to verify the 346 Chain of Trust on the host machine through other mechanisms. 347 348 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 349 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 350 will not include the corresponding certificates, causing a boot failure. 351 352- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 353 inherent support for specific EL3 type interrupts. Setting this build option 354 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 355 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 356 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 357 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 358 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 359 the Secure Payload interrupts needs to be synchronously handed over to Secure 360 EL1 for handling. The default value of this option is ``0``, which means the 361 Group 0 interrupts are assumed to be handled by Secure EL1. 362 363- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError 364 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to 365 ``0`` (default), these exceptions will be trapped in the current exception 366 level (or in EL1 if the current exception level is EL0). 367 368- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 369 software operations are required for CPUs to enter and exit coherency. 370 However, newer systems exist where CPUs' entry to and exit from coherency 371 is managed in hardware. Such systems require software to only initiate these 372 operations, and the rest is managed in hardware, minimizing active software 373 management. In such systems, this boolean option enables TF-A to carry out 374 build and run-time optimizations during boot and power management operations. 375 This option defaults to 0 and if it is enabled, then it implies 376 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 377 378 If this flag is disabled while the platform which TF-A is compiled for 379 includes cores that manage coherency in hardware, then a compilation error is 380 generated. This is based on the fact that a system cannot have, at the same 381 time, cores that manage coherency in hardware and cores that don't. In other 382 words, a platform cannot have, at the same time, cores that require 383 ``HW_ASSISTED_COHERENCY=1`` and cores that require 384 ``HW_ASSISTED_COHERENCY=0``. 385 386 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 387 translation library (xlat tables v2) must be used; version 1 of translation 388 library is not supported. 389 390- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 391 bottom, higher addresses at the top. This buid flag can be set to '1' to 392 invert this behavior. Lower addresses will be printed at the top and higher 393 addresses at the bottom. 394 395- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 396 runtime software in AArch32 mode, which is required to run AArch32 on Juno. 397 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in 398 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable 399 images. 400 401- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 402 used for generating the PKCS keys and subsequent signing of the certificate. 403 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option 404 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR 405 compliant and is retained only for compatibility. The default value of this 406 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. 407 408- ``KEY_SIZE``: This build flag enables the user to select the key size for 409 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 410 depend on the chosen algorithm and the cryptographic module. 411 412 +-----------+------------------------------------+ 413 | KEY_ALG | Possible key sizes | 414 +===========+====================================+ 415 | rsa | 1024 , 2048 (default), 3072, 4096* | 416 +-----------+------------------------------------+ 417 | ecdsa | unavailable | 418 +-----------+------------------------------------+ 419 420 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 421 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 422 423- ``HASH_ALG``: This build flag enables the user to select the secure hash 424 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 425 The default value of this flag is ``sha256``. 426 427- ``LDFLAGS``: Extra user options appended to the linkers' command line in 428 addition to the one set by the build system. 429 430- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 431 output compiled into the build. This should be one of the following: 432 433 :: 434 435 0 (LOG_LEVEL_NONE) 436 10 (LOG_LEVEL_ERROR) 437 20 (LOG_LEVEL_NOTICE) 438 30 (LOG_LEVEL_WARNING) 439 40 (LOG_LEVEL_INFO) 440 50 (LOG_LEVEL_VERBOSE) 441 442 All log output up to and including the selected log level is compiled into 443 the build. The default value is 40 in debug builds and 20 in release builds. 444 445- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 446 feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set. 447 This option defaults to 0 and is an experimental feature in the stage of 448 development. 449 450- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 451 specifies the file that contains the Non-Trusted World private key in PEM 452 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 453 454- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 455 optional. It is only needed if the platform makefile specifies that it 456 is required in order to build the ``fwu_fip`` target. 457 458- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 459 contents upon world switch. It can take either 0 (don't save and restore) or 460 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 461 wants the timer registers to be saved and restored. 462 463- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 464 for the BL image. It can be either 0 (include) or 1 (remove). The default 465 value is 0. 466 467- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 468 the underlying hardware is not a full PL011 UART but a minimally compliant 469 generic UART, which is a subset of the PL011. The driver will not access 470 any register that is not part of the SBSA generic UART specification. 471 Default value is 0 (a full PL011 compliant UART is present). 472 473- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 474 must be subdirectory of any depth under ``plat/``, and must contain a 475 platform makefile named ``platform.mk``. For example, to build TF-A for the 476 Arm Juno board, select PLAT=juno. 477 478- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 479 instead of the normal boot flow. When defined, it must specify the entry 480 point address for the preloaded BL33 image. This option is incompatible with 481 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 482 over ``PRELOADED_BL33_BASE``. 483 484- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 485 vector address can be programmed or is fixed on the platform. It can take 486 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 487 programmable reset address, it is expected that a CPU will start executing 488 code directly at the right address, both on a cold and warm reset. In this 489 case, there is no need to identify the entrypoint on boot and the boot path 490 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 491 does not need to be implemented in this case. 492 493- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 494 possible for the PSCI power-state parameter: original and extended State-ID 495 formats. This flag if set to 1, configures the generic PSCI layer to use the 496 extended format. The default value of this flag is 0, which means by default 497 the original power-state format is used by the PSCI implementation. This flag 498 should be specified by the platform makefile and it governs the return value 499 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 500 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 501 set to 1 as well. 502 503- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features 504 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 505 or later CPUs. 506 507 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be 508 set to ``1``. 509 510 This option is disabled by default. 511 512- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 513 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 514 entrypoint) or 1 (CPU reset to BL31 entrypoint). 515 The default value is 0. 516 517- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 518 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 519 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 520 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 521 522- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 523 file that contains the ROT private key in PEM format and enforces public key 524 hash generation. If ``SAVE_KEYS=1``, this 525 file name will be used to save the key. 526 527- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 528 certificate generation tool to save the keys used to establish the Chain of 529 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 530 531- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 532 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 533 target. 534 535- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 536 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, 537 this file name will be used to save the key. 538 539- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 540 optional. It is only needed if the platform makefile specifies that it 541 is required in order to build the ``fwu_fip`` target. 542 543- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 544 Delegated Exception Interface to BL31 image. This defaults to ``0``. 545 546 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 547 set to ``1``. 548 549- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 550 isolated on separate memory pages. This is a trade-off between security and 551 memory usage. See "Isolating code and read-only data on separate memory 552 pages" section in :ref:`Firmware Design`. This flag is disabled by default 553 and affects all BL images. 554 555- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 556 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 557 allocated in RAM discontiguous from the loaded firmware image. When set, the 558 platform is expected to provide definitons for ``BL31_NOBITS_BASE`` and 559 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 560 sections are placed in RAM immediately following the loaded firmware image. 561 562- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 563 This build option is only valid if ``ARCH=aarch64``. The value should be 564 the path to the directory containing the SPD source, relative to 565 ``services/spd/``; the directory is expected to contain a makefile called 566 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 567 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 568 cannot be enabled when the ``SPM_MM`` option is enabled. 569 570- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 571 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 572 execution in BL1 just before handing over to BL31. At this point, all 573 firmware images have been loaded in memory, and the MMU and caches are 574 turned off. Refer to the "Debugging options" section for more details. 575 576- ``SPMD_SPM_AT_SEL2`` : this boolean option is used jointly with the SPM 577 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 578 component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2 579 extension. This is the default when enabling the SPM Dispatcher. When 580 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 581 state. This latter configuration supports pre-Armv8.4 platforms (aka not 582 implementing the Armv8.4-SecEL2 extension). 583 584- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 585 Partition Manager (SPM) implementation. The default value is ``0`` 586 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 587 enabled (``SPD=spmd``). 588 589- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 590 description of secure partitions. The build system will parse this file and 591 package all secure partition blobs into the FIP. This file is not 592 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 593 594- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 595 secure interrupts (caught through the FIQ line). Platforms can enable 596 this directive if they need to handle such interruption. When enabled, 597 the FIQ are handled in monitor mode and non secure world is not allowed 598 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 599 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 600 601- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 602 Boot feature. When set to '1', BL1 and BL2 images include support to load 603 and verify the certificates and images in a FIP, and BL1 includes support 604 for the Firmware Update. The default value is '0'. Generation and inclusion 605 of certificates in the FIP and FWU_FIP depends upon the value of the 606 ``GENERATE_COT`` option. 607 608 .. warning:: 609 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 610 already exist in disk, they will be overwritten without further notice. 611 612- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 613 specifies the file that contains the Trusted World private key in PEM 614 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 615 616- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 617 synchronous, (see "Initializing a BL32 Image" section in 618 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 619 synchronous method) or 1 (BL32 is initialized using asynchronous method). 620 Default is 0. 621 622- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 623 routing model which routes non-secure interrupts asynchronously from TSP 624 to EL3 causing immediate preemption of TSP. The EL3 is responsible 625 for saving and restoring the TSP context in this routing model. The 626 default routing model (when the value is 0) is to route non-secure 627 interrupts to TSP allowing it to save its context and hand over 628 synchronously to EL3 via an SMC. 629 630 .. note:: 631 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 632 must also be set to ``1``. 633 634- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 635 linker. When the ``LINKER`` build variable points to the armlink linker, 636 this flag is enabled automatically. To enable support for armlink, platforms 637 will have to provide a scatter file for the BL image. Currently, Tegra 638 platforms use the armlink support to compile BL3-1 images. 639 640- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 641 memory region in the BL memory map or not (see "Use of Coherent memory in 642 TF-A" section in :ref:`Firmware Design`). It can take the value 1 643 (Coherent memory region is included) or 0 (Coherent memory region is 644 excluded). Default is 1. 645 646- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 647 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 648 Default is 0. 649 650- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 651 firmware configuration framework. This will move the io_policies into a 652 configuration device tree, instead of static structure in the code base. 653 This is currently an experimental feature. 654 655- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 656 at runtime using fconf. If this flag is enabled, COT descriptors are 657 statically captured in tb_fw_config file in the form of device tree nodes 658 and properties. Currently, COT descriptors used by BL2 are moved to the 659 device tree and COT descriptors used by BL1 are retained in the code 660 base statically. This is currently an experimental feature. 661 662- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 663 runtime using firmware configuration framework. The platform specific SDEI 664 shared and private events configuration is retrieved from device tree rather 665 than static C structures at compile time. This is currently an experimental 666 feature and is only supported if SDEI_SUPPORT build flag is enabled. 667 668- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 669 and Group1 secure interrupts using the firmware configuration framework. The 670 platform specific secure interrupt property descriptor is retrieved from 671 device tree in runtime rather than depending on static C structure at compile 672 time. This is currently an experimental feature. 673 674- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 675 This feature creates a library of functions to be placed in ROM and thus 676 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 677 is 0. 678 679- ``V``: Verbose build. If assigned anything other than 0, the build commands 680 are printed. Default is 0. 681 682- ``VERSION_STRING``: String used in the log output for each TF-A image. 683 Defaults to a string formed by concatenating the version number, build type 684 and build string. 685 686- ``W``: Warning level. Some compiler warning options of interest have been 687 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 688 each level enabling more warning options. Default is 0. 689 690- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 691 the CPU after warm boot. This is applicable for platforms which do not 692 require interconnect programming to enable cache coherency (eg: single 693 cluster platforms). If this option is enabled, then warm boot path 694 enables D-caches immediately after enabling MMU. This option defaults to 0. 695 696- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 697 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 698 default value of this flag is ``no``. Note this option must be enabled only 699 for ARM architecture greater than Armv8.5-A. 700 701- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 702 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 703 The default value of this flag is ``0``. 704 705 ``AT`` speculative errata workaround disables stage1 page table walk for 706 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 707 produces either the correct result or failure without TLB allocation. 708 709 This boolean option enables errata for all below CPUs. 710 711 +---------+--------------+-------------------------+ 712 | Errata | CPU | Workaround Define | 713 +=========+==============+=========================+ 714 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 715 +---------+--------------+-------------------------+ 716 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 717 +---------+--------------+-------------------------+ 718 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 719 +---------+--------------+-------------------------+ 720 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 721 +---------+--------------+-------------------------+ 722 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 723 +---------+--------------+-------------------------+ 724 725 .. note:: 726 This option is enabled by build only if platform sets any of above defines 727 mentioned in ’Workaround Define' column in the table. 728 If this option is enabled for the EL3 software then EL2 software also must 729 implement this workaround due to the behaviour of the errata mentioned 730 in new SDEN document which will get published soon. 731 732- ``RAS_TRAP_LOWER_EL_ERR_ACCESS``: This flag enables/disables the SCR_EL3.TERR 733 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 734 This flag is disabled by default. 735 736- ``OPENSSL_DIR``: This flag is used to provide the installed openssl directory 737 path on the host machine which is used to build certificate generation and 738 firmware encryption tool. 739 740- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 741 functions that wait for an arbitrary time length (udelay and mdelay). The 742 default value is 0. 743 744GICv3 driver options 745-------------------- 746 747GICv3 driver files are included using directive: 748 749``include drivers/arm/gic/v3/gicv3.mk`` 750 751The driver can be configured with the following options set in the platform 752makefile: 753 754- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 755 Enabling this option will add runtime detection support for the 756 GIC-600, so is safe to select even for a GIC500 implementation. 757 This option defaults to 0. 758 759- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 760 functionality. This option defaults to 0 761 762- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 763 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 764 functions. This is required for FVP platform which need to simulate GIC save 765 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 766 767- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 768 This option defaults to 0. 769 770- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 771 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 772 773Debugging options 774----------------- 775 776To compile a debug version and make the build more verbose use 777 778.. code:: shell 779 780 make PLAT=<platform> DEBUG=1 V=1 all 781 782AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for 783example DS-5) might not support this and may need an older version of DWARF 784symbols to be emitted by GCC. This can be achieved by using the 785``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the 786version to 2 is recommended for DS-5 versions older than 5.16. 787 788When debugging logic problems it might also be useful to disable all compiler 789optimizations by using ``-O0``. 790 791.. warning:: 792 Using ``-O0`` could cause output images to be larger and base addresses 793 might need to be recalculated (see the **Memory layout on Arm development 794 platforms** section in the :ref:`Firmware Design`). 795 796Extra debug options can be passed to the build system by setting ``CFLAGS`` or 797``LDFLAGS``: 798 799.. code:: shell 800 801 CFLAGS='-O0 -gdwarf-2' \ 802 make PLAT=<platform> DEBUG=1 V=1 all 803 804Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 805ignored as the linker is called directly. 806 807It is also possible to introduce an infinite loop to help in debugging the 808post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 809``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 810section. In this case, the developer may take control of the target using a 811debugger when indicated by the console output. When using DS-5, the following 812commands can be used: 813 814:: 815 816 # Stop target execution 817 interrupt 818 819 # 820 # Prepare your debugging environment, e.g. set breakpoints 821 # 822 823 # Jump over the debug loop 824 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 825 826 # Resume execution 827 continue 828 829-------------- 830 831*Copyright (c) 2019-2020, Arm Limited. All rights reserved.* 832