1 /* 2 * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 /* Required platform porting definitions */ 20 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 21 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 22 U(FVP_MAX_PE_PER_CPU)) 23 24 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 25 PLATFORM_CORE_COUNT + U(1)) 26 27 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 28 29 /* 30 * Other platform porting definitions are provided by included headers 31 */ 32 33 /* 34 * Required ARM standard platform porting definitions 35 */ 36 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 37 38 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 39 40 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 41 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 42 43 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 44 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 45 46 /* virtual address used by dynamic mem_protect for chunk_base */ 47 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 48 49 /* No SCP in FVP */ 50 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 51 52 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 53 #define PLAT_ARM_DRAM2_SIZE UL(0x80000000) 54 55 #define PLAT_HW_CONFIG_DTB_BASE ULL(0x82000000) 56 #define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000) 57 58 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 59 PLAT_HW_CONFIG_DTB_BASE, \ 60 PLAT_HW_CONFIG_DTB_SIZE, \ 61 MT_MEMORY | MT_RO | MT_NS) 62 /* 63 * Load address of BL33 for this platform port 64 */ 65 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 66 67 /* 68 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 69 * plat_arm_mmap array defined for each BL stage. 70 */ 71 #if defined(IMAGE_BL31) 72 # if SPM_MM 73 # define PLAT_ARM_MMAP_ENTRIES 10 74 # define MAX_XLAT_TABLES 9 75 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 76 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 77 # else 78 # define PLAT_ARM_MMAP_ENTRIES 9 79 # if USE_DEBUGFS 80 # define MAX_XLAT_TABLES 8 81 # else 82 # define MAX_XLAT_TABLES 7 83 # endif 84 # endif 85 #elif defined(IMAGE_BL32) 86 # define PLAT_ARM_MMAP_ENTRIES 9 87 # define MAX_XLAT_TABLES 6 88 #elif !USE_ROMLIB 89 # define PLAT_ARM_MMAP_ENTRIES 11 90 # define MAX_XLAT_TABLES 5 91 #else 92 # define PLAT_ARM_MMAP_ENTRIES 12 93 # define MAX_XLAT_TABLES 6 94 #endif 95 96 /* 97 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 98 * plus a little space for growth. 99 */ 100 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 101 102 /* 103 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 104 */ 105 106 #if USE_ROMLIB 107 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 108 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 109 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x6000) 110 #else 111 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 112 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 113 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 114 #endif 115 116 /* 117 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 118 * little space for growth. 119 */ 120 #if TRUSTED_BOARD_BOOT 121 #if COT_DESC_IN_DTB 122 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION) 123 #else 124 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) 125 #endif 126 #else 127 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) 128 #endif 129 130 #if RESET_TO_BL31 131 /* Size of Trusted SRAM - the first 4KB of shared memory */ 132 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 133 ARM_SHARED_RAM_SIZE) 134 #else 135 /* 136 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 137 * calculated using the current BL31 PROGBITS debug size plus the sizes of 138 * BL2 and BL1-RW 139 */ 140 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000) 141 #endif /* RESET_TO_BL31 */ 142 143 #ifndef __aarch64__ 144 /* 145 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 146 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 147 * BL2 and BL1-RW 148 */ 149 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 150 #endif 151 152 /* 153 * Size of cacheable stacks 154 */ 155 #if defined(IMAGE_BL1) 156 # if TRUSTED_BOARD_BOOT 157 # define PLATFORM_STACK_SIZE UL(0x1000) 158 # else 159 # define PLATFORM_STACK_SIZE UL(0x500) 160 # endif 161 #elif defined(IMAGE_BL2) 162 # if TRUSTED_BOARD_BOOT 163 # define PLATFORM_STACK_SIZE UL(0x1000) 164 # else 165 # define PLATFORM_STACK_SIZE UL(0x440) 166 # endif 167 #elif defined(IMAGE_BL2U) 168 # define PLATFORM_STACK_SIZE UL(0x400) 169 #elif defined(IMAGE_BL31) 170 # define PLATFORM_STACK_SIZE UL(0x800) 171 #elif defined(IMAGE_BL32) 172 # define PLATFORM_STACK_SIZE UL(0x440) 173 #endif 174 175 #define MAX_IO_DEVICES 3 176 #define MAX_IO_HANDLES 4 177 178 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 179 #define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE 180 #define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 181 182 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 183 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 184 185 /* 186 * PL011 related constants 187 */ 188 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 189 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 190 191 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 192 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 193 194 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 195 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 196 197 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 198 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 199 200 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 201 202 /* CCI related constants */ 203 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 204 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 205 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 206 207 /* CCI-500/CCI-550 on Base platform */ 208 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 209 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 210 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 211 212 /* CCN related constants. Only CCN 502 is currently supported */ 213 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 214 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 215 216 /* System timer related constants */ 217 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 218 219 /* Mailbox base address */ 220 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 221 222 223 /* TrustZone controller related constants 224 * 225 * Currently only filters 0 and 2 are connected on Base FVP. 226 * Filter 0 : CPU clusters (no access to DRAM by default) 227 * Filter 1 : not connected 228 * Filter 2 : LCDs (access to VRAM allowed by default) 229 * Filter 3 : not connected 230 * Programming unconnected filters will have no effect at the 231 * moment. These filter could, however, be connected in future. 232 * So care should be taken not to configure the unused filters. 233 * 234 * Allow only non-secure access to all DRAM to supported devices. 235 * Give access to the CPUs and Virtio. Some devices 236 * would normally use the default ID so allow that too. 237 */ 238 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 239 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 240 241 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 242 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 243 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 244 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 245 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 246 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 247 248 /* 249 * GIC related constants to cater for both GICv2 and GICv3 instances of an 250 * FVP. They could be overridden at runtime in case the FVP implements the 251 * legacy VE memory map. 252 */ 253 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 254 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 255 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 256 257 /* 258 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 259 * terminology. On a GICv2 system or mode, the lists will be merged and treated 260 * as Group 0 interrupts. 261 */ 262 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 263 ARM_G1S_IRQ_PROPS(grp), \ 264 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 265 GIC_INTR_CFG_LEVEL), \ 266 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 267 GIC_INTR_CFG_LEVEL) 268 269 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 270 271 #if SDEI_IN_FCONF 272 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 273 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 274 #else 275 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 276 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 277 #endif 278 279 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 280 PLAT_SP_IMAGE_NS_BUF_SIZE) 281 282 #define PLAT_SP_PRI PLAT_RAS_PRI 283 284 /* 285 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 286 */ 287 #ifdef __aarch64__ 288 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 289 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 290 #else 291 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 292 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 293 #endif 294 295 #endif /* PLATFORM_DEF_H */ 296