1# 2# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include lib/libfdt/libfdt.mk 8 9RESET_TO_BL31 := 1 10ifeq (${RESET_TO_BL31}, 0) 11$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled") 12endif 13 14ifeq (${ENABLE_PIE}, 1) 15override SEPARATE_CODE_AND_RODATA := 1 16endif 17 18CTX_INCLUDE_AARCH32_REGS := 0 19ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1) 20$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled") 21endif 22 23ifeq (${TRUSTED_BOARD_BOOT}, 1) 24$(error "TRUSTED_BOARD_BOOT must be disabled") 25endif 26 27PRELOADED_BL33_BASE := 0x80080000 28 29FPGA_PRELOADED_DTB_BASE := 0x80070000 30$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE)) 31 32FPGA_PRELOADED_CMD_LINE := 0x1000 33$(eval $(call add_define,FPGA_PRELOADED_CMD_LINE)) 34 35# Treating this as a memory-constrained port for now 36USE_COHERENT_MEM := 0 37 38# This can be overridden depending on CPU(s) used in the FPGA image 39HW_ASSISTED_COHERENCY := 1 40 41PL011_GENERIC_UART := 1 42 43FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 44 45# select a different set of CPU files, depending on whether we compile for 46# hardware assisted coherency cores or not 47ifeq (${HW_ASSISTED_COHERENCY}, 0) 48# Cores used without DSU 49 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 50 lib/cpus/aarch64/cortex_a53.S \ 51 lib/cpus/aarch64/cortex_a57.S \ 52 lib/cpus/aarch64/cortex_a72.S \ 53 lib/cpus/aarch64/cortex_a73.S 54else 55# AArch64-only cores 56 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ 57 lib/cpus/aarch64/cortex_a76ae.S \ 58 lib/cpus/aarch64/cortex_a77.S \ 59 lib/cpus/aarch64/cortex_a78.S \ 60 lib/cpus/aarch64/neoverse_n1.S \ 61 lib/cpus/aarch64/neoverse_e1.S \ 62 lib/cpus/aarch64/neoverse_zeus.S \ 63 lib/cpus/aarch64/cortex_hercules_ae.S \ 64 lib/cpus/aarch64/cortex_a65.S \ 65 lib/cpus/aarch64/cortex_a65ae.S \ 66 lib/cpus/aarch64/cortex_klein.S \ 67 lib/cpus/aarch64/cortex_matterhorn.S 68 69# AArch64/AArch32 cores 70 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 71 lib/cpus/aarch64/cortex_a75.S 72endif 73 74# Allow detection of GIC-600 75GICV3_SUPPORT_GIC600 := 1 76 77# Include GICv3 driver files 78include drivers/arm/gic/v3/gicv3.mk 79 80FPGA_GIC_SOURCES := ${GICV3_SOURCES} \ 81 plat/common/plat_gicv3.c \ 82 plat/arm/board/arm_fpga/fpga_gicv3.c 83 84FDT_SOURCES := fdts/arm_fpga.dts 85 86PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include 87 88PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S 89 90BL31_SOURCES += common/fdt_wrappers.c \ 91 common/fdt_fixup.c \ 92 drivers/delay_timer/delay_timer.c \ 93 drivers/delay_timer/generic_delay_timer.c \ 94 drivers/arm/pl011/${ARCH}/pl011_console.S \ 95 plat/common/plat_psci_common.c \ 96 plat/arm/board/arm_fpga/fpga_pm.c \ 97 plat/arm/board/arm_fpga/fpga_topology.c \ 98 plat/arm/board/arm_fpga/fpga_console.c \ 99 plat/arm/board/arm_fpga/fpga_bl31_setup.c \ 100 ${FPGA_CPU_LIBS} \ 101 ${FPGA_GIC_SOURCES} 102 103$(eval $(call MAKE_S,$(BUILD_PLAT),plat/arm/board/arm_fpga/rom_trampoline.S,31)) 104$(eval $(call MAKE_LD,$(BUILD_PLAT)/build_axf.ld,plat/arm/board/arm_fpga/build_axf.ld.S,31)) 105 106bl31.axf: bl31 dtbs ${BUILD_PLAT}/rom_trampoline.o ${BUILD_PLAT}/build_axf.ld 107 $(ECHO) " LD $@" 108 $(Q)$(LD) -T ${BUILD_PLAT}/build_axf.ld -L ${BUILD_PLAT} --strip-debug -o ${BUILD_PLAT}/bl31.axf 109 110all: bl31.axf 111