1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 /* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */ 9 10 #include <common/debug.h> 11 #include <drivers/marvell/ccu.h> 12 #include <lib/mmio.h> 13 14 #include <armada_common.h> 15 #include <mvebu.h> 16 #include <mvebu_def.h> 17 18 #if LOG_LEVEL >= LOG_LEVEL_INFO 19 #define DEBUG_ADDR_MAP 20 #endif 21 22 /* common defines */ 23 #define WIN_ENABLE_BIT (0x1) 24 /* Physical address of the base of the window = {AddrLow[19:0],20'h0} */ 25 #define ADDRESS_SHIFT (20 - 4) 26 #define ADDRESS_MASK (0xFFFFFFF0) 27 #define CCU_WIN_ALIGNMENT (0x100000) 28 29 #define IS_DRAM_TARGET(tgt) ((((tgt) == DRAM_0_TID) || \ 30 ((tgt) == DRAM_1_TID) || \ 31 ((tgt) == RAR_TID)) ? 1 : 0) 32 33 #define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + \ 34 0x90 + 4 * (win)) 35 36 /* For storage of CR, SCR, ALR, AHR abd GCR */ 37 static uint32_t ccu_regs_save[MVEBU_CCU_MAX_WINS * 4 + 1]; 38 39 #ifdef DEBUG_ADDR_MAP 40 static void dump_ccu(int ap_index) 41 { 42 uint32_t win_id, win_cr, alr, ahr; 43 uint8_t target_id; 44 uint64_t start, end; 45 46 /* Dump all AP windows */ 47 printf("\tbank target start end\n"); 48 printf("\t----------------------------------------------------\n"); 49 for (win_id = 0; win_id < MVEBU_CCU_MAX_WINS; win_id++) { 50 win_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 51 if (win_cr & WIN_ENABLE_BIT) { 52 target_id = (win_cr >> CCU_TARGET_ID_OFFSET) & 53 CCU_TARGET_ID_MASK; 54 alr = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, 55 win_id)); 56 ahr = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_index, 57 win_id)); 58 start = ((uint64_t)alr << ADDRESS_SHIFT); 59 end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT); 60 printf("\tccu%d %02x 0x%016llx 0x%016llx\n", 61 win_id, target_id, start, end); 62 } 63 } 64 win_cr = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_index)); 65 target_id = (win_cr >> CCU_GCR_TARGET_OFFSET) & CCU_GCR_TARGET_MASK; 66 printf("\tccu GCR %d - all other transactions\n", target_id); 67 } 68 #endif 69 70 void ccu_win_check(struct addr_map_win *win) 71 { 72 /* check if address is aligned to 1M */ 73 if (IS_NOT_ALIGN(win->base_addr, CCU_WIN_ALIGNMENT)) { 74 win->base_addr = ALIGN_UP(win->base_addr, CCU_WIN_ALIGNMENT); 75 NOTICE("%s: Align up the base address to 0x%llx\n", 76 __func__, win->base_addr); 77 } 78 79 /* size parameter validity check */ 80 if (IS_NOT_ALIGN(win->win_size, CCU_WIN_ALIGNMENT)) { 81 win->win_size = ALIGN_UP(win->win_size, CCU_WIN_ALIGNMENT); 82 NOTICE("%s: Aligning size to 0x%llx\n", 83 __func__, win->win_size); 84 } 85 } 86 87 int ccu_is_win_enabled(int ap_index, uint32_t win_id) 88 { 89 return mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)) & 90 WIN_ENABLE_BIT; 91 } 92 93 void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id) 94 { 95 uint32_t ccu_win_reg; 96 uint32_t alr, ahr; 97 uint64_t end_addr; 98 99 if ((win_id == 0) || (win_id > MVEBU_CCU_MAX_WINS)) { 100 ERROR("Enabling wrong CCU window %d!\n", win_id); 101 return; 102 } 103 104 end_addr = (win->base_addr + win->win_size - 1); 105 alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK); 106 ahr = (uint32_t)((end_addr >> ADDRESS_SHIFT) & ADDRESS_MASK); 107 108 mmio_write_32(CCU_WIN_ALR_OFFSET(ap_index, win_id), alr); 109 mmio_write_32(CCU_WIN_AHR_OFFSET(ap_index, win_id), ahr); 110 111 ccu_win_reg = WIN_ENABLE_BIT; 112 ccu_win_reg |= (win->target_id & CCU_TARGET_ID_MASK) 113 << CCU_TARGET_ID_OFFSET; 114 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), ccu_win_reg); 115 } 116 117 static void ccu_disable_win(int ap_index, uint32_t win_id) 118 { 119 uint32_t win_reg; 120 121 if ((win_id == 0) || (win_id > MVEBU_CCU_MAX_WINS)) { 122 ERROR("Disabling wrong CCU window %d!\n", win_id); 123 return; 124 } 125 126 win_reg = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 127 win_reg &= ~WIN_ENABLE_BIT; 128 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), win_reg); 129 } 130 131 /* Insert/Remove temporary window for using the out-of reset default 132 * CPx base address to access the CP configuration space prior to 133 * the further base address update in accordance with address mapping 134 * design. 135 * 136 * NOTE: Use the same window array for insertion and removal of 137 * temporary windows. 138 */ 139 void ccu_temp_win_insert(int ap_index, struct addr_map_win *win, int size) 140 { 141 uint32_t win_id; 142 143 for (int i = 0; i < size; i++) { 144 win_id = MVEBU_CCU_MAX_WINS - 1 - i; 145 ccu_win_check(win); 146 ccu_enable_win(ap_index, win, win_id); 147 win++; 148 } 149 } 150 151 /* 152 * NOTE: Use the same window array for insertion and removal of 153 * temporary windows. 154 */ 155 void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size) 156 { 157 uint32_t win_id; 158 159 for (int i = 0; i < size; i++) { 160 uint64_t base; 161 uint32_t target; 162 163 win_id = MVEBU_CCU_MAX_WINS - 1 - i; 164 165 target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 166 target >>= CCU_TARGET_ID_OFFSET; 167 target &= CCU_TARGET_ID_MASK; 168 169 base = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, win_id)); 170 base <<= ADDRESS_SHIFT; 171 172 if ((win->target_id != target) || (win->base_addr != base)) { 173 ERROR("%s: Trying to remove bad window-%d!\n", 174 __func__, win_id); 175 continue; 176 } 177 ccu_disable_win(ap_index, win_id); 178 win++; 179 } 180 } 181 182 /* Returns current DRAM window target (DRAM_0_TID, DRAM_1_TID, RAR_TID) 183 * NOTE: Call only once for each AP. 184 * The AP0 DRAM window is located at index 2 only at the BL31 execution start. 185 * Then it relocated to index 1 for matching the rest of APs DRAM settings. 186 * Calling this function after relocation will produce wrong results on AP0 187 */ 188 static uint32_t ccu_dram_target_get(int ap_index) 189 { 190 /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. 191 * All the rest of detected APs will use window at index 1. 192 * The AP0 DRAM window is moved from index 2 to 1 during 193 * init_ccu() execution. 194 */ 195 const uint32_t win_id = (ap_index == 0) ? 2 : 1; 196 uint32_t target; 197 198 target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 199 target >>= CCU_TARGET_ID_OFFSET; 200 target &= CCU_TARGET_ID_MASK; 201 202 return target; 203 } 204 205 void ccu_dram_target_set(int ap_index, uint32_t target) 206 { 207 /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. 208 * All the rest of detected APs will use window at index 1. 209 * The AP0 DRAM window is moved from index 2 to 1 210 * during init_ccu() execution. 211 */ 212 const uint32_t win_id = (ap_index == 0) ? 2 : 1; 213 uint32_t dram_cr; 214 215 dram_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 216 dram_cr &= ~(CCU_TARGET_ID_MASK << CCU_TARGET_ID_OFFSET); 217 dram_cr |= (target & CCU_TARGET_ID_MASK) << CCU_TARGET_ID_OFFSET; 218 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), dram_cr); 219 } 220 221 /* Setup CCU DRAM window and enable it */ 222 void ccu_dram_win_config(int ap_index, struct addr_map_win *win) 223 { 224 #if IMAGE_BLE /* BLE */ 225 /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. 226 * Since the BootROM is not accessing DRAM at BLE stage, 227 * the DRAM window can be temporarely disabled. 228 */ 229 const uint32_t win_id = (ap_index == 0) ? 2 : 1; 230 #else /* end of BLE */ 231 /* At the ccu_init() execution stage, DRAM windows of all APs 232 * are arranged at index 1. 233 * The AP0 still has the old window BootROM DRAM at index 2, so 234 * the window-1 can be safely disabled without breaking the DRAM access. 235 */ 236 const uint32_t win_id = 1; 237 #endif 238 239 ccu_disable_win(ap_index, win_id); 240 /* enable write secure (and clear read secure) */ 241 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), 242 CCU_WIN_ENA_WRITE_SECURE); 243 ccu_win_check(win); 244 ccu_enable_win(ap_index, win, win_id); 245 } 246 247 /* Save content of CCU window + GCR */ 248 static void ccu_save_win_range(int ap_id, int win_first, 249 int win_last, uint32_t *buffer) 250 { 251 int win_id, idx; 252 /* Save CCU */ 253 for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) { 254 buffer[idx++] = mmio_read_32(CCU_WIN_CR_OFFSET(ap_id, win_id)); 255 buffer[idx++] = mmio_read_32(CCU_WIN_SCR_OFFSET(ap_id, win_id)); 256 buffer[idx++] = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_id, win_id)); 257 buffer[idx++] = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_id, win_id)); 258 } 259 buffer[idx] = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_id)); 260 } 261 262 /* Restore content of CCU window + GCR */ 263 static void ccu_restore_win_range(int ap_id, int win_first, 264 int win_last, uint32_t *buffer) 265 { 266 int win_id, idx; 267 /* Restore CCU */ 268 for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) { 269 mmio_write_32(CCU_WIN_CR_OFFSET(ap_id, win_id), buffer[idx++]); 270 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_id, win_id), buffer[idx++]); 271 mmio_write_32(CCU_WIN_ALR_OFFSET(ap_id, win_id), buffer[idx++]); 272 mmio_write_32(CCU_WIN_AHR_OFFSET(ap_id, win_id), buffer[idx++]); 273 } 274 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_id), buffer[idx]); 275 } 276 277 void ccu_save_win_all(int ap_id) 278 { 279 ccu_save_win_range(ap_id, 0, MVEBU_CCU_MAX_WINS - 1, ccu_regs_save); 280 } 281 282 void ccu_restore_win_all(int ap_id) 283 { 284 ccu_restore_win_range(ap_id, 0, MVEBU_CCU_MAX_WINS - 1, ccu_regs_save); 285 } 286 287 int init_ccu(int ap_index) 288 { 289 struct addr_map_win *win, *dram_win; 290 uint32_t win_id, win_reg; 291 uint32_t win_count, array_id; 292 uint32_t dram_target; 293 #if IMAGE_BLE 294 /* In BootROM context CCU Window-1 295 * has SRAM_TID target and should not be disabled 296 */ 297 const uint32_t win_start = 2; 298 #else 299 const uint32_t win_start = 1; 300 #endif 301 302 INFO("Initializing CCU Address decoding\n"); 303 304 /* Get the array of the windows and fill the map data */ 305 marvell_get_ccu_memory_map(ap_index, &win, &win_count); 306 if (win_count <= 0) { 307 INFO("No windows configurations found\n"); 308 } else if (win_count > (MVEBU_CCU_MAX_WINS - 1)) { 309 ERROR("CCU mem map array > than max available windows (%d)\n", 310 MVEBU_CCU_MAX_WINS); 311 win_count = MVEBU_CCU_MAX_WINS; 312 } 313 314 /* Need to set GCR to DRAM before all CCU windows are disabled for 315 * securing the normal access to DRAM location, which the ATF is running 316 * from. Once all CCU windows are set, which have to include the 317 * dedicated DRAM window as well, the GCR can be switched to the target 318 * defined by the platform configuration. 319 */ 320 dram_target = ccu_dram_target_get(ap_index); 321 win_reg = (dram_target & CCU_GCR_TARGET_MASK) << CCU_GCR_TARGET_OFFSET; 322 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); 323 324 /* If the DRAM window was already configured at the BLE stage, 325 * only the window target considered valid, the address range should be 326 * updated according to the platform configuration. 327 */ 328 for (dram_win = win, array_id = 0; array_id < win_count; 329 array_id++, dram_win++) { 330 if (IS_DRAM_TARGET(dram_win->target_id)) { 331 dram_win->target_id = dram_target; 332 break; 333 } 334 } 335 336 /* Disable all AP CCU windows 337 * Window-0 is always bypassed since it already contains 338 * data allowing the internal configuration space access 339 */ 340 for (win_id = win_start; win_id < MVEBU_CCU_MAX_WINS; win_id++) { 341 ccu_disable_win(ap_index, win_id); 342 /* enable write secure (and clear read secure) */ 343 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), 344 CCU_WIN_ENA_WRITE_SECURE); 345 } 346 347 /* win_id is the index of the current ccu window 348 * array_id is the index of the current memory map window entry 349 */ 350 for (win_id = win_start, array_id = 0; 351 ((win_id < MVEBU_CCU_MAX_WINS) && (array_id < win_count)); 352 win_id++) { 353 ccu_win_check(win); 354 ccu_enable_win(ap_index, win, win_id); 355 win++; 356 array_id++; 357 } 358 359 /* Get & set the default target according to board topology */ 360 win_reg = (marvell_get_ccu_gcr_target(ap_index) & CCU_GCR_TARGET_MASK) 361 << CCU_GCR_TARGET_OFFSET; 362 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); 363 364 #ifdef DEBUG_ADDR_MAP 365 dump_ccu(ap_index); 366 #endif 367 368 INFO("Done CCU Address decoding Initializing\n"); 369 370 return 0; 371 } 372 373 void errata_wa_init(void) 374 { 375 /* 376 * EERATA ID: RES-3033912 - Internal Address Space Init state causes 377 * a hang upon accesses to [0xf070_0000, 0xf07f_ffff] 378 * Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to 379 * split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and 380 * [0x80_0000, 0xff_ffff] that cause accesses to the 381 * segment of [0xf070_0000, 0xf07f_ffff] to act as RAZWI. 382 */ 383 mmio_write_32(CCU_RGF(4), 0x37f9b809); 384 mmio_write_32(CCU_RGF(5), 0x7ffa0009); 385 } 386