1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 /* AP806 Marvell SoC driver */ 9 10 #include <common/debug.h> 11 #include <drivers/marvell/ccu.h> 12 #include <drivers/marvell/cache_llc.h> 13 #include <drivers/marvell/io_win.h> 14 #include <drivers/marvell/mci.h> 15 #include <drivers/marvell/mochi/ap_setup.h> 16 #include <lib/mmio.h> 17 18 #include <mvebu_def.h> 19 20 #define SMMU_sACR (MVEBU_SMMU_BASE + 0x10) 21 #define SMMU_sACR_PG_64K (1 << 16) 22 23 #define CCU_GSPMU_CR (MVEBU_CCU_BASE(MVEBU_AP0) + \ 24 0x3F0) 25 #define GSPMU_CPU_CONTROL (0x1 << 0) 26 27 #define CCU_HTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) + \ 28 0x200) 29 #define CCU_SET_POC_OFFSET 5 30 31 #define DSS_CR0 (MVEBU_RFU_BASE + 0x100) 32 #define DVM_48BIT_VA_ENABLE (1 << 21) 33 34 /* Secure MoChi incoming access */ 35 #define SEC_MOCHI_IN_ACC_REG (MVEBU_RFU_BASE + 0x4738) 36 #define SEC_MOCHI_IN_ACC_IHB0_EN (1) 37 #define SEC_MOCHI_IN_ACC_IHB1_EN (1 << 3) 38 #define SEC_MOCHI_IN_ACC_IHB2_EN (1 << 6) 39 #define SEC_MOCHI_IN_ACC_PIDI_EN (1 << 9) 40 #define SEC_IN_ACCESS_ENA_ALL_MASTERS (SEC_MOCHI_IN_ACC_IHB0_EN | \ 41 SEC_MOCHI_IN_ACC_IHB1_EN | \ 42 SEC_MOCHI_IN_ACC_IHB2_EN | \ 43 SEC_MOCHI_IN_ACC_PIDI_EN) 44 45 /* SYSRST_OUTn Config definitions */ 46 #define MVEBU_SYSRST_OUT_CONFIG_REG (MVEBU_MISC_SOC_BASE + 0x4) 47 #define WD_MASK_SYS_RST_OUT (1 << 2) 48 49 /* Generic Timer System Controller */ 50 #define MVEBU_MSS_GTCR_REG (MVEBU_REGS_BASE + 0x581000) 51 #define MVEBU_MSS_GTCR_ENABLE_BIT 0x1 52 53 /* 54 * AXI Configuration. 55 */ 56 57 /* Used for Units of AP-806 (e.g. SDIO and etc) */ 58 #define MVEBU_AXI_ATTR_BASE (MVEBU_REGS_BASE + 0x6F4580) 59 #define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \ 60 0x4 * index) 61 62 enum axi_attr { 63 AXI_SDIO_ATTR = 0, 64 AXI_DFX_ATTR, 65 AXI_MAX_ATTR, 66 }; 67 68 static void apn_sec_masters_access_en(uint32_t enable) 69 { 70 uint32_t reg; 71 72 /* Open/Close incoming access for all masters. 73 * The access is disabled in trusted boot mode 74 * Could only be done in EL3 75 */ 76 reg = mmio_read_32(SEC_MOCHI_IN_ACC_REG); 77 if (enable) 78 mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg | 79 SEC_IN_ACCESS_ENA_ALL_MASTERS); 80 else 81 mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg & 82 ~SEC_IN_ACCESS_ENA_ALL_MASTERS); 83 } 84 85 static void setup_smmu(void) 86 { 87 uint32_t reg; 88 89 /* Set the SMMU page size to 64 KB */ 90 reg = mmio_read_32(SMMU_sACR); 91 reg |= SMMU_sACR_PG_64K; 92 mmio_write_32(SMMU_sACR, reg); 93 } 94 95 static void init_aurora2(void) 96 { 97 uint32_t reg; 98 99 /* Enable GSPMU control by CPU */ 100 reg = mmio_read_32(CCU_GSPMU_CR); 101 reg |= GSPMU_CPU_CONTROL; 102 mmio_write_32(CCU_GSPMU_CR, reg); 103 104 #if LLC_ENABLE 105 /* Enable LLC for AP806 in exclusive mode */ 106 llc_enable(0, 1); 107 108 /* Set point of coherency to DDR. 109 * This is required by units which have 110 * SW cache coherency 111 */ 112 reg = mmio_read_32(CCU_HTC_CR); 113 reg |= (0x1 << CCU_SET_POC_OFFSET); 114 mmio_write_32(CCU_HTC_CR, reg); 115 #endif /* LLC_ENABLE */ 116 117 errata_wa_init(); 118 } 119 120 121 /* MCIx indirect access register are based by default at 0xf4000000/0xf6000000 122 * to avoid conflict of internal registers of units connected via MCIx, which 123 * can be based on the same address (i.e CP1 base is also 0xf4000000), 124 * the following routines remaps the MCIx indirect bases to another domain 125 */ 126 static void mci_remap_indirect_access_base(void) 127 { 128 uint32_t mci; 129 130 for (mci = 0; mci < MCI_MAX_UNIT_ID; mci++) 131 mmio_write_32(MCIX4_REG_START_ADDRESS_REG(mci), 132 MVEBU_MCI_REG_BASE_REMAP(mci) >> 133 MCI_REMAP_OFF_SHIFT); 134 } 135 136 static void apn806_axi_attr_init(void) 137 { 138 uint32_t index, data; 139 140 /* Initialize AXI attributes for APN806 */ 141 142 /* Go over the AXI attributes and set Ax-Cache and Ax-Domain */ 143 for (index = 0; index < AXI_MAX_ATTR; index++) { 144 switch (index) { 145 /* DFX works with no coherent only - 146 * there's no option to configure the Ax-Cache and Ax-Domain 147 */ 148 case AXI_DFX_ATTR: 149 continue; 150 default: 151 /* Set Ax-Cache as cacheable, no allocate, modifiable, 152 * bufferable 153 * The values are different because Read & Write 154 * definition is different in Ax-Cache 155 */ 156 data = mmio_read_32(MVEBU_AXI_ATTR_REG(index)); 157 data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK; 158 data |= (CACHE_ATTR_WRITE_ALLOC | 159 CACHE_ATTR_CACHEABLE | 160 CACHE_ATTR_BUFFERABLE) << 161 MVEBU_AXI_ATTR_ARCACHE_OFFSET; 162 data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK; 163 data |= (CACHE_ATTR_READ_ALLOC | 164 CACHE_ATTR_CACHEABLE | 165 CACHE_ATTR_BUFFERABLE) << 166 MVEBU_AXI_ATTR_AWCACHE_OFFSET; 167 /* Set Ax-Domain as Outer domain */ 168 data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK; 169 data |= DOMAIN_OUTER_SHAREABLE << 170 MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; 171 data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK; 172 data |= DOMAIN_OUTER_SHAREABLE << 173 MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; 174 mmio_write_32(MVEBU_AXI_ATTR_REG(index), data); 175 } 176 } 177 } 178 179 static void dss_setup(void) 180 { 181 /* Enable 48-bit VA */ 182 mmio_setbits_32(DSS_CR0, DVM_48BIT_VA_ENABLE); 183 } 184 185 void misc_soc_configurations(void) 186 { 187 uint32_t reg; 188 189 /* Un-mask Watchdog reset from influencing the SYSRST_OUTn. 190 * Otherwise, upon WD timeout, the WD reset signal won't trigger reset 191 */ 192 reg = mmio_read_32(MVEBU_SYSRST_OUT_CONFIG_REG); 193 reg &= ~(WD_MASK_SYS_RST_OUT); 194 mmio_write_32(MVEBU_SYSRST_OUT_CONFIG_REG, reg); 195 } 196 197 void ap_init(void) 198 { 199 /* Setup Aurora2. */ 200 init_aurora2(); 201 202 /* configure MCI mapping */ 203 mci_remap_indirect_access_base(); 204 205 /* configure IO_WIN windows */ 206 init_io_win(MVEBU_AP0); 207 208 /* configure CCU windows */ 209 init_ccu(MVEBU_AP0); 210 211 /* configure DSS */ 212 dss_setup(); 213 214 /* configure the SMMU */ 215 setup_smmu(); 216 217 /* Open APN incoming access for all masters */ 218 apn_sec_masters_access_en(1); 219 220 /* configure axi for APN*/ 221 apn806_axi_attr_init(); 222 223 /* misc configuration of the SoC */ 224 misc_soc_configurations(); 225 } 226 227 void ap_ble_init(void) 228 { 229 } 230 231 int ap_get_count(void) 232 { 233 return 1; 234 } 235 236 void update_cp110_default_win(int cp_id) 237 { 238 } 239