| 6ce4c6c0 | 20-Feb-2023 |
Rob Hughes <robert.hughes@arm.com> |
docs(ethos-n): update porting-guide.rst for NPU
Add some missing configuration that must be done for supporting NPU on
other platforms.
Signed-off-by: Rob Hughes <robert.hughes@arm.com>
Signed-off-
docs(ethos-n): update porting-guide.rst for NPU
Add some missing configuration that must be done for supporting NPU on
other platforms.
Signed-off-by: Rob Hughes <robert.hughes@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: Ic505ea60f73b970d0d7ded101830eb2ce8c7ab64
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| 33bcaed1 | 17-Jan-2023 |
Rob Hughes <robert.hughes@arm.com> |
feat(ethos-n)!: load NPU firmware at BL2
BL2 on Juno now loads the Arm(R) Ethos(TM)-N NPU firmware into a fixed
address, using the existing image loading framework.
Includes support for TRUSTED_BOA
feat(ethos-n)!: load NPU firmware at BL2
BL2 on Juno now loads the Arm(R) Ethos(TM)-N NPU firmware into a fixed
address, using the existing image loading framework.
Includes support for TRUSTED_BOARD_BOOT, if enabled, using the firmware
content and key certificates from the FIP.
Supports the ARM_IO_IN_DTB option so can specify the firmware location
from the dtb rather than it being hardcoded to the FIP
Update makefile to automatically embed the appropriate images into the
FIP.
BREAKING CHANGE: Building the FIP when TZMP1 support is enabled in the
NPU driver now requires a parameter to specify the NPU firmware file.
Signed-off-by: Rob Hughes <robert.hughes@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I8cd64fb20d58f8bd539facb085606213d6cead06
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| 035c9119 | 26-Aug-2022 |
Bjorn Engstrom <bjoern.engstroem@arm.com> |
build(ethos-n): add TZMP1 build flag
For the Arm(R) Ethos(TM)-N NPU Driver to support running inference with
protected memory the TZC must be configured with appropriate regions.
This is controlled
build(ethos-n): add TZMP1 build flag
For the Arm(R) Ethos(TM)-N NPU Driver to support running inference with
protected memory the TZC must be configured with appropriate regions.
This is controlled in build time by the now added build flag.
The new build flag is only supported with the Arm Juno platform and the
TZC is configured with default memory regions as if TZMP1 wasn't
enabled to facilitate adding the new memory regions later.
Signed-off-by: Bjorn Engstrom <bjoern.engstroem@arm.com>
Signed-off-by: Rob Hughes <robert.hughes@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I9dc49ac5d091cfbc8c20d7c3ab394a2836438b0f
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| a4c69581 | 15-Mar-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3" into integration |
| 42d4d3ba | 22-Nov-2022 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3
BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is runnin
refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3
BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is running at EL3 exception level
These two scenarios are not exactly same even though first implicitly
means second to be true. To distinguish between these two use cases we
introduce new macros.
BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2.
Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where
BL2 runs at EL3 (including four world systems).
BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the
repository.
Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
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| 2b932f83 | 06-Mar-2023 |
Belsare, Akshay <akshay.belsare@amd.com> |
docs(zynqmp): add ddr address usage
Update documentation for TF-A DDR address range usage when the FSBL is
run on RPU instead of APU.
Change-Id: I223d67c35ac9ce3384820531a7453d3b32a1eb58
Signed-off
docs(zynqmp): add ddr address usage
Update documentation for TF-A DDR address range usage when the FSBL is
run on RPU instead of APU.
Change-Id: I223d67c35ac9ce3384820531a7453d3b32a1eb58
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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| c52a142b | 27-Feb-2023 |
Akshay Belsare <akshay.belsare@amd.com> |
fix(zynqmp): conditional reservation of memory in DTB
When the TF-A is placed in DDR memory range, the DDR memory range is
getting explicitly reserved in the default device tree by TF-A.
This create
fix(zynqmp): conditional reservation of memory in DTB
When the TF-A is placed in DDR memory range, the DDR memory range is
getting explicitly reserved in the default device tree by TF-A.
This creates an error condition in the use case where Device tree is
not present or it is present at a different location.
To fix this, a new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is
introduced. The TF-A will reserve the DDR memory only when a valid
DTB address is provided to XILINX_OF_BOARD_DTB_ADDR during build.
Now the user has options, either manually reserve the desired
DDR address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.
Change-Id: I846fa373ba9f7c984eda3a55ccaaa622082cad81
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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| 9c571fb0 | 17-Feb-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(zynqmp): add support for custom sip service" into integration |
| 496d7081 | 15-Feb-2023 |
Amit Nagal <amit.nagal@amd.com> |
feat(zynqmp): add support for custom sip service
Add support for custom sip service.
Bare minimum implementation for custom_smc_handler is provided
by platform. Actual definition for custom_smc_hand
feat(zynqmp): add support for custom sip service
Add support for custom sip service.
Bare minimum implementation for custom_smc_handler is provided
by platform. Actual definition for custom_smc_handler will be provided
by custom pkg.
This feature is going to be used by external libraries. For example
for checking it's status.
The similar approach is also used by qti/{sc7180,sc7280} platforms
by providing a way to select QTISECLIB_PATH.
This code is providing a generic way how to wire any code
via custom $(CUSTOM_PKG_PATH)/custom_pkg.mk makefile with also an
option to wire custom SMC. SMC functionality depends on "package".
Change-Id: Icedffd582f76f89fc399b0bb2e05cdaee9b743a0
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
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| 2537f072 | 15-Feb-2023 |
Akshay Belsare <akshay.belsare@amd.com> |
fix(zynqmp): with DEBUG=1 move bl31 to DDR range
Due to size constraints in OCM memory range keeping the bl31 with
DEBUG=1 overlaps with the memory range from other Firmware thus
affecting the bootf
fix(zynqmp): with DEBUG=1 move bl31 to DDR range
Due to size constraints in OCM memory range keeping the bl31 with
DEBUG=1 overlaps with the memory range from other Firmware thus
affecting the bootflow on target.
bl31 binary can not be placed in OCM memory range when built with
DEBUG=1.
With DEBUG=1, by default bl31 is moved to DDR memory range
0x1000-0x7FFFF.
The user can provide a custom DDR memory range during build time using
the build parameters ZYNQMP_ATF_MEM_BASE and ZYNQMP_ATF_MEM_SIZE.
Change-Id: I167d5eadbae7c6d3ec9b32f494b0b1a819bea5b0
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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| 5a77fd3b | 15-Feb-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "docs(qemu): delineate flash based boot method" into integration |
| 0cbcccc0 | 13-Feb-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
docs: fix broken Juno links
Certain links to Juno documentation point to a location that were
removed at some point, or are unused. Fix links to point to the latest
available version on Arm's public
docs: fix broken Juno links
Certain links to Juno documentation point to a location that were
removed at some point, or are unused. Fix links to point to the latest
available version on Arm's public documentation site, and remove those
that are no longer being used.
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Change-Id: I59202767db8834e9c302b2826f3faee47d3a5edd
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| d9bd35e3 | 06-Feb-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
docs(qemu): delineate flash based boot method
Make the language around the explanation for booting via secure flash
clearer. Provide details into the intent of the options given to QEMU.
Change-Id:
docs(qemu): delineate flash based boot method
Make the language around the explanation for booting via secure flash
clearer. Provide details into the intent of the options given to QEMU.
Change-Id: Ia573b900aaa2346cad4f82191110b978f9bd5481
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| 30e8bc36 | 18-Jan-2023 |
Akshay Belsare <akshay.belsare@amd.com> |
feat(versal-net): add jtag dcc support
Add support for JTAG Debug Communication Channel(DCC), using the dcc
console driver, for Versal NET platform.
UART0/UART1 is not configured when the JTAG DCC i
feat(versal-net): add jtag dcc support
Add support for JTAG Debug Communication Channel(DCC), using the dcc
console driver, for Versal NET platform.
UART0/UART1 is not configured when the JTAG DCC is used as console for
the platform.
Though DCC is not using any UART, VERSAL_NET_UART_BASE needs
to be defined in the platform code. If its not defined, build errors
are observed.
Now VERSAL_NET_UART_BASE by default points to UART0 base.
Check for valid console(pl011, pl011_0, pl011_1, dcc) is
being done in the platform makefile, the error condition in
setting the value of VERSAL_NET_UART_BASE is redundant, thus the error
message is removed from the code.
Change-Id: I1085433055abea13526230cff4d4183ff7a01477
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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| 9b1dad8b | 01-Dec-2022 |
laurenw-arm <lauren.wehrmeister@arm.com> |
docs(arm): add ARM_ROTPK_LOCATION variant full key
Updating documentation to reflect the new ARM_ROTPK_LOCATION variant of
the full ROTPK, as opposed to the hash of it.
Change-Id: I0f83c519bd607ef1
docs(arm): add ARM_ROTPK_LOCATION variant full key
Updating documentation to reflect the new ARM_ROTPK_LOCATION variant of
the full ROTPK, as opposed to the hash of it.
Change-Id: I0f83c519bd607ef1270c7d30ee9bc55451ce4ae2
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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| 9aef90cc | 21-Nov-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "docs(qemu): document steps to run in OpenCI" into integration |
| a5667be0 | 15-Nov-2022 |
Harrison Mutai <harrison.mutai@arm.com> |
docs(qemu): document steps to run in OpenCI
Add details on how to run QEMU in OpenCI, and what tests are currently
supported.
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Change-Id: I291e
docs(qemu): document steps to run in OpenCI
Add details on how to run QEMU in OpenCI, and what tests are currently
supported.
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Change-Id: I291e4eb64a58c766519ff7dcac4841ae75c3934e
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| b688120c | 16-Nov-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs(marvell): fix typo 8K => A8K" into integration |
| c65bf2d1 | 27-Oct-2022 |
Boyan Karatotev <boyan.karatotev@arm.com> |
docs: add top level section numbering
Top level sections are not numbered. Adding numbers makes referring to
sections easier. For example the Maintainers page changes from
"about/3.1" to simply "1.3
docs: add top level section numbering
Top level sections are not numbered. Adding numbers makes referring to
sections easier. For example the Maintainers page changes from
"about/3.1" to simply "1.3.1".
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: If90a18ee8d6a6858d58f0687f31ea62b69399e04
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| 981b9dcb | 14-Nov-2022 |
Yann Gautier <yann.gautier@st.com> |
refactor(stm32mp1): remove STM32MP_USE_STM32IMAGE
The code managing legacy boot (without FIP) that was under
STM32MP_USE_STM32IMAGE flag is remove.
Change-Id: I04452453ed84567b0de39e900594a81526562
refactor(stm32mp1): remove STM32MP_USE_STM32IMAGE
The code managing legacy boot (without FIP) that was under
STM32MP_USE_STM32IMAGE flag is remove.
Change-Id: I04452453ed84567b0de39e900594a81526562259
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| b82a30c2 | 06-Oct-2022 |
Lionel Debieve <lionel.debieve@foss.st.com> |
docs(st): update documentation for TRUSTED_BOARD_BOOT
Update the documentation to indicate commands needed for
TRUSTED_BOARD_BOOT management.
Change-Id: I7b8781eaa7f8b6b8d675a625c7ff2e1ee767222a
Si
docs(st): update documentation for TRUSTED_BOARD_BOOT
Update the documentation to indicate commands needed for
TRUSTED_BOARD_BOOT management.
Change-Id: I7b8781eaa7f8b6b8d675a625c7ff2e1ee767222a
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
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| 42c70c08 | 11-Nov-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
build: deprecate Arm TC0 FVP platform
Arm has decided to deprecate the TC0 platform. The development of
software and fast models for TC0 platform has been discontinued.
TC0 platform has been superse
build: deprecate Arm TC0 FVP platform
Arm has decided to deprecate the TC0 platform. The development of
software and fast models for TC0 platform has been discontinued.
TC0 platform has been superseded by the TC1 and TC2 platforms,
which are already supported in TF-A and CI repositories.
Change-Id: I0269816a6ee733f732669027eae4e14cd60b6084
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| f41e23ea | 10-Nov-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "mp/ras_refactoring" into integration
* changes:
docs: document do_panic() and panic() helper functions
fix(ras): restrict RAS support for NS world |
| a6a1dcbe | 08-Nov-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
chore(docs): move deprecated platforms information around
We used to have a dedicated page for deprecated platforms information.
This document contained 2 pieces of information:
a) the process for
chore(docs): move deprecated platforms information around
We used to have a dedicated page for deprecated platforms information.
This document contained 2 pieces of information:
a) the process for deprecating a platform port;
b) the list of deprecated platforms to this day.
I think it makes more sense to move b) to the platforms ports landing
page, such that it is more visible.
This also has the nice effect to move the 'Deprecated platforms' title
as the last entry of the 'Platform ports' table of contents, like so:
- Platform ports
- 1. Allwinner ARMv8 SoCs
- 2. Arm Development Platforms
...
- 39. Broadcom Stingray
- Deprecated platforms
instead of it being lost in the middle of supported platform ports.
Regarding a), this gets moved under the "Processes & Policies" section.
More specifically, it gets clubbed with the existing platform
compatibility policy. The combined document gets renamed into a
"Platforms Ports Policy" document.
Change-Id: I6e9ce2abc68b8a8ac88e7bd5f21749c14c9a2af6
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| 2fe661c2 | 08-Nov-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
chore(docs): refresh platform ports landing page
- Remove mentions of Arm SGM-775 and MediaTek MT6795 platforms.
Both platform ports were deleted from TF-A source tree in the
last release (v2
chore(docs): refresh platform ports landing page
- Remove mentions of Arm SGM-775 and MediaTek MT6795 platforms.
Both platform ports were deleted from TF-A source tree in the
last release (v2.7).
- Remove mention of Arm Morello platform, as it now has a dedicated
documentation page accessible from the table of contents
(see docs/plat/arm/morello/).
Change-Id: Ie3acdddab81f5589bb36114a8a766200f5b08ad4
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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