1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/pubsub_events.h> 24 #include <lib/extensions/amu.h> 25 #include <lib/extensions/brbe.h> 26 #include <lib/extensions/mpam.h> 27 #include <lib/extensions/sme.h> 28 #include <lib/extensions/spe.h> 29 #include <lib/extensions/sve.h> 30 #include <lib/extensions/sys_reg_trace.h> 31 #include <lib/extensions/trbe.h> 32 #include <lib/extensions/trf.h> 33 #include <lib/utils.h> 34 35 #if ENABLE_FEAT_TWED 36 /* Make sure delay value fits within the range(0-15) */ 37 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 38 #endif /* ENABLE_FEAT_TWED */ 39 40 static void manage_extensions_secure(cpu_context_t *ctx); 41 42 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 43 { 44 u_register_t sctlr_elx, actlr_elx; 45 46 /* 47 * Initialise SCTLR_EL1 to the reset value corresponding to the target 48 * execution state setting all fields rather than relying on the hw. 49 * Some fields have architecturally UNKNOWN reset values and these are 50 * set to zero. 51 * 52 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 53 * 54 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 55 * required by PSCI specification) 56 */ 57 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 58 if (GET_RW(ep->spsr) == MODE_RW_64) { 59 sctlr_elx |= SCTLR_EL1_RES1; 60 } else { 61 /* 62 * If the target execution state is AArch32 then the following 63 * fields need to be set. 64 * 65 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 66 * instructions are not trapped to EL1. 67 * 68 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 69 * instructions are not trapped to EL1. 70 * 71 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 72 * CP15DMB, CP15DSB, and CP15ISB instructions. 73 */ 74 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 75 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 76 } 77 78 #if ERRATA_A75_764081 79 /* 80 * If workaround of errata 764081 for Cortex-A75 is used then set 81 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 82 */ 83 sctlr_elx |= SCTLR_IESB_BIT; 84 #endif 85 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 86 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 87 88 /* 89 * Base the context ACTLR_EL1 on the current value, as it is 90 * implementation defined. The context restore process will write 91 * the value from the context to the actual register and can cause 92 * problems for processor cores that don't expect certain bits to 93 * be zero. 94 */ 95 actlr_elx = read_actlr_el1(); 96 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 97 } 98 99 /****************************************************************************** 100 * This function performs initializations that are specific to SECURE state 101 * and updates the cpu context specified by 'ctx'. 102 *****************************************************************************/ 103 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 104 { 105 u_register_t scr_el3; 106 el3_state_t *state; 107 108 state = get_el3state_ctx(ctx); 109 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 110 111 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 112 /* 113 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 114 * indicated by the interrupt routing model for BL31. 115 */ 116 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 117 #endif 118 119 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 120 /* Get Memory Tagging Extension support level */ 121 unsigned int mte = get_armv8_5_mte_support(); 122 #endif 123 /* 124 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 125 * is set, or when MTE is only implemented at EL0. 126 */ 127 #if CTX_INCLUDE_MTE_REGS 128 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 129 scr_el3 |= SCR_ATA_BIT; 130 #else 131 if (mte == MTE_IMPLEMENTED_EL0) { 132 scr_el3 |= SCR_ATA_BIT; 133 } 134 #endif /* CTX_INCLUDE_MTE_REGS */ 135 136 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 137 if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) { 138 if (GET_RW(ep->spsr) != MODE_RW_64) { 139 ERROR("S-EL2 can not be used in AArch32\n."); 140 panic(); 141 } 142 143 scr_el3 |= SCR_EEL2_BIT; 144 } 145 146 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 147 148 /* 149 * Initialize EL1 context registers unless SPMC is running 150 * at S-EL2. 151 */ 152 #if !SPMD_SPM_AT_SEL2 153 setup_el1_context(ctx, ep); 154 #endif 155 156 manage_extensions_secure(ctx); 157 } 158 159 #if ENABLE_RME 160 /****************************************************************************** 161 * This function performs initializations that are specific to REALM state 162 * and updates the cpu context specified by 'ctx'. 163 *****************************************************************************/ 164 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 165 { 166 u_register_t scr_el3; 167 el3_state_t *state; 168 169 state = get_el3state_ctx(ctx); 170 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 171 172 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT; 173 174 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 175 } 176 #endif /* ENABLE_RME */ 177 178 /****************************************************************************** 179 * This function performs initializations that are specific to NON-SECURE state 180 * and updates the cpu context specified by 'ctx'. 181 *****************************************************************************/ 182 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 183 { 184 u_register_t scr_el3; 185 el3_state_t *state; 186 187 state = get_el3state_ctx(ctx); 188 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 189 190 /* SCR_NS: Set the NS bit */ 191 scr_el3 |= SCR_NS_BIT; 192 193 #if !CTX_INCLUDE_PAUTH_REGS 194 /* 195 * If the pointer authentication registers aren't saved during world 196 * switches the value of the registers can be leaked from the Secure to 197 * the Non-secure world. To prevent this, rather than enabling pointer 198 * authentication everywhere, we only enable it in the Non-secure world. 199 * 200 * If the Secure world wants to use pointer authentication, 201 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 202 */ 203 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 204 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 205 206 /* Allow access to Allocation Tags when MTE is implemented. */ 207 scr_el3 |= SCR_ATA_BIT; 208 209 #if HANDLE_EA_EL3_FIRST_NS 210 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 211 scr_el3 |= SCR_EA_BIT; 212 #endif 213 214 #if RAS_TRAP_NS_ERR_REC_ACCESS 215 /* 216 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 217 * and RAS ERX registers from EL1 and EL2(from any security state) 218 * are trapped to EL3. 219 * Set here to trap only for NS EL1/EL2 220 * 221 */ 222 scr_el3 |= SCR_TERR_BIT; 223 #endif 224 225 #ifdef IMAGE_BL31 226 /* 227 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 228 * indicated by the interrupt routing model for BL31. 229 */ 230 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 231 #endif 232 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 233 234 /* Initialize EL1 context registers */ 235 setup_el1_context(ctx, ep); 236 237 /* Initialize EL2 context registers */ 238 #if CTX_INCLUDE_EL2_REGS 239 240 /* 241 * Initialize SCTLR_EL2 context register using Endianness value 242 * taken from the entrypoint attribute. 243 */ 244 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 245 sctlr_el2 |= SCTLR_EL2_RES1; 246 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 247 sctlr_el2); 248 249 /* 250 * Program the ICC_SRE_EL2 to make sure the correct bits are set 251 * when restoring NS context. 252 */ 253 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 254 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 255 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 256 icc_sre_el2); 257 #endif /* CTX_INCLUDE_EL2_REGS */ 258 } 259 260 /******************************************************************************* 261 * The following function performs initialization of the cpu_context 'ctx' 262 * for first use that is common to all security states, and sets the 263 * initial entrypoint state as specified by the entry_point_info structure. 264 * 265 * The EE and ST attributes are used to configure the endianness and secure 266 * timer availability for the new execution context. 267 ******************************************************************************/ 268 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 269 { 270 u_register_t scr_el3; 271 el3_state_t *state; 272 gp_regs_t *gp_regs; 273 274 /* Clear any residual register values from the context */ 275 zeromem(ctx, sizeof(*ctx)); 276 277 /* 278 * SCR_EL3 was initialised during reset sequence in macro 279 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 280 * affect the next EL. 281 * 282 * The following fields are initially set to zero and then updated to 283 * the required value depending on the state of the SPSR_EL3 and the 284 * Security state and entrypoint attributes of the next EL. 285 */ 286 scr_el3 = read_scr(); 287 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_EA_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 288 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 289 290 /* 291 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 292 * Exception level as specified by SPSR. 293 */ 294 if (GET_RW(ep->spsr) == MODE_RW_64) { 295 scr_el3 |= SCR_RW_BIT; 296 } 297 298 /* 299 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 300 * Secure timer registers to EL3, from AArch64 state only, if specified 301 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 302 * bit always behaves as 1 (i.e. secure physical timer register access 303 * is not trapped) 304 */ 305 if (EP_GET_ST(ep->h.attr) != 0U) { 306 scr_el3 |= SCR_ST_BIT; 307 } 308 309 /* 310 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 311 * SCR_EL3.HXEn. 312 */ 313 #if ENABLE_FEAT_HCX 314 scr_el3 |= SCR_HXEn_BIT; 315 #endif 316 317 /* 318 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 319 * registers are trapped to EL3. 320 */ 321 #if ENABLE_FEAT_RNG_TRAP 322 scr_el3 |= SCR_TRNDR_BIT; 323 #endif 324 325 #if FAULT_INJECTION_SUPPORT 326 /* Enable fault injection from lower ELs */ 327 scr_el3 |= SCR_FIEN_BIT; 328 #endif 329 330 /* 331 * CPTR_EL3 was initialized out of reset, copy that value to the 332 * context register. 333 */ 334 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 335 336 /* 337 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 338 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 339 * next mode is Hyp. 340 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 341 * same conditions as HVC instructions and when the processor supports 342 * ARMv8.6-FGT. 343 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 344 * CNTPOFF_EL2 register under the same conditions as HVC instructions 345 * and when the processor supports ECV. 346 */ 347 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 348 || ((GET_RW(ep->spsr) != MODE_RW_64) 349 && (GET_M32(ep->spsr) == MODE32_hyp))) { 350 scr_el3 |= SCR_HCE_BIT; 351 352 if (is_armv8_6_fgt_present()) { 353 scr_el3 |= SCR_FGTEN_BIT; 354 } 355 356 if (get_armv8_6_ecv_support() 357 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 358 scr_el3 |= SCR_ECVEN_BIT; 359 } 360 } 361 362 #if ENABLE_FEAT_TWED 363 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 364 /* Set delay in SCR_EL3 */ 365 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 366 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 367 << SCR_TWEDEL_SHIFT); 368 369 /* Enable WFE delay */ 370 scr_el3 |= SCR_TWEDEn_BIT; 371 #endif /* ENABLE_FEAT_TWED */ 372 373 /* 374 * Populate EL3 state so that we've the right context 375 * before doing ERET 376 */ 377 state = get_el3state_ctx(ctx); 378 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 379 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 380 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 381 382 /* 383 * Store the X0-X7 value from the entrypoint into the context 384 * Use memcpy as we are in control of the layout of the structures 385 */ 386 gp_regs = get_gpregs_ctx(ctx); 387 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 388 } 389 390 /******************************************************************************* 391 * Context management library initialization routine. This library is used by 392 * runtime services to share pointers to 'cpu_context' structures for secure 393 * non-secure and realm states. Management of the structures and their associated 394 * memory is not done by the context management library e.g. the PSCI service 395 * manages the cpu context used for entry from and exit to the non-secure state. 396 * The Secure payload dispatcher service manages the context(s) corresponding to 397 * the secure state. It also uses this library to get access to the non-secure 398 * state cpu context pointers. 399 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 400 * which will be used for programming an entry into a lower EL. The same context 401 * will be used to save state upon exception entry from that EL. 402 ******************************************************************************/ 403 void __init cm_init(void) 404 { 405 /* 406 * The context management library has only global data to intialize, but 407 * that will be done when the BSS is zeroed out. 408 */ 409 } 410 411 /******************************************************************************* 412 * This is the high-level function used to initialize the cpu_context 'ctx' for 413 * first use. It performs initializations that are common to all security states 414 * and initializations specific to the security state specified in 'ep' 415 ******************************************************************************/ 416 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 417 { 418 unsigned int security_state; 419 420 assert(ctx != NULL); 421 422 /* 423 * Perform initializations that are common 424 * to all security states 425 */ 426 setup_context_common(ctx, ep); 427 428 security_state = GET_SECURITY_STATE(ep->h.attr); 429 430 /* Perform security state specific initializations */ 431 switch (security_state) { 432 case SECURE: 433 setup_secure_context(ctx, ep); 434 break; 435 #if ENABLE_RME 436 case REALM: 437 setup_realm_context(ctx, ep); 438 break; 439 #endif 440 case NON_SECURE: 441 setup_ns_context(ctx, ep); 442 break; 443 default: 444 ERROR("Invalid security state\n"); 445 panic(); 446 break; 447 } 448 } 449 450 /******************************************************************************* 451 * Enable architecture extensions on first entry to Non-secure world. 452 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 453 * it is zero. 454 ******************************************************************************/ 455 static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 456 { 457 #if IMAGE_BL31 458 #if ENABLE_SPE_FOR_LOWER_ELS 459 spe_enable(el2_unused); 460 #endif 461 462 #if ENABLE_AMU 463 amu_enable(el2_unused, ctx); 464 #endif 465 466 #if ENABLE_SME_FOR_NS 467 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ 468 sme_enable(ctx); 469 #elif ENABLE_SVE_FOR_NS 470 /* Enable SVE and FPU/SIMD for non-secure world. */ 471 sve_enable(ctx); 472 #endif 473 474 #if ENABLE_MPAM_FOR_LOWER_ELS 475 mpam_enable(el2_unused); 476 #endif 477 478 #if ENABLE_TRBE_FOR_NS 479 trbe_enable(); 480 #endif /* ENABLE_TRBE_FOR_NS */ 481 482 #if ENABLE_BRBE_FOR_NS 483 brbe_enable(); 484 #endif /* ENABLE_BRBE_FOR_NS */ 485 486 #if ENABLE_SYS_REG_TRACE_FOR_NS 487 sys_reg_trace_enable(ctx); 488 #endif /* ENABLE_SYS_REG_TRACE_FOR_NS */ 489 490 #if ENABLE_TRF_FOR_NS 491 trf_enable(); 492 #endif /* ENABLE_TRF_FOR_NS */ 493 #endif 494 } 495 496 /******************************************************************************* 497 * Enable architecture extensions on first entry to Secure world. 498 ******************************************************************************/ 499 static void manage_extensions_secure(cpu_context_t *ctx) 500 { 501 #if IMAGE_BL31 502 #if ENABLE_SME_FOR_NS 503 #if ENABLE_SME_FOR_SWD 504 /* 505 * Enable SME, SVE, FPU/SIMD in secure context, secure manager must 506 * ensure SME, SVE, and FPU/SIMD context properly managed. 507 */ 508 sme_enable(ctx); 509 #else /* ENABLE_SME_FOR_SWD */ 510 /* 511 * Disable SME, SVE, FPU/SIMD in secure context so non-secure world can 512 * safely use the associated registers. 513 */ 514 sme_disable(ctx); 515 #endif /* ENABLE_SME_FOR_SWD */ 516 #elif ENABLE_SVE_FOR_NS 517 #if ENABLE_SVE_FOR_SWD 518 /* 519 * Enable SVE and FPU in secure context, secure manager must ensure that 520 * the SVE and FPU register contexts are properly managed. 521 */ 522 sve_enable(ctx); 523 #else /* ENABLE_SVE_FOR_SWD */ 524 /* 525 * Disable SVE and FPU in secure context so non-secure world can safely 526 * use them. 527 */ 528 sve_disable(ctx); 529 #endif /* ENABLE_SVE_FOR_SWD */ 530 #endif /* ENABLE_SVE_FOR_NS */ 531 #endif /* IMAGE_BL31 */ 532 } 533 534 /******************************************************************************* 535 * The following function initializes the cpu_context for a CPU specified by 536 * its `cpu_idx` for first use, and sets the initial entrypoint state as 537 * specified by the entry_point_info structure. 538 ******************************************************************************/ 539 void cm_init_context_by_index(unsigned int cpu_idx, 540 const entry_point_info_t *ep) 541 { 542 cpu_context_t *ctx; 543 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 544 cm_setup_context(ctx, ep); 545 } 546 547 /******************************************************************************* 548 * The following function initializes the cpu_context for the current CPU 549 * for first use, and sets the initial entrypoint state as specified by the 550 * entry_point_info structure. 551 ******************************************************************************/ 552 void cm_init_my_context(const entry_point_info_t *ep) 553 { 554 cpu_context_t *ctx; 555 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 556 cm_setup_context(ctx, ep); 557 } 558 559 /******************************************************************************* 560 * Prepare the CPU system registers for first entry into realm, secure, or 561 * normal world. 562 * 563 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 564 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 565 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 566 * For all entries, the EL1 registers are initialized from the cpu_context 567 ******************************************************************************/ 568 void cm_prepare_el3_exit(uint32_t security_state) 569 { 570 u_register_t sctlr_elx, scr_el3, mdcr_el2; 571 cpu_context_t *ctx = cm_get_context(security_state); 572 bool el2_unused = false; 573 uint64_t hcr_el2 = 0U; 574 575 assert(ctx != NULL); 576 577 if (security_state == NON_SECURE) { 578 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 579 CTX_SCR_EL3); 580 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 581 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 582 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 583 CTX_SCTLR_EL1); 584 sctlr_elx &= SCTLR_EE_BIT; 585 sctlr_elx |= SCTLR_EL2_RES1; 586 #if ERRATA_A75_764081 587 /* 588 * If workaround of errata 764081 for Cortex-A75 is used 589 * then set SCTLR_EL2.IESB to enable Implicit Error 590 * Synchronization Barrier. 591 */ 592 sctlr_elx |= SCTLR_IESB_BIT; 593 #endif 594 write_sctlr_el2(sctlr_elx); 595 } else if (el_implemented(2) != EL_IMPL_NONE) { 596 el2_unused = true; 597 598 /* 599 * EL2 present but unused, need to disable safely. 600 * SCTLR_EL2 can be ignored in this case. 601 * 602 * Set EL2 register width appropriately: Set HCR_EL2 603 * field to match SCR_EL3.RW. 604 */ 605 if ((scr_el3 & SCR_RW_BIT) != 0U) 606 hcr_el2 |= HCR_RW_BIT; 607 608 /* 609 * For Armv8.3 pointer authentication feature, disable 610 * traps to EL2 when accessing key registers or using 611 * pointer authentication instructions from lower ELs. 612 */ 613 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 614 615 write_hcr_el2(hcr_el2); 616 617 /* 618 * Initialise CPTR_EL2 setting all fields rather than 619 * relying on the hw. All fields have architecturally 620 * UNKNOWN reset values. 621 * 622 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 623 * accesses to the CPACR_EL1 or CPACR from both 624 * Execution states do not trap to EL2. 625 * 626 * CPTR_EL2.TTA: Set to zero so that Non-secure System 627 * register accesses to the trace registers from both 628 * Execution states do not trap to EL2. 629 * If PE trace unit System registers are not implemented 630 * then this bit is reserved, and must be set to zero. 631 * 632 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 633 * to SIMD and floating-point functionality from both 634 * Execution states do not trap to EL2. 635 */ 636 write_cptr_el2(CPTR_EL2_RESET_VAL & 637 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 638 | CPTR_EL2_TFP_BIT)); 639 640 /* 641 * Initialise CNTHCTL_EL2. All fields are 642 * architecturally UNKNOWN on reset and are set to zero 643 * except for field(s) listed below. 644 * 645 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to 646 * Hyp mode of Non-secure EL0 and EL1 accesses to the 647 * physical timer registers. 648 * 649 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 650 * Hyp mode of Non-secure EL0 and EL1 accesses to the 651 * physical counter registers. 652 */ 653 write_cnthctl_el2(CNTHCTL_RESET_VAL | 654 EL1PCEN_BIT | EL1PCTEN_BIT); 655 656 /* 657 * Initialise CNTVOFF_EL2 to zero as it resets to an 658 * architecturally UNKNOWN value. 659 */ 660 write_cntvoff_el2(0); 661 662 /* 663 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 664 * MPIDR_EL1 respectively. 665 */ 666 write_vpidr_el2(read_midr_el1()); 667 write_vmpidr_el2(read_mpidr_el1()); 668 669 /* 670 * Initialise VTTBR_EL2. All fields are architecturally 671 * UNKNOWN on reset. 672 * 673 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 674 * 2 address translation is disabled, cache maintenance 675 * operations depend on the VMID. 676 * 677 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 678 * translation is disabled. 679 */ 680 write_vttbr_el2(VTTBR_RESET_VAL & 681 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 682 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 683 684 /* 685 * Initialise MDCR_EL2, setting all fields rather than 686 * relying on hw. Some fields are architecturally 687 * UNKNOWN on reset. 688 * 689 * MDCR_EL2.HLP: Set to one so that event counter 690 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 691 * occurs on the increment that changes 692 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 693 * implemented. This bit is RES0 in versions of the 694 * architecture earlier than ARMv8.5, setting it to 1 695 * doesn't have any effect on them. 696 * 697 * MDCR_EL2.TTRF: Set to zero so that access to Trace 698 * Filter Control register TRFCR_EL1 at EL1 is not 699 * trapped to EL2. This bit is RES0 in versions of 700 * the architecture earlier than ARMv8.4. 701 * 702 * MDCR_EL2.HPMD: Set to one so that event counting is 703 * prohibited at EL2. This bit is RES0 in versions of 704 * the architecture earlier than ARMv8.1, setting it 705 * to 1 doesn't have any effect on them. 706 * 707 * MDCR_EL2.TPMS: Set to zero so that accesses to 708 * Statistical Profiling control registers from EL1 709 * do not trap to EL2. This bit is RES0 when SPE is 710 * not implemented. 711 * 712 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 713 * EL1 System register accesses to the Debug ROM 714 * registers are not trapped to EL2. 715 * 716 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 717 * System register accesses to the powerdown debug 718 * registers are not trapped to EL2. 719 * 720 * MDCR_EL2.TDA: Set to zero so that System register 721 * accesses to the debug registers do not trap to EL2. 722 * 723 * MDCR_EL2.TDE: Set to zero so that debug exceptions 724 * are not routed to EL2. 725 * 726 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 727 * Monitors. 728 * 729 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 730 * EL1 accesses to all Performance Monitors registers 731 * are not trapped to EL2. 732 * 733 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 734 * and EL1 accesses to the PMCR_EL0 or PMCR are not 735 * trapped to EL2. 736 * 737 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 738 * architecturally-defined reset value. 739 * 740 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 741 * owning exception level is NS-EL1 and, tracing is 742 * prohibited at NS-EL2. These bits are RES0 when 743 * FEAT_TRBE is not implemented. 744 */ 745 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 746 MDCR_EL2_HPMD) | 747 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 748 >> PMCR_EL0_N_SHIFT)) & 749 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 750 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 751 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 752 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 753 MDCR_EL2_TPMCR_BIT | 754 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 755 756 write_mdcr_el2(mdcr_el2); 757 758 /* 759 * Initialise HSTR_EL2. All fields are architecturally 760 * UNKNOWN on reset. 761 * 762 * HSTR_EL2.T<n>: Set all these fields to zero so that 763 * Non-secure EL0 or EL1 accesses to System registers 764 * do not trap to EL2. 765 */ 766 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 767 /* 768 * Initialise CNTHP_CTL_EL2. All fields are 769 * architecturally UNKNOWN on reset. 770 * 771 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 772 * physical timer and prevent timer interrupts. 773 */ 774 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 775 ~(CNTHP_CTL_ENABLE_BIT)); 776 } 777 manage_extensions_nonsecure(el2_unused, ctx); 778 } 779 780 cm_el1_sysregs_context_restore(security_state); 781 cm_set_next_eret_context(security_state); 782 } 783 784 #if CTX_INCLUDE_EL2_REGS 785 /******************************************************************************* 786 * Save EL2 sysreg context 787 ******************************************************************************/ 788 void cm_el2_sysregs_context_save(uint32_t security_state) 789 { 790 u_register_t scr_el3 = read_scr(); 791 792 /* 793 * Always save the non-secure and realm EL2 context, only save the 794 * S-EL2 context if S-EL2 is enabled. 795 */ 796 if ((security_state != SECURE) || 797 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 798 cpu_context_t *ctx; 799 el2_sysregs_t *el2_sysregs_ctx; 800 801 ctx = cm_get_context(security_state); 802 assert(ctx != NULL); 803 804 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 805 806 el2_sysregs_context_save_common(el2_sysregs_ctx); 807 #if ENABLE_SPE_FOR_LOWER_ELS 808 el2_sysregs_context_save_spe(el2_sysregs_ctx); 809 #endif 810 #if CTX_INCLUDE_MTE_REGS 811 el2_sysregs_context_save_mte(el2_sysregs_ctx); 812 #endif 813 #if ENABLE_MPAM_FOR_LOWER_ELS 814 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 815 #endif 816 #if ENABLE_FEAT_FGT 817 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 818 #endif 819 #if ENABLE_FEAT_ECV 820 el2_sysregs_context_save_ecv(el2_sysregs_ctx); 821 #endif 822 #if ENABLE_FEAT_VHE 823 el2_sysregs_context_save_vhe(el2_sysregs_ctx); 824 #endif 825 #if RAS_EXTENSION 826 el2_sysregs_context_save_ras(el2_sysregs_ctx); 827 #endif 828 #if CTX_INCLUDE_NEVE_REGS 829 el2_sysregs_context_save_nv2(el2_sysregs_ctx); 830 #endif 831 #if ENABLE_TRF_FOR_NS 832 el2_sysregs_context_save_trf(el2_sysregs_ctx); 833 #endif 834 #if ENABLE_FEAT_CSV2_2 835 el2_sysregs_context_save_csv2(el2_sysregs_ctx); 836 #endif 837 #if ENABLE_FEAT_HCX 838 el2_sysregs_context_save_hcx(el2_sysregs_ctx); 839 #endif 840 } 841 } 842 843 /******************************************************************************* 844 * Restore EL2 sysreg context 845 ******************************************************************************/ 846 void cm_el2_sysregs_context_restore(uint32_t security_state) 847 { 848 u_register_t scr_el3 = read_scr(); 849 850 /* 851 * Always restore the non-secure and realm EL2 context, only restore the 852 * S-EL2 context if S-EL2 is enabled. 853 */ 854 if ((security_state != SECURE) || 855 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 856 cpu_context_t *ctx; 857 el2_sysregs_t *el2_sysregs_ctx; 858 859 ctx = cm_get_context(security_state); 860 assert(ctx != NULL); 861 862 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 863 864 el2_sysregs_context_restore_common(el2_sysregs_ctx); 865 #if ENABLE_SPE_FOR_LOWER_ELS 866 el2_sysregs_context_restore_spe(el2_sysregs_ctx); 867 #endif 868 #if CTX_INCLUDE_MTE_REGS 869 el2_sysregs_context_restore_mte(el2_sysregs_ctx); 870 #endif 871 #if ENABLE_MPAM_FOR_LOWER_ELS 872 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 873 #endif 874 #if ENABLE_FEAT_FGT 875 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 876 #endif 877 #if ENABLE_FEAT_ECV 878 el2_sysregs_context_restore_ecv(el2_sysregs_ctx); 879 #endif 880 #if ENABLE_FEAT_VHE 881 el2_sysregs_context_restore_vhe(el2_sysregs_ctx); 882 #endif 883 #if RAS_EXTENSION 884 el2_sysregs_context_restore_ras(el2_sysregs_ctx); 885 #endif 886 #if CTX_INCLUDE_NEVE_REGS 887 el2_sysregs_context_restore_nv2(el2_sysregs_ctx); 888 #endif 889 #if ENABLE_TRF_FOR_NS 890 el2_sysregs_context_restore_trf(el2_sysregs_ctx); 891 #endif 892 #if ENABLE_FEAT_CSV2_2 893 el2_sysregs_context_restore_csv2(el2_sysregs_ctx); 894 #endif 895 #if ENABLE_FEAT_HCX 896 el2_sysregs_context_restore_hcx(el2_sysregs_ctx); 897 #endif 898 } 899 } 900 #endif /* CTX_INCLUDE_EL2_REGS */ 901 902 /******************************************************************************* 903 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 904 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 905 * updating EL1 and EL2 registers. Otherwise, it calls the generic 906 * cm_prepare_el3_exit function. 907 ******************************************************************************/ 908 void cm_prepare_el3_exit_ns(void) 909 { 910 #if CTX_INCLUDE_EL2_REGS 911 cpu_context_t *ctx = cm_get_context(NON_SECURE); 912 assert(ctx != NULL); 913 914 /* Assert that EL2 is used. */ 915 #if ENABLE_ASSERTIONS 916 el3_state_t *state = get_el3state_ctx(ctx); 917 u_register_t scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 918 #endif 919 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 920 (el_implemented(2U) != EL_IMPL_NONE)); 921 922 /* 923 * Currently some extensions are configured using 924 * direct register updates. Therefore, do this here 925 * instead of when setting up context. 926 */ 927 manage_extensions_nonsecure(0, ctx); 928 929 /* 930 * Set the NS bit to be able to access the ICC_SRE_EL2 931 * register when restoring context. 932 */ 933 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 934 935 /* 936 * Ensure the NS bit change is committed before the EL2/EL1 937 * state restoration. 938 */ 939 isb(); 940 941 /* Restore EL2 and EL1 sysreg contexts */ 942 cm_el2_sysregs_context_restore(NON_SECURE); 943 cm_el1_sysregs_context_restore(NON_SECURE); 944 cm_set_next_eret_context(NON_SECURE); 945 #else 946 cm_prepare_el3_exit(NON_SECURE); 947 #endif /* CTX_INCLUDE_EL2_REGS */ 948 } 949 950 /******************************************************************************* 951 * The next four functions are used by runtime services to save and restore 952 * EL1 context on the 'cpu_context' structure for the specified security 953 * state. 954 ******************************************************************************/ 955 void cm_el1_sysregs_context_save(uint32_t security_state) 956 { 957 cpu_context_t *ctx; 958 959 ctx = cm_get_context(security_state); 960 assert(ctx != NULL); 961 962 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 963 964 #if IMAGE_BL31 965 if (security_state == SECURE) 966 PUBLISH_EVENT(cm_exited_secure_world); 967 else 968 PUBLISH_EVENT(cm_exited_normal_world); 969 #endif 970 } 971 972 void cm_el1_sysregs_context_restore(uint32_t security_state) 973 { 974 cpu_context_t *ctx; 975 976 ctx = cm_get_context(security_state); 977 assert(ctx != NULL); 978 979 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 980 981 #if IMAGE_BL31 982 if (security_state == SECURE) 983 PUBLISH_EVENT(cm_entering_secure_world); 984 else 985 PUBLISH_EVENT(cm_entering_normal_world); 986 #endif 987 } 988 989 /******************************************************************************* 990 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 991 * given security state with the given entrypoint 992 ******************************************************************************/ 993 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 994 { 995 cpu_context_t *ctx; 996 el3_state_t *state; 997 998 ctx = cm_get_context(security_state); 999 assert(ctx != NULL); 1000 1001 /* Populate EL3 state so that ERET jumps to the correct entry */ 1002 state = get_el3state_ctx(ctx); 1003 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1004 } 1005 1006 /******************************************************************************* 1007 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1008 * pertaining to the given security state 1009 ******************************************************************************/ 1010 void cm_set_elr_spsr_el3(uint32_t security_state, 1011 uintptr_t entrypoint, uint32_t spsr) 1012 { 1013 cpu_context_t *ctx; 1014 el3_state_t *state; 1015 1016 ctx = cm_get_context(security_state); 1017 assert(ctx != NULL); 1018 1019 /* Populate EL3 state so that ERET jumps to the correct entry */ 1020 state = get_el3state_ctx(ctx); 1021 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1022 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1023 } 1024 1025 /******************************************************************************* 1026 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1027 * pertaining to the given security state using the value and bit position 1028 * specified in the parameters. It preserves all other bits. 1029 ******************************************************************************/ 1030 void cm_write_scr_el3_bit(uint32_t security_state, 1031 uint32_t bit_pos, 1032 uint32_t value) 1033 { 1034 cpu_context_t *ctx; 1035 el3_state_t *state; 1036 u_register_t scr_el3; 1037 1038 ctx = cm_get_context(security_state); 1039 assert(ctx != NULL); 1040 1041 /* Ensure that the bit position is a valid one */ 1042 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1043 1044 /* Ensure that the 'value' is only a bit wide */ 1045 assert(value <= 1U); 1046 1047 /* 1048 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1049 * and set it to its new value. 1050 */ 1051 state = get_el3state_ctx(ctx); 1052 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1053 scr_el3 &= ~(1UL << bit_pos); 1054 scr_el3 |= (u_register_t)value << bit_pos; 1055 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1056 } 1057 1058 /******************************************************************************* 1059 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1060 * given security state. 1061 ******************************************************************************/ 1062 u_register_t cm_get_scr_el3(uint32_t security_state) 1063 { 1064 cpu_context_t *ctx; 1065 el3_state_t *state; 1066 1067 ctx = cm_get_context(security_state); 1068 assert(ctx != NULL); 1069 1070 /* Populate EL3 state so that ERET jumps to the correct entry */ 1071 state = get_el3state_ctx(ctx); 1072 return read_ctx_reg(state, CTX_SCR_EL3); 1073 } 1074 1075 /******************************************************************************* 1076 * This function is used to program the context that's used for exception 1077 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1078 * the required security state 1079 ******************************************************************************/ 1080 void cm_set_next_eret_context(uint32_t security_state) 1081 { 1082 cpu_context_t *ctx; 1083 1084 ctx = cm_get_context(security_state); 1085 assert(ctx != NULL); 1086 1087 cm_set_next_context(ctx); 1088 } 1089