docs(arm): document BL2 mem params override

Add documentation for the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag,
which allows platforms to supply their own
bl2_mem_params_desc.c implementation instead o

docs(arm): document BL2 mem params override

Add documentation for the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag,
which allows platforms to supply their own
bl2_mem_params_desc.c implementation instead of using the common
Arm platform implementation.

Change-Id: I1eb8d262ba404f10a3cc2a0ff23bbc3f70041115
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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docs(rdaspen): measured boot support

Add optional measured boot support for RDaspen platform to enable
image and data measurement.

Change-Id: I49097cc1bbbda3c96a6ca22f1e7e76087b3ee856
Signed-off-by

docs(rdaspen): measured boot support

Add optional measured boot support for RDaspen platform to enable
image and data measurement.

Change-Id: I49097cc1bbbda3c96a6ca22f1e7e76087b3ee856
Signed-off-by: Maximilian Berndt <maximilian.berndt@arm.com>

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docs(rdaspen): bl32 and GPT support

Added optional BL32 support for the RDaspen platform to enable
Trusted OS integration when required.

Updated documentation to clarify that if BL32 is not set, BL

docs(rdaspen): bl32 and GPT support

Added optional BL32 support for the RDaspen platform to enable
Trusted OS integration when required.

Updated documentation to clarify that if BL32 is not set, BL33 will
load directly after BL31.

Revised the ARM_GPT_SUPPORT description to note that it must be
enabled when the FIP image resides in a GPT partition on Secure Flash.

Change-Id: I79905efd026994290d0bc6c07cdf1f5a903c9194
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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fix(docs): fix some broken links

Fix few broken links from docs.

Link check was done with following steps -

[..]
tf-a/docs$ make clean -j8; poetry run make html -j8
tf-a/docs$ poetry run sphinx-bu

fix(docs): fix some broken links

Fix few broken links from docs.

Link check was done with following steps -

[..]
tf-a/docs$ make clean -j8; poetry run make html -j8
tf-a/docs$ poetry run sphinx-build -j8 -q -b linkcheck . build/
[..]

Add link check conf values to config.py
- avoid reporting false broken links when `#`(anchors) are present
in the link.
- avoid checking for broken links in "change-log.md", this is summary
of commit msg's we are not going to fix broken links in cmt-msg's

Change-Id: I384094c8dcf3e93875c9052afa79ad826b9901d9
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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docs(rdaspen): introduce rdaspen docs

RD-Aspen platform is formally introduced into the
documentation.

Refactors RD platforms separately, and a generic
Automotive RD index doc file is created.

Mai

docs(rdaspen): introduce rdaspen docs

RD-Aspen platform is formally introduced into the
documentation.

Refactors RD platforms separately, and a generic
Automotive RD index doc file is created.

Maintainers list updated for platform maintainer
of rdaspen.

Change-Id: I289a8caaa6f0e34e953f4101ee2814f1500bc9c8
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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feat(arm): unify Linux kernel as BL33 handling

Streamlines and unifies how Arm platforms pass arguments to the Linux
kernel when it is loaded as BL33. It replaces the FVP specific macro
`FVP_HW_CONF

feat(arm): unify Linux kernel as BL33 handling

Streamlines and unifies how Arm platforms pass arguments to the Linux
kernel when it is loaded as BL33. It replaces the FVP specific macro
`FVP_HW_CONFIG_ADDR` with a common macro `ARM_HW_CONFIG_ADDR` for
accessing the device tree blob base address.

For FVP the DT address is set to use `ARM_PRELOADED_DTB_BASE` if
provided, falling back to a default address otherwise.

This provides a consistent mechanism for Arm platforms to define and
override the DTB base address used during kernel handoff. It reduces the
chance of misconfiguration, and simplifies platform integration.

Change-Id: Ib668dbb1de9d42cf41c0b0ee9a316f054891752a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fvp): add a GICv5 device tree

Tested with Linux v6.17-rc1, it boots as long as cpu idle is disabled.

Change-Id: Iadeb157e9d911c4228dc62c5610676f4c07f6c11
Co-developed-by: Sascha Bischoff <sasc

feat(fvp): add a GICv5 device tree

Tested with Linux v6.17-rc1, it boots as long as cpu idle is disabled.

Change-Id: Iadeb157e9d911c4228dc62c5610676f4c07f6c11
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Co-developed-by: Lorenzo Pieralisi <lorenzo.pieralisi2@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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docs(fvp): add GICv5 build instructions and limitations

Add documentation for enabling GICv5 support in the FVP platform,
including required build options and guidance on usage. Also document
curren

docs(fvp): add GICv5 build instructions and limitations

Add documentation for enabling GICv5 support in the FVP platform,
including required build options and guidance on usage. Also document
current limitations and known constraints.

Introduce build-time checks to ensure incompatible configurations
(e.g., with SPMD or RMMD) fail early with a clear error message.

Initial GICv5 support in FVP is intended to facilitate early Linux
kernel bring-up and to assist with upstream kernel patch development.

Note: This patch is a temporary measure and should be reverted once
proper and complete GICv5 support is upstreamed in TF-A.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I2af839aec600040dfde75d74d02eff5a57ecda4e

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feat(fvp): add GICv5 support

Factors out GICv3 specific code and replace it with GICv5. This can be
selected with FVP_USE_GIC_DRIVER=FVP_GICV5. Specifically, the FCONF
logic does not apply to GICv5

feat(fvp): add GICv5 support

Factors out GICv3 specific code and replace it with GICv5. This can be
selected with FVP_USE_GIC_DRIVER=FVP_GICV5. Specifically, the FCONF
logic does not apply to GICv5 as the bindings are completely different.

This patch does not include a device tree. This will be added at a later
date.

Change-Id: Ifd0c7b4e0bc2ea1e53a6779ab4c50c4aec39dafb
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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docs(fvp): add FVP_HW_CONFIG_ADDR documentation

Add documentation to describe FVP_HW_CONFIG_ADDR, its default, and its
intended use.

Change-Id: If4cd4e712aa914fee1aeab2fa9fbe682f180b956
Signed-off-

docs(fvp): add FVP_HW_CONFIG_ADDR documentation

Add documentation to describe FVP_HW_CONFIG_ADDR, its default, and its
intended use.

Change-Id: If4cd4e712aa914fee1aeab2fa9fbe682f180b956
Signed-off-by: emily.boarer@arm.com

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docs(juno): revert SCP version for Juno to 2.14.0

Updated the Juno platform documentation to reflect testing with SCP
version 2.14.0 instead of 2.15.0. The version used in testing was
reverted in [1

docs(juno): revert SCP version for Juno to 2.14.0

Updated the Juno platform documentation to reflect testing with SCP
version 2.14.0 instead of 2.15.0. The version used in testing was
reverted in [1] due to instability in the tftf-manual-reboot tests
caused by upgrading to v2.15 and v2.16.

[1] https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/37997

Change-Id: I48c2b51a33950ad096e021d7bdd9cdb6a1303f8c
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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chore(tc): remove TC2 platform variant

Remove TC2 platform support which was deprecated in the last release.

Change-Id: Ibf4a94a0168151ebc66eaca044a143c51e974a1f
Signed-off-by: Manish V Badarkhe <M

chore(tc): remove TC2 platform variant

Remove TC2 platform support which was deprecated in the last release.

Change-Id: Ibf4a94a0168151ebc66eaca044a143c51e974a1f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes Ie33671b0,I1543aa6d into integration

* changes:
docs(fvp): clarify what `FVP` means
fix(fvp): allow PSCI 0.2 in the device tree

fix(plat): remove fvp_r

The platform has not been maintained for some years and is generally
broken. Remove it to avoid confusion.

Change-Id: I93d832d51e114689ec79969af5d96071a03f4a88
Signed-off-by

fix(plat): remove fvp_r

The platform has not been maintained for some years and is generally
broken. Remove it to avoid confusion.

Change-Id: I93d832d51e114689ec79969af5d96071a03f4a88
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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docs(fvp): clarify what `FVP` means

An FVP, as a general Arm product, is a simulation of any kind of system.
This includes all such models from FVP_TC4, FVP_RD_V3, to FVP_Base and
others. On the oth

docs(fvp): clarify what `FVP` means

An FVP, as a general Arm product, is a simulation of any kind of system.
This includes all such models from FVP_TC4, FVP_RD_V3, to FVP_Base and
others. On the other hand, an FVP as a TF-A platform means systems that
are compatible with FVP_Base. This, however, is an implicit assumption
and the term "FVP" causes ambiguity when used by TF-A developers and
interpreted by outsiders.

This patch makes this assumption explicit with a brief explanation of
the ambiguity and by specifically stating which FVPs are supported by
our fvp platform. For clarity, non-base models are removed from the list
as they have their own separate platform ports and dedicated
documentation.

Change-Id: Ie33671b09d951de0c6120061b2f4a084fd7e510a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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docs(arm): enable Linux boot from fip as BL33

Document additional functionality of TF-A to package the Linux kernel in
the fip image as a BL33 and boot it. A ramdisk is used as a file system.
The ra

docs(arm): enable Linux boot from fip as BL33

Document additional functionality of TF-A to package the Linux kernel in
the fip image as a BL33 and boot it. A ramdisk is used as a file system.
The ramdisk properties are injected in to the device tree at build time.

Change-Id: I326f920fdac4bd20572f6f0da07d012def114274
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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docs(fvp): update fvp build time options

Add new fvp specific build time options. Specifically the below:

- INITRD_SIZE
- INITRD_PATH
- INITRD_BASE

Change-Id: Ieadf01fce7a0a0a8e9e7582d7b7e371b2472

docs(fvp): update fvp build time options

Add new fvp specific build time options. Specifically the below:

- INITRD_SIZE
- INITRD_PATH
- INITRD_BASE

Change-Id: Ieadf01fce7a0a0a8e9e7582d7b7e371b247207c2
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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docs(arm): add initrd props to dtb at build time

Document the ability of the FVP platform to boot a Linux Kernel as a
preloaded image. A preloaded Linux Kernel can be booted in a normal
flow as well

docs(arm): add initrd props to dtb at build time

Document the ability of the FVP platform to boot a Linux Kernel as a
preloaded image. A preloaded Linux Kernel can be booted in a normal
flow as well as in RESET_TO_BL31. This is made possible by updating
the device tree with initrd properties at build time.

Change-Id: I4e1d8c24f82510d21b2afa06b429a18da4d623bd
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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docs(fvp): update FVP versions used

Patch series:
https://review.trustedfirmware.org/q/topic:%22gr/fvp_11_28_23%22

Migrated FVP's to use version 11.28.23 and also removed some model
testing that ar

docs(fvp): update FVP versions used

Patch series:
https://review.trustedfirmware.org/q/topic:%22gr/fvp_11_28_23%22

Migrated FVP's to use version 11.28.23 and also removed some model
testing that are now no more available or not working with newer model
configuration.

Change-Id: I58c5406ff49ad4c537391c61259d71d9610e875a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(fvp): increase GPT PPS to 1TB

- Increase PPS for FVP from 64GB to 1TB.
- GPT L0 table for 1TB PPS requires 8KB memory.
- Set FVP_TRUSTED_SRAM_SIZE to 384 with ENABLE_RME=1
option.
- Add 256MB

feat(fvp): increase GPT PPS to 1TB

- Increase PPS for FVP from 64GB to 1TB.
- GPT L0 table for 1TB PPS requires 8KB memory.
- Set FVP_TRUSTED_SRAM_SIZE to 384 with ENABLE_RME=1
option.
- Add 256MB of PCIe memory region 1 and 3GB of
PCIe memory region 2 to FVP PAS regions array.

Change-Id: Icadd528576f53c55b5d461ff4dcd357429ba622a
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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docs(arm): update docs to reflect rotpk key changes

The hashing algorithm for the rotpk is now HASH_ALG,
not always sha-256. The public development keys are
no longer in the repository and are now g

docs(arm): update docs to reflect rotpk key changes

The hashing algorithm for the rotpk is now HASH_ALG,
not always sha-256. The public development keys are
no longer in the repository and are now generated at
run-time, updates the documentation to reflect this.

Change-Id: Ic336f7aca858e9b6a1af6d6e6dc5f4aa428da179
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge changes from topic "rd1ae-bl32" into integration

* changes:
feat(rd1ae): add Generic Timer in device tree
docs(rd1ae): update documentation to include BL32
feat(rd1ae): add support for O

Merge changes from topic "rd1ae-bl32" into integration

* changes:
feat(rd1ae): add Generic Timer in device tree
docs(rd1ae): update documentation to include BL32
feat(rd1ae): add support for OP-TEE SPMC

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docs(rd1ae): update documentation to include BL32

Update the boot sequence in the RD-1 AE documentation
to include BL32 (OP-TEE).

Signed-off-by: Ziad Elhanafy <ziad.elhanafy@arm.com>
Change-Id: I25

docs(rd1ae): update documentation to include BL32

Update the boot sequence in the RD-1 AE documentation
to include BL32 (OP-TEE).

Signed-off-by: Ziad Elhanafy <ziad.elhanafy@arm.com>
Change-Id: I25fdc114bb71d3ad7e1bb2d845f758d6af037e3d

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