1Booting Firmware Update images 2------------------------------ 3 4When Firmware Update (FWU) is enabled there are at least 2 new images 5that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the 6FWU FIP. 7 8The additional fip images must be loaded with: 9 10:: 11 12 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address] 13 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address] 14 15The address ns_bl1u_base_address is the value of NS_BL1U_BASE. 16In the same way, the address ns_bl2u_base_address is the value of 17NS_BL2U_BASE. 18 19Booting an EL3 payload 20---------------------- 21 22The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for 23the secondary CPUs holding pen to work properly. Unfortunately, its reset value 24is undefined on the FVP platform and the FVP platform code doesn't clear it. 25Therefore, one must modify the way the model is normally invoked in order to 26clear the mailbox at start-up. 27 28One way to do that is to create an 8-byte file containing all zero bytes using 29the following command: 30 31.. code:: shell 32 33 dd if=/dev/zero of=mailbox.dat bs=1 count=8 34 35and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``) 36using the following model parameters: 37 38:: 39 40 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs] 41 --data=mailbox.dat@0x04000000 [Foundation FVP] 42 43To provide the model with the EL3 payload image, the following methods may be 44used: 45 46#. If the EL3 payload is able to execute in place, it may be programmed into 47 flash memory. On Base Cortex and AEM FVPs, the following model parameter 48 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already 49 used for the FIP): 50 51 :: 52 53 -C bp.flashloader1.fname="<path-to>/<el3-payload>" 54 55 On Foundation FVP, there is no flash loader component and the EL3 payload 56 may be programmed anywhere in flash using method 3 below. 57 58#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5 59 command may be used to load the EL3 payload ELF image over JTAG: 60 61 :: 62 63 load <path-to>/el3-payload.elf 64 65#. The EL3 payload may be pre-loaded in volatile memory using the following 66 model parameters: 67 68 :: 69 70 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs] 71 --data="<path-to>/<el3-payload>"@address [Foundation FVP] 72 73 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address 74 used when building TF-A. 75 76Booting a preloaded kernel image 77-------------------------------- 78 79TF-A can boot a Linux kernel, which uses a ramdisk as a filesystem. The 80required initrd properties are injected in to the device tree blob (DTB) at 81build time. 82 83Preloaded kernel image - Normal flow 84^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 85 86The following example uses a simplified boot flow to boot a Linux kernel 87using TF-A. This can be useful if the kernel is already present in memory 88(like in FVP). 89 90For example, if the kernel is loaded at ``0x80080000`` the firmware can be 91built like this: 92 93.. code:: shell 94 95 make PLAT=fvp DEBUG=1 \ 96 ARM_LINUX_KERNEL_AS_BL33=1 \ 97 PRELOADED_BL33_BASE=0x80080000 \ 98 INITRD_SIZE=0x8000000 \ 99 all fip 100 101The options ``INITRD_SIZE`` or ``INITRD_PATH`` triggers the insertion of initrd 102properties in to the DTB. ``INITRD_BASE`` is also required but a default value 103is set by the FVP platform. 104 105The options available here are: 106 107 :: 108 INITRD_BASE: Set the initrd base address in memory. Defaults to 0x90000000 in FVP. 109 INITRD_SIZE: Set the initrd size in dec or hex format. Hex format must precede with '0x'. 110 INITRD_PATH: Provide an initrd path for the build time to determine its exact size. 111 112Users can provide either ``INITRD_SIZE`` or ``INITRD_PATH`` to set the initrd 113size value. ``INITRD_SIZE`` takes prioty over ``INITRD_PATH``. 114 115Now the FVP binary can be run with the following command: 116 117.. code:: shell 118 119 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 120 -C bp.secureflashloader.fname=<path-to>/bl1.bin \ 121 -C bp.flashloader0.fname=<path-to>/fip.bin \ 122 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 123 --data cluster0.cpu0="<path-to>/<initrd.bin>"@0x90000000 124 125.. note:: 126 Providing a higher value for an initrd size than the actual size of the file 127 is supported but it will trigger a non-breaking "Initramfs unpacking failed" 128 error by the kernel at runtime. This error can be ignored because initrd's 129 can be stacked one after another, when the kernel unpacks the first initrd it 130 looks for another in the extra space which it won't find, hence the error. 131 132Booting a preloaded kernel image - Reset to BL31 (Base FVP) 133^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 134 135We can also boot a Linux kernel by jumping directly to BL31 ``RESET_TO_BL31=1``. 136This requires preloading a DTB into memory. We can inject the initrd start and 137end properties into the DTB (HW_CONFIG) at build time which is then stored by 138TF-A in ``build/fvp/<build-type>/fdts/`` directory. 139 140For example, we can build the firmware as: 141 142.. code:: shell 143 144 make PLAT=fvp DEBUG=1 \ 145 RESET_TO_BL31=1 \ 146 ARM_LINUX_KERNEL_AS_BL33=1 \ 147 PRELOADED_BL33_BASE=0x80080000 \ 148 ARM_PRELOADED_DTB_BASE=0x87F00000 \ 149 INITRD_BASE=0x88000000 \ 150 INITRD_PATH=<path-to>/initrd.bin 151 152Now we can run the binary as: 153 154.. code:: shell 155 156 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 157 -C cluster0.NUM_CORES=4 \ 158 -C cluster0.cpu0.RVBAR=0x04001000 \ 159 -C cluster0.cpu1.RVBAR=0x04001000 \ 160 -C cluster0.cpu2.RVBAR=0x04001000 \ 161 -C cluster0.cpu3.RVBAR=0x04001000 \ 162 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000 \ 163 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 164 --data cluster0.cpu0="<path-to>/<initrd.bin>"@0x88000000 \ 165 --data cluster0.cpu0="<path-to>/fdts/fvp-base-gicv3-psci.dtb"@87F00000 166 167Obtaining the Flattened Device Trees 168^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 169 170Depending on the FVP configuration and Linux configuration used, different 171FDT files are required. FDT source files for the Foundation and Base FVPs can 172be found in the TF-A source directory under ``fdts/``. The Foundation FVP has 173a subset of the Base FVP components. For example, the Foundation FVP lacks 174CLCD and MMC support, and has only one CPU cluster. 175 176.. note:: 177 It is not recommended to use the FDTs built along the kernel because not 178 all FDTs are available from there. 179 180The dynamic configuration capability is enabled in the firmware for FVPs. 181This means that the firmware can authenticate and load the FDT if present in 182FIP. A default FDT is packaged into FIP during the build based on 183the build configuration. This can be overridden by using the ``FVP_HW_CONFIG`` 184or ``FVP_HW_CONFIG_DTS`` build options (refer to 185:ref:`build_options_arm_fvp_platform` for details on the options). 186 187- ``fvp-base-gicv2-psci.dts`` 188 189 For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs 190 without shifted affinities and with Base memory map configuration. 191 192- ``fvp-base-gicv3-psci.dts`` 193 194 For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs 195 without shifted affinities and with Base memory map configuration and 196 Linux GICv3 support. 197 198- ``fvp-base-gicv3-psci-1t.dts`` 199 200 For use with models such as the AEMv8-RevC Base FVP with shifted affinities, 201 single threaded CPUs, Base memory map configuration and Linux GICv3 support. 202 203- ``fvp-base-gicv3-psci-dynamiq.dts`` 204 205 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities, 206 single cluster, single threaded CPUs, Base memory map configuration and Linux 207 GICv3 support. 208 209- ``fvp-foundation-gicv2-psci.dts`` 210 211 For use with Foundation FVP with Base memory map configuration. 212 213- ``fvp-foundation-gicv3-psci.dts`` 214 215 (Default) For use with Foundation FVP with Base memory map configuration 216 and Linux GICv3 support. 217 218-------------- 219 220*Copyright (c) 2019-2024, Arm Limited. All rights reserved.* 221