1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x2.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26.global check_erratum_cortex_x2_3701772 27 28#if WORKAROUND_CVE_2022_23960 29 wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2 30#endif /* WORKAROUND_CVE_2022_23960 */ 31 32cpu_reset_prologue cortex_x2 33 34workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765 35 ldr x0, =0x6 36 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 37 ldr x0, =0xF3A08002 38 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 39 ldr x0, =0xFFF0F7FE 40 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 41 ldr x0, =0x40000001003ff 42 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 43workaround_reset_end cortex_x2, ERRATUM(2002765) 44 45check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0) 46 47workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096 48 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT 49workaround_reset_end cortex_x2, ERRATUM(2017096) 50 51check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0) 52 53workaround_reset_start cortex_x2, ERRATUM(2058056), ERRATA_X2_2058056 54 sysreg_bitfield_insert CORTEX_X2_CPUECTLR2_EL1, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 55 CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH 56workaround_reset_end cortex_x2, ERRATUM(2058056) 57 58check_erratum_ls cortex_x2, ERRATUM(2058056), CPU_REV(2, 1) 59 60workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180 61 /* Apply instruction patching sequence */ 62 ldr x0, =0x3 63 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 64 ldr x0, =0xF3A08002 65 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 66 ldr x0, =0xFFF0F7FE 67 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 68 ldr x0, =0x10002001003FF 69 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 70 ldr x0, =0x4 71 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 72 ldr x0, =0xBF200000 73 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 74 ldr x0, =0xFFEF0000 75 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 76 ldr x0, =0x10002001003F3 77 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 78workaround_reset_end cortex_x2, ERRATUM(2081180) 79 80check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0) 81 82workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908 83 /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ 84 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13) 85workaround_reset_end cortex_x2, ERRATUM(2083908) 86 87check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 88 89workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715 90 /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */ 91 sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22 92workaround_reset_end cortex_x2, ERRATUM(2147715) 93 94check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 95 96workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384 97 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17 98 99 /* Apply instruction patching sequence */ 100 ldr x0, =0x5 101 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 102 ldr x0, =0x10F600E000 103 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 104 ldr x0, =0x10FF80E000 105 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 106 ldr x0, =0x80000000003FF 107 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 108workaround_reset_end cortex_x2, ERRATUM(2216384) 109 110check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0) 111 112workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622 113 /* Apply the workaround */ 114 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, BIT(0) 115workaround_reset_end cortex_x2, ERRATUM(2282622) 116 117check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1) 118 119workaround_reset_start cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941 120 errata_dsu_2313941_wa_impl 121workaround_reset_end cortex_x2, ERRATUM(2313941) 122 123check_erratum_custom_start cortex_x2, ERRATUM(2313941) 124 check_errata_dsu_2313941_impl 125 ret 126check_erratum_custom_end cortex_x2, ERRATUM(2313941) 127 128workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105 129 /* Set bit 40 in CPUACTLR2_EL1 */ 130 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40 131workaround_reset_end cortex_x2, ERRATUM(2371105) 132 133check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0) 134 135workaround_reset_start cortex_x2, ERRATUM(2742423), ERRATA_X2_2742423 136 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 137 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(55) 138 sysreg_bit_clear CORTEX_X2_CPUACTLR5_EL1, BIT(56) 139workaround_reset_end cortex_x2, ERRATUM(2742423) 140 141check_erratum_ls cortex_x2, ERRATUM(2742423), CPU_REV(2, 1) 142 143workaround_runtime_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515 144 /* dsb before isb of power down sequence */ 145 dsb sy 146workaround_runtime_end cortex_x2, ERRATUM(2768515) 147 148check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1) 149 150workaround_reset_start cortex_x2, ERRATUM(2778471), ERRATA_X2_2778471 151 sysreg_bit_set CORTEX_X2_CPUACTLR3_EL1, BIT(47) 152workaround_reset_end cortex_x2, ERRATUM(2778471) 153 154check_erratum_ls cortex_x2, ERRATUM(2778471), CPU_REV(2, 1) 155 156add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772 157 158check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1) 159 160workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 161#if IMAGE_BL31 162 /* 163 * The Cortex-X2 generic vectors are overridden to apply errata 164 * mitigation on exception entry from lower ELs. 165 */ 166 override_vector_table wa_cve_vbar_cortex_x2 167#endif /* IMAGE_BL31 */ 168workaround_reset_end cortex_x2, CVE(2022, 23960) 169 170check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 171 172/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 173workaround_reset_start cortex_x2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 174 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(46) 175workaround_reset_end cortex_x2, CVE(2024, 5660) 176 177check_erratum_ls cortex_x2, CVE(2024, 5660), CPU_REV(2, 1) 178 179 /* ---------------------------------------------------- 180 * HW will do the cache maintenance while powering down 181 * ---------------------------------------------------- 182 */ 183func cortex_x2_core_pwr_dwn 184 /* --------------------------------------------------- 185 * Enable CPU power down bit in power control register 186 * --------------------------------------------------- 187 */ 188 sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 189 190 apply_erratum cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515, NO_GET_CPU_REV 191 isb 192 ret 193endfunc cortex_x2_core_pwr_dwn 194 195cpu_reset_func_start cortex_x2 196 /* Disable speculative loads */ 197 msr SSBS, xzr 198 enable_mpmm 199cpu_reset_func_end cortex_x2 200 201 /* --------------------------------------------- 202 * This function provides Cortex X2 specific 203 * register information for crash reporting. 204 * It needs to return with x6 pointing to 205 * a list of register names in ascii and 206 * x8 - x15 having values of registers to be 207 * reported. 208 * --------------------------------------------- 209 */ 210.section .rodata.cortex_x2_regs, "aS" 211cortex_x2_regs: /* The ascii list of register names to be reported */ 212 .asciz "cpuectlr_el1", "" 213 214func cortex_x2_cpu_reg_dump 215 adr x6, cortex_x2_regs 216 mrs x8, CORTEX_X2_CPUECTLR_EL1 217 ret 218endfunc cortex_x2_cpu_reg_dump 219 220declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ 221 cortex_x2_reset_func, \ 222 cortex_x2_core_pwr_dwn 223