core: move sockets PTA to core/tee

The sockets pseudo-TA is architecture-independent. Move it to
core/tee and drop the pta_ prefix which is not really useful.

Signed-off-by: Jerome Forissier <jerom

core: move sockets PTA to core/tee

The sockets pseudo-TA is architecture-independent. Move it to
core/tee and drop the pta_ prefix which is not really useful.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: move PTAs from core/arch/arm/pta to core/pta

All pseudo-TAs in core/arch/arm/pta are not architecture-
specific so move them out of the arch directory.

sdp_pta.c is renamed sdp.c since _pta i

core: move PTAs from core/arch/arm/pta to core/pta

All pseudo-TAs in core/arch/arm/pta are not architecture-
specific so move them out of the arch directory.

sdp_pta.c is renamed sdp.c since _pta is redundant.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: move test PTAs to core/pta/tests

Moves the test PTAs out of the arch-dependent tree into core/pta/tests.
File names are shortened a bit since the full paths make the purpose
clear.

Signed-off

core: move test PTAs to core/pta/tests

Moves the test PTAs out of the arch-dependent tree into core/pta/tests.
File names are shortened a bit since the full paths make the purpose
clear.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: prepare to move PTAs under core/pta and core/pta/tests

Most pseudo-TAs are currently under core/arch/arm/pta. This is wrong
since none of those are architecture-dependent. This patch creates
c

core: prepare to move PTAs under core/pta and core/pta/tests

Most pseudo-TAs are currently under core/arch/arm/pta. This is wrong
since none of those are architecture-dependent. This patch creates
core/pta and core/pta/tests to prepare for the following scheme:
- PTAs that implement a GP TEE API (sockets, for example) should be in
core/tee
- PTAs that implement other system services should be in /core/pta
- Test PTAs should be in core/pta/tests
- Platform-specific PTAs belong in the platform's directory
- Architecture-specific (but not platform-specific) PTAs should go
in core/arch/$(ARCH)/pta (there are none currently)

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pta/gprof.c: remove <arm.h> include

The gprof pseudo-TA does not need <arm.h> so remove it.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@

core: pta/gprof.c: remove <arm.h> include

The gprof pseudo-TA does not need <arm.h> so remove it.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Squashed commit upgrading to libtomcrypt-1.18.2-develop-20180819

Squash merging branch import/libtomcrypt-1.18.2-develop-20180819

5ecac6e9227c ("core: ltc: adapt to new version of LibTomCrypt")
54d

Squashed commit upgrading to libtomcrypt-1.18.2-develop-20180819

Squash merging branch import/libtomcrypt-1.18.2-develop-20180819

5ecac6e9227c ("core: ltc: adapt to new version of LibTomCrypt")
54d7f2f10c33 ("core: ltc: aes_modes_armv8a_ce_a64.S: get rid of literal load of addend vector")
68b1adf4c3db ("core: ltc: aes_modes_armv8a_ce_a64.S: fix incorrect assembly syntax")
b73cfbef058f ("core: ltc: make key in accel_ecb_encrypt() and accel_ecb_decrypt() const")
7160452f6698 ("core: ltc: fix 'switch case misses default'")
05313fd03df1 ("core: ltc: move AES CE files under aes/")
00ed54001f7d ("core: ltc: add custom DH key generation function dh_make_key()")
279e09ee4c7c ("core: ltc: tomcrypt_custom.h: OP-TEE thread support")
e61adb1a2203 ("core: crypto: libtomcrypt: fix LTC_CLEAN_STACK bug")
5c75c2d02f13 ("core: LTC use only _CFG_CORE_LTC_ variables")
5decfe20864a ("core: crypto: arm64 ce: update AES CBC routines")
c54b6344cc4e ("core: crypto: cleanup and fix CE accelerated AES CTR")
3f4d78d04eef ("core: crypto: arm32: add counter increment in ce_aes_ctr_encrypt()")
a85a4f88e39d ("Remove 'All rights reserved' from Linaro files")
14ec45d62762 ("Remove license notice from Linaro files")
084691667db2 ("Add SPDX license identifiers")
48de810896b8 ("LTC: add GHASH acceleration")
9f4ecf2ea898 ("arm32: AES using ARMv8-A cryptographic extensions")
a360627e4130 ("arm64: libtomcrypt: rename AES CE files")
48dab9f6464b ("arm64: libtomcrypt: move inline assembly to .S file")
7479ed2a4be9 ("ltc: bugfix find_prng()")
271db0fe9309 ("ltc: make cipher_descriptor a pointer to descriptors")
cbf6e51b6086 ("ltc: make hash_descriptor a pointer to descriptors")
6982b2b65910 ("ltc: make prng_descriptor a pointer to descriptors")
034ed64a6bb2 ("arm: Fix SHA-1 with cryptographic extensions")
468fcca20d8b ("arm64: SHA-224/SHA-256 using ARMv8-A cryptographic extensions")
a55567f8611c ("arm: update SHA-256 32-bit CE implementation to process multiple blocks")
ee62ece8ecf4 ("arm: update SHA-1 32-bit CE implementation to process multiple blocks")
4287faa43c7c ("arm64: SHA-1 using ARMv8-A cryptographic extensions")
0c6c51d33f05 ("ECC: optimize the pool of temporary variables")
f79f07210b95 ("arm64: AES XTS using ARMv8-A cryptographic extensions")
dc3e64eee4af ("arm64: AES using ARMv8-A cryptographic extensions")
fcad408195d8 ("SHA-1 ARMv8 crypto extension implementation")
e9fa8daa66ed ("SHA-256 ARMv8 crypto extension implementation")
36c11ddb0f2f ("Import LibTomCrypt v1.18.2 branch "develop" (Aug 19, 2019)")
01c7a0fe164c ("Remove LibTomCrypt")

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ltc: force alignment of A32 assembler functions to 4 bytes

The Clang assembler will not align all the functions containing A32
code (as opposed to thumb) on 4-byte boundaries, contrary to GCC.

core: ltc: force alignment of A32 assembler functions to 4 bytes

The Clang assembler will not align all the functions containing A32
code (as opposed to thumb) on 4-byte boundaries, contrary to GCC.
This can cause a runtime exception (undef-abort).

Add a ".balign 4" to the ENTRY macro to fix that.

See also commit ff7c2da6d14b ("Force alignment of assembler functions
(FUNC and LOCAL_FUNC) to 4 bytes") [1].

Link: [1] https://github.com/OP-TEE/optee_os/commit/ff7c2da6d14b
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: ltc: aes_modes_armv8a_ce_a64.S: get rid of literal load of addend vector

Cherry pick of Linux kernel commit ed6ed11830a9 ("crypto:
arm64/aes-modes - get rid of literal load of addend vector").

core: ltc: aes_modes_armv8a_ce_a64.S: get rid of literal load of addend vector

Cherry pick of Linux kernel commit ed6ed11830a9 ("crypto:
arm64/aes-modes - get rid of literal load of addend vector"). Original
commit message:

"
Replace the literal load of the addend vector with a sequence that
performs each add individually. This sequence is only 2 instructions
longer than the original, and 2% faster on Cortex-A53.

This is an improvement by itself, but also works around a Clang issue,
whose integrated assembler does not implement the GNU ARM asm syntax
completely, and does not support the =literal notation for FP registers
(more info at https://bugs.llvm.org/show_bug.cgi?id=38642)
"

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

show more ...

core: ltc: aes_modes_armv8a_ce_a64.S: fix incorrect assembly syntax

"umov w0, v0.4s[0]" is not valid UAL syntax; the 4 should not be here.
GCC accepts it fine but Clang does not. Fix it.

Signed-off

core: ltc: aes_modes_armv8a_ce_a64.S: fix incorrect assembly syntax

"umov w0, v0.4s[0]" is not valid UAL syntax; the 4 should not be here.
GCC accepts it fine but Clang does not. Fix it.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: arm64: crypto: AES-GCM: fix incorrect assembly syntax

"umov w0, v0.4s[0]" is not valid UAL syntax; the 4 should not be here.
GCC accepts it fine but Clang does not. Fix it.

Signed-off-by: Jer

core: arm64: crypto: AES-GCM: fix incorrect assembly syntax

"umov w0, v0.4s[0]" is not valid UAL syntax; the 4 should not be here.
GCC accepts it fine but Clang does not. Fix it.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: dt: add __noreturn to _fdt_fill_device_info() stub

When CFG_DT != y, the stub function _fdt_fill_device_info() just
panics. Therefore it deserves the __noreturn attribute. Adding it makes
a Cl

core: dt: add __noreturn to _fdt_fill_device_info() stub

When CFG_DT != y, the stub function _fdt_fill_device_info() just
panics. Therefore it deserves the __noreturn attribute. Adding it makes
a Clang warning go away.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

Get rid of option -Wno-suggest-attribute=noreturn

The GCC option -Wno-suggest-attribute=noreturn is not supported by
Clang. Instead of playing with compiler options, let's fix the code
according to

Get rid of option -Wno-suggest-attribute=noreturn

The GCC option -Wno-suggest-attribute=noreturn is not supported by
Clang. Instead of playing with compiler options, let's fix the code
according to the following rules:
- If a function is know to never return, it should have the __noreturn
attribute in the header file.
- If only some implementation of a function never returns, __noreturn
shall be applied to that particular implementation in the .c file.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: driver: generic resources for crypto device driver

Add a generic cryptographic driver interface connecting
TEE Crypto generic APIs to HW driver interface

The Generic Crypto Driver interface i

core: driver: generic resources for crypto device driver

Add a generic cryptographic driver interface connecting
TEE Crypto generic APIs to HW driver interface

The Generic Crypto Driver interface in the core/driver/crypto/crypto_api
is implemented to be able to use a HW driver.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

show more ...

ftrace: exclude only foreign interrupt time

Current TA function execution time feature only reports user mode
execution time and exclude any non-user mode execution time. But in
case of syscalls whi

ftrace: exclude only foreign interrupt time

Current TA function execution time feature only reports user mode
execution time and exclude any non-user mode execution time. But in
case of syscalls which are essentially function invocations from TA
into the kernel, we shouldn't exclude syscall execution time in order
to account for actual function execution time. That means we only
exclude time that is spent serving foreign interrupts.

So changes in this patch allows to incorporate syscall execution time
in the function graph output.

Fixes: f5df167c2ffb ("ftrace: Add function execution time support")
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

show more ...

hikey960: add ASAN shadow offset for 32-bit build

Adds the proper CFG_ASAN_SHADOW_OFFSET value for HiKey960 in 32-bit
mode. This allows to run with the kernel address sanitizer enabled
(CFG_CORE_SAN

hikey960: add ASAN shadow offset for 32-bit build

Adds the proper CFG_ASAN_SHADOW_OFFSET value for HiKey960 in 32-bit
mode. This allows to run with the kernel address sanitizer enabled
(CFG_CORE_SANITIZE_KADDRESS=y).

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: imx: add mx6dapalis/mx6qapalis platform flavor

Add Toradex Apalis iMX6D and iMX6Q (1GB module variant) platform
flavors.

CFG_DDR_SIZE needs to be manually set by the user (e.g. 0x80000000)
if

core: imx: add mx6dapalis/mx6qapalis platform flavor

Add Toradex Apalis iMX6D and iMX6Q (1GB module variant) platform
flavors.

CFG_DDR_SIZE needs to be manually set by the user (e.g. 0x80000000)
if using the 2GB module variants.

Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Reviewed-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Acked-by: Jerome Forissier <jerome@forissier.org>

show more ...

core: imx: add support for i.MX 8MN

Add support for i.MX 8MN.
Add board flavor:
* imx8mnevk

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@lin

core: imx: add support for i.MX 8MN

Add support for i.MX 8MN.
Add board flavor:
* imx8mnevk

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

show more ...

core: imx: add support for i.MX 8QM

Add support for i.MX 8QM.
Add board flavors:
* imx8qmmek

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Clement Faure <clement.faure@n

core: imx: add support for i.MX 8QM

Add support for i.MX 8QM.
Add board flavors:
* imx8qmmek

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

show more ...

core: imx: add support for i.MX 8QxP

Add support for i.MX 8QxP
Add board flavors:
* imx8qxpmek

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Alessandro Di Chiara <alessa

core: imx: add support for i.MX 8QxP

Add support for i.MX 8QxP
Add board flavors:
* imx8qxpmek

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Alessandro Di Chiara <alessandro.dichiara@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

show more ...

core: imx: allow to boot without console

Allow imx SoCs to boot without console when CONSOLE_UART_BASE is not
defined.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Foris

core: imx: allow to boot without console

Allow imx SoCs to boot without console when CONSOLE_UART_BASE is not
defined.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

show more ...

core: imx: add device tree support for uart

Allow driver to read device tree to enable uart.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@lin

core: imx: add device tree support for uart

Allow driver to read device tree to enable uart.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

show more ...

build: do not use -Wp with the preprocessor and use -o instead of a redirection

This patch cleans up the command line where we use the C preprocessor
to better reflect the documented usage in the GC

build: do not use -Wp with the preprocessor and use -o instead of a redirection

This patch cleans up the command line where we use the C preprocessor
to better reflect the documented usage in the GCC man page, thus
preparing for Clang support.

1. When invoking the C preprocessor, there is no need for -Wp to pass
arguments, so remove it.

2. -MD is not supposed to take a file name when passed to cpp. The
dependency output file name is overridden with -MF.

3. Lastly, it is better to use -o to specify the output file instead
of redirecting standard output, because if an error occurs during
preprocessing we don't want the output file to be created.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: add missing arch_extension to thread assembly

Compilation with newer gcc versions fails:

core/arch/arm/kernel/thread_optee_smc_a32.S: Assembler messages:
core/arch/arm/kernel/thread_optee_smc

core: add missing arch_extension to thread assembly

Compilation with newer gcc versions fails:

core/arch/arm/kernel/thread_optee_smc_a32.S: Assembler messages:
core/arch/arm/kernel/thread_optee_smc_a32.S:29: Error: selected processor does not support `smc #0' in ARM mode

add the required .arch_extension sec to the recently added assembly
file.

Fixes: 2786f1438fc8 ("core: thread: separate old SMC interface handling")
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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core: import IS_ENABLED macro from Zephyr OS

The IS_ENABLED macro checks whether a macro is defined to the value
1 or may not be defined at all. This allows checks in the code instead
of using #ifde

core: import IS_ENABLED macro from Zephyr OS

The IS_ENABLED macro checks whether a macro is defined to the value
1 or may not be defined at all. This allows checks in the code instead
of using #ifdef:

#define CFG_MX6Q 1

if (IS_ENABLED(CFG_MX6Q))
printf("MX6Q enabled")
if (IS_ENABLED(CFG_MX6D))
printf("MX6D enabled")

expands to:

if (1)
printf("MX6Q enabled")
if (0)
printf("MX6Q enabled")

where the second if statement can be optimized out by the compiler.

This implementation was imported from Zephyr OS commit
ff07fc7f0a19 ("lib: libc: fix alignment of HEAP base address for ARM").

The Copyright is attributed to Intel, since the original
commit 5bc458a0fae5 ("util.h: Add IS_ENABLED() macro for
expression-legal ifdef-checking") was done by Andy Ross
<andrew.j.ross@intel.com>.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

show more ...

core: arm64: add read_ctr_el0 function

Add the read_ctr_el0 function in the arm64.h file

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>