xref: /optee_os/core/arch/arm/plat-rockchip/main.c (revision 0ec6631d0bba9c4d442b997c379cf1c3524c8bcd)
1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3  * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd.
4  * Copyright (C) 2019, Theobroma Systems Design und Consulting GmbH
5  */
6 
7 #include <console.h>
8 #include <drivers/gic.h>
9 #include <drivers/serial8250_uart.h>
10 #include <io.h>
11 #include <kernel/generic_boot.h>
12 #include <kernel/panic.h>
13 #include <kernel/pm_stubs.h>
14 #include <mm/core_memprot.h>
15 #include <platform_config.h>
16 #include <stdint.h>
17 #include <tee/entry_std.h>
18 #include <tee/entry_fast.h>
19 
20 static struct gic_data gic_data;
21 static struct serial8250_uart_data console_data;
22 
23 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE);
24 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
25 			CONSOLE_UART_SIZE);
26 
27 static const struct thread_handlers handlers = {
28 	.cpu_on = pm_do_nothing,
29 	.cpu_off = pm_do_nothing,
30 	.cpu_suspend = pm_do_nothing,
31 	.cpu_resume = pm_do_nothing,
32 	.system_off = pm_do_nothing,
33 	.system_reset = pm_do_nothing,
34 };
35 
36 void main_init_gic(void)
37 {
38 	vaddr_t gicc_base = 0;
39 	vaddr_t gicd_base = 0;
40 
41 #if !defined(CFG_ARM_GICV3)
42 	gicc_base = (vaddr_t)phys_to_virt(GICC_BASE, MEM_AREA_IO_SEC);
43 	if (!gicc_base)
44 		panic();
45 #endif
46 
47 	gicd_base = (vaddr_t)phys_to_virt(GICD_BASE, MEM_AREA_IO_SEC);
48 	if (!gicd_base)
49 		panic();
50 
51 	/* Initialize GIC */
52 	gic_init(&gic_data, gicc_base, gicd_base);
53 	itr_init(&gic_data.chip);
54 }
55 
56 void main_secondary_init_gic(void)
57 {
58 	gic_cpu_init(&gic_data);
59 }
60 
61 const struct thread_handlers *generic_boot_get_handlers(void)
62 {
63 	return &handlers;
64 }
65 
66 void console_init(void)
67 {
68 	serial8250_uart_init(&console_data, CONSOLE_UART_BASE,
69 			     CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);
70 	register_serial_console(&console_data.chip);
71 }
72