xref: /optee_os/core/arch/arm/plat-rockchip/main.c (revision a557db0a42f352d279fc7664b77355afb2f6f5f8)
1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3  * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd.
4  */
5 
6 #include <console.h>
7 #include <drivers/gic.h>
8 #include <drivers/serial8250_uart.h>
9 #include <io.h>
10 #include <kernel/generic_boot.h>
11 #include <kernel/panic.h>
12 #include <kernel/pm_stubs.h>
13 #include <mm/core_memprot.h>
14 #include <platform_config.h>
15 #include <stdint.h>
16 #include <tee/entry_std.h>
17 #include <tee/entry_fast.h>
18 
19 static struct gic_data gic_data;
20 static struct serial8250_uart_data console_data;
21 
22 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE);
23 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
24 			CONSOLE_UART_SIZE);
25 
26 static const struct thread_handlers handlers = {
27 	.cpu_on = pm_do_nothing,
28 	.cpu_off = pm_do_nothing,
29 	.cpu_suspend = pm_do_nothing,
30 	.cpu_resume = pm_do_nothing,
31 	.system_off = pm_do_nothing,
32 	.system_reset = pm_do_nothing,
33 };
34 
35 void main_init_gic(void)
36 {
37 	vaddr_t gicc_base;
38 	vaddr_t gicd_base;
39 
40 	gicc_base = (vaddr_t)phys_to_virt_io(GICC_BASE);
41 	gicd_base = (vaddr_t)phys_to_virt_io(GICD_BASE);
42 
43 	if (!gicc_base || !gicd_base)
44 		panic();
45 
46 	gic_init(&gic_data, gicc_base, gicd_base);
47 	itr_init(&gic_data.chip);
48 }
49 
50 void main_secondary_init_gic(void)
51 {
52 	gic_cpu_init(&gic_data);
53 }
54 
55 const struct thread_handlers *generic_boot_get_handlers(void)
56 {
57 	return &handlers;
58 }
59 
60 void console_init(void)
61 {
62 	serial8250_uart_init(&console_data, CONSOLE_UART_BASE,
63 			     CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);
64 	register_serial_console(&console_data.chip);
65 }
66