Searched refs:TSP_HW_PVR1_BUF_MID2_MASK (Results 1 – 13 of 13) sorted by relevance
443 #define TSP_HW_PVR1_BUF_MID2_MASK 0x0FFFFFFF macro
347 #define TSP_HW_PVR1_BUF_MID2_MASK 0x0FFFFFFF macro
3781 … REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (u32StartAddr1>>MIU_BUS) & TSP_HW_PVR1_BUF_MID2_MASK); in HAL_PVR_SetBuf()3837 REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (u32MidAddr1>>4) & TSP_HW_PVR1_BUF_MID2_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
382 #define TSP_HW_PVR1_BUF_MID2_MASK 0x0FFFFFFF macro
4923 … REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (phyMiuOffsetPvrBuf1>>MIU_BUS) & TSP_HW_PVR1_BUF_MID2_MASK); in HAL_PVR_SetBuf()5053 REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (u32MidAddr1>>4) & TSP_HW_PVR1_BUF_MID2_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
384 #define TSP_HW_PVR1_BUF_MID2_MASK 0x0FFFFFFF macro
416 #define TSP_HW_PVR1_BUF_MID2_MASK 0x0FFFFFFF macro
418 #define TSP_HW_PVR1_BUF_MID2_MASK 0x0FFFFFFF macro
5433 … REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (phyMiuOffsetPvrBuf1>>MIU_BUS) & TSP_HW_PVR1_BUF_MID2_MASK); in HAL_PVR_SetBuf()5564 REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (u32MidAddr1>>4) & TSP_HW_PVR1_BUF_MID2_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
5096 … REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (phyMiuOffsetPvrBuf1>>MIU_BUS) & TSP_HW_PVR1_BUF_MID2_MASK); in HAL_PVR_SetBuf()5206 REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (u32MidAddr1>>4) & TSP_HW_PVR1_BUF_MID2_MASK); in HAL_PVR_SetStr2Miu_MidAddr()