Searched refs:REG_MIU_CROSSBAR (Results 1 – 15 of 15) sorted by relevance
200 #define REG_MIU_CROSSBAR (0x61300UL * 2) macro201 #define REG_MIU_CROSSBAR_CTRL (REG_MIU_CROSSBAR + 0x0*4)
1137 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_DMA_Start()1138 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar in HAL_CIPHER_DMA_Start()1301 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_OTPHash_Start()1302 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar in HAL_CIPHER_OTPHash_Start()1945 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_Hash_Start()1946 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar in HAL_CIPHER_Hash_Start()
81 #define REG_MIU_CROSSBAR (0x61300 * 2) //bank 0x1613 macro
1178 MS_U32 MIUCrossBar = REG32_R(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_DMA_Start()1179 REG32_W(_u32RegBase + REG_MIU_CROSSBAR, MIUCrossBar | 0xf); //enable MIU crossbar in HAL_CIPHER_DMA_Start()1342 MS_U32 MIUCrossBar = REG32_R(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_OTPHash_Start()1343 REG32_W(_u32RegBase + REG_MIU_CROSSBAR, MIUCrossBar | 0xf); //enable MIU crossbar in HAL_CIPHER_OTPHash_Start()1986 MS_U32 MIUCrossBar = REG32_R(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_Hash_Start()1987 REG32_W(_u32RegBase + REG_MIU_CROSSBAR, MIUCrossBar | 0xf); //enable MIU crossbar in HAL_CIPHER_Hash_Start()
1134 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_DMA_Start()1135 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar in HAL_CIPHER_DMA_Start()1298 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_OTPHash_Start()1299 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar in HAL_CIPHER_OTPHash_Start()1942 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_Hash_Start()1943 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar in HAL_CIPHER_Hash_Start()
1169 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_DMA_Start()1170 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar in HAL_CIPHER_DMA_Start()1382 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_OTPHash_Start()1383 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar in HAL_CIPHER_OTPHash_Start()2011 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_Hash_Start()2012 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar in HAL_CIPHER_Hash_Start()