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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regCA.h 98 // Description: CA Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_CA_H_ 103 #define _REG_CA_H_ 104 105 106 //-------------------------------------------------------------------------------------------------- 107 // Abbreviation 108 //-------------------------------------------------------------------------------------------------- 109 // Addr Address 110 // Buf Buffer 111 // Clr Clear 112 // CmdQ Command queue 113 // Cnt Count 114 // Ctrl Control 115 // Flt Filter 116 // Hw Hardware 117 // Int Interrupt 118 // Len Length 119 // Ovfw Overflow 120 // Pkt Packet 121 // Rec Record 122 // Recv Receive 123 // Rmn Remain 124 // Reg Register 125 // Req Request 126 // Rst Reset 127 // Scmb Scramble 128 // Sec Section 129 // Stat Status 130 // Sw Software 131 // Ts Transport Stream 132 133 134 //-------------------------------------------------------------------------------------------------- 135 // Global Definition 136 //-------------------------------------------------------------------------------------------------- 137 #define MAX_DEVICEID_SIZE 16UL 138 139 140 //-------------------------------------------------------------------------------------------------- 141 // Compliation Option 142 //-------------------------------------------------------------------------------------------------- 143 144 145 //------------------------------------------------------------------------------------------------- 146 // Harware Capability 147 //------------------------------------------------------------------------------------------------- 148 149 150 //------------------------------------------------------------------------------------------------- 151 // Type and Structure 152 //------------------------------------------------------------------------------------------------- 153 #define REG_OTP_BASE (0x90000UL * 2) 154 #define REG_OTP_CTRL_BASE (0xA1300UL * 2) 155 156 #define REG_OTP_CTRL_0 (REG_OTP_CTRL_BASE + 0x00 * 4) 157 #define REG_OTP_CTRL_0_VALUE (0x1303003cUL) 158 #define REG_OTP_CTRL_PV (REG_OTP_CTRL_BASE + 0x08 * 4) 159 #define REG_OTP_CTRL_PG_VERIFY_FAIL_FLAG (1UL << 4) 160 161 #define REG_RNG_BASE (0xA1C00UL * 2) 162 #define REG_RNG_SCPU (REG_RNG_BASE + 0x12 * 4) 163 #define REG_RNG_ACPU (REG_RNG_BASE + 0x13 * 4) 164 #if defined (MCU_AEON) 165 #define REG_RNG_TRNG (REG_RNG_SCPU) 166 #else 167 #define REG_RNG_TRNG (REG_RNG_ACPU) 168 #endif 169 #define REG_RNG_TRNG_ACK 0x80000000UL 170 #define REG_RNG_TRNG_VALID_MASK 0x00010000UL 171 #define REG_RNG_TRNG_OUT_MASK 0x0000FFFFUL 172 173 174 #define REG_RSA_BASE (0xA1D00UL * 2) //bank: 1A1D 175 #define REG_RSA_SEC_RANGE_SET 0x6UL 176 #define REG_RSA_SEC_RANGE_ENABLE 0x00010000UL 177 #define REG_RSA_SEC_RANGE_MASK 0x0000FFFFUL 178 #define REG_RSA_SEC_RANGE_START(_a_) (REG_RSA_BASE + (0x00 + (_a_)* 2) * 4 ) //0~5 179 #define REG_RSA_SEC_RANGE_END(_a_) (REG_RSA_BASE + (0x01 + (_a_)* 2) * 4 ) //0~5 180 181 //BDMA for move BGC FW to SEC51 182 #define REG_BDMA_BASE (0x00900UL * 2) 183 #define REG_BDMA_CTRL (REG_BDMA_BASE + 0x0) 184 #define REG_BDMA_STATUS (REG_BDMA_BASE + 0x1*4) 185 #define REG_BDMA_SRC_SEL (REG_BDMA_BASE + 0x2*4) 186 #define REG_BDMA_SRC_ADDR_L (REG_BDMA_BASE + 0x4*4) 187 #define REG_BDMA_SRC_ADDR_H (REG_BDMA_BASE + 0x5*4) 188 #define REG_BDMA_DST_ADDR_L (REG_BDMA_BASE + 0x6*4) 189 #define REG_BDMA_DST_ADDR_H (REG_BDMA_BASE + 0x7*4) 190 #define REG_BDMA_SIZE_L (REG_BDMA_BASE + 0x8*4) 191 #define REG_BDMA_SIZE_H (REG_BDMA_BASE + 0x9*4) 192 193 //SEC51 194 #define REG_ONEWAY_BASE (0x60F00UL * 2) 195 #define REG_ONEWAY_42 (REG_ONEWAY_BASE + 0x42*4) 196 #define SEC51_SW_RST 0x0001UL 197 #define REG_ONEWAY_52 (REG_ONEWAY_BASE + 0x52*4) 198 #define SEC51_SW_LOCK 0x0001UL 199 200 #define REG_MIU_CROSSBAR (0x61300UL * 2) 201 #define REG_MIU_CROSSBAR_CTRL (REG_MIU_CROSSBAR + 0x0*4) 202 #define REG_MIU_CROSSBAR_EN 0x0008UL 203 204 #define REG_MBX_BASE (0x03300UL * 2) 205 206 #define BGC_SEC_MAX 0x8UL 207 208 //define a BGC command field 209 #define BGC_CMD_CTRL (REG_MBX_BASE + 0x60*4) 210 #define BGC_CMD_SEC_GO 0x0001UL //ACPU: write 1 to trigger, Sec51 write 0 to finish a command 211 #define BGC_CMD_SEC_STATUS 0x0002UL //ACPU: read only, 0: cmd ok, 1:cmd fail 212 #define BGC_CMD_SEC_TYPE 0x003CUL 213 #define BGC_CMD_SEC_TYPE_SHT 2UL 214 #define BGC_CMD_TYPE_SECID 0x0UL 215 #define BGC_CMD_TYPE_LENGTH 0x1UL 216 #define BGC_CMD_TYPE_ADDR 0x2UL 217 #define BGC_CMD_TYPE_SIZE 0x3UL 218 #define BGC_CMD_TYPE_GOLDEN 0x4UL 219 #define BGC_CMD_TYPE_SET_PASSWD 0x5UL 220 #define BGC_CMD_TYPE_RESET_PASSWD 0x6UL 221 #define BGC_CMD_TYPE_INTERVAL 0x7UL 222 #define BGC_CMD_TYPE_ALGO 0x8UL 223 #define BGC_SEC_ALGO_SHA256 0x0UL 224 #define BGC_CMD_TYPE_MODE 0x9UL 225 #define BGC_SEC_MODE_STATIC 0x1UL 226 #define BGC_SEC_MODE_DYNAMIC 0x0UL 227 #define BGC_CMD_TYPE_RESET_MODE 0xAUL 228 #define BGC_SEC_RESET_AV 0x01UL 229 #define BGC_SEC_RESET_ACPU 0x02UL 230 #define BGC_SEC_RESET_SCPU 0x04UL 231 #define BGC_SEC_RESET_SYSTEM 0x08UL 232 #define BGC_SEC_RESET_INTERRUPT 0x10UL 233 234 #define BGC_CMD_TYPE_ENABLE 0xFUL 235 //0xB for acpu forbid 236 //0xC for Read BGC_CMD_SEC_RESET_STATUS //RO 237 //0xD for Read BGC_CMD_SEC_INTEGRITY_CHECK_STATUS //RO 238 #define BGC_CMD_SEC_DATA 0xFF00UL // DATA or Length 239 #define BGC_CMD_SEC_DATA_SHT 8UL 240 241 //define a BGC response when BGC run fail 242 #define BGC_RESP_FAIL (REG_MBX_BASE + 0x61*4) 243 #define BGC_RESP_SECID 0x000FUL 244 #define BGC_RESP_RESET_AV 0x0100UL 245 #define BGC_RESP_RESET_ACPU 0x0200UL 246 #define BGC_RESP_RESET_SCPU 0x0400UL 247 #define BGC_RESP_RESET_SYSTEM 0x0800UL 248 #define BGC_RESP_HASH_FAIL 0x8000UL 249 250 #define REG_INTR_CPUINIT_BASE (0x00500UL * 2)//1005 251 #define REG_INTR_CPUINIT_HST3 (REG_INTR_CPUINIT_BASE + 0x26 * 4) 252 #define REG_HST3TO2_INT 0x0004UL 253 254 #define REG_PM_SLEEP_BASE (0x00E00UL * 2)//000E 255 #define REG_TOP_SW_RST (REG_PM_SLEEP_BASE + 0x2E*4) 256 #define REG_TOP_SW_RST_MSK 0x00FFUL 257 #define REG_TOP_SW_RST_PASSWD 0x79UL 258 259 //ONEWAY PM 260 #define REG_PMONEWAY_BASE (0x02500UL * 2) //0025 261 #define REG_STR_AUTH_RESULT (REG_PMONEWAY_BASE + (0x00 << 2)) 262 #define REG_STR_PTR (REG_PMONEWAY_BASE + (0x08 << 2)) 263 #define REG_WARM_BOOT_IND (REG_PMONEWAY_BASE + (0x10 << 2)) 264 #define REG_WARM_BOOT_IND_MAGIC 0x7A2D 265 #define REG_STR_KEY (REG_PMONEWAY_BASE + (0x21 << 2)) 266 #define REG_STR_DMA_KEY_VALID 0x02 267 #define REG_STR_SPS_KEY_VALID 0x04 268 269 #endif // #ifndef __REG_CA_H_ 270