1 ////////////////////////////////////////////////////////////////////////////////
2 //
3 // Copyright (c) 2006-2013 MStar Semiconductor, Inc.
4 // All rights reserved.
5 //
6 // Unless otherwise stipulated in writing, any and all information contained
7 // herein regardless in any format shall remain the sole proprietary of
8 // MStar Semiconductor Inc. and be kept in strict confidence
9 // ("MStar Confidential Information") by the recipient.
10 // Any unauthorized act including without limitation unauthorized disclosure,
11 // copying, use, reproduction, sale, distribution, modification, disassembling,
12 // reverse engineering and compiling of the contents of MStar Confidential
13 // Information is unlawful and strictly prohibited. MStar hereby reserves the
14 // rights to any and all damages, losses, costs and expenses resulting therefrom.
15 //
16 ////////////////////////////////////////////////////////////////////////////////
17
18 ////////////////////////////////////////////////////////////////////////////////////////////////////
19 // file halCIPHER.c
20 // @brief CIPHER HAL
21 // @author MStar Semiconductor,Inc.
22 ////////////////////////////////////////////////////////////////////////////////////////////////////
23 #ifdef MSOS_TYPE_LINUX_KERNEL
24 #include <linux/string.h>
25 #include <linux/uaccess.h>
26 #include <linux/compat.h>
27 #else
28 #include <stdio.h>
29 #include <string.h>
30 #endif
31
32
33 #include "MsCommon.h"
34 #include "regCIPHER.h"
35 #include "halCIPHER.h"
36 #include "drvCIPHER.h"
37 #include "halCHIP.h"
38
39 #ifndef MSOS_TYPE_LINUX_KERNEL
40 extern void * memset ( void * ptr, int value, size_t num );
41 extern void * memcpy ( void * destination, const void * source, size_t num );
42 extern int printf ( const char * format, ... );
43 #endif
44 //--------------------------------------------------------------------------------------------------
45 // Driver Compiler Option
46 //--------------------------------------------------------------------------------------------------
47
48 //--------------------------------------------------------------------------------------------------
49 // Macro of bit operations
50 //--------------------------------------------------------------------------------------------------
51 #define DELAY_WAITING 1UL
52 #define DELAY_RESCHEDULE 10UL
53 #define COMQ_AVALIABLE 0x10UL
54 #define CIPHER_KEY_SIZE 32UL
55 #define CRYPTODMA_DEBUG_SIZE 32UL
56 #define HASH_MANUAL_BLOCK_SIZE 64UL
57 #define PID_SIZE 2UL
58 #define MIU_SELECT_BIT 0x80000000UL
59
60 //--------------------------------------------------------------------------------------------------
61 // TSP Hardware Abstraction Layer
62 //--------------------------------------------------------------------------------------------------
63 static MS_VIRT _u32RegBase = 0;
64 static REG_AESDMACtrl *_AESDMACtrl = 0 ;
65 static CIPHER_DBGMSG_LEVEL _HAL_CIPHERDBGLevel = CIPHER_DBG_ERR;
66
67 // Algorithm Table for AES/TDES/DES
68 static MS_BOOL _CryptodMA_AlgoTable[4][E_DMA_MODE_NUM][E_DMA_RESIDUE_NUM][E_DMA_SB_NUM];
69
70
71 #define REG32_W(reg, value) do { \
72 (reg)->H = ((value) >> 16); \
73 (reg)->L = ((value) & 0x0000FFFF); \
74 } while(0)
75
76 #define REG32(addr) (*(volatile MS_U32 *) (addr))
77 #define REG16(add) *((volatile MS_U16 *)(add))
78
79 #ifdef CIPHER_NO_PRINTF
80 #define HAL_DEBUG_CIPHER(debug_level, x)
81 #else
82 #define HAL_DEBUG_CIPHER(debug_level, x) do { if (_HAL_CIPHERDBGLevel >= (debug_level)) (x); } while(0)
83 #endif
84 //--------------------------------------------------------------------------------------------------
85 // Local Variable
86 //--------------------------------------------------------------------------------------------------
87
88 MS_PHY _u32DmaInAddr;
89 MS_U32 _u32DmaInNum;
90 MS_PHY _u32DmaOut_StartAddr;
91 MS_PHY _u32DmaOut_EndAddr;
92 MS_PHY _u32ReportAddr;
93 MS_U32 _u32OTPHashLengthPadding;
94
95 MS_U8 _pu8CipherKey[CIPHER_KEY_SIZE];
96 MS_U8 _pu8CipherKey2[CIPHER_KEY_SIZE];
97 MS_U8 _pu8IV[CIPHER_KEY_SIZE];
98 MS_U8 _pu8IV2[CIPHER_KEY_SIZE];
99 MS_U8 _pu8Data[CIPHER_KEY_SIZE];
100 MS_U8 _pu8PID0[PID_SIZE];
101 MS_U8 _pu8PID1[PID_SIZE];
102
103 MS_U32 _u32CmdLen = 0 ;
104
105 // [NOTE] Solve Strict-Aliasing //
106 union {
107 CMD_DmaFormat0 DmaCtrl0;
108 MS_U32 u32DmaCtrl0;
109 }_uDmaCtrl0;
110
111 union{
112 CMD_DmaFormat1 DmaCtrl1;
113 MS_U32 u32DmaCtrl1;
114 }_uDmaCtrl1;
115
116 union{
117 CMD_DmaFormat2 DmaCtrl2;
118 MS_U32 u32DmaCtrl2;
119 }_uDmaCtrl2;
120
121 union{
122 CMD_DmaFormat3 DmaCtrl3;
123 MS_U32 u32DmaCtrl3;
124 }_uDmaCtrl3;
125
126 union{
127 Hash_DmaFormat0 HashCtrl0;
128 MS_U32 u32HashCtrl0;
129 }_uHashCtrl0;
130
131 union{
132 Hash_DmaFormat1 HashCtrl1;
133 MS_U32 u32HashCtrl1;
134 }_uHashCtrl1;
135
136 union{
137 CMD_HashFormat2 HashCtrl2;
138 MS_U32 u32HashCtrl2;
139 }_uHashCtrl2;
140
141 MS_PHY _u32HashSrcAddr;
142 MS_PHY _u32HashDestAddr;
143 MS_U32 _u32InitWordCnt;
144 MS_U32 _u32HashMsgLen;
145
146 MS_U8 _pu8HashIV[HASH_CMD_IV_SIZE];
147 MS_U8 _pu8HashMsg[HASH_CMD_MSG_SIZE];
148 MS_U8 _pu8HashHMACHostKey[HASH_CMD_HMAC_HOSTKEY_SIZE];
149
150 static MS_U32 _CIPHER_CAVid = 0x0F;
151
152 //--------------------------------------------------------------------------------------------------
153 // Inline Function
154 //--------------------------------------------------------------------------------------------------
WRITE_CMDQ(MS_U32 u32Value)155 void WRITE_CMDQ(MS_U32 u32Value)
156 {
157 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s] = 0x%08X \n",__func__, (unsigned int)(u32Value)));
158 REG32(&_AESDMACtrl->Cmd_Queue) = (u32Value) ;
159 }
160
_HAL_CIPHER_TransMIUAddr(MS_PHY * phyAddr)161 MS_BOOL _HAL_CIPHER_TransMIUAddr(MS_PHY* phyAddr)
162 {
163 CHIP_MIU_ID eMIUSel;
164 MS_PHY phyOffset;
165
166 if(NULL == phyAddr)
167 {
168 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]NULL Address!\n",__func__, __LINE__));
169 return FALSE;
170 }
171
172 _phy_to_miu_offset(eMIUSel,phyOffset,*phyAddr);
173
174 if(E_CHIP_MIU_0 == eMIUSel)
175 {
176 *phyAddr = phyOffset;
177 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]Physical address trans to MIU0\n",__func__, __LINE__));
178 }
179 else
180 {
181 *phyAddr = (phyOffset | MIU_SELECT_BIT);
182 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]Physical address trans to MIU1\n",__func__, __LINE__));
183 }
184
185 return TRUE;
186 }
187
_HAL_CIPHER_GetCmdLen(HAL_CIPHER_CMDTYPE CmdType)188 MS_U32 _HAL_CIPHER_GetCmdLen(HAL_CIPHER_CMDTYPE CmdType)
189 {
190
191 MS_U32 u32CmdLen = 0 ;
192
193
194 if ( E_CIPHER_TYPE_DMA == CmdType )
195 {
196 u32CmdLen = 7;
197
198 if ( _uDmaCtrl1.DmaCtrl1.RR == TRUE )
199 {
200 u32CmdLen += 1 ;
201 }
202 if ( _uDmaCtrl0.DmaCtrl0.DIV == TRUE )
203 {
204 u32CmdLen += 4 ;
205 }
206 if ( _uDmaCtrl1.DmaCtrl1.SD == E_DMA_SRC_DIRECT )
207 {
208 u32CmdLen += 4 ;
209 }
210 if ( _uDmaCtrl0.DmaCtrl0.DK == TRUE )
211 {
212 if((_uDmaCtrl0.DmaCtrl0.Aes_mode == CMD_AES_MODE_192) || (_uDmaCtrl0.DmaCtrl0.Aes_mode == CMD_AES_MODE_256))
213 {
214 u32CmdLen += 8 ;
215 }
216 else
217 {
218 u32CmdLen += 4 ;
219 }
220 }
221 if ( _uDmaCtrl2.DmaCtrl2.HP == TRUE )
222 {
223 u32CmdLen += 1 ;
224 }
225 if ( _uDmaCtrl3.DmaCtrl3.DK2 == TRUE )
226 {
227 u32CmdLen += 4 ;
228 }
229 if ( _uDmaCtrl3.DmaCtrl3.DIV2 == TRUE )
230 {
231 u32CmdLen += 4 ;
232 }
233
234 return u32CmdLen ;
235 }
236
237
238 if ( E_CIPHER_TYPE_SHA == CmdType )
239 {
240
241 u32CmdLen = 3 ;
242
243 if (_uHashCtrl0.HashCtrl0.CMD == CMD_HASH_START_RR )
244 {
245 u32CmdLen += 1 ;
246 }
247
248 if (_uHashCtrl0.HashCtrl0.Src != CMD_HASH_SRC_REG )
249 {
250 u32CmdLen += 1 ;
251 }
252
253 if(_uHashCtrl2.HashCtrl2.RR == TRUE)
254 {
255 u32CmdLen += 1 ;
256 }
257
258 if (_uHashCtrl0.HashCtrl0.IWC_Sel == CMD_HASH_IWC_CMDQ )
259 {
260 u32CmdLen += 1 ;
261 }
262
263 if ((_uHashCtrl0.HashCtrl0.Dest == CMD_HASH_OUTPUT_DRAM ) || (_uHashCtrl0.HashCtrl0.Dest == CMD_HASH_OUTPUT_R2 ))
264 {
265 u32CmdLen += 1 ;
266 }
267
268 if (_uHashCtrl0.HashCtrl0.InitHashSel == CMD_HASH_IV_CMD )
269 {
270 u32CmdLen += 8 ;
271 }
272
273 if (_uHashCtrl0.HashCtrl0.Src == CMD_HASH_SRC_REG )
274 {
275 u32CmdLen += 16 ;
276 }
277
278 if((_uHashCtrl0.HashCtrl0.HMAC_KeySel == CMD_HMAC_KSEL_HK) && (_uHashCtrl0.HashCtrl0.DK == CMD_HMAC_KSEL_DIR_HK))
279 {
280 u32CmdLen += 4 ;
281 }
282
283 return u32CmdLen ;
284
285 }
286
287 if ( E_CIPHER_TYPE_OTPHASH == CmdType )
288 {
289 u32CmdLen = 7 ;
290
291 if ( _uDmaCtrl1.DmaCtrl1.NL == TRUE )
292 {
293 u32CmdLen += 1 ;
294 }
295 if ( _uDmaCtrl1.DmaCtrl1.RR == TRUE )
296 {
297 u32CmdLen += 1 ;
298 }
299 if ( _uDmaCtrl3.DmaCtrl3.AP == TRUE && _uDmaCtrl3.DmaCtrl3.IK == FALSE)
300 {
301 u32CmdLen += 1 ;
302 }
303
304 return u32CmdLen ;
305 }
306
307
308 return 0 ;
309
310 }
311
_HAL_CIPHER_TransKey(CIPHER_KEY_SRC src,MS_U32 idx)312 HAL_CIPHER_KEYSRC _HAL_CIPHER_TransKey(CIPHER_KEY_SRC src, MS_U32 idx)
313 {
314 HAL_CIPHER_KEYSRC KeySrc = E_DMA_KSEL_REGKEY;
315
316 if(src == E_CIPHER_KSRC_KL)
317 {
318 KeySrc = E_DMA_KSEL_SK0;
319 }
320 else if(src == E_CIPHER_KSRC_OTP)
321 {
322 KeySrc = E_DMA_KSEL_MK0 + idx;
323 }
324 else if(src == E_CIPHER_KSRC_CPU)
325 {
326 KeySrc = E_DMA_KSEL_REGKEY;
327 }
328 else if(src == E_CIPHER_KSRC_CAIP)
329 {
330 KeySrc = E_DMA_KSEL_CAIP;
331 }
332
333 return KeySrc;
334 }
335
_HAL_CIPHER_TransMainAlgo(CIPHER_MAIN_ALGO algo)336 HAL_CIPHER_ALGO _HAL_CIPHER_TransMainAlgo(CIPHER_MAIN_ALGO algo)
337 {
338 HAL_CIPHER_ALGO hal_algo;
339 switch(algo)
340 {
341 case E_CIPHER_MAIN_AES:
342 hal_algo = E_DMA_ALGO_AES;
343 break;
344 case E_CIPHER_MAIN_DES:
345 hal_algo = E_DMA_ALGO_DES;
346 break;
347 case E_CIPHER_MAIN_TDES:
348 hal_algo = E_DMA_ALGO_TDES;
349 break;
350 case E_CIPHER_MAIN_M6_S56_CCBC:
351 hal_algo = E_DMA_ALGO_M6_S56_CCBC;
352 break;
353 case E_CIPHER_MAIN_M6_S56:
354 hal_algo = E_DMA_ALGO_M6_S56;
355 break;
356 case E_CIPHER_MAIN_M6_KE56:
357 hal_algo = E_DMA_ALGO_M6_KE56;
358 break;
359 case E_CIPHER_MAIN_RC4:
360 hal_algo = E_DMA_ALGO_RC4;
361 break;
362 case E_CIPHER_MAIN_RC4_128:
363 hal_algo = E_DMA_ALGO_RC4_128;
364 break;
365 case E_CIPHER_MAIN_SM4:
366 hal_algo = E_DMA_ALGO_SM4;
367 break;
368 default:
369 hal_algo = E_DMA_ALGO_NONE;
370 }
371
372 return hal_algo;
373 }
374
_HAL_CIPHER_TransSubAlgo(CIPHER_SUB_ALGO algo)375 HAL_CIPHER_MODE _HAL_CIPHER_TransSubAlgo(CIPHER_SUB_ALGO algo)
376 {
377 HAL_CIPHER_MODE hal_algo;
378 switch(algo)
379 {
380 case E_CIPHER_SUB_ECB:
381 hal_algo = E_DMA_MODE_ECB;
382 break;
383 case E_CIPHER_SUB_CBC:
384 hal_algo = E_DMA_MODE_CBC;
385 break;
386 case E_CIPHER_SUB_CTR:
387 hal_algo = E_DMA_MODE_CTR;
388 break;
389 case E_CIPHER_SUB_CBC_MAC:
390 hal_algo = E_DMA_MODE_CBC_MAC;
391 break;
392 case E_CIPHER_SUB_CTR_64:
393 hal_algo = E_DMA_MODE_CTR_64;
394 break;
395 case E_CIPHER_SUB_CMAC_Key:
396 hal_algo = E_DMA_MODE_CMAC_Key;
397 break;
398 case E_CIPHER_SUB_CMAC_Algo:
399 hal_algo = E_DMA_MODE_CMAC_Algo;
400 break;
401 case E_CIPHER_SUB_PCBC_ADD:
402 hal_algo = E_DMA_MODE_PCBC_ADD;
403 break;
404 case E_CIPHER_SUB_PCBC_XOR:
405 hal_algo = E_DMA_MODE_PCBC_XOR;
406 break;
407 case E_CIPHER_SUB_OTPHASH:
408 hal_algo = E_DMA_MODE_OTPHASH;
409 break;
410 default:
411 hal_algo = E_DMA_MODE_NONE;
412 }
413
414 return hal_algo;
415
416 }
417
_HAL_CIPHER_TransResAlgo(CIPHER_RES_ALGO algo)418 HAL_CIPHER_RESIDUE _HAL_CIPHER_TransResAlgo(CIPHER_RES_ALGO algo)
419 {
420 HAL_CIPHER_RESIDUE hal_algo;
421 switch(algo)
422 {
423 case E_CIPHER_RES_CLR:
424 hal_algo = E_DMA_RESIDUE_CLR;
425 break;
426 case E_CIPHER_RES_CTS:
427 hal_algo = E_DMA_RESIDUE_CTS;
428 break;
429 case E_CIPHER_RES_SCTE52:
430 hal_algo = E_DMA_RESIDUE_SCTE52;
431 break;
432 default:
433 hal_algo = E_DMA_RESIDUE_NONE;
434 }
435
436 return hal_algo;
437 }
438
_HAL_CIPHER_TransSBAlgo(CIPHER_SB_ALGO algo)439 HAL_CIPHER_SHORTBLOCK _HAL_CIPHER_TransSBAlgo(CIPHER_SB_ALGO algo)
440 {
441 HAL_CIPHER_SHORTBLOCK hal_algo;
442 switch(algo)
443 {
444 case E_CIPHER_SB_CLR:
445 hal_algo = E_DMA_SB_CLR;
446 break;
447 case E_CIPHER_SB_IV1:
448 hal_algo = E_DMA_SB_IV1;
449 break;
450 case E_CIPHER_SB_IV2:
451 hal_algo = E_DMA_SB_IV2;
452 break;
453 default:
454 hal_algo = E_DMA_SB_NONE;
455 }
456
457 return hal_algo;
458
459 }
460
_HAL_CIPHER_TransHASHAlgo(CIPHER_HASH_ALGO algo)461 HAL_CIPHER_HASHMODE _HAL_CIPHER_TransHASHAlgo(CIPHER_HASH_ALGO algo)
462 {
463 HAL_CIPHER_HASHMODE hal_algo;
464 switch(algo)
465 {
466 case E_CIPHER_HASH_ALGO_SHA1:
467 hal_algo = E_HASH_SHA1;
468 break;
469 case E_CIPHER_HASH_ALGO_SHA256:
470 hal_algo = E_HASH_SHA256;
471 break;
472 case E_CIPHER_HASH_ALGO_MD5:
473 hal_algo = E_HASH_MD5;
474 break;
475 case E_CIPHER_HASH_ALGO_SM3:
476 hal_algo = E_HASH_SM3;
477 break;
478 default:
479 hal_algo = E_HASH_SHA256;
480 }
481
482 return hal_algo;
483 }
484
HAL_CIPHER_DMA_AlgoTable_Init(void)485 void HAL_CIPHER_DMA_AlgoTable_Init(void)
486 {
487
488 memset(_CryptodMA_AlgoTable , 0x0 , sizeof(_CryptodMA_AlgoTable));
489
490 // AES algorithms //
491 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
492 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
493 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
494 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
495 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_IV1] = TRUE ;
496 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV1] = TRUE ;
497 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_CLR] = TRUE ;
498 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC_MAC][E_DMA_RESIDUE_CLR][E_DMA_RESIDUE_CLR] = TRUE ;
499 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CTR][E_DMA_RESIDUE_NONE][E_DMA_SB_NONE] = TRUE ; // residue & sb don't care
500
501 // DES Algorithms //
502 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
503 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
504 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
505 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
506 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_IV1] = TRUE ;
507 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV1] = TRUE ;
508 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV2] = TRUE ;
509 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_CLR] = TRUE ;
510 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CTR][E_DMA_RESIDUE_NONE][E_DMA_SB_NONE] = TRUE ; // residue & sb don't care
511
512 // TDES Algorithm //
513 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
514 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
515 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CTR][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
516 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
517 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_IV1] = TRUE ;
518 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
519 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV1] = TRUE ;
520 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV2] = TRUE ;
521 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_CLR] = TRUE ;
522
523 }
524
525
HAL_CIPHER_DMA_CheckAlgo(HAL_CIPHER_ALGO eAlgo,HAL_CIPHER_MODE eMode,HAL_CIPHER_RESIDUE eRes,HAL_CIPHER_SHORTBLOCK eSB)526 MS_BOOL HAL_CIPHER_DMA_CheckAlgo(HAL_CIPHER_ALGO eAlgo, HAL_CIPHER_MODE eMode, HAL_CIPHER_RESIDUE eRes, HAL_CIPHER_SHORTBLOCK eSB)
527 {
528 // Special Cases //
529 if (eAlgo > E_DMA_ALGO_TDES )
530 {
531 if ((E_DMA_ALGO_RC4==eAlgo)&&(E_DMA_RESIDUE_NONE==eRes)&&(E_DMA_SB_CLR == eSB)&&(E_DMA_MODE_NONE==eMode))
532 { //RC4/none/none/none
533 return TRUE ;
534 }
535 if ((E_DMA_ALGO_M6_KE56==eAlgo)&&(E_DMA_MODE_ECB==eMode)&&(E_DMA_RESIDUE_NONE==eRes)&&(E_DMA_SB_CLR==eSB))
536 { //M6_KE56/ecb/none/clr
537 return TRUE;
538 }
539 if ((E_DMA_ALGO_M6_S56==eAlgo)&&(E_DMA_MODE_ECB==eMode)&&(E_DMA_RESIDUE_NONE==eRes)&&(E_DMA_SB_CLR==eSB))
540 { //M6_S56/ecb/none/clr
541 return TRUE;
542 }
543 if ((E_DMA_ALGO_M6_S56_CCBC==eAlgo)&&(E_DMA_MODE_NONE==eMode)&&(E_DMA_RESIDUE_NONE==eRes)&&(E_DMA_SB_CLR==eSB))
544 { //M6_S56_CCBC/none/none/clr
545 return TRUE;
546 }
547 return FALSE ;
548 }
549
550 // Reference table for Algorithm AES/TDES/DES //
551 return _CryptodMA_AlgoTable[eAlgo][eMode][eRes][eSB] ;
552 }
553
HAL_CIPHER_SetBank(MS_VIRT u32BankAddr)554 void HAL_CIPHER_SetBank(MS_VIRT u32BankAddr)
555 {
556 _u32RegBase = u32BankAddr;
557 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE);
558
559 }
560
HAL_CIPHER_SetDbgLevel(CIPHER_DBGMSG_LEVEL eDBGMsgLevel)561 void HAL_CIPHER_SetDbgLevel(CIPHER_DBGMSG_LEVEL eDBGMsgLevel)
562 {
563 _HAL_CIPHERDBGLevel = eDBGMsgLevel;
564 }
565
HAL_CIPHER_ResetStatus(MS_BOOL RstDma,MS_BOOL RstHash)566 void HAL_CIPHER_ResetStatus(MS_BOOL RstDma , MS_BOOL RstHash)
567 {
568 if (RstDma)
569 {
570 _uDmaCtrl0.u32DmaCtrl0 = 0 ;
571 _uDmaCtrl1.u32DmaCtrl1 = 0 ;
572 _uDmaCtrl2.u32DmaCtrl2 = 0 ;
573 _uDmaCtrl3.u32DmaCtrl3 = 0 ;
574
575 _u32DmaInAddr = 0;
576 _u32DmaInNum = 0 ;
577 _u32OTPHashLengthPadding = 0;
578 _u32DmaOut_StartAddr = 0;
579 _u32DmaOut_EndAddr = 0;
580 _u32ReportAddr = 0 ;
581 memset(&_pu8CipherKey , 0x0, CIPHER_KEY_SIZE );
582 memset(&_pu8IV , 0x0, CIPHER_KEY_SIZE );
583 memset(&_pu8CipherKey2 , 0x0, CIPHER_KEY_SIZE );
584 memset(&_pu8IV2 , 0x0, CIPHER_KEY_SIZE );
585 memset(&_pu8Data , 0x0, CIPHER_KEY_SIZE );
586 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Reset DMA value\n", __FUNCTION__, __LINE__));
587
588 }
589
590 if (RstHash)
591 {
592 (_uHashCtrl0.u32HashCtrl0) = 0 ;
593 (_uHashCtrl1.u32HashCtrl1) = 0 ;
594 (_uHashCtrl2.u32HashCtrl2) = 0 ;
595
596 _u32HashSrcAddr = 0 ;
597 _u32InitWordCnt = 0 ;
598 _u32HashDestAddr = 0 ;
599 _u32HashMsgLen = 0 ;
600
601 memset(_pu8HashIV, 0x0 ,HASH_CMD_IV_SIZE);
602 memset(_pu8HashMsg, 0x0 , HASH_CMD_MSG_SIZE);
603 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Reset HASH value\n", __FUNCTION__, __LINE__));
604 }
605
606 }
607
HAL_CIPHER_ResetException(void)608 void HAL_CIPHER_ResetException(void)
609 {
610 MS_U32 u32DMACtrl = REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]);
611 REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = u32DMACtrl | REG_EXCEPT_FLAG_CLEAR; //clear all except flag
612 REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = u32DMACtrl & ~REG_EXCEPT_FLAG_CLEAR; //enable acpu except flag
613 }
614
HAL_CIPHER_ResetKey(MS_U32 u32KeyIdx)615 MS_BOOL HAL_CIPHER_ResetKey(MS_U32 u32KeyIdx)
616 {
617 HAL_CIPHER_KEYSRC KeySrc;
618
619 //Check Key Index
620 if(u32KeyIdx > HAL_CRYPTODMA_DMA_KEY_SLOT-1)
621 {
622 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Invalid Key Index[%u]\n",
623 __func__, __LINE__, u32KeyIdx));
624 return FALSE;
625 }
626
627 KeySrc = _HAL_CIPHER_TransKey(E_CIPHER_KSRC_KL, u32KeyIdx);
628
629 _uDmaCtrl0.DmaCtrl0.DK = FALSE;
630 _uDmaCtrl0.DmaCtrl0.KeySel = KeySrc|CMD_DMA_KSEL_CLR_SK;
631 _uDmaCtrl0.DmaCtrl0.Key_Index = u32KeyIdx;
632
633 return TRUE;
634
635 }
HAL_CIPHER_SWReset(void)636 void HAL_CIPHER_SWReset(void)
637 {
638 MS_U32 DMA_CTRL = REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]);
639 REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = DMA_CTRL | REG_DMA_SW_RESET; //reset CryptoDMA
640 REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = DMA_CTRL & ~REG_DMA_SW_RESET; //enable CryptoDMA
641
642 }
643
HAL_CIPHER_Set_OBFIdx(MS_BOOL bDMA,MS_U8 u8ReadIdx,MS_U8 u8WriteIdx)644 MS_BOOL HAL_CIPHER_Set_OBFIdx(MS_BOOL bDMA, MS_U8 u8ReadIdx, MS_U8 u8WriteIdx)
645 {
646 if(bDMA)
647 {
648 _uDmaCtrl2.DmaCtrl2.OBF_IDX_READ = u8ReadIdx;
649 _uDmaCtrl2.DmaCtrl2.OBF_IDX_WRITE = u8WriteIdx;
650 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Set DMA Obf Index Read:[%u], Write:[%u]\n",
651 __func__, __LINE__, u8ReadIdx, u8WriteIdx));
652 }
653 else
654 {
655 _uHashCtrl1.HashCtrl1.OBF_IDX_READ = u8ReadIdx;
656 _uHashCtrl1.HashCtrl1.OBF_IDX_WRITE = u8WriteIdx;
657 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Set HASH Obf Index Read:[%u], Write:[%u]\n",
658 __func__, __LINE__, u8ReadIdx, u8WriteIdx));
659 }
660
661 return TRUE;
662 }
663
HAL_CIPHER_DMA_Set_InputSrcFrom(CIPHER_MEM_TYPE InputSrcFrom,MS_U8 * pu8Data,MS_U32 u32Size)664 void HAL_CIPHER_DMA_Set_InputSrcFrom(CIPHER_MEM_TYPE InputSrcFrom, MS_U8* pu8Data, MS_U32 u32Size)
665 {
666 HAL_CIPHER_DATASRC src = E_DMA_SRC_DRAM;
667
668 switch(InputSrcFrom)
669 {
670 case E_CIPHER_DRAM:
671 _u32DmaInAddr = 0;
672 src = E_DMA_SRC_DRAM;
673 break;
674
675 case E_CIPHER_DQMEM://only for R2
676 _u32DmaInAddr = HAL_CIPHER_BASE_DQMEM;
677 src = E_DMA_SRC_DQMEM;
678 break;
679
680 case E_CIPHER_IQMEM://only for R2
681 _u32DmaInAddr = HAL_CIPHER_BASE_IQMEM;
682 src = E_DMA_SRC_IQMEM;
683 break;
684
685 // TODO: future work, DIRECT data from pu8Data
686 #if 0
687 case E_CIPHER_DIRECT:
688 HAL_CIPHER_DMA_Set_Data(pu8Data, u32Size);
689 src = E_DMA_SRC_DIRECT;
690 break;
691 #endif
692
693 case E_CIPHER_OTP: //only for OTPHASH
694 _u32DmaInAddr = 0;
695 src = E_DMA_SRC_HW_INPUT;
696 break;
697
698 default:
699 _u32DmaInAddr = 0;
700 src = E_DMA_SRC_DRAM;
701 break;
702 }
703
704 _uDmaCtrl1.DmaCtrl1.SD = (MS_U32)src;
705
706 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set input source from [%d]\n", __func__, __LINE__, src));
707 }
708
HAL_CIPHER_DMA_Set_OutputDstTo(CIPHER_MEM_TYPE OutputDstTo,MS_U8 * pu8Data,MS_U32 u32Size)709 MS_BOOL HAL_CIPHER_DMA_Set_OutputDstTo(CIPHER_MEM_TYPE OutputDstTo, MS_U8* pu8Data, MS_U32 u32Size)
710 {
711 HAL_CIPHER_DATADST dst = E_DMA_DST_DRAM;
712 MS_BOOL bDstKL = FALSE;
713
714 switch(OutputDstTo)
715 {
716 case E_CIPHER_DRAM:
717 _u32DmaOut_StartAddr = 0;
718 _u32DmaOut_EndAddr = 0;
719 dst = E_DMA_DST_DRAM;
720 break;
721
722 case E_CIPHER_DQMEM: //only for R2
723 _u32DmaOut_StartAddr = HAL_CIPHER_BASE_DQMEM;
724 _u32DmaOut_EndAddr = HAL_CIPHER_BASE_DQMEM;
725 dst = E_DMA_DST_DQMEM;
726 break;
727
728 case E_CIPHER_IQMEM: //only for R2
729 _u32DmaOut_StartAddr = HAL_CIPHER_BASE_IQMEM;
730 _u32DmaOut_EndAddr = HAL_CIPHER_BASE_IQMEM;
731 dst = E_DMA_DST_IQMEM;
732 break;
733
734 case E_CIPHER_DIRECT: //for ACPU, OTPHASH
735 dst = E_DMA_DST_REGFILE;
736 break;
737
738 case E_CIPHER_KL_LUT: //for KL transform algorithm
739 _u32DmaOut_StartAddr = HAL_CIPHER_BASE_LUT;
740 _u32DmaOut_EndAddr = HAL_CIPHER_BASE_LUT;
741 dst = E_DMA_DST_DRAM;
742 bDstKL = TRUE;
743 break;
744
745 case E_CIPHER_KL_M: //for KL transform algorithm
746 _u32DmaOut_StartAddr = HAL_CIPHER_BASE_M;
747 _u32DmaOut_EndAddr = HAL_CIPHER_BASE_M;
748 dst = E_DMA_DST_DRAM;
749 bDstKL = TRUE;
750 break;
751
752 case E_CIPHER_KL_BC: //for KL transform algorithm
753 _u32DmaOut_StartAddr = HAL_CIPHER_BASE_BC;
754 _u32DmaOut_EndAddr = HAL_CIPHER_BASE_BC;
755 dst = E_DMA_DST_DRAM;
756 bDstKL = TRUE;
757 break;
758
759 default:
760 _u32DmaOut_StartAddr = 0;
761 _u32DmaOut_EndAddr = 0;
762 dst = E_DMA_DST_DRAM;
763 break;
764 }
765
766 _uDmaCtrl1.DmaCtrl1.Dest0= (MS_U32)dst;
767
768 if(bDstKL)
769 {
770 HAL_CIPHER_DMA_Set_OutputDstKL(TRUE);
771 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set output destination to KL [0x%4x]\n", __func__, __LINE__, (unsigned int)_u32DmaOut_StartAddr));
772 }
773 else
774 {
775 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set output destination to [%d]\n", __func__, __LINE__, dst));
776 }
777
778 return TRUE;
779 }
780
HAL_CIPHER_DMA_Set_OutputDstKL(MS_BOOL bDstKL)781 void HAL_CIPHER_DMA_Set_OutputDstKL(MS_BOOL bDstKL)
782 {
783 if(bDstKL)
784 {
785 _uDmaCtrl1.DmaCtrl1.Dest1 = CMD_DMA_OUTPUT_SRAM_KL;
786 _uDmaCtrl0.DmaCtrl0.DK = TRUE;
787 }
788 else
789 {
790 _uDmaCtrl1.DmaCtrl1.Dest1 = CMD_DMA_OUTPUT_DEST;
791 }
792 }
793
HAL_CIPHER_DMA_Set_FileinDesc(MS_PHY u32FileinAddr,MS_U32 u32FileinNum)794 void HAL_CIPHER_DMA_Set_FileinDesc(MS_PHY u32FileinAddr, MS_U32 u32FileinNum)
795 {
796
797 _u32DmaInAddr += u32FileinAddr;
798 _u32DmaInNum = u32FileinNum ;
799 }
800
HAL_CIPHER_DMA_Set_FileoutDesc(MS_PHY u32FileoutSAddr,MS_PHY u32phyFileoutEAddr)801 void HAL_CIPHER_DMA_Set_FileoutDesc(MS_PHY u32FileoutSAddr, MS_PHY u32phyFileoutEAddr)
802 {
803 _u32DmaOut_StartAddr += u32FileoutSAddr;
804 _u32DmaOut_EndAddr += u32phyFileoutEAddr;
805
806 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d] _u32DmaOut_StartAddr = %x _u32DmaOut_EndAddr = %x\n", __func__, __LINE__, (unsigned int)_u32DmaOut_StartAddr, (unsigned int)_u32DmaOut_EndAddr));
807 }
808
HAL_CIPHER_OTPHash_Set_FileinDesc(MS_PHY u32FileinAddr,MS_U32 u32FileinNum,MS_U32 u32CurrentRound,CIPHER_MEM_TYPE eInputSrcFrom)809 void HAL_CIPHER_OTPHash_Set_FileinDesc(MS_PHY u32FileinAddr, MS_U32 u32FileinNum, MS_U32 u32CurrentRound, CIPHER_MEM_TYPE eInputSrcFrom)
810 {
811 if(E_CIPHER_OTP == eInputSrcFrom)
812 {
813 _u32DmaInAddr = u32CurrentRound;
814 }
815 else
816 {
817 _u32DmaInAddr = u32FileinAddr + u32CurrentRound*HAL_CRYPTODMA_OTPHASH_UNIT;
818 }
819
820 _u32OTPHashLengthPadding = u32FileinNum;
821 if((u32FileinNum - u32CurrentRound*HAL_CRYPTODMA_OTPHASH_UNIT) >= HAL_CRYPTODMA_OTPHASH_UNIT)
822 {
823 _u32DmaInNum = HAL_CRYPTODMA_OTPHASH_UNIT;
824 }
825 else
826 {
827 _u32DmaInNum = u32FileinNum - u32CurrentRound*HAL_CRYPTODMA_OTPHASH_UNIT;
828 }
829
830 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d] _u32DmaInAddr = %x _u32DmaInNum = %x _u32OTPHashLengthPadding = %x\n", __func__, __LINE__, (unsigned int)_u32DmaInAddr, (unsigned int)_u32DmaInNum, (unsigned int)_u32OTPHashLengthPadding));
831 }
832
HAL_CIPHER_DMA_Set_Key(DRV_CIPHER_KEY stKey)833 MS_BOOL HAL_CIPHER_DMA_Set_Key(DRV_CIPHER_KEY stKey)
834 {
835 HAL_CIPHER_KEYSRC KeySrc = 0;
836 HAL_CIPHER_ALGO algo = 0;
837 MS_BOOL bDK = FALSE;
838
839 algo = _uDmaCtrl0.DmaCtrl0.Algo;
840
841 if(E_DMA_ALGO_NONE == algo)
842 {
843 //No key
844 bDK = TRUE;
845 memset(_pu8CipherKey, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX);
846 goto SET_KEY_DONE;
847 }
848 //Check Key Source, Index
849 if(((E_CIPHER_KSRC_KL == stKey.eKeySrc) && (stKey.u8KeyIdx > HAL_CRYPTODMA_DMA_KEY_SLOT-1)) ||
850 ((E_CIPHER_KSRC_OTP == stKey.eKeySrc) && (stKey.u8KeyIdx > HAL_CRYPTODMA_OTP_SCK_NUM-1)))
851 {
852 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Invalid KeySrc[%d], Index[%d]\n",
853 __func__, __LINE__, stKey.eKeySrc, stKey.u8KeyIdx));
854 return FALSE;
855 }
856
857 //DRV to HAL Type transfer
858 KeySrc = _HAL_CIPHER_TransKey(stKey.eKeySrc, stKey.u8KeyIdx);
859
860 // key from CPU
861 if(E_DMA_KSEL_REGKEY == KeySrc)
862 {
863 if ((NULL != stKey.pu8KeyData) && (stKey.u8KeyLen != 0) && (stKey.u8KeyLen <= HAL_CRYPTODMA_KEYLEN_MAX) )
864 {
865 if(E_DMA_ALGO_AES == algo)
866 {
867 if((stKey.u8KeyLen != E_DMA_AES_KEY128) && (stKey.u8KeyLen != E_DMA_AES_KEY192) && (stKey.u8KeyLen != E_DMA_AES_KEY256))
868 {
869 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Invalid KeyLen[%d]\n",
870 __func__, __LINE__, stKey.u8KeyLen));
871 return FALSE ;
872 }
873
874 if(stKey.u8KeyLen == E_DMA_AES_KEY192)
875 {
876 _uDmaCtrl0.DmaCtrl0.Aes_mode = CMD_AES_MODE_192;
877 }
878 else if(stKey.u8KeyLen == E_DMA_AES_KEY256)
879 {
880 _uDmaCtrl0.DmaCtrl0.Aes_mode = CMD_AES_MODE_256;
881 }
882 }
883
884 memset(_pu8CipherKey, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX );
885 memcpy(_pu8CipherKey, (MS_U8 *)stKey.pu8KeyData , stKey.u8KeyLen);
886 bDK = TRUE ;
887 KeySrc = 0;
888 }
889 else
890 {
891 return FALSE ;
892 }
893
894 }
895 else if(E_DMA_KSEL_CAIP == KeySrc)
896 {
897 bDK = FALSE ;
898 KeySrc = 0 ;
899 }
900 else// key from KL or OTP
901 {
902 bDK = FALSE;
903 }
904
905 SET_KEY_DONE:
906
907 _uDmaCtrl0.DmaCtrl0.Key_Index = stKey.u8KeyIdx;
908 _uDmaCtrl0.DmaCtrl0.DK = bDK;
909 _uDmaCtrl0.DmaCtrl0.KeySel = KeySrc;
910
911 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set DK[%d], KeySel[%d]\n",
912 __func__, __LINE__, bDK, KeySrc));
913
914 return TRUE ;
915 }
916
HAL_CIPHER_DMA_Set_IV(MS_U8 * pu8IV,MS_U32 u32Size)917 void HAL_CIPHER_DMA_Set_IV(MS_U8* pu8IV, MS_U32 u32Size)
918 {
919 MS_BOOL bDIV = FALSE;
920
921 if ((NULL != pu8IV) && (u32Size != 0) && (u32Size <= HAL_CRYPTODMA_KEYLEN_MAX) )
922 {
923 memset(_pu8IV, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX);
924 memcpy(_pu8IV, (MS_U8 *)pu8IV, u32Size);
925 bDIV = TRUE;
926 }
927 else // Data from Dram
928 {
929 memset(_pu8IV, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX);
930 bDIV = FALSE;
931 }
932
933 _uDmaCtrl0.DmaCtrl0.DIV = bDIV ;
934
935 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set DIV[%d]\n",
936 __func__, __LINE__, bDIV));
937 }
938
939
940 // Set Direct Data to Register Input, if Dram input, set pu8Data = NULL ;
HAL_CIPHER_DMA_Set_Data(MS_U8 * pu8Data,MS_U32 u32Size)941 MS_BOOL HAL_CIPHER_DMA_Set_Data(MS_U8* pu8Data, MS_U32 u32Size)
942 {
943 HAL_CIPHER_DATASRC eDataSrc = E_DMA_SRC_DRAM;
944
945 // Data size can't be zero //
946 if (( 0 == u32Size ) && (NULL != pu8Data ))
947 {
948 return FALSE ;
949 }
950
951 if (NULL != pu8Data ) // Data from CMDQ
952 {
953 _u32DmaInNum = u32Size ;
954 memset(_pu8Data, 0x0, HAL_CRYPTODMA_DIRDATA_MAX);
955 memcpy(_pu8Data, (MS_U8 *)pu8Data, u32Size);
956 eDataSrc = E_DMA_SRC_DIRECT ;
957 }
958 else // Data from Dram
959 {
960 memset(_pu8Data, 0x0 , HAL_CRYPTODMA_DIRDATA_MAX );
961 eDataSrc = E_DMA_SRC_DRAM ;
962 }
963
964 _uDmaCtrl1.DmaCtrl1.SD = (MS_U32)eDataSrc ;
965
966 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set SD[%d]\n",
967 __func__, __LINE__, eDataSrc));
968
969 return TRUE ;
970 }
971
HAL_CIPHER_DMA_Set_CaVid(MS_U32 u32CAVid)972 MS_BOOL HAL_CIPHER_DMA_Set_CaVid(MS_U32 u32CAVid)
973 {
974 MS_U32 u32Tmp = u32CAVid;
975
976 if(u32Tmp > HAL_CRYPTODMA_CAVID_MAX)
977 {
978 return FALSE;
979 }
980
981 if(u32Tmp == 0)
982 {
983 u32Tmp = _CIPHER_CAVid ;
984 }
985 else
986 {
987 u32Tmp = u32CAVid ;
988 }
989
990 _uDmaCtrl1.DmaCtrl1.CaVid = u32Tmp ;
991
992 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set CAVid [0x%x]\n",
993 __func__, __LINE__, (unsigned int)u32Tmp));
994
995 return TRUE;
996 }
997
HAL_CIPHER_DMA_Set_Config(MS_BOOL OutputReg)998 void HAL_CIPHER_DMA_Set_Config(MS_BOOL OutputReg)
999 {
1000 _uDmaCtrl1.DmaCtrl1.Dest0 = OutputReg ;
1001 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set dest[%d]\n",
1002 __func__, __LINE__, OutputReg));
1003 }
1004
1005
HAL_CIPHER_DMA_Set_ReportMode(MS_BOOL RptInDram,MS_PHY u32DramAddr)1006 void HAL_CIPHER_DMA_Set_ReportMode(MS_BOOL RptInDram, MS_PHY u32DramAddr)
1007 {
1008 MS_BOOL bRR = FALSE;
1009
1010 if (RptInDram)
1011 {
1012 bRR = TRUE ;
1013 _u32ReportAddr = u32DramAddr;
1014
1015 }
1016 else
1017 {
1018 bRR = FALSE ;
1019 _u32ReportAddr = 0;
1020
1021 }
1022
1023 _uDmaCtrl1.DmaCtrl1.RR = bRR;
1024
1025 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set report mode[%d], report address[0x%08x]\n",
1026 __func__, __LINE__, bRR, (unsigned int)_u32ReportAddr));
1027 }
1028
1029 // [NOTE] HW Bug, the DMA can't support DRAM Data Swap, Data Error for input and output
HAL_CIPHER_DMA_Set_DataSwap(MS_BOOL InDataSwap,MS_BOOL OutDataSwap,MS_BOOL DInByteSwap,MS_BOOL DOutByteSwap)1030 void HAL_CIPHER_DMA_Set_DataSwap(MS_BOOL InDataSwap , MS_BOOL OutDataSwap,
1031 MS_BOOL DInByteSwap, MS_BOOL DOutByteSwap )
1032 {
1033 _uDmaCtrl1.DmaCtrl1.CIS = InDataSwap ;
1034 _uDmaCtrl1.DmaCtrl1.COS = OutDataSwap ;
1035 //_uDmaCtrl1.DmaCtrl1.DODS = DOutBitSwap ;
1036 _uDmaCtrl1.DmaCtrl1.DOBS = DOutByteSwap ;
1037 _uDmaCtrl1.DmaCtrl1.DIBS = DInByteSwap;
1038
1039 }
1040
1041
1042 //void HAL_CIPHER_DMA_Set_Algo(CipherAlgo algo , CipherMode subalgo , Cipher_Residue eRes , Cipher_ShortBlock eSB )
HAL_CIPHER_DMA_Set_Algo(DRV_CIPHER_ALGO stAlgo)1043 void HAL_CIPHER_DMA_Set_Algo(DRV_CIPHER_ALGO stAlgo)
1044 {
1045 HAL_CIPHER_ALGO algo;
1046 HAL_CIPHER_MODE subalgo;
1047 HAL_CIPHER_RESIDUE eRes;
1048 HAL_CIPHER_SHORTBLOCK eSB;
1049
1050 if(_uDmaCtrl1.DmaCtrl1.CaVid == E_CIPHER_CAVID1)
1051 {
1052 algo = (HAL_CIPHER_ALGO)stAlgo.eMainAlgo;
1053 subalgo = (HAL_CIPHER_MODE)stAlgo.eSubAlgo;
1054
1055 // For OTPHASH in E_CIPHER_CAVID1
1056 if(stAlgo.eSubAlgo == E_CIPHER_SUB_OTPHASH)
1057 subalgo = E_DMA_MODE_OTPHASH;
1058 }
1059 else
1060 {
1061 algo = _HAL_CIPHER_TransMainAlgo(stAlgo.eMainAlgo);
1062 subalgo = _HAL_CIPHER_TransSubAlgo(stAlgo.eSubAlgo);
1063 }
1064
1065 eRes = _HAL_CIPHER_TransResAlgo(stAlgo.eResAlgo);
1066 eSB = _HAL_CIPHER_TransSBAlgo(stAlgo.eSBAlgo);
1067
1068 _uDmaCtrl0.DmaCtrl0.Algo= algo ;
1069 _uDmaCtrl0.DmaCtrl0.SubAlgo= subalgo ;
1070 _uDmaCtrl0.DmaCtrl0.Residue = eRes ;
1071 _uDmaCtrl0.DmaCtrl0.SB = eSB ;
1072
1073 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set algorithm, MAIN[%d], SUB[%d], RES[%d], SB[%d]\n",
1074 __func__, __LINE__, algo, subalgo, eRes, eSB));
1075 }
1076
HAL_CIPHER_DMA_Set_OTPHash(MS_U32 u32CurrentRound,MS_U32 u32OTPHashRound)1077 void HAL_CIPHER_DMA_Set_OTPHash(MS_U32 u32CurrentRound, MS_U32 u32OTPHashRound)
1078 {
1079 _uDmaCtrl3.DmaCtrl3.AP = 0;
1080 _uDmaCtrl3.DmaCtrl3.IK = 0;
1081 // First OTPHASH enable IK, other disable IK
1082 if(u32CurrentRound == 0)
1083 {
1084 _uDmaCtrl3.DmaCtrl3.IK = 1;
1085 }
1086 // Final OTPHASH enable AP, other disable AP
1087 if(u32CurrentRound == u32OTPHashRound)
1088 {
1089 _uDmaCtrl3.DmaCtrl3.AP = 1;
1090 }
1091
1092 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set OTPHASH, AP[%d], IK[%d]\n",
1093 __func__, __LINE__, _uDmaCtrl3.DmaCtrl3.AP, _uDmaCtrl3.DmaCtrl3.IK));
1094 }
1095
HAL_CIPHER_DMA_WriteCMDQ(MS_U32 u32Cmd)1096 void HAL_CIPHER_DMA_WriteCMDQ(MS_U32 u32Cmd)
1097 {
1098 WRITE_CMDQ(u32Cmd) ;
1099 }
1100
HAL_CIPHER_DMA_GetData(MS_U8 * u8Data)1101 void HAL_CIPHER_DMA_GetData(MS_U8 *u8Data)
1102 {
1103
1104 MS_U32 tmp ;
1105
1106 // [Note] for u8Data is not always 4 bytes alignment.
1107 tmp = REG32(&_AESDMACtrl->Dma_Out[0]);
1108 u8Data[0] = (tmp >> 0) & 0xFF ;
1109 u8Data[1] = (tmp >> 8) & 0xFF ;
1110 u8Data[2] = (tmp >> 16) & 0xFF ;
1111 u8Data[3] = (tmp >> 24) & 0xFF ;
1112
1113 tmp = REG32(&_AESDMACtrl->Dma_Out[1]);
1114 u8Data[4] = (tmp >> 0) & 0xFF ;
1115 u8Data[5] = (tmp >> 8) & 0xFF ;
1116 u8Data[6] = (tmp >> 16) & 0xFF ;
1117 u8Data[7] = (tmp >> 24) & 0xFF ;
1118
1119 tmp = REG32(&_AESDMACtrl->Dma_Out[2]);
1120 u8Data[8] = (tmp >> 0) & 0xFF ;
1121 u8Data[9] = (tmp >> 8) & 0xFF ;
1122 u8Data[10] = (tmp >> 16) & 0xFF ;
1123 u8Data[11] = (tmp >> 24) & 0xFF ;
1124
1125 tmp = REG32(&_AESDMACtrl->Dma_Out[3]);
1126 u8Data[12] = (tmp >> 0) & 0xFF ;
1127 u8Data[13] = (tmp >> 8) & 0xFF ;
1128 u8Data[14] = (tmp >> 16) & 0xFF ;
1129 u8Data[15] = (tmp >> 24) & 0xFF ;
1130
1131 }
1132
HAL_CIPHER_DMA_GetRpt(MS_U32 * DmaRpt)1133 void HAL_CIPHER_DMA_GetRpt(MS_U32 *DmaRpt)
1134 {
1135 MS_U32 i ;
1136
1137 for (i = 0 ; i < DMA_RPT_REG_SIZE ; i++)
1138 {
1139 DmaRpt[i] = REG32(&_AESDMACtrl->Dma_Reportp[i]);
1140 }
1141 }
1142
HAL_CIPHER_DMA_Start(MS_BOOL Decrypt,HAL_CIPHER_INTMODE IntMode,MS_BOOL bWaitCmdQ,MS_U16 u16CmdID)1143 MS_BOOL HAL_CIPHER_DMA_Start(MS_BOOL Decrypt, HAL_CIPHER_INTMODE IntMode, MS_BOOL bWaitCmdQ, MS_U16 u16CmdID)
1144 {
1145 MS_U32 u32SpareCnt = 0 , CmdLen = 0 ;
1146
1147 _uDmaCtrl0.DmaCtrl0.OVT = FALSE ;
1148
1149 //Set Thread Id
1150 _uDmaCtrl1.DmaCtrl1.TID = u16CmdID ;
1151
1152 _uDmaCtrl1.DmaCtrl1.IntM = IntMode ;
1153
1154 CmdLen = _HAL_CIPHER_GetCmdLen(E_CIPHER_TYPE_DMA);
1155
1156 _uDmaCtrl0.DmaCtrl0.CMD = ((Decrypt?0x3:0x2) & 0xF);
1157
1158 _uDmaCtrl1.DmaCtrl1.NL = CMD_NEW_LINE;
1159
1160 //Parser patch
1161 if(TRUE == _uDmaCtrl2.DmaCtrl2.HP)
1162 {
1163 MS_U32 u32Tmp = 0;
1164 u32Tmp = _AESDMACtrl->Dma_Ctrl[1];
1165 u32Tmp |= REG_PARSER_LG_PATH_EN;
1166 _AESDMACtrl->Dma_Ctrl[1] = u32Tmp;
1167 }
1168
1169 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613
1170 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar
1171
1172
1173 if(_uDmaCtrl1.DmaCtrl1.SD == CMD_DMA_DATA_DRAM)
1174 {
1175 if(_HAL_CIPHER_TransMIUAddr(&_u32DmaInAddr) == FALSE)
1176 {
1177 return FALSE;
1178 }
1179 }
1180
1181 if(_uDmaCtrl1.DmaCtrl1.Dest0 == CMD_DMA_OUTPUT_DRAM)
1182 {
1183 if(_HAL_CIPHER_TransMIUAddr(&_u32DmaOut_StartAddr) == FALSE)
1184 {
1185 return FALSE;
1186 }
1187 if(_HAL_CIPHER_TransMIUAddr(&_u32DmaOut_EndAddr) == FALSE)
1188 {
1189 return FALSE;
1190 }
1191 }
1192
1193 DMA_RETRY:
1194 // [HW] Hardware will check Current spare count first, and others read spare count will be zero!
1195 u32SpareCnt = REG32(&_AESDMACtrl->SpareCnt) ;
1196
1197 if (u32SpareCnt > CmdLen)
1198 {
1199 u32SpareCnt -= CmdLen ;
1200
1201 WRITE_CMDQ( (_uDmaCtrl0.u32DmaCtrl0)) ;
1202 WRITE_CMDQ( (_uDmaCtrl1.u32DmaCtrl1)) ;
1203 WRITE_CMDQ( (_uDmaCtrl2.u32DmaCtrl2)) ;
1204 WRITE_CMDQ( (_uDmaCtrl3.u32DmaCtrl3)) ;
1205
1206 WRITE_CMDQ((MS_U32)_u32DmaInAddr) ;
1207 WRITE_CMDQ(_u32DmaInNum) ;
1208 WRITE_CMDQ((MS_U32)_u32DmaOut_StartAddr);
1209 WRITE_CMDQ((MS_U32)_u32DmaOut_EndAddr);
1210
1211 if (_uDmaCtrl1.DmaCtrl1.RR == TRUE )
1212 {
1213 WRITE_CMDQ((MS_U32)_u32ReportAddr);
1214 }
1215
1216 // DMA Initial Vector from CmdQ
1217 if (_uDmaCtrl0.DmaCtrl0.DIV == TRUE )
1218 {
1219 #if 0
1220 WRITE_CMDQ(_pu8IV[15]<<24 |_pu8IV[14]<<16 | _pu8IV[13]<<8 | _pu8IV[12]);
1221 WRITE_CMDQ(_pu8IV[11]<<24 |_pu8IV[10]<<16 | _pu8IV[ 9]<<8 | _pu8IV[ 8]);
1222 WRITE_CMDQ(_pu8IV[ 3]<<24 |_pu8IV[ 2]<<16 | _pu8IV[ 1]<<8 | _pu8IV[ 0]);
1223 WRITE_CMDQ(_pu8IV[ 7]<<24 |_pu8IV[ 6]<<16 | _pu8IV[ 5]<<8 | _pu8IV[ 4]);
1224 #else
1225 WRITE_CMDQ(_pu8IV[ 0]<<24 |_pu8IV[ 1]<<16 | _pu8IV[ 2]<<8 | _pu8IV[ 3]);
1226 WRITE_CMDQ(_pu8IV[ 4]<<24 |_pu8IV[ 5]<<16 | _pu8IV[ 6]<<8 | _pu8IV[ 7]);
1227 WRITE_CMDQ(_pu8IV[ 8]<<24 |_pu8IV[ 9]<<16 | _pu8IV[10]<<8 | _pu8IV[11]);
1228 WRITE_CMDQ(_pu8IV[12]<<24 |_pu8IV[13]<<16 | _pu8IV[14]<<8 | _pu8IV[15]);
1229 #endif
1230 }
1231
1232 // DMA Data from CmdQ
1233 if (_uDmaCtrl1.DmaCtrl1.SD == CMD_DMA_DATA_REG )
1234 {
1235 #if 0
1236 WRITE_CMDQ(_pu8Data[15]<<24 |_pu8Data[14]<<16 | _pu8Data[13]<<8 | _pu8Data[12]);
1237 WRITE_CMDQ(_pu8Data[11]<<24 |_pu8Data[10]<<16 | _pu8Data[ 9]<<8 | _pu8Data[ 8]);
1238 WRITE_CMDQ(_pu8Data[ 7]<<24 |_pu8Data[ 6]<<16 | _pu8Data[ 5]<<8 | _pu8Data[ 4]);
1239 WRITE_CMDQ(_pu8Data[ 3]<<24 |_pu8Data[ 2]<<16 | _pu8Data[ 1]<<8 | _pu8Data[ 0]);
1240 #else
1241 WRITE_CMDQ(_pu8Data[ 0]<<24 |_pu8Data[ 1]<<16 | _pu8Data[ 2]<<8 | _pu8Data[ 3]);
1242 WRITE_CMDQ(_pu8Data[ 4]<<24 |_pu8Data[ 5]<<16 | _pu8Data[ 6]<<8 | _pu8Data[ 7]);
1243 WRITE_CMDQ(_pu8Data[ 8]<<24 |_pu8Data[ 9]<<16 | _pu8Data[10]<<8 | _pu8Data[11]);
1244 WRITE_CMDQ(_pu8Data[12]<<24 |_pu8Data[13]<<16 | _pu8Data[14]<<8 | _pu8Data[15]);
1245 #endif
1246 }
1247
1248 // DMA Key from CmdQ
1249 if (_uDmaCtrl0.DmaCtrl0.DK == TRUE )
1250 {
1251 #if 0
1252 WRITE_CMDQ(_pu8CipherKey[15]<<24 |_pu8CipherKey[14]<<16 | _pu8CipherKey[13]<<8 | _pu8CipherKey[12]);
1253 WRITE_CMDQ(_pu8CipherKey[11]<<24 |_pu8CipherKey[10]<<16 | _pu8CipherKey[ 9]<<8 | _pu8CipherKey[ 8]);
1254 WRITE_CMDQ(_pu8CipherKey[ 7]<<24 |_pu8CipherKey[ 6]<<16 | _pu8CipherKey[ 5]<<8 | _pu8CipherKey[ 4]);
1255 WRITE_CMDQ(_pu8CipherKey[ 3]<<24 |_pu8CipherKey[ 2]<<16 | _pu8CipherKey[ 1]<<8 | _pu8CipherKey[ 0]);
1256 #else
1257
1258 if(_uDmaCtrl0.DmaCtrl0.Aes_mode == CMD_AES_MODE_192)
1259 {
1260 WRITE_CMDQ(_pu8CipherKey[24]<<24 |_pu8CipherKey[25]<<16 | _pu8CipherKey[26]<<8 | _pu8CipherKey[27]);
1261 WRITE_CMDQ(_pu8CipherKey[28]<<24 |_pu8CipherKey[29]<<16 | _pu8CipherKey[30]<<8 | _pu8CipherKey[31]);
1262 WRITE_CMDQ(_pu8CipherKey[ 0]<<24 |_pu8CipherKey[ 1]<<16 | _pu8CipherKey[ 2]<<8 | _pu8CipherKey[ 3]);
1263 WRITE_CMDQ(_pu8CipherKey[ 4]<<24 |_pu8CipherKey[ 5]<<16 | _pu8CipherKey[ 6]<<8 | _pu8CipherKey[ 7]);
1264 WRITE_CMDQ(_pu8CipherKey[ 8]<<24 |_pu8CipherKey[ 9]<<16 | _pu8CipherKey[10]<<8 | _pu8CipherKey[11]);
1265 WRITE_CMDQ(_pu8CipherKey[12]<<24 |_pu8CipherKey[13]<<16 | _pu8CipherKey[14]<<8 | _pu8CipherKey[15]);
1266 WRITE_CMDQ(_pu8CipherKey[16]<<24 |_pu8CipherKey[17]<<16 | _pu8CipherKey[18]<<8 | _pu8CipherKey[19]);
1267 WRITE_CMDQ(_pu8CipherKey[20]<<24 |_pu8CipherKey[21]<<16 | _pu8CipherKey[22]<<8 | _pu8CipherKey[23]);
1268 }
1269 else if(_uDmaCtrl0.DmaCtrl0.Aes_mode == CMD_AES_MODE_256)
1270 {
1271 WRITE_CMDQ(_pu8CipherKey[ 0]<<24 |_pu8CipherKey[ 1]<<16 | _pu8CipherKey[ 2]<<8 | _pu8CipherKey[ 3]);
1272 WRITE_CMDQ(_pu8CipherKey[ 4]<<24 |_pu8CipherKey[ 5]<<16 | _pu8CipherKey[ 6]<<8 | _pu8CipherKey[ 7]);
1273 WRITE_CMDQ(_pu8CipherKey[ 8]<<24 |_pu8CipherKey[ 9]<<16 | _pu8CipherKey[10]<<8 | _pu8CipherKey[11]);
1274 WRITE_CMDQ(_pu8CipherKey[12]<<24 |_pu8CipherKey[13]<<16 | _pu8CipherKey[14]<<8 | _pu8CipherKey[15]);
1275 WRITE_CMDQ(_pu8CipherKey[16]<<24 |_pu8CipherKey[17]<<16 | _pu8CipherKey[18]<<8 | _pu8CipherKey[19]);
1276 WRITE_CMDQ(_pu8CipherKey[20]<<24 |_pu8CipherKey[21]<<16 | _pu8CipherKey[22]<<8 | _pu8CipherKey[23]);
1277 WRITE_CMDQ(_pu8CipherKey[24]<<24 |_pu8CipherKey[25]<<16 | _pu8CipherKey[26]<<8 | _pu8CipherKey[27]);
1278 WRITE_CMDQ(_pu8CipherKey[28]<<24 |_pu8CipherKey[29]<<16 | _pu8CipherKey[30]<<8 | _pu8CipherKey[31]);
1279 }
1280 else
1281 {
1282 WRITE_CMDQ(_pu8CipherKey[ 0]<<24 |_pu8CipherKey[ 1]<<16 | _pu8CipherKey[ 2]<<8 | _pu8CipherKey[ 3]);
1283 WRITE_CMDQ(_pu8CipherKey[ 4]<<24 |_pu8CipherKey[ 5]<<16 | _pu8CipherKey[ 6]<<8 | _pu8CipherKey[ 7]);
1284 WRITE_CMDQ(_pu8CipherKey[ 8]<<24 |_pu8CipherKey[ 9]<<16 | _pu8CipherKey[10]<<8 | _pu8CipherKey[11]);
1285 WRITE_CMDQ(_pu8CipherKey[12]<<24 |_pu8CipherKey[13]<<16 | _pu8CipherKey[14]<<8 | _pu8CipherKey[15]);
1286 }
1287
1288 #endif
1289 }
1290
1291 // PID for HW parser
1292 if (_uDmaCtrl2.DmaCtrl2.HP == TRUE )
1293 {
1294 WRITE_CMDQ(_pu8PID0[ 0]<<27 |_pu8PID0[ 1]<<19 | _pu8PID1[ 0]<<14 | _pu8PID1[ 1]<<6);
1295
1296 }
1297
1298 if (_uDmaCtrl3.DmaCtrl3.DIV2 == TRUE )
1299 {
1300 WRITE_CMDQ(_pu8IV2[ 0]<<24 |_pu8IV2[ 1]<<16 | _pu8IV2[ 2]<<8 | _pu8IV2[ 3]);
1301 WRITE_CMDQ(_pu8IV2[ 4]<<24 |_pu8IV2[ 5]<<16 | _pu8IV2[ 6]<<8 | _pu8IV2[ 7]);
1302 WRITE_CMDQ(_pu8IV2[ 8]<<24 |_pu8IV2[ 9]<<16 | _pu8IV2[10]<<8 | _pu8IV2[11]);
1303 WRITE_CMDQ(_pu8IV2[12]<<24 |_pu8IV2[13]<<16 | _pu8IV2[14]<<8 | _pu8IV2[15]);
1304 }
1305
1306 if (_uDmaCtrl3.DmaCtrl3.DK2 == TRUE )
1307 {
1308 if(_uDmaCtrl3.DmaCtrl3.Aes_mode2 == CMD_AES_MODE_192)
1309 {
1310 WRITE_CMDQ(_pu8CipherKey2[24]<<24 |_pu8CipherKey2[25]<<16 | _pu8CipherKey2[26]<<8 | _pu8CipherKey2[27]);
1311 WRITE_CMDQ(_pu8CipherKey2[28]<<24 |_pu8CipherKey2[29]<<16 | _pu8CipherKey2[30]<<8 | _pu8CipherKey2[31]);
1312 WRITE_CMDQ(_pu8CipherKey2[ 0]<<24 |_pu8CipherKey2[ 1]<<16 | _pu8CipherKey2[ 2]<<8 | _pu8CipherKey2[ 3]);
1313 WRITE_CMDQ(_pu8CipherKey2[ 4]<<24 |_pu8CipherKey2[ 5]<<16 | _pu8CipherKey2[ 6]<<8 | _pu8CipherKey2[ 7]);
1314 WRITE_CMDQ(_pu8CipherKey2[ 8]<<24 |_pu8CipherKey2[ 9]<<16 | _pu8CipherKey2[10]<<8 | _pu8CipherKey2[11]);
1315 WRITE_CMDQ(_pu8CipherKey2[12]<<24 |_pu8CipherKey2[13]<<16 | _pu8CipherKey2[14]<<8 | _pu8CipherKey2[15]);
1316 WRITE_CMDQ(_pu8CipherKey2[16]<<24 |_pu8CipherKey2[17]<<16 | _pu8CipherKey2[18]<<8 | _pu8CipherKey2[19]);
1317 WRITE_CMDQ(_pu8CipherKey2[20]<<24 |_pu8CipherKey2[21]<<16 | _pu8CipherKey2[22]<<8 | _pu8CipherKey2[23]);
1318 }
1319 else if(_uDmaCtrl3.DmaCtrl3.Aes_mode2 == CMD_AES_MODE_256)
1320 {
1321 WRITE_CMDQ(_pu8CipherKey2[ 0]<<24 |_pu8CipherKey2[ 1]<<16 | _pu8CipherKey2[ 2]<<8 | _pu8CipherKey2[ 3]);
1322 WRITE_CMDQ(_pu8CipherKey2[ 4]<<24 |_pu8CipherKey2[ 5]<<16 | _pu8CipherKey2[ 6]<<8 | _pu8CipherKey2[ 7]);
1323 WRITE_CMDQ(_pu8CipherKey2[ 8]<<24 |_pu8CipherKey2[ 9]<<16 | _pu8CipherKey2[10]<<8 | _pu8CipherKey2[11]);
1324 WRITE_CMDQ(_pu8CipherKey2[12]<<24 |_pu8CipherKey2[13]<<16 | _pu8CipherKey2[14]<<8 | _pu8CipherKey2[15]);
1325 WRITE_CMDQ(_pu8CipherKey2[16]<<24 |_pu8CipherKey2[17]<<16 | _pu8CipherKey2[18]<<8 | _pu8CipherKey2[19]);
1326 WRITE_CMDQ(_pu8CipherKey2[20]<<24 |_pu8CipherKey2[21]<<16 | _pu8CipherKey2[22]<<8 | _pu8CipherKey2[23]);
1327 WRITE_CMDQ(_pu8CipherKey2[24]<<24 |_pu8CipherKey2[25]<<16 | _pu8CipherKey2[26]<<8 | _pu8CipherKey2[27]);
1328 WRITE_CMDQ(_pu8CipherKey2[28]<<24 |_pu8CipherKey2[29]<<16 | _pu8CipherKey2[30]<<8 | _pu8CipherKey2[31]);
1329 }
1330 else
1331 {
1332 WRITE_CMDQ(_pu8CipherKey2[ 0]<<24 |_pu8CipherKey2[ 1]<<16 | _pu8CipherKey2[ 2]<<8 | _pu8CipherKey2[ 3]);
1333 WRITE_CMDQ(_pu8CipherKey2[ 4]<<24 |_pu8CipherKey2[ 5]<<16 | _pu8CipherKey2[ 6]<<8 | _pu8CipherKey2[ 7]);
1334 WRITE_CMDQ(_pu8CipherKey2[ 8]<<24 |_pu8CipherKey2[ 9]<<16 | _pu8CipherKey2[10]<<8 | _pu8CipherKey2[11]);
1335 WRITE_CMDQ(_pu8CipherKey2[12]<<24 |_pu8CipherKey2[13]<<16 | _pu8CipherKey2[14]<<8 | _pu8CipherKey2[15]);
1336 }
1337 }
1338
1339 // [HW] Hardware will check Current spare count != Write back Spare count to start operation.
1340 REG32(&_AESDMACtrl->SpareCnt) = u32SpareCnt ;
1341 return TRUE ;
1342
1343 }
1344 else
1345 {
1346 // [HW] Check Current spare count == Write back Spare count to start wait cmd
1347 REG32(&_AESDMACtrl->SpareCnt) = u32SpareCnt ;
1348 if (bWaitCmdQ)
1349 {
1350 // Retry until CMDQ avaliable
1351 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA retry!\n",__func__, __LINE__));
1352 goto DMA_RETRY;
1353 }
1354 else
1355 {
1356 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA Fail!\n",__func__, __LINE__));
1357 // Return Fail, Command abort
1358 return FALSE ;
1359 }
1360 }
1361 //DMA_FAIL:
1362
1363 }
1364
HAL_CIPHER_OTPHash_Start(HAL_CIPHER_INTMODE IntMode,MS_BOOL bWaitCmdQ,MS_U16 u16CmdID)1365 MS_BOOL HAL_CIPHER_OTPHash_Start(HAL_CIPHER_INTMODE IntMode, MS_BOOL bWaitCmdQ, MS_U16 u16CmdID)
1366 {
1367 MS_U32 u32SpareCnt = 0 , CmdLen = 0 ;
1368
1369 _uDmaCtrl0.DmaCtrl0.OVT = FALSE ;
1370
1371 //Set Thread Id
1372 _uDmaCtrl1.DmaCtrl1.TID = u16CmdID ;
1373
1374 _uDmaCtrl1.DmaCtrl1.IntM = IntMode ;
1375
1376 _uDmaCtrl1.DmaCtrl1.NL = CMD_NEW_LINE;
1377
1378 CmdLen = _HAL_CIPHER_GetCmdLen(E_CIPHER_TYPE_OTPHASH);
1379
1380 _uDmaCtrl0.DmaCtrl0.CMD = CMD_DMA_ENCRYPT;
1381
1382 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613
1383 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar
1384
1385 DMA_RETRY:
1386 // [HW] Hardware will check Current spare count first, and others read spare count will be zero!
1387 u32SpareCnt = REG32(&_AESDMACtrl->SpareCnt) ;
1388
1389 if (u32SpareCnt > CmdLen)
1390 {
1391 u32SpareCnt -= CmdLen ;
1392
1393 WRITE_CMDQ( (_uDmaCtrl0.u32DmaCtrl0)) ;
1394 WRITE_CMDQ( (_uDmaCtrl1.u32DmaCtrl1)) ;
1395 WRITE_CMDQ( (_uDmaCtrl2.u32DmaCtrl2)) ;
1396 WRITE_CMDQ( (_uDmaCtrl3.u32DmaCtrl3)) ;
1397
1398 WRITE_CMDQ((MS_U32)_u32DmaInAddr) ;
1399 WRITE_CMDQ(_u32DmaInNum) ;
1400 WRITE_CMDQ((MS_U32)_u32DmaOut_StartAddr);
1401 WRITE_CMDQ((MS_U32)_u32DmaOut_EndAddr);
1402
1403 if(_uDmaCtrl3.DmaCtrl3.AP == TRUE && _uDmaCtrl3.DmaCtrl3.IK == FALSE)
1404 {
1405 WRITE_CMDQ(_u32OTPHashLengthPadding);
1406 }
1407
1408 if (_uDmaCtrl1.DmaCtrl1.RR == TRUE )
1409 {
1410 WRITE_CMDQ((MS_U32)_u32ReportAddr);
1411 }
1412
1413 // [HW] Hardware will check Current spare count != Write back Spare count to start operation.
1414 REG32(&_AESDMACtrl->SpareCnt) = u32SpareCnt ;
1415 return TRUE ;
1416 }
1417 else
1418 {
1419 // [HW] Check Current spare count == Write back Spare count to start wait cmd
1420 REG32(&_AESDMACtrl->SpareCnt) = u32SpareCnt ;
1421 if (bWaitCmdQ)
1422 {
1423 // Retry until CMDQ avaliable
1424 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA retry!\n",__func__, __LINE__));
1425 goto DMA_RETRY;
1426 }
1427 else
1428 {
1429 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA Fail!\n",__func__, __LINE__));
1430 // Return Fail, Command abort
1431 return FALSE ;
1432 }
1433 }
1434
1435 }
1436
HAL_CIPHER_DMA_CmdDone(MS_U32 u32CmdID,MS_U32 * u32Ret)1437 MS_BOOL HAL_CIPHER_DMA_CmdDone(MS_U32 u32CmdID, MS_U32 *u32Ret)
1438 {
1439 MS_U32 u32ExcTmp = 0;
1440 MS_U32 u32Rpt = REG32(&_AESDMACtrl->Dma_Reportp[0]) ;
1441 MS_U32 u32RptId = u32Rpt & REG_CIPHER_RPT_THREAD_MSK;
1442
1443 if(u32RptId == u32CmdID)
1444 {
1445 u32ExcTmp = (MS_U32) REG32(&_AESDMACtrl->Dma_Ctrl[REG_EXCEPT_FLAG]);
1446 *u32Ret = u32ExcTmp;
1447 }
1448 else
1449 {
1450 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA Cmd[%u] Not done!ReportId[%u]\n",
1451 __func__, __LINE__, u32CmdID, u32RptId));
1452 return FALSE;
1453 }
1454
1455 return TRUE;
1456
1457 }
1458
HAL_CIPHER_GetException(MS_U32 * pu32ExcFlag)1459 void HAL_CIPHER_GetException(MS_U32 *pu32ExcFlag)
1460 {
1461 MS_U32 u32ExcTmp = (MS_U32) REG32(&_AESDMACtrl->Dma_Ctrl[REG_EXCEPT_FLAG]);
1462 *pu32ExcFlag = u32ExcTmp;
1463 }
1464
HAL_CIPHER_ReadException(MS_U32 u32ExcTmp)1465 MS_U32 HAL_CIPHER_ReadException(MS_U32 u32ExcTmp)
1466 {
1467 MS_U32 i = 0;
1468 MS_U32 u32ExcOut = 0;
1469
1470 for(i = 0;i<CRYPTODMA_DEBUG_SIZE;i++) //check each error flag
1471 {
1472 if((u32ExcTmp & (1 << i)) >> i)
1473 {
1474 switch(i)
1475 {
1476 case E_CIPHER_NDS_Region_fail:
1477 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_NDS_Region_fail\n", __func__, __LINE__));
1478 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1479 break;
1480 case E_CIPHER_NDS_keyoff:
1481 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_NDS_keyoff\n", __func__, __LINE__));
1482 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1483 break;
1484 case E_CIPHER_sha_write_scr:
1485 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_write_scr\n", __func__, __LINE__));
1486 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1487 break;
1488 case E_CIPHER_sha_read_scr:
1489 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_read_scr\n", __func__, __LINE__));
1490 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1491 break;
1492 case E_CIPHER_sha_error_flag:
1493 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_error_flag\n", __func__, __LINE__));
1494 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1495 break;
1496 case E_CIPHER_except_read_scr:
1497 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_read_scr\n", __func__, __LINE__));
1498 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1499 break;
1500 case E_CIPHER_except_key:
1501 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_key\n", __func__, __LINE__));
1502 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1503 break;
1504 case E_CIPHER_except_CAVid:
1505 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_CAVid\n", __func__, __LINE__));
1506 u32ExcOut |= HAL_CIPHER_EXCEPT_CAVID;
1507 break;
1508 case E_CIPHER_except_des:
1509 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_des\n", __func__, __LINE__));
1510 u32ExcOut |= HAL_CIPHER_EXCEPT_ALGO;
1511 break;
1512 case E_CIPHER_except_NDS:
1513 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_NDS\n", __func__, __LINE__));
1514 u32ExcOut |= HAL_CIPHER_EXCEPT_ALGO;
1515 break;
1516 case E_CIPHER_except_chain:
1517 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_chain\n", __func__, __LINE__));
1518 u32ExcOut |= HAL_CIPHER_EXCEPT_ALGO;
1519 break;
1520 case E_CIPHER_except_algo:
1521 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_algo\n", __func__, __LINE__));
1522 u32ExcOut |= HAL_CIPHER_EXCEPT_ALGO;
1523 break;
1524 case E_CIPHER_except_key_HID:
1525 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_key_HID\n", __func__, __LINE__));
1526 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1527 break;
1528 case E_CIPHER_except_key_cbc_mac:
1529 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_key_cbc_mac\n", __func__, __LINE__));
1530 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1531 break;
1532 case E_CIPHER_except_file_dqmem:
1533 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_file_dqmem\n", __func__, __LINE__));
1534 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1535 break;
1536 case E_CIPHER_except_hash_dqmem:
1537 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_hash_dqmem\n", __func__, __LINE__));
1538 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1539 break;
1540 case E_CIPHER_disable_masterkey0:
1541 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_masterkey0\n", __func__, __LINE__));
1542 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1543 break;
1544 case E_CIPHER_disable_masterkey1:
1545 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_masterkey1\n", __func__, __LINE__));
1546 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1547 break;
1548 case E_CIPHER_disable_cck:
1549 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_cck\n", __func__, __LINE__));
1550 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1551 break;
1552 case E_CIPHER_disable_reg_key_0:
1553 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_reg_key_0\n", __func__, __LINE__));
1554 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1555 break;
1556 case E_CIPHER_disable_reg_key_1:
1557 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_reg_key_1\n", __func__, __LINE__));
1558 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1559 break;
1560 case E_CIPHER_disable_reg_key_2:
1561 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_reg_key_2\n", __func__, __LINE__));
1562 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1563 break;
1564 case E_CIPHER_disable_reg_key_3:
1565 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_reg_key_3\n", __func__, __LINE__));
1566 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1567 break;
1568 case E_CIPHER_dma_forbid_qmem2dram:
1569 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_dma_forbid_qmem2dram\n", __func__, __LINE__));
1570 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1571 break;
1572 case E_CIPHER_dma_forbid_cryptodma_keyslot_qmem:
1573 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_dma_forbid_cryptodma_keyslot_qmem\n", __func__, __LINE__));
1574 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1575 break;
1576 case E_CIPHER_sha_forbid_qmem2dram:
1577 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_forbid_qmem2dram\n", __func__, __LINE__));
1578 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1579 break;
1580 case E_CIPHER_sha_forbid_cryptodma_keyslot_qmem:
1581 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_forbid_cryptodma_keyslot_qmem\n", __func__, __LINE__));
1582 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1583 break;
1584 case E_CIPHER_tdes_key_error:
1585 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_tdes_key_error\n", __func__, __LINE__));
1586 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1587 break;
1588 case E_CIPHER_write_address_error:
1589 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_write_address_error\n", __func__, __LINE__));
1590 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1591 break;
1592 case E_CIPHER_except_str:
1593 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_str\n", __func__, __LINE__));
1594 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1595 break;
1596 case E_CIPHER_except_sha_str:
1597 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_sha_str\n", __func__, __LINE__));
1598 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1599 break;
1600 default:
1601 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] Unknown error \n", __func__, __LINE__));
1602 break;
1603
1604 }
1605
1606 }
1607
1608 }
1609
1610 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]Exception out [0x%08x]\n", __func__, __LINE__, (unsigned int)u32ExcOut));
1611
1612 return u32ExcOut;
1613
1614 }
1615
HAL_CIPHER_IntEnable(void)1616 void HAL_CIPHER_IntEnable(void)
1617 {
1618 MS_U16 u16MaskTmp = REG16(_u32RegBase + REG_HST0_FIQ_MASK_63_48);
1619 u16MaskTmp &= REG_HTS0_FIQ_MASK_CRYPTODMA; //FIQ 56 in reg_hst0_fiq_mask_63_48_
1620 REG16(_u32RegBase + REG_HST0_FIQ_MASK_63_48) = u16MaskTmp;
1621 }
1622
HAL_CIPHER_IntClear(void)1623 void HAL_CIPHER_IntClear(void)
1624 {
1625 REG16(_u32RegBase + REG_HST0_FIQ_STATUS_63_48) = REG_HTS0_FIQ_CRYPTODMA; //set 1 to clear interrupt
1626 }
1627
1628 //======================================================================
1629
HAL_CIPHER_Hash_GetRpt(MS_U32 * HashRpt,MS_U32 u32Size)1630 void HAL_CIPHER_Hash_GetRpt(MS_U32 *HashRpt, MS_U32 u32Size)
1631 {
1632 MS_U32 i , tmp;
1633
1634 if (u32Size < HASH_RPT_REG_SIZE )
1635 {
1636 tmp = u32Size ;
1637 }
1638 else
1639 {
1640 tmp = HASH_RPT_REG_SIZE ;
1641 }
1642
1643 for (i = 0 ; i < tmp ; i++)
1644 {
1645 HashRpt[i] = REG32(&_AESDMACtrl->Hash_Reportp[i]);
1646 }
1647 }
1648
HAL_CIPHER_Hash_Set_Config(CIPHER_HASH_ALGO algo,MS_BOOL bAutoPad,MS_BOOL bInv16)1649 void HAL_CIPHER_Hash_Set_Config(CIPHER_HASH_ALGO algo , MS_BOOL bAutoPad , MS_BOOL bInv16)
1650 {
1651 HAL_CIPHER_HASHMODE hash_mode = E_HASH_SHA1;
1652 hash_mode = _HAL_CIPHER_TransHASHAlgo(algo);
1653
1654 _uHashCtrl0.HashCtrl0.HashSel = hash_mode ;
1655 _uHashCtrl0.HashCtrl0.AutoPad = bAutoPad ;
1656 _uHashCtrl0.HashCtrl0.Inv16 = bInv16; //Inverse the byte order per 16 bytes
1657
1658 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH Mode[%d], AutoPad[%d], Inverse16[%d]!\n",
1659 __func__, __LINE__, hash_mode, bAutoPad, bInv16));
1660 }
1661
HAL_CIPHER_Hash_Set_ReportMode(MS_BOOL RptInDram,MS_U32 u32DramAddr)1662 void HAL_CIPHER_Hash_Set_ReportMode(MS_BOOL RptInDram, MS_U32 u32DramAddr)
1663 {
1664 if (RptInDram)
1665 {
1666 _u32ReportAddr = u32DramAddr;
1667
1668 }
1669 else
1670 {
1671 _u32ReportAddr = 0;
1672 }
1673
1674 _uHashCtrl2.HashCtrl2.RR = RptInDram ;
1675
1676 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set report mode[%d], report address[0x%08x]\n",
1677 __func__, __LINE__, RptInDram, (unsigned int)_u32ReportAddr));
1678 }
1679
HAL_CIPHER_Hash_SetHMACKey(DRV_CIPHER_HMAC_KEY stHMACKey,CIPHER_HMAC_KPAD eKpad,MS_BOOL bClear)1680 MS_BOOL HAL_CIPHER_Hash_SetHMACKey(DRV_CIPHER_HMAC_KEY stHMACKey, CIPHER_HMAC_KPAD eKpad, MS_BOOL bClear)
1681 {
1682 MS_BOOL bHMAC = TRUE;
1683 MS_U32 u32HMACKeySel = 0;
1684 MS_U32 u32Kpad = CMD_HASH_IKP;
1685 HAL_CIPHER_KEYSRC KeySrc;
1686
1687 //Check Key Source, Index
1688 if(((E_CIPHER_KSRC_KL == stHMACKey.eKeySrc) && (stHMACKey.u8KeyIdx > HAL_CRYPTODMA_DMA_KEY_SLOT-1)) ||
1689 ((E_CIPHER_KSRC_OTP == stHMACKey.eKeySrc) && (stHMACKey.u8KeyIdx > HAL_CRYPTODMA_OTP_SCK_NUM-1)))
1690 {
1691 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Invalid KeySrc[%d], Index[%d]\n",
1692 __func__, __LINE__, stHMACKey.eKeySrc, stHMACKey.u8KeyIdx));
1693 return FALSE;
1694 }
1695
1696 //DRV to HAL Type transfer
1697 KeySrc = _HAL_CIPHER_TransKey(stHMACKey.eKeySrc, stHMACKey.u8KeyIdx);
1698
1699 switch(KeySrc)
1700 {
1701 case E_DMA_KSEL_REGKEY:
1702 u32HMACKeySel = CMD_HMAC_KSEL_HK;
1703 break;
1704 case E_DMA_KSEL_STRN:
1705 u32HMACKeySel = CMD_HMAC_KSEL_STRN;
1706 break;
1707 case E_DMA_KSEL_MK0:
1708 u32HMACKeySel = CMD_HMAC_KSEL_MK0;
1709 break;
1710 case E_DMA_KSEL_MK1:
1711 u32HMACKeySel = CMD_HMAC_KSEL_MK1;
1712 break;
1713 case E_DMA_KSEL_SK0:
1714 u32HMACKeySel = CMD_HMAC_KSEL_SK;
1715 _uHashCtrl0.HashCtrl0.HASH_Key_Index = stHMACKey.u8KeyIdx;
1716 break;
1717 default:
1718 u32HMACKeySel = 0;
1719 break;
1720 }
1721
1722 if(eKpad == E_CIPHER_HMAC_OKPAD)
1723 {
1724 u32Kpad = CMD_HASH_OKP;
1725 }
1726
1727 if(bClear)
1728 {
1729 u32HMACKeySel += (MS_U32)CMD_HMAC_KSEL_CLR_SK;
1730 }
1731
1732 if(KeySrc == E_DMA_KSEL_REGKEY)
1733 {
1734 //command mode
1735 if (0 != stHMACKey.pu8KeyData)
1736 {
1737 memset(_pu8HashHMACHostKey, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX );
1738 memcpy(_pu8HashHMACHostKey, (MS_U8 *)stHMACKey.pu8KeyData , stHMACKey.u8KeyLen);
1739 _uHashCtrl0.HashCtrl0.DK = CMD_HMAC_KSEL_DIR_HK;
1740 }
1741 else
1742 {
1743 memset(_pu8HashHMACHostKey, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX );
1744 bHMAC = FALSE;
1745 }
1746 }
1747
1748 _uHashCtrl0.HashCtrl0.HMAC = bHMAC;
1749 _uHashCtrl0.HashCtrl0.KPAD = u32Kpad;
1750 _uHashCtrl0.HashCtrl0.HMAC_KeySel = u32HMACKeySel;
1751
1752 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HMAC[%d], HMAC KPAD[%u] HMAC KeySel[%u]!\n",
1753 __func__, __LINE__, bHMAC, u32Kpad, u32HMACKeySel));
1754
1755 return TRUE;
1756 }
1757
HAL_CIPHER_Hash_Set_CaVid(MS_U32 u32CAVid)1758 MS_BOOL HAL_CIPHER_Hash_Set_CaVid(MS_U32 u32CAVid)
1759 {
1760 MS_U32 u32Tmp = u32CAVid;
1761
1762 if(u32Tmp > HAL_CRYPTODMA_CAVID_MAX)
1763 {
1764 return FALSE;
1765 }
1766
1767 if(u32Tmp == 0)
1768 {
1769 u32Tmp = _CIPHER_CAVid ;
1770 }
1771 else
1772 {
1773 u32Tmp = u32CAVid;
1774 }
1775
1776 _uHashCtrl1.HashCtrl1.CaVid = u32Tmp;
1777
1778 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set CAVid [0x%x]\n",
1779 __func__, __LINE__, (unsigned int)u32Tmp));
1780
1781 return TRUE;
1782 }
1783
HAL_CIPHER_Hash_Set_IV(MS_U8 * pu8IV,MS_U32 u32IVSize,MS_U32 u32IVSel)1784 MS_BOOL HAL_CIPHER_Hash_Set_IV(MS_U8* pu8IV, MS_U32 u32IVSize ,MS_U32 u32IVSel)
1785 {
1786 // 256 bits for sha256 , 160 bits for sha1
1787 _uHashCtrl0.HashCtrl0.InitHashSel = u32IVSel ;
1788
1789 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH IVSel [%u]\n",
1790 __func__, __LINE__, u32IVSel));
1791
1792 if(u32IVSel == CMD_HASH_IV_CMD)
1793 {
1794 if((pu8IV != NULL) && (u32IVSize > 0))
1795 {
1796 memset(_pu8HashIV, 0x0, HASH_CMD_IV_SIZE);
1797 memcpy(_pu8HashIV, (MS_U8 *)pu8IV , u32IVSize);
1798
1799 return TRUE;
1800 }
1801 else
1802 {
1803 return FALSE;
1804 }
1805 }
1806
1807 return TRUE;
1808 }
1809
1810
HAL_CIPHER_Hash_Set_InitWordCnt(HAL_CIPHER_IWCTYPE eIWCType,MS_U32 u32StartBytes)1811 MS_BOOL HAL_CIPHER_Hash_Set_InitWordCnt(HAL_CIPHER_IWCTYPE eIWCType, MS_U32 u32StartBytes)
1812 {
1813 MS_U32 u32IWCType = 0;
1814 MS_U32 u32IWC = 0;
1815 MS_U32 Rpt[2] = {0};
1816
1817 if(eIWCType == E_CIPHER_HASH_IWC_PRV) //Init Word Count from report
1818 {
1819 u32IWCType = CMD_HASH_IWC_RPT;
1820 HAL_CIPHER_Hash_GetRpt(Rpt, 2); //For debug
1821 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set IWC from report is [%u]\n",
1822 __func__, __LINE__, Rpt[1]>>2));
1823 }
1824 else
1825 {
1826 u32IWCType = CMD_HASH_IWC_CMDQ;
1827 if((u32StartBytes % HASH_MANUAL_BLOCK_SIZE) != 0)
1828 {
1829 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Error:Init word count is 64 bytes alignment!\n",
1830 __func__, __LINE__));
1831 return FALSE;
1832 }
1833
1834 if(u32StartBytes != 0)
1835 {
1836 u32IWC = u32StartBytes/4; //Init Word Count
1837 }
1838 else
1839 {
1840 u32IWC = 0;
1841 }
1842 }
1843
1844 _u32InitWordCnt = u32IWC;
1845 _uHashCtrl0.HashCtrl0.IWC_Sel = u32IWCType;
1846
1847 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set IWC type[%u], IWC[%u]\n",
1848 __func__, __LINE__, u32IWCType, _u32InitWordCnt));
1849
1850 return TRUE;
1851 }
1852
HAL_CIPHER_Hash_Set_MsgSrcFrom(CIPHER_MEM_TYPE eMemType,MS_U32 * u32HashSrc)1853 MS_BOOL HAL_CIPHER_Hash_Set_MsgSrcFrom(CIPHER_MEM_TYPE eMemType, MS_U32 *u32HashSrc)
1854 {
1855 MS_U32 u32SrcTmp = 0;
1856 switch(eMemType)
1857 {
1858 case E_CIPHER_DRAM:
1859 u32SrcTmp = CMD_HASH_SRC_DRAM;
1860 _u32HashSrcAddr = 0;
1861 break;
1862 case E_CIPHER_DQMEM:
1863 u32SrcTmp = CMD_HASH_SRC_R2;
1864 _u32HashSrcAddr = HAL_CIPHER_BASE_DQMEM;
1865 break;
1866 case E_CIPHER_IQMEM:
1867 u32SrcTmp = CMD_HASH_SRC_R2;
1868 _u32HashSrcAddr = HAL_CIPHER_BASE_IQMEM;
1869 break;
1870 case E_CIPHER_DIRECT:
1871 u32SrcTmp = CMD_HASH_SRC_REG;
1872 _u32HashSrcAddr = 0;
1873 break;
1874 default:
1875 u32SrcTmp = CMD_HASH_SRC_DRAM;
1876 _u32HashSrcAddr = 0;
1877 break;
1878 }
1879
1880 *u32HashSrc = u32SrcTmp;
1881
1882 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH source from [%u]\n",
1883 __func__, __LINE__, u32SrcTmp));
1884
1885 return TRUE;
1886 }
1887
HAL_CIPHER_Hash_Set_OutputDstTo(CIPHER_MEM_TYPE eMemType,MS_U32 * u32HashDst)1888 MS_BOOL HAL_CIPHER_Hash_Set_OutputDstTo(CIPHER_MEM_TYPE eMemType, MS_U32 *u32HashDst)
1889 {
1890 MS_U32 u32DstTmp = 0;
1891 switch(eMemType)
1892 {
1893 case E_CIPHER_DRAM:
1894 u32DstTmp = CMD_HASH_OUTPUT_DRAM;
1895 _u32HashDestAddr = 0;
1896 break;
1897 case E_CIPHER_DQMEM:
1898 u32DstTmp = CMD_HASH_OUTPUT_R2;
1899 _u32HashDestAddr = HAL_CIPHER_BASE_DQMEM;
1900 break;
1901 case E_CIPHER_IQMEM:
1902 u32DstTmp = CMD_HASH_OUTPUT_R2;
1903 _u32HashDestAddr = HAL_CIPHER_BASE_IQMEM;
1904 break;
1905 case E_CIPHER_DIRECT:
1906 u32DstTmp = CMD_HASH_OUTPUT_RPT;
1907 _u32HashDestAddr = 0;
1908 break;
1909 default:
1910 u32DstTmp = CMD_HASH_OUTPUT_RPT;
1911 _u32HashDestAddr = 0;
1912 break;
1913 }
1914
1915 *u32HashDst = u32DstTmp;
1916 _uHashCtrl0.HashCtrl0.Dest = u32DstTmp;
1917 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH destination[%u]\n",
1918 __func__, __LINE__, u32DstTmp));
1919
1920 return TRUE;
1921 }
1922
HAL_CIPHER_Hash_Set_OuputAddr(MS_PHY u32OutputPAddr,MS_U32 u32DstSel)1923 MS_BOOL HAL_CIPHER_Hash_Set_OuputAddr(MS_PHY u32OutputPAddr, MS_U32 u32DstSel)
1924 {
1925 if ((CMD_HASH_OUTPUT_DRAM == u32DstSel) || (CMD_HASH_OUTPUT_R2 == u32DstSel))
1926 {
1927 if (0 != u32OutputPAddr)
1928 {
1929 _u32HashDestAddr += u32OutputPAddr;
1930 }
1931 else
1932 {
1933 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Error:Hash output address is NULL\n",__func__, __LINE__));
1934 return FALSE;
1935 }
1936 }
1937 return TRUE;
1938 }
1939
HAL_CIPHER_Hash_SetMsgLength(MS_U32 u32Size)1940 void HAL_CIPHER_Hash_SetMsgLength( MS_U32 u32Size )
1941 {
1942 _u32HashMsgLen = u32Size;
1943
1944 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH message length[%u]\n",
1945 __func__, __LINE__, u32Size));
1946
1947 return ;
1948 }
1949
HAL_CIPHER_Hash_SetHOS(MS_BOOL bHos)1950 void HAL_CIPHER_Hash_SetHOS(MS_BOOL bHos)
1951 {
1952 _uHashCtrl0.HashCtrl0.HOS = bHos;
1953
1954 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HOS[%d]\n",
1955 __func__, __LINE__, bHos));
1956
1957 return ;
1958 }
1959
1960
HAL_CIPHER_Hash_SetMsg(MS_PHY u32MsgPAddr,MS_U32 u32Size,MS_U32 u32SrcSel)1961 MS_BOOL HAL_CIPHER_Hash_SetMsg(MS_PHY u32MsgPAddr, MS_U32 u32Size ,MS_U32 u32SrcSel )
1962 {
1963 _uHashCtrl0.HashCtrl0.Src = u32SrcSel;
1964 _u32HashMsgLen = u32Size;
1965
1966 if ((CMD_HASH_SRC_DRAM == u32SrcSel) || (CMD_HASH_SRC_R2 == u32SrcSel))
1967 {
1968 if (0 != u32MsgPAddr)
1969 {
1970 _u32HashSrcAddr += u32MsgPAddr;
1971 }
1972 else
1973 {
1974 return FALSE;
1975 }
1976 }
1977 else if (CMD_HASH_SRC_REG == u32SrcSel)
1978 {
1979 if((u32MsgPAddr == 0) || (u32Size > HASH_CMD_MSG_SIZE))
1980 {
1981 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Error:Set HASH direct message size[%u] over 64 bytes\n",
1982 __func__, __LINE__, u32Size));
1983 return FALSE;
1984 }
1985 _u32HashSrcAddr = 0;
1986 memset(_pu8HashMsg , 0x0 , HASH_CMD_MSG_SIZE);
1987 memcpy(_pu8HashMsg , (MS_U8 *)(MsOS_PA2KSEG1(u32MsgPAddr)) , u32Size);
1988 }
1989
1990 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH message source[%u], size[%u]\n",
1991 __func__, __LINE__, u32SrcSel, _u32HashMsgLen));
1992
1993 return TRUE;
1994
1995 }
1996
1997
HAL_CIPHER_Hash_Start(HAL_CIPHER_INTMODE IntMode,MS_BOOL bWaitCmdQ,MS_BOOL bRst,MS_U16 u16CmdID)1998 MS_BOOL HAL_CIPHER_Hash_Start(HAL_CIPHER_INTMODE IntMode , MS_BOOL bWaitCmdQ , MS_BOOL bRst, MS_U16 u16CmdID)
1999 {
2000 MS_U32 u32SpareCnt = 0 , CmdLen = 0 , i = 0 ;
2001 MS_U32 u32Tmp;
2002
2003 _uHashCtrl1.HashCtrl1.TID = u16CmdID;
2004 _uHashCtrl0.HashCtrl0.CMD = CMD_HASH_START_RR ;
2005
2006 _uHashCtrl0.HashCtrl0.OVT = FALSE ;
2007 _uHashCtrl0.HashCtrl0.IntM = IntMode ;
2008
2009 CmdLen = _HAL_CIPHER_GetCmdLen(E_CIPHER_TYPE_SHA);
2010
2011 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613
2012 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar
2013
2014
2015 SHA_RETRY:
2016 u32SpareCnt = REG32(&_AESDMACtrl->SpareCnt) ;
2017
2018 if (u32SpareCnt > CmdLen)
2019 {
2020 u32SpareCnt -= CmdLen ;
2021
2022 WRITE_CMDQ( (_uHashCtrl0.u32HashCtrl0)) ;
2023
2024 WRITE_CMDQ( (_uHashCtrl1.u32HashCtrl1)) ;
2025
2026 WRITE_CMDQ( (_uHashCtrl2.u32HashCtrl2)) ;
2027
2028 WRITE_CMDQ(_u32HashMsgLen) ;
2029
2030 //SRC
2031 if (_uHashCtrl0.HashCtrl0.Src != CMD_HASH_SRC_REG)
2032 {
2033 WRITE_CMDQ(_u32HashSrcAddr) ;
2034 }
2035
2036 //RR address
2037 if (_uHashCtrl2.HashCtrl2.RR == TRUE)
2038 {
2039 WRITE_CMDQ(_u32ReportAddr) ;
2040 }
2041
2042 // IWC
2043 if (CMD_HASH_IWC_CMDQ == _uHashCtrl0.HashCtrl0.IWC_Sel)
2044 {
2045 WRITE_CMDQ(_u32InitWordCnt);
2046 }
2047 else
2048 {
2049 REG32(&_AESDMACtrl->Hash_Reportp[1]) = _u32InitWordCnt;
2050 }
2051
2052 // DST
2053 if ((CMD_HASH_OUTPUT_DRAM == _uHashCtrl0.HashCtrl0.Dest) || (_uHashCtrl0.HashCtrl0.Dest == CMD_HASH_OUTPUT_R2 ))
2054 {
2055 WRITE_CMDQ(_u32HashDestAddr);
2056 }
2057
2058 // HASH Initial Vector from CmdQ
2059 if (CMD_HASH_IV_CMD == _uHashCtrl0.HashCtrl0.InitHashSel )
2060 {
2061 for ( i = 0 ; i < (HASH_CMD_IV_SIZE/4) ; i ++ )
2062 {
2063 u32Tmp = ((_pu8HashIV[4*i+0]<<24)|(_pu8HashIV[4*i+1]<<16)|(_pu8HashIV[4*i+2]<<8)|(_pu8HashIV[4*i+3]) );
2064
2065 WRITE_CMDQ(u32Tmp);
2066 }
2067 }
2068
2069 // HASH Data from CmdQ
2070 if ( CMD_HASH_SRC_REG == _uHashCtrl0.HashCtrl0.Src )
2071 {
2072 for ( i = 0 ; i < (HASH_CMD_MSG_SIZE/4) ; i ++ )
2073 {
2074 u32Tmp = ( (_pu8HashMsg[i*4+0]<<24)
2075 |(_pu8HashMsg[i*4+1]<<16)
2076 |(_pu8HashMsg[i*4+2]<<8)
2077 |(_pu8HashMsg[i*4+3]<<0)
2078 );
2079
2080 WRITE_CMDQ(u32Tmp);
2081 }
2082 }
2083
2084 if((CMD_HMAC_KSEL_HK == _uHashCtrl0.HashCtrl0.HMAC_KeySel) && (CMD_HMAC_KSEL_DIR_HK == _uHashCtrl0.HashCtrl0.DK))
2085 {
2086 for ( i = 0 ; i < (HASH_CMD_HMAC_HOSTKEY_SIZE/4) ; i ++ )
2087 {
2088 u32Tmp = ((_pu8HashHMACHostKey[4*i+0]<<24)|(_pu8HashHMACHostKey[4*i+1]<<16)|(_pu8HashHMACHostKey[4*i+2]<<8)|(_pu8HashHMACHostKey[4*i+3]) );
2089
2090 WRITE_CMDQ(u32Tmp);
2091 }
2092 }
2093 // [HW] Hardware will check Current spare count != Write back Spare count to start operation.
2094 REG32(&_AESDMACtrl->SpareCnt) = u32SpareCnt ;
2095 return TRUE ;
2096
2097 }
2098 else
2099 {
2100 // [HW] Check Current spare count == Write back Spare count to start wait cmd
2101 REG32(&_AESDMACtrl->SpareCnt) = u32SpareCnt ;
2102
2103 if (bWaitCmdQ)
2104 {
2105 // Retry until CMDQ avaliable
2106 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]HASH cmd retry!\n",
2107 __func__, __LINE__));
2108 goto SHA_RETRY;
2109 }
2110 else
2111 {
2112 // Return Fail, Command abort
2113 return FALSE ;
2114 }
2115 }
2116 }
2117
HAL_CIPHER_Hash_CmdDone(MS_U32 u32CmdID,MS_U32 * u32Ret)2118 MS_BOOL HAL_CIPHER_Hash_CmdDone(MS_U32 u32CmdID, MS_U32 *u32Ret)
2119 {
2120 MS_U32 u32ExcTmp = 0;
2121
2122 MS_U32 u32Tmp = REG32(&_AESDMACtrl->Hash_Reportp[0]) ;
2123 MS_U32 u32RptId = u32Tmp & REG_CIPHER_RPT_THREAD_MSK;
2124
2125 if(u32RptId == u32CmdID)
2126 {
2127 u32ExcTmp = (MS_U32)REG32(&_AESDMACtrl->Dma_Ctrl[REG_EXCEPT_FLAG]);
2128 *u32Ret = u32ExcTmp;
2129 }
2130 else
2131 {
2132 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]HASH Cmd[%u] Not done!ReportId[%u]\n",
2133 __func__, __LINE__, u32CmdID, u32RptId));
2134 return FALSE;
2135 }
2136
2137 return TRUE;
2138 }
2139
HAL_CIPHER_Hash_ExceptFilter(MS_U32 * pu32Exception,CIPHER_KEY_SRC eKeySrc,MS_U8 u8KeyIdx)2140 void HAL_CIPHER_Hash_ExceptFilter(MS_U32 *pu32Exception, CIPHER_KEY_SRC eKeySrc, MS_U8 u8KeyIdx)
2141 {
2142 //Because CryptoDMA will check every key slot usage for HMAC
2143 //We need to filter out the correct key exception
2144 MS_U32 u32ExcTmp = 0;
2145 HAL_CIPHER_KEYSRC KeySrc = 0;
2146 MS_U32 i = 0;
2147
2148 u32ExcTmp = *pu32Exception;
2149
2150 //DRV to HAL Type transfer
2151 KeySrc = _HAL_CIPHER_TransKey(eKeySrc, u8KeyIdx);
2152
2153 //Only check HMAC key exception
2154 for(i = E_CIPHER_disable_masterkey0;i<=E_CIPHER_disable_reg_key_3;i++) //check each error flag
2155 {
2156 if((u32ExcTmp & (1 << i)) >> i)
2157 {
2158 switch(i)
2159 {
2160 case E_CIPHER_disable_masterkey0:
2161 if(E_DMA_KSEL_MK0 != KeySrc)
2162 u32ExcTmp &= (~(1 << E_CIPHER_disable_masterkey0));
2163 break;
2164
2165 case E_CIPHER_disable_masterkey1:
2166 if(E_DMA_KSEL_MK1 != KeySrc)
2167 u32ExcTmp &= (~(1 << E_CIPHER_disable_masterkey1));
2168 break;
2169
2170 case E_CIPHER_disable_cck:
2171 if(E_DMA_KSEL_CCCK != KeySrc)
2172 u32ExcTmp &= (~(1 << E_CIPHER_disable_cck));
2173 break;
2174
2175 case E_CIPHER_disable_reg_key_0:
2176 if(E_DMA_KSEL_SK0 != KeySrc)
2177 u32ExcTmp &= (~(1 << E_CIPHER_disable_reg_key_0));
2178 break;
2179
2180 case E_CIPHER_disable_reg_key_1:
2181 if(E_DMA_KSEL_SK1 != KeySrc)
2182 u32ExcTmp &= (~(1 << E_CIPHER_disable_reg_key_1));
2183 break;
2184
2185 case E_CIPHER_disable_reg_key_2:
2186 if(E_DMA_KSEL_SK2 != KeySrc)
2187 u32ExcTmp &= (~(1 << E_CIPHER_disable_reg_key_2));
2188 break;
2189
2190 case E_CIPHER_disable_reg_key_3:
2191 if(E_DMA_KSEL_SK3 != KeySrc)
2192 u32ExcTmp &= (~(1 << E_CIPHER_disable_reg_key_3));
2193 break;
2194
2195 default:
2196 break;
2197 }
2198 }
2199 }
2200
2201 *pu32Exception = u32ExcTmp;
2202
2203 return;
2204
2205 }
2206 // =====================================
2207 // Parser function implementation
2208 // =====================================
HAL_CIPHER_PARSER_Set_Mode(CIPHER_PARSER_MODE eMode)2209 void HAL_CIPHER_PARSER_Set_Mode(CIPHER_PARSER_MODE eMode)
2210
2211 {
2212 HAL_CIPHER_PARSER_HDCPMODE eHDCPMode = 0;
2213 HAL_CIPHER_PARSER_TSMODE eTSMode = 0;
2214 HAL_CIPHER_PARSER_PKTMODE ePKTMode = 0;
2215 HAL_CIPHER_PARSER_AUTOMODE eAutoMode = 0;
2216 HAL_CIPHER_PARSER_ITMODE eITMode = 0;
2217 HAL_CIPHER_PARSER_CLEARMODE eClearMode = 0;
2218
2219 switch(eMode)
2220 {
2221 case E_CIPHER_PARSER_TS_PKT192:
2222 eHDCPMode = E_PARSER_HDCPMODE_NONE;
2223 eTSMode = E_PARSER_TSMODE_TS;
2224 ePKTMode = E_PARSER_PKTMODE_192;
2225 eAutoMode = E_PARSER_AUTOMODE_EN;
2226 eITMode = E_PARSER_ITMODE_EN;
2227 eClearMode = E_PARSER_CLEARMODE_NONE;
2228 break;
2229 case E_CIPHER_PARSER_TS_PKT192_CLEAR:
2230 eHDCPMode = E_PARSER_HDCPMODE_NONE;
2231 eTSMode = E_PARSER_TSMODE_TS;
2232 ePKTMode = E_PARSER_PKTMODE_192;
2233 eAutoMode = E_PARSER_AUTOMODE_EN;
2234 eITMode = E_PARSER_ITMODE_EN;
2235 eClearMode = E_PARSER_CLEARMODE_EN;
2236 break;
2237 case E_CIPHER_PARSER_TS_PKT188:
2238 eHDCPMode = E_PARSER_HDCPMODE_NONE;
2239 eTSMode = E_PARSER_TSMODE_TS;
2240 ePKTMode = E_PARSER_PKTMODE_188;
2241 eAutoMode = E_PARSER_AUTOMODE_EN;
2242 eITMode = E_PARSER_ITMODE_EN;
2243 eClearMode = E_PARSER_CLEARMODE_NONE;
2244 break;
2245 case E_CIPHER_PARSER_TS_PKT188_CLEAR:
2246 eHDCPMode = E_PARSER_HDCPMODE_NONE;
2247 eTSMode = E_PARSER_TSMODE_TS;
2248 ePKTMode = E_PARSER_PKTMODE_188;
2249 eAutoMode = E_PARSER_AUTOMODE_EN;
2250 eITMode = E_PARSER_ITMODE_EN;
2251 eClearMode = E_PARSER_CLEARMODE_EN;
2252 break;
2253 case E_CIPHER_PARSER_HDCP20_PKT192:
2254 eHDCPMode = E_PARSER_HDCPMODE_HDCP20;
2255 eTSMode = E_PARSER_TSMODE_PES;
2256 ePKTMode = E_PARSER_PKTMODE_192;
2257 eAutoMode = E_PARSER_AUTOMODE_EN;
2258 eITMode = E_PARSER_ITMODE_EN;
2259 eClearMode = E_PARSER_CLEARMODE_NONE;
2260 break;
2261 case E_CIPHER_PARSER_HDCP20_PKT192_CLEAR:
2262 eHDCPMode = E_PARSER_HDCPMODE_HDCP20;
2263 eTSMode = E_PARSER_TSMODE_PES;
2264 ePKTMode = E_PARSER_PKTMODE_192;
2265 eAutoMode = E_PARSER_AUTOMODE_EN;
2266 eITMode = E_PARSER_ITMODE_NONE;
2267 eClearMode = E_PARSER_CLEARMODE_EN;
2268 break;
2269 case E_CIPHER_PARSER_HDCP20_PKT188:
2270 eHDCPMode = E_PARSER_HDCPMODE_HDCP20;
2271 eTSMode = E_PARSER_TSMODE_PES;
2272 ePKTMode = E_PARSER_PKTMODE_188;
2273 eAutoMode = E_PARSER_AUTOMODE_EN;
2274 eITMode = E_PARSER_ITMODE_EN;
2275 eClearMode = E_PARSER_CLEARMODE_NONE;
2276 break;
2277 case E_CIPHER_PARSER_HDCP20_PKT188_CLEAR:
2278 eHDCPMode = E_PARSER_HDCPMODE_HDCP20;
2279 eTSMode = E_PARSER_TSMODE_PES;
2280 ePKTMode = E_PARSER_PKTMODE_188;
2281 eAutoMode = E_PARSER_AUTOMODE_EN;
2282 eITMode = E_PARSER_ITMODE_NONE;
2283 eClearMode = E_PARSER_CLEARMODE_EN;
2284 break;
2285 default:
2286 printf("Error: Not suport parser mode!\n");
2287 break;
2288 }
2289
2290 _uDmaCtrl2.DmaCtrl2.HP = TRUE;
2291 _uDmaCtrl2.DmaCtrl2.HDCP = eHDCPMode;
2292 _uDmaCtrl2.DmaCtrl2.TS = eTSMode;
2293 _uDmaCtrl2.DmaCtrl2.P192 = ePKTMode;
2294 _uDmaCtrl2.DmaCtrl2.AT = eAutoMode;
2295 _uDmaCtrl2.DmaCtrl2.IT = eITMode;
2296 _uDmaCtrl2.DmaCtrl2.CR = eClearMode;
2297
2298 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Parser config:HDCP[%d], TS[%d], P192[%d], AT[%d], IT[%d], ClearMode[%d]\n",
2299 __func__, __LINE__, eHDCPMode, eTSMode, ePKTMode, eAutoMode, eITMode, eClearMode));
2300
2301
2302 }
2303
HAL_CIPHER_PARSER_Set_MaskSCB(MS_BOOL bEnable)2304 void HAL_CIPHER_PARSER_Set_MaskSCB(MS_BOOL bEnable)
2305 {
2306 _uDmaCtrl2.DmaCtrl2.TsSbMk = bEnable;
2307 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Enable MaskSCB[%d]!\n",
2308 __func__, __LINE__, bEnable));
2309 }
2310
HAL_CIPHER_PARSER_Set_SCB(CIPHER_PARSER_SCB eSCB)2311 void HAL_CIPHER_PARSER_Set_SCB(CIPHER_PARSER_SCB eSCB)
2312 {
2313 MS_U8 u8SCB = 0;
2314
2315 if(eSCB == E_CIPHER_PARSER_SCB_10)
2316 {
2317 u8SCB = CMD_PARSER_SCB10;
2318 }
2319 else if(eSCB == E_CIPHER_PARSER_SCB_11)
2320 {
2321 u8SCB = CMD_PARSER_SCB11;
2322 }
2323 else
2324 {
2325 u8SCB = 0;
2326 }
2327 _uDmaCtrl2.DmaCtrl2.TsSbPn = u8SCB;
2328 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set SCB[%u]!\n",
2329 __func__, __LINE__, u8SCB));
2330 }
2331
HAL_CIPHER_PARSER_Set_ForceSCB(MS_BOOL bInsert,CIPHER_PARSER_SCB eSCB)2332 void HAL_CIPHER_PARSER_Set_ForceSCB(MS_BOOL bInsert, CIPHER_PARSER_SCB eSCB)
2333 {
2334 MS_U8 u8SCB = 0;
2335
2336 if(bInsert)
2337 {
2338 if(eSCB == E_CIPHER_PARSER_SCB_10)
2339 {
2340 u8SCB = CMD_PARSER_SCB10;
2341 }
2342 else if(eSCB == E_CIPHER_PARSER_SCB_11)
2343 {
2344 u8SCB = CMD_PARSER_SCB11;
2345 }
2346 else
2347 {
2348 u8SCB = 0;
2349 }
2350 }
2351
2352 _uDmaCtrl2.DmaCtrl2.InSb = bInsert;
2353 _uDmaCtrl2.DmaCtrl2.TsInSb = u8SCB;
2354
2355 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set Insert Enable[%d], SCB[%u]!\n",
2356 __func__, __LINE__, bInsert, u8SCB));
2357
2358 }
2359
HAL_CIPHER_PARSER_Rmv_SCB(MS_BOOL bRemove)2360 void HAL_CIPHER_PARSER_Rmv_SCB(MS_BOOL bRemove)
2361 {
2362 _uDmaCtrl2.DmaCtrl2.RmSb = bRemove;
2363 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Remove SCB[%d]!\n",
2364 __func__, __LINE__, bRemove));
2365 }
2366
HAL_CIPHER_PARSER_BypassPid(MS_BOOL bEnable)2367 void HAL_CIPHER_PARSER_BypassPid(MS_BOOL bEnable)
2368 {
2369 _uDmaCtrl2.DmaCtrl2.BPS = bEnable;
2370 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Bypass PID[%d]!\n",
2371 __func__, __LINE__, bEnable));
2372 }
2373
HAL_CIPHER_PARSER_Set_PID(CIPHER_PARSER_PID stPID)2374 void HAL_CIPHER_PARSER_Set_PID(CIPHER_PARSER_PID stPID)
2375 {
2376 if(stPID.pu8PID0 != NULL)
2377 {
2378 memset(_pu8PID0, 0x0 , PID_SIZE );
2379 memcpy(_pu8PID0, stPID.pu8PID0, PID_SIZE);
2380 }
2381 else
2382 {
2383 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set PID0 NULL!\n",
2384 __func__, __LINE__));
2385 }
2386
2387 if(stPID.pu8PID1 != NULL)
2388 {
2389 memset(_pu8PID1, 0x0 , PID_SIZE );
2390 memcpy(_pu8PID1, stPID.pu8PID1 , PID_SIZE);
2391 }
2392 else
2393 {
2394 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set PID1 NULL!\n",
2395 __func__, __LINE__));
2396 }
2397 }
2398
HAL_CIPHER_PARSER_Set_Key2(DRV_CIPHER_KEY stKey)2399 MS_BOOL HAL_CIPHER_PARSER_Set_Key2(DRV_CIPHER_KEY stKey)
2400 {
2401 HAL_CIPHER_KEYSRC KeySrc = 0;
2402 HAL_CIPHER_ALGO algo = 0;
2403 MS_BOOL bDK2 = FALSE;
2404 MS_BOOL bTwoKey = FALSE;
2405
2406 algo = _uDmaCtrl0.DmaCtrl0.Algo;
2407
2408 if(E_DMA_ALGO_NONE == algo)
2409 {
2410 //No key
2411 bDK2 = FALSE;
2412 bTwoKey = FALSE;
2413 memset(_pu8CipherKey2, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX);
2414 goto SET_KEY_DONE;
2415 }
2416
2417 //Check Key Source, Index
2418 if(((E_CIPHER_KSRC_KL == stKey.eKeySrc) && (stKey.u8KeyIdx > HAL_CRYPTODMA_DMA_KEY_SLOT-1)) ||
2419 ((E_CIPHER_KSRC_OTP == stKey.eKeySrc) && (stKey.u8KeyIdx > HAL_CRYPTODMA_OTP_SCK_NUM-1)))
2420 {
2421 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Invalid KeySrc[%d], Index[%d]\n",
2422 __func__, __LINE__, stKey.eKeySrc, stKey.u8KeyIdx));
2423 return FALSE;
2424 }
2425
2426 //DRV to HAL Type transfer
2427 KeySrc = _HAL_CIPHER_TransKey(stKey.eKeySrc, stKey.u8KeyIdx);
2428
2429 // key from CPU
2430 if(E_DMA_KSEL_REGKEY == KeySrc)
2431 {
2432 if ((0 != stKey.pu8KeyData) && (stKey.u8KeyLen != 0) && (stKey.u8KeyLen <= HAL_CRYPTODMA_KEYLEN_MAX) )
2433 {
2434 if(E_DMA_ALGO_AES == algo)
2435 {
2436 if((stKey.u8KeyLen != E_DMA_AES_KEY128) && (stKey.u8KeyLen != E_DMA_AES_KEY192) && (stKey.u8KeyLen != E_DMA_AES_KEY256))
2437 {
2438 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Invalid KeyLen[%d]\n",
2439 __func__, __LINE__, stKey.u8KeyLen));
2440 return FALSE ;
2441 }
2442
2443 if(stKey.u8KeyLen == E_DMA_AES_KEY192)
2444 {
2445 _uDmaCtrl3.DmaCtrl3.Aes_mode2 = CMD_AES_MODE_192;
2446 }
2447 else if(stKey.u8KeyLen == E_DMA_AES_KEY256)
2448 {
2449 _uDmaCtrl3.DmaCtrl3.Aes_mode2 = CMD_AES_MODE_256;
2450 }
2451 }
2452
2453 memset(_pu8CipherKey2, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX );
2454 memcpy(_pu8CipherKey2, (MS_U8 *)stKey.pu8KeyData , stKey.u8KeyLen);
2455 bDK2 = TRUE;
2456 KeySrc = 0;
2457 }
2458 else
2459 {
2460 return FALSE ;
2461 }
2462 }
2463 else if(E_DMA_KSEL_CAIP == KeySrc)
2464 {
2465 bDK2 = FALSE ;
2466 KeySrc = 0 ;
2467 }
2468 else// key from KL or OTP
2469 {
2470 bDK2 = FALSE;
2471 }
2472
2473 bTwoKey = TRUE;
2474
2475 SET_KEY_DONE:
2476
2477 _uDmaCtrl0.DmaCtrl0.Key_Index = stKey.u8KeyIdx;
2478 _uDmaCtrl3.DmaCtrl3.DK2 = bDK2;
2479 _uDmaCtrl3.DmaCtrl3.KeySel2 = KeySrc;
2480 _uDmaCtrl2.DmaCtrl2.TK = bTwoKey;
2481
2482 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set DK2[%d], KeySel2[%d]\n",
2483 __func__, __LINE__, bDK2, KeySrc));
2484
2485 return TRUE ;
2486
2487 }
2488
HAL_CIPHER_PARSER_Set_IV2(MS_U8 * pu8IV2,MS_U8 u8IVLen)2489 MS_BOOL HAL_CIPHER_PARSER_Set_IV2(MS_U8 *pu8IV2, MS_U8 u8IVLen)
2490 {
2491 if((pu8IV2 != NULL) && (u8IVLen != 0))
2492 {
2493 memset(_pu8IV2, 0, CIPHER_KEY_SIZE);
2494 memcpy(_pu8IV2, pu8IV2, u8IVLen);
2495 _uDmaCtrl3.DmaCtrl3.DIV2 = TRUE;
2496
2497 return TRUE;
2498 }
2499 else
2500 {
2501 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set IV2 NULL!\n",
2502 __func__, __LINE__));
2503 return FALSE;
2504 }
2505
2506 }
2507
HAL_CIPHER_PARSER_Set_ClearStartMode(MS_BOOL bEnable)2508 void HAL_CIPHER_PARSER_Set_ClearStartMode(MS_BOOL bEnable)
2509 {
2510 _uDmaCtrl3.DmaCtrl3.CRS = bEnable;
2511 }
2512
2513 // =====================================
2514 // MISC function implementation
2515 // =====================================
HAL_CIPHER_Misc_Random(MS_U8 * pu8Buf,MS_U32 u32Size)2516 MS_BOOL HAL_CIPHER_Misc_Random(MS_U8 *pu8Buf, MS_U32 u32Size)
2517 {
2518 MS_U16 u16TRN = 0;
2519 MS_U16 u16PreTRN = 0;
2520 MS_U32 u32Count = 0;
2521
2522 if(NULL == pu8Buf || 0 == u32Size)
2523 return FALSE;
2524
2525 #if defined (MCU_AEON)
2526
2527 while(u32Count < u32Size)
2528 {
2529 do{
2530 do{
2531 //Toggle random number bit
2532 REG32(_u32RegBase+REG_RNG_TRNG_SCPU) ^= REG_RNG_TRNG_ACK_SCPU;
2533 }//Read random number valid
2534 while( !(REG32(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_VALID_SCPU_MASK) );
2535 }
2536 while( (u16TRN = (REG32(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_OUT_SCPU_MASK))==u16PreTRN );
2537 u16PreTRN = u16TRN;
2538
2539 if(0 == ((u32Size - u32Count)%2UL))
2540 {
2541 *(pu8Buf+u32Count) = u16TRN & 0xFFUL;
2542 *(pu8Buf+u32Count+1) = (u16TRN & 0xFF00UL) >> 8;
2543 u32Count += 2;
2544 }
2545 else
2546 {
2547 *(pu8Buf+u32Count) = u16TRN & 0xFFUL;
2548 u32Count += 1;
2549 }
2550 }
2551
2552 #else
2553
2554 while(u32Count < u32Size)
2555 {
2556 do{
2557 do{
2558 //Toggle random number bit
2559 REG32(_u32RegBase+REG_RNG_TRNG_ACPU) ^= REG_RNG_TRNG_ACK_ACPU;
2560 }//Read random number valid
2561 while( !(REG32(_u32RegBase+REG_RNG_TRNG_ACPU) & REG_RNG_TRNG_VALID_ACPU_MASK) );
2562 }
2563 while( (u16TRN = (REG32(_u32RegBase+REG_RNG_TRNG_ACPU) & REG_RNG_TRNG_OUT_ACPU_MASK))==u16PreTRN );
2564 u16PreTRN = u16TRN;
2565
2566 if(0 == ((u32Size - u32Count)%2UL))
2567 {
2568 *(pu8Buf+u32Count) = u16TRN & 0xFFUL;
2569 *(pu8Buf+u32Count+1) = (u16TRN & 0xFF00UL) >> 8;
2570 u32Count += 2;
2571 }
2572 else
2573 {
2574 *(pu8Buf+u32Count) = u16TRN & 0xFFUL;
2575 u32Count += 1;
2576 }
2577 }
2578 #endif
2579
2580 return TRUE;
2581 }
2582
2583
2584