1 //////////////////////////////////////////////////////////////////////////////// 2 // 3 // Copyright (c) 2006-2009 MStar Semiconductor, Inc. 4 // All rights reserved. 5 // 6 // Unless otherwise stipulated in writing, any and all information contained 7 // herein regardless in any format shall remain the sole proprietary of 8 // MStar Semiconductor Inc. and be kept in strict confidence 9 // (��MStar Confidential Information��) by the recipient. 10 // Any unauthorized act including without limitation unauthorized disclosure, 11 // copying, use, reproduction, sale, distribution, modification, disassembling, 12 // reverse engineering and compiling of the contents of MStar Confidential 13 // Information is unlawful and strictly prohibited. MStar hereby reserves the 14 // rights to any and all damages, losses, costs and expenses resulting therefrom. 15 // 16 //////////////////////////////////////////////////////////////////////////////// 17 18 //////////////////////////////////////////////////////////////////////////////////////////////////// 19 // 20 // File name: regCIPHER.h 21 // Description: CIPHER Register Definition 22 // 23 //////////////////////////////////////////////////////////////////////////////////////////////////// 24 25 #ifndef __REG_CIPHER_H__ 26 #define __REG_CIPHER_H__ 27 28 29 //-------------------------------------------------------------------------------------------------- 30 // Abbreviation 31 //-------------------------------------------------------------------------------------------------- 32 // Addr Address 33 // Buf Buffer 34 // Clr Clear 35 // CmdQ Command queue 36 // Cnt Count 37 // Ctrl Control 38 // Flt Filter 39 // Hw Hardware 40 // Int Interrupt 41 // Len Length 42 // Ovfw Overflow 43 // Pkt Packet 44 // Rec Record 45 // Recv Receive 46 // Rmn Remain 47 // Reg Register 48 // Req Request 49 // Rst Reset 50 // Scmb Scramble 51 // Sec Section 52 // Stat Status 53 // Sw Software 54 // Ts Transport Stream 55 56 #include "MsTypes.h" 57 //-------------------------------------------------------------------------------------------------- 58 // Global Definition 59 //-------------------------------------------------------------------------------------------------- 60 61 62 //-------------------------------------------------------------------------------------------------- 63 // Compliation Option 64 //-------------------------------------------------------------------------------------------------- 65 66 67 //------------------------------------------------------------------------------------------------- 68 // Harware Capability 69 //------------------------------------------------------------------------------------------------- 70 71 72 //------------------------------------------------------------------------------------------------- 73 // Type and Structure 74 //------------------------------------------------------------------------------------------------- 75 #if defined (MCU_AEON) 76 #define REG_CIPHERCTRL_BASE (0x1A0200 * 2) // bank 0x2A02 77 #else 78 #define REG_CIPHERCTRL_BASE (0xA0B00 * 2) // bank 0x1A0B 79 #endif 80 #define REG_IRQCTRL_BASE (0x01900 * 2) // bank 0x1019 81 #define REG_MIU_CROSSBAR (0x61300 * 2) //bank 0x1613 82 83 #define REG32_Data volatile MS_U32 84 85 #define DMA_CTRL_REG_SIZE 5UL //0x02:ctrl 0x03:reserved 0x04:reserved 0x05:except_flag 0x06:cryptoDMA_debug 86 #define DMA_DIRECT_OUTPUT_SIZE 4UL 87 #define HASH_RPT_REG_SIZE 10UL 88 #define DMA_RPT_REG_SIZE 2UL 89 #define HMAC_KEY_SIZE 4UL 90 #define HWPA_KEY_SIZE 4UL 91 #define HWPA_IV_SIZE 4UL 92 93 #define RESERVE_SIZE1 3UL 94 #define RESERVE_SIZE2 21UL 95 96 #define HASH_CMD_MSG_SIZE (64UL) //16*4 97 #define HASH_CMD_IV_SIZE (32UL) //8*4 98 #define HASH_CMD_HMAC_HOSTKEY_SIZE (16UL) 99 100 typedef struct _REG_AESDMACtrl 101 { 102 REG32_Data SpareCnt_ORG ; 103 REG32_Data Cmd_Queue_ORG; 104 REG32_Data Dma_Ctrl[DMA_CTRL_REG_SIZE]; //0x02:ctrl 0x03:debug data 0x04:reserved 0x05:except_flag 0x06:cryptoDMA_debug 105 #define REG_DMA_CTRL 0x0 106 #define REG_EXCEPT_FLAG 0x3 107 #define REG_EXCEPT_FLAG_SIZE 27 108 #define REG_CRYPTODMA_DEBUG 0x4 109 #define REG_EXCEPT_FLAG_CLEAR 0x80000 110 #define REG_PARSER_LG_PATH_EN 0x400 111 #define REG_DMA_SW_RESET 0x1 112 #define REG_DMA_STR_KEY_VALID 0x80000000 113 REG32_Data Dma_Out[DMA_DIRECT_OUTPUT_SIZE]; 114 REG32_Data Hash_Reportp[HASH_RPT_REG_SIZE]; 115 #define REG_CIPHER_RPT_THREAD_MSK 0xFFFF 116 #define REG_CIPHER_RPT_OK 0x80000000 117 #define REG_CIPHER_RPT_SHT 31 118 REG32_Data Dma_Reportp[DMA_RPT_REG_SIZE]; 119 REG32_Data CryptoDMA2MI_NS; 120 REG32_Data Debug_Port; 121 REG32_Data HMAC_Key[HMAC_KEY_SIZE]; 122 REG32_Data RESERVE1[RESERVE_SIZE1]; 123 REG32_Data HWPA_Ctrl; 124 REG32_Data HWPA_IV2[HWPA_IV_SIZE]; 125 REG32_Data HWPA_Key2[HWPA_KEY_SIZE]; 126 REG32_Data Cipher_Status; 127 REG32_Data Parser_Status; 128 REG32_Data RESERVE2[RESERVE_SIZE2]; 129 REG32_Data SpareCnt ; 130 REG32_Data Cmd_Queue; 131 132 133 }REG_AESDMACtrl; 134 135 typedef enum 136 { 137 E_CIPHER_NDS_Region_fail, 138 E_CIPHER_NDS_keyoff, 139 E_CIPHER_sha_write_scr, 140 E_CIPHER_sha_read_scr, 141 E_CIPHER_sha_error_flag, 142 E_CIPHER_except_read_scr, 143 E_CIPHER_except_key, 144 E_CIPHER_except_CAVid, 145 E_CIPHER_except_des, 146 E_CIPHER_except_NDS, 147 E_CIPHER_except_chain, 148 E_CIPHER_except_algo, 149 E_CIPHER_except_key_HID, 150 E_CIPHER_except_key_cbc_mac, 151 E_CIPHER_except_file_dqmem, 152 E_CIPHER_except_hash_dqmem, 153 E_CIPHER_disable_masterkey0, 154 E_CIPHER_disable_masterkey1, 155 E_CIPHER_disable_cck, 156 E_CIPHER_disable_reg_key_0, 157 E_CIPHER_disable_reg_key_1, 158 E_CIPHER_disable_reg_key_2, 159 E_CIPHER_disable_reg_key_3, 160 E_CIPHER_dma_forbid_qmem2dram, 161 E_CIPHER_dma_forbid_cryptodma_keyslot_qmem, 162 E_CIPHER_sha_forbid_qmem2dram, 163 E_CIPHER_sha_forbid_cryptodma_keyslot_qmem, 164 E_CIPHER_tdes_key_error, 165 E_CIPHER_write_address_error, 166 E_CIPHER_except_str, 167 E_CIPHER_except_sha_str 168 169 }REG_Cipher_ExceptFlag; 170 171 typedef enum 172 { 173 E_CIPHER_DEBUG_HASH_BUSY = 0x40, 174 E_CIPHER_DEBUG_DMA_BUSY = 0x80, 175 176 }REG_CIPHER_Debug; 177 178 179 typedef struct _CMD_DmaFormat0 180 { 181 MS_U32 CL:6; 182 #define CMD_LEN_MASK 0x3FUL 183 184 MS_U32 DIV:1; 185 186 MS_U32 DK:1; 187 188 MS_U32 OVT:1; 189 190 MS_U32 SB:3; 191 #define CMD_DMA_SB_SEL_CLR 0x0UL 192 #define CMD_DMA_SB_SEL_IV1 0x1UL 193 #define CMD_DMA_SB_SEL_IV2 0x2UL 194 195 MS_U32 Residue:3; 196 #define CMD_DMA_RESIDUE_CLR 0x0UL 197 #define CMD_DMA_RESIDUE_CTS 0x1UL 198 #define CMD_DMA_RESIDUE_SCTE52 0x2UL 199 200 //jamietest MS_U32 Decrypt:1; 201 202 MS_U32 SubAlgo:4; 203 #define CMD_DMA_SUBALGO_ECB 0x0UL 204 #define CMD_DMA_SUBALGO_CBC 0x1UL 205 #define CMD_DMA_SUBALGO_CTR 0x2UL 206 #define CMD_DMA_SUBALGO_CBC_MAC 0x3UL // [NOTE] This sub algorithm is AES only 207 #define CMD_DMA_SUBALGO_CTR64 0x4UL 208 #define CMD_DMA_SUBALGO_CMAC_KEY 0x5UL 209 #define CMD_DMA_SUBALGO_CMAC_ALGO 0x6UL 210 211 MS_U32 Algo:4; 212 #define CMD_DMA_ALGO_AES 0x1UL 213 #define CMD_DMA_ALGO_DES 0x2UL 214 #define CMD_DMA_ALGO_TDES 0x3UL 215 #define CMD_DMA_ALGO_M6 0x4UL 216 #define CMD_DMA_ALGO_M6_CCBC_DIS 0x5UL 217 #define CMD_DMA_ALGO_M6_KE56 0x6UL 218 #define CMD_DMA_ALGO_M6_KE56_CCBC_DIS 0x7UL 219 #define CMD_DMA_RC4 0x8UL 220 221 MS_U32 KeySel:4; //jamietest KeySel:3 222 223 // bit [3] 224 #define CMD_DMA_KSEL_CLR_SK 0x8UL 225 226 // bit [2:0] 227 #define CMD_DMA_KSEL_SK0 0x0UL //session key 0 228 #define CMD_DMA_KSEL_SK1 0x1UL 229 #define CMD_DMA_KSEL_SK2 0x2UL 230 #define CMD_DMA_KSEL_SK3 0x3UL 231 #define CMD_DMA_KSEL_MK0 0x4UL //SCK3 232 #define CMD_DMA_KSEL_MK1 0x5UL //SCK4 233 #define CMD_DMA_KSEL_CCCK 0x6UL //SCK6 234 #define CMD_DMA_KSEL_TRNG 0x7UL //PM Key 235 236 MS_U32 CMD:3; 237 #define CMD_DMA_ENCRYPT 0x2UL 238 #define CMD_DMA_DECRYPT 0x3UL 239 #define CMD_DMA_MASK 0x2FUL 240 241 MS_U32 HID:2; //[NOTE] Set by HW only 242 #define CMD_ACPU 0x0UL 243 #define CMD_R2 0x1UL 244 #define CMD_BGC51 0x2UL 245 246 }CMD_DmaFormat0; 247 248 249 typedef struct _CMD_DmaFormat1 250 { 251 MS_U32 TID:16; 252 MS_U32 CaVid:5; 253 MS_U32 IntM:1; 254 #define CMD_INT_MODE_NONE 0x0UL 255 #define CMD_INT_MODE_EN 0x1UL 256 //#define CMD_INT_MODE_WAIT_CLR 0x2 // Block next operation until interrupt is cleared 257 MS_U32 NL:1; 258 #define CMD_NEW_LINE 0x1UL 259 260 MS_U32 RR:1; // Report Mode 261 #define CMD_DMA_RPT_MODE_REG 0x0UL 262 #define CMD_DMA_RPT_MODE_DRAM 0x1UL 263 264 MS_U32 Dest:1; // File output Dest 265 #define CMD_DMA_OUTPUT_DRAM 0x0UL 266 #define CMD_DMA_OUTPUT_REG 0x1UL //[NOTE] if HID = R2 , the output will be written into DQRAM 267 268 MS_U32 SD:2; // Source Data 269 #define CMD_DMA_DATA_REG 0x0UL 270 #define CMD_DMA_DATA_DRAM 0x1UL 271 #define CMD_DMA_DATA_R2 0x2UL //[NOTE] bit[15] = 0, IQMEM. bit[15] = 1, DQMEM 272 #define CMD_DMA_DATA_HW_INPUT 0x3UL //jamietest 273 MS_U32 DIBS:1; // Data Input Byte Swap 274 MS_U32 DOBS:1; // Output Data Byte swap 275 MS_U32 DestKL:1; // [NOTE] if DestKL = 0 ,Write output data to DRAM, Regfile or QMEM by setting, DestKL = 1 output to SRAM of KL 276 #define CMD_DMA_OUTPUT_DEST 0x0UL 277 #define CMD_DMA_OUTPUT_SRAM_KL 0x1UL 278 MS_U32 COS:1; // Output Data Swap 279 MS_U32 CIS:1; // Input Data Swap 280 281 }CMD_DmaFormat1; 282 283 typedef struct _CMD_DmaFormat2 284 { 285 MS_U32 OBF_IDX_WRITE:5; 286 MS_U32 CTROT:4; 287 MS_U32 DMP:1; 288 MS_U32 TK:1; 289 MS_U32 TsInSb:2; 290 MS_U32 BPS:1; 291 MS_U32 TsSbMk:1; 292 MS_U32 TsSbPn:2; 293 #define CMD_PARSER_SCB10 0x2UL 294 #define CMD_PARSER_SCB11 0x3UL 295 MS_U32 InSb:1; 296 MS_U32 RmSb:1; 297 MS_U32 CR:1; 298 MS_U32 IT:1; 299 MS_U32 AT:1; 300 MS_U32 P192:1; 301 MS_U32 TS:1; 302 MS_U32 HDCP:1; 303 MS_U32 HP:1; 304 MS_U32 OBF_IDX_READ:5; 305 306 MS_U32 NS:1; 307 #define CMD_DMA_SECURE_IP 0x0UL 308 #define CMD_DMA_NON_SECURE_IP 0x1UL 309 310 }CMD_DmaFormat2; 311 312 typedef struct _CMD_DmaFormat3 313 { 314 MS_U32 Rsv1:4; 315 MS_U32 CRS:1; 316 MS_U32 MP:1; 317 MS_U32 DIV2:1; 318 MS_U32 DK2:1; 319 MS_U32 Rsv2:15; 320 MS_U32 KeySel2:4; 321 MS_U32 Decrypt2:1; 322 MS_U32 IK:1; 323 MS_U32 AP:1; 324 MS_U32 Rsv3:2; 325 326 }CMD_DmaFormat3; 327 328 329 typedef struct _CMD_HashFormat0 330 { 331 MS_U32 CL:6; 332 MS_U32 IntM:1; 333 334 MS_U32 IWC_Sel:1; 335 #define CMD_HASH_IWC_RPT 0x0UL 336 #define CMD_HASH_IWC_CMDQ 0x1UL 337 338 MS_U32 OVT:1; 339 MS_U32 HOS:1; //reverse hash output 340 341 MS_U32 Inv16:1; //invere byte order per 16 byte 342 MS_U32 KPAD:1; 343 #define CMD_HASH_IKP 0x0UL 344 #define CMD_HASH_OKP 0x1UL 345 MS_U32 HMAC:1; 346 #define CMD_HASH_NONE 0x0UL 347 #define CMD_HASH_HMAC 0x1UL 348 349 350 MS_U32 HMAC_KeySel:4; 351 352 // bit [3:0] 353 #define CMD_HMAC_KSEL_HK 0x0UL 354 #define CMD_HMAC_KSEL_STRN 0x1UL 355 #define CMD_HMAC_KSEL_MK0 0x2UL 356 #define CMD_HMAC_KSEL_MK1 0x3UL 357 #define CMD_HMAC_KSEL_CCCK 0x4UL 358 #define CMD_HMAC_KSEL_SK0 0x5UL 359 #define CMD_HMAC_KSEL_SK1 0x6UL 360 #define CMD_HMAC_KSEL_SK2 0x7UL 361 #define CMD_HMAC_KSEL_SK3 0x8UL 362 363 MS_U32 DK:1; //HMAC command key, clear seesion key 364 #define CMD_HMAC_KSEL_CLR_SK 0x1UL //HMAC KSEL = 5-8 365 #define CMD_HMAC_KSEL_DIR_HK 0x1UL //HMAC KSEL = 0 366 367 MS_U32 Dest:2; 368 #define CMD_HASH_OUTPUT_RPT 0x0UL 369 #define CMD_HASH_OUTPUT_R2 0x2UL //IQMEM or DQMEM 370 #define CMD_HASH_OUTPUT_DRAM 0x3UL 371 372 MS_U32 Src:2; 373 #define CMD_HASH_SRC_DRAM 0x0UL 374 #define CMD_HASH_SRC_PRV_RPT 0x1UL //use previous hash operation result in hasg_rpt_reg2~9 375 #define CMD_HASH_SRC_R2 0x2UL //[NOTE] bit[15] = 0, IQMEM. bit[15] = 1, DQMEM 376 #define CMD_HASH_SRC_REG 0x3UL 377 MS_U32 AutoPad:1; 378 MS_U32 InitHashSel:2; 379 #define CMD_HASH_IV_FIPS 0x0UL 380 #define CMD_HASH_IV_CMD 0x1UL 381 #define CMD_HASH_IV_PRV_RPT 0x2UL 382 383 MS_U32 HashSel:2; //jamietest 384 #define CMD_HASH_SHA1 0x0UL 385 #define CMD_HASH_SHA256 0x1UL 386 #define CMD_HASH_MD5 0x2UL 387 388 MS_U32 CMD:3; 389 #define CMD_HASH_START 0x4UL 390 #define CMD_HASH_START_RR 0x6UL 391 392 MS_U32 HID:2; 393 #define CMD_ACPU 0x0UL 394 #define CMD_R2 0x1UL 395 #define CMD_BGC51 0x2UL 396 397 }Hash_DmaFormat0; 398 399 typedef struct _CMD_HashFormat1 400 { 401 MS_U32 TID:16; 402 MS_U32 CaVid:5; 403 MS_U32 OBF_IDX_WRITE:5; 404 MS_U32 OBF_IDX_READ:5; 405 MS_U32 NS:1; 406 #define CMD_HASH_SECURE_IP 0x0UL 407 #define CMD_HASH_NON_SECURE_IP 0x1UL 408 409 }Hash_DmaFormat1; 410 411 typedef struct _CMD_HashFormat2 412 { 413 MS_U32 Rsv:31; 414 MS_U32 RR:1; 415 416 }CMD_HashFormat2; 417 418 419 //===================================================================== 420 // RSA Register Definition 421 //===================================================================== 422 423 #define REG_RSA_BASE (0x31800UL) 424 425 #define REG_RSA_COMMON ( REG_RSA_BASE + 0x0UL ) 426 #define REG_RSA_ONEWAY_SYSREG ( REG_RSA_BASE + 0x1UL ) 427 #define REG_RSA_CTRL ( REG_RSA_BASE + 0x2UL ) 428 #define REG_RSA_IND32_ADDR ( REG_RSA_BASE + 0x3UL ) 429 #define REG_RSA_IND32_WDATA ( REG_RSA_BASE + 0x4UL ) 430 431 #define REG_RSA_SEC_RANGE_START(_a_) ( REG_RSA_BASE + ((_a_)* 2) + 0x5 ) // a = 0 ~ 5 432 #define REG_RSA_SEC_RANGE_END(_a_) ( REG_RSA_BASE + ((_a_)* 2) + 0x6 ) 433 434 #define REG_RSA_KEY_SEL ( REG_RSA_BASE + 0x32UL ) 435 #define REG_RSA_WDATA ( REG_RSA_BASE + 0x39UL ) 436 #define REG_RSA_LV_PROTECT_EN ( REG_RSA_BASE + 0x3aUL ) 437 #define REG_RSA_MAILBOX(_a_) ( REG_RSA_BASE + 0x40UL + (_a_) ) 438 439 //===================================================================== 440 // MISC Register Definition 441 //===================================================================== 442 #define REG_RNG_BASE (0x143800UL)//(0xA1C00 * 2) 443 #define REG_OTP_PUB0_BASE (0xC5800UL)//(0x62C00 * 2) 444 #define REG_OTP_PUB1_BASE (0xC5A00UL)//(0x62D00 * 2) 445 #define REG_OTP_PUB2_BASE (0xC5C00UL)//(0x62E00 * 2) 446 447 #define REG_RNG_TRNG_ACPU (REG_RNG_BASE + 0x13 * 4) 448 449 #define REG_RNG_TRNG_ACK_ACPU 0x80000000UL 450 #define REG_RNG_TRNG_VALID_ACPU_MASK 0x00010000UL 451 #define REG_RNG_TRNG_OUT_ACPU_MASK 0x0000FFFFUL 452 453 #define REG_RNG_TRNG_SCPU (REG_RNG_BASE + 0x12 * 4) 454 455 #define REG_RNG_TRNG_ACK_SCPU 0x80000000UL 456 #define REG_RNG_TRNG_VALID_SCPU_MASK 0x00010000UL 457 #define REG_RNG_TRNG_OUT_SCPU_MASK 0x0000FFFFUL 458 459 //===================================================================== 460 // IRQ Register Definition 461 //===================================================================== 462 #define REG_HST0_FIQ_STATUS_63_48 (REG_IRQCTRL_BASE + (0xfUL * 4)) 463 #define REG_HST0_FIQ_MASK_63_48 (REG_IRQCTRL_BASE + (0x7UL * 4)) 464 465 #define REG_HTS0_FIQ_MASK_CRYPTODMA (0xFEFFUL) 466 #define REG_HTS0_FIQ_CRYPTODMA (0x0100UL) //FIQ 56 is CryptoDMA 467 468 #endif // #ifndef __REG_CIPHER_H__ 469