Home
last modified time | relevance | path

Searched refs:REG_MISC_STATUS_0D (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/include/
H A DregHDMITx.h336 #define REG_MISC_STATUS_0D 0x0DU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/include/
H A DregHDMITx.h336 #define REG_MISC_STATUS_0D 0x0DU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/include/
H A DregHDMITx.h336 #define REG_MISC_STATUS_0D 0x0DU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/include/
H A DregHDMITx.h336 #define REG_MISC_STATUS_0D 0x0DU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/include/
H A DregHDMITx.h346 #define REG_MISC_STATUS_0D 0x0DU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/include/
H A DregHDMITx.h346 #define REG_MISC_STATUS_0D 0x0DU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/
H A DhalHDMITx.c627 …MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, (MS_U16)(u32Int>>16), (MS_U16)(u3… in MHal_HDMITx_Int_Disable()
652 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, 0xFFFF, (~u32Int)>>16 ); in MHal_HDMITx_Int_Enable()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/
H A DhalHDMITx.c650 …MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, (MS_U16)(u32Int>>16), (MS_U16)(u3… in MHal_HDMITx_Int_Disable()
675 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, 0xFFFF, (~u32Int)>>16 ); in MHal_HDMITx_Int_Enable()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/
H A DhalHDMITx.c676 …MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, (MS_U16)(u32Int>>16), (MS_U16)(u3… in MHal_HDMITx_Int_Disable()
701 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, 0xFFFF, (~u32Int)>>16 ); in MHal_HDMITx_Int_Enable()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/
H A DhalHDMITx.c664 …MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, (MS_U16)(u32Int>>16), (MS_U16)(u3… in MHal_HDMITx_Int_Disable()
689 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, 0xFFFF, (~u32Int)>>16 ); in MHal_HDMITx_Int_Enable()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/
H A DhalHDMITx.c798 …MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, (MS_U16)(u32Int>>16), (MS_U16)(u3… in MHal_HDMITx_Int_Disable()
823 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, 0xFFFF, (~u32Int)>>16 ); in MHal_HDMITx_Int_Enable()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/
H A DhalHDMITx.c853 …MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, (MS_U16)(u32Int>>16), (MS_U16)(u3… in MHal_HDMITx_Int_Disable()
878 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, 0xFFFF, (~u32Int)>>16 ); in MHal_HDMITx_Int_Enable()