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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 ///////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regHDMITx.h 98 /// @author MStar Semiconductor,Inc. 99 /// @brief HDMITx Register Definition 100 ///////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_HDMITX_H_ 103 #define _REG_HDMITX_H_ 104 105 //#include "MsCommon.h" 106 107 //------------------------------------------------------------------------------------------------- 108 // Hardware Capability 109 //------------------------------------------------------------------------------------------------- 110 111 112 //------------------------------------------------------------------------------------------------- 113 // Macro and Define 114 //------------------------------------------------------------------------------------------------- 115 116 #define HDMITX_MISC_REG_BASE (0x172000U) 117 #define HDMITX_HDCP_REG_BASE (0x172100U) 118 #define HDMITX_REG_BASE (0x172200U) 119 #define HDMITX_VIDEO_REG_BASE (0x172300U) 120 #define HDMITX_AUDIO_REG_BASE (0x172400U) 121 #define HDMITX_PHY_REG_BASE (0x172600U) 122 123 #define HDMITX_SECUTZPC_BASE (0x173A00U) 124 #define HDMITX_HDCP2TX_BASE (0x172500U) 125 126 #define HDMITX_2_REG_BASE (0x172700U) 127 //#define HDMIRX_COMBOPHY0_REG_BASE (0x172800U) 128 //#define HDMIRX_COMBOPHY1_REG_BASE (0x172900U) 129 130 #define PMBK_PMSLEEP_REG_BASE (0x000E00U) 131 #define CLKGEN1_REG_BASE (0x103300U) 132 #define CLKGEN0_REG_BASE (0x100B00U) 133 #define CHIPTOP_REG_BASE (0x101E00U) 134 #define HDCP_REG_BASE (0x173800U) 135 136 //***** Bank 1728 - COMBO PHY 0 *****// 137 #define REG_COMBOPHY1_CONFIG_3C 0x3CU 138 139 //***** Bank 1729 - COMBO PHY 1 *****// 140 #define REG_COMBOPHY0_CONFIG_4C 0x4CU 141 #define REG_COMBOPHY0_CONFIG_4B 0x4BU 142 #define REG_COMBOPHY0_CONFIG_4A 0x4AU 143 #define REG_COMBOPHY0_CONFIG_49 0x49U 144 #define REG_COMBOPHY0_CONFIG_09 0x09U 145 #define REG_COMBOPHY0_CONFIG_22 0x22U 146 147 //***** Bank 1026 - PADTOP *****// 148 #define REG_SYNC_GPIO0 0x1EU 149 150 //***** Bank 1033(0x28) - CHIPTOP *****// 151 #define REG_CKG_HDMITx_CLK_28 0x28U 152 #define REG_I2S_GPIO4 0x1BU 153 #define REG_CKG0_ODCLK_SOURCE 0x4AU 154 #define REG_CKG0_53 0x53U 155 #define REG_CKG0_5A 0x5AU 156 #define REG_CKG0_7E 0x7EU 157 158 //***** Bank 172C - HDMITX *****// 159 #define REG_HDMI_CONFIG1_00 0x00U 160 #define REG_ACT_HDMI_PKTS_CMD_01 0x01U 161 #define REG_PKT_NUL_CFG_02 0x02U 162 #define REG_PKT_GC_CFG_03 0x03U 163 #define REG_PKT_GC12_04 0x04U 164 #define REG_PKT_ACR_1_05 0x05U 165 #define REG_PKT_ACR_2_06 0x06U 166 #define REG_PKT_ACR_3_07 0x07U 167 #define REG_PKT_ACR_CFG_08 0x08U 168 #define REG_PKT_AVI_1_09 0x09U 169 #define REG_PKT_AVI_2_0A 0x0AU 170 #define REG_PKT_AVI_3_0B 0x0BU 171 #define REG_PKT_AVI_4_0C 0x0CU 172 #define REG_PKT_AVI_5_0D 0x0DU 173 #define REG_PKT_AVI_6_0E 0x0EU 174 #define REG_PKT_AVI_7_0F 0x0FU 175 #define REG_PKT_AVI_CFG_10 0x10U 176 #define REG_PKT_AUD_1_11 0x11U 177 #define REG_PKT_AUD_2_12 0x12U 178 #define REG_PKT_AUD_3_13 0x13U 179 #define REG_PKT_AUD_CFG_14 0x14U 180 #define REG_PKT_SPD_1_15 0x15U 181 #define REG_PKT_SPD_2_16 0x16U 182 #define REG_PKT_SPD_3_17 0x17U 183 #define REG_PKT_SPD_4_18 0x18U 184 #define REG_PKT_SPD_5_19 0x19U 185 #define REG_PKT_SPD_6_1A 0x1AU 186 #define REG_PKT_SPD_7_1B 0x1BU 187 #define REG_PKT_SPD_8_1C 0x1CU 188 #define REG_PKT_SPD_9_1D 0x1DU 189 #define REG_PKT_SPD_10_1E 0x1EU 190 #define REG_PKT_SPD_11_1F 0x1FU 191 #define REG_PKT_SPD_12_20 0x20U 192 #define REG_PKT_SPD_13_21 0x21U 193 #define REG_PKT_SPD_CFG_22 0x22U 194 #define REG_PKT_MPG_1_23 0x23U 195 #define REG_PKT_MPG_2_24 0x24U 196 #define REG_PKT_MPG_3_25 0x25U 197 #define REG_PKT_MPG_CFG_26 0x26U 198 #define REG_PKT_VS_1_27 0x27U 199 #define REG_PKT_VS_2_28 0x28U 200 #define REG_PKT_VS_3_29 0x29U 201 #define REG_PKT_VS_4_2A 0x2AU 202 #define REG_PKT_VS_5_2B 0x2BU 203 #define REG_PKT_VS_6_2C 0x2CU 204 #define REG_PKT_VS_7_2D 0x2DU 205 #define REG_PKT_VS_8_2E 0x2EU 206 #define REG_PKT_VS_9_2F 0x2FU 207 #define REG_PKT_VS_10_30 0x30U 208 #define REG_PKT_VS_11_31 0x31U 209 #define REG_PKT_VS_12_32 0x32U 210 #define REG_PKT_VS_13_33 0x33U 211 #define REG_PKT_VS_14_34 0x34U 212 #define REG_PKT_VS_CFG_35 0x35U 213 #define REG_USER_TYPE_36 0x36U 214 #define REG_USER_HB_37 0x37U 215 #define REG_PKT_ACP_0_38 0x38U 216 #define REG_PKT_ACP_1_39 0x39U 217 #define REG_PKT_ACP_2_3A 0x3AU 218 #define REG_PKT_ACP_3_3B 0x3BU 219 #define REG_PKT_ACP_4_3C 0x3CU 220 #define REG_PKT_ACP_5_3D 0x3DU 221 #define REG_PKT_ACP_6_3E 0x3EU 222 #define REG_PKT_ACP_7_3F 0x3FU 223 #define REG_PKT_ACP_CFG_40 0x40U 224 #define REG_PKT_ISRC_0_41 0x41U 225 #define REG_PKT_ISRC_1_42 0x42U 226 #define REG_PKT_ISRC_2_43 0x43U 227 #define REG_PKT_ISRC_3_44 0x44U 228 #define REG_PKT_ISRC_4_45 0x45U 229 #define REG_PKT_ISRC_5_46 0x46U 230 #define REG_PKT_ISRC_6_47 0x47U 231 #define REG_PKT_ISRC_7_48 0x48U 232 #define REG_PKT_ISRC_8_49 0x49U 233 #define REG_PKT_ISRC_9_4A 0x4AU 234 #define REG_PKT_ISRC_10_4B 0x4BU 235 #define REG_PKT_ISRC_11_4C 0x4CU 236 #define REG_PKT_ISRC_12_4D 0x4DU 237 #define REG_PKT_ISRC_13_4E 0x4EU 238 #define REG_PKT_ISRC_14_4F 0x4FU 239 #define REG_PKT_ISRC_15_50 0x50U 240 #define REG_PKT_ISRC_CFG_51 0x51U 241 #define REG_TMDS_DE_CNT_52 0x52U 242 #define REG_HPLL_LOCK_CNT_53 0x53U 243 #define REG_PKT_GM_CFG_54 0x54U 244 #define REG_PKT_GM_HB2_55 0x55U 245 #define REG_PKT_GM_1_56 0x56U 246 #define REG_PKT_GM_3_57 0x57U 247 #define REG_PKT_GM_5_58 0x58U 248 #define REG_PKT_GM_7_59 0x59U 249 #define REG_PKT_GM_9_5A 0x5AU 250 #define REG_PKT_GM_11_5B 0x5BU 251 #define REG_PKT_GM_13_5C 0x5CU 252 #define REG_PKT_GM_15_5D 0x5DU 253 #define REG_PKT_GM_17_5E 0x5EU 254 #define REG_PKT_GM_19_5F 0x5FU 255 #define REG_PKT_N_PKT_60 0x60U 256 #define REG_PKT_N_PKT_61 0x61U 257 258 //***** Bank 172D - HDMITX_Video *****// 259 #define REG_VE_CONFIG_00 0x00U 260 #define REG_VE_CONFIG_01 0x01U 261 #define REG_VE_CONFIG_02 0x02U 262 #define REG_VE_CONFIG_03 0x03U 263 #define REG_VE_CONFIG_04 0x04U 264 #define REG_VE_CONFIG_05 0x05U 265 #define REG_VE_CONFIG_06 0x06U 266 #define REG_VE_CONFIG_07 0x07U 267 #define REG_VE_CONFIG_08 0x08U 268 #define REG_VE_CONFIG_09 0x09U 269 #define REG_VE_CONFIG_0A 0x0AU 270 #define REG_VE_CONFIG_0B 0x0BU 271 #define REG_VE_CONFIG_0C 0x0CU 272 #define REG_VE_CONFIG_0D 0x0DU 273 #define REG_VE_CONFIG_0E 0x0EU 274 #define REG_VE_CONFIG_0F 0x0FU 275 #define REG_VE_CONFIG_10 0x10U 276 #define REG_VE_CONFIG_11 0x11U 277 #define REG_VE_CONFIG_12 0x12U 278 #define REG_VE_CONFIG_13 0x13U 279 #define REG_VE_CONFIG_14 0x14U 280 #define REG_VE_STATUS_15 0x15U 281 #define REG_VE_STATUS_16 0x16U 282 #define REG_VE_CONFIG_17 0x17U 283 #define REG_VE_CONFIG_18 0x18U 284 #define REG_VE_CONFIG_20 0x20U 285 #define REG_VE_CONFIG_21 0x21U 286 #define REG_VE_CONFIG_22 0x22U 287 #define REG_VE_CONFIG_23 0x23U 288 #define REG_VE_CONFIG_24 0x24U 289 #define REG_VE_CONFIG_25 0x25U 290 #define REG_VE_CONFIG_26 0x26U 291 #define REG_VE_CONFIG_27 0x27U 292 #define REG_VE_CONFIG_28 0x28U 293 #define REG_VE_CONFIG_29 0x29U 294 #define REG_VE_CONFIG_2A 0x2AU 295 #define REG_VE_CONFIG_2D 0x2DU 296 #define REG_VE_CONFIG_30 0x30U 297 #define REG_VE_CONFIG_31 0x31U 298 #define REG_VE_CONFIG_32 0x32U 299 #define REG_VE_CONFIG_33 0x33U 300 #define REG_VE_CONFIG_34 0x34U 301 #define REG_VE_CONFIG_35 0x35U 302 #define REG_VE_CONFIG_36 0x36U 303 #define REG_VE_CONFIG_37 0x37U 304 #define REG_VE_CONFIG_38 0x38U 305 #define REG_VE_CONFIG_39 0x39U 306 #define REG_VE_CONFIG_3A 0x3AU 307 #define REG_VE_CONFIG_3B 0x3BU 308 #define REG_VE_CONFIG_3C 0x3CU 309 #define REG_VE_CONFIG_3D 0x3DU 310 #define REG_VE_CONFIG_50 0x50U 311 #define REG_VE_CONFIG_52 0x52U 312 #define REG_VE_CONFIG_53 0x53U 313 #define REG_VE_CONFIG_54 0x54U 314 #define REG_VE_CONFIG_55 0x55U 315 316 //***** Bank 172E - HDMITX_Audio *****// 317 #define REG_AE_CH_STATUS0_00 0x00U 318 #define REG_AE_CH_STATUS1_01 0x01U 319 #define REG_AE_CH_STATUS2_02 0x02U 320 #define REG_AE_CH_STATUS3_03 0x03U 321 #define REG_AE_CH_STATUS4_04 0x04U 322 #define REG_AE_CONFIG_05 0x05U 323 #define REG_AE_STATUS_06 0x06U 324 #define REG_AE_STATUS_07 0x07U 325 #define REG_AE_CH_STATUS0_0A 0x0AU 326 #define REG_AE_CH_STATUS1_0B 0x0BU 327 #define REG_AE_CH_STATUS2_0C 0x0CU 328 #define REG_AE_CH_STATUS3_0D 0x0DU 329 #define REG_AE_CH_STATUS4_0E 0x0EU 330 331 332 //***** Bank 172A - MISC *****// 333 #define REG_MISC_CONFIG_00 0x00U 334 #define REG_MISC_CONFIG_01 0x01U 335 #define REG_MISC_CONFIG_02 0x02U 336 #define REG_MISC_CONFIG_03 0x03U 337 #define REG_MISC_CONFIG_04 0x04U 338 #define REG_MISC_CONFIG_05 0x05U 339 #define REG_MISC_CONFIG_06 0x06U 340 #define REG_MISC_CONFIG_07 0x07U 341 #define REG_MISC_CONFIG_08 0x08U 342 #define REG_MISC_CONFIG_09 0x09U 343 #define REG_MISC_STATUS_0A 0x0AU 344 #define REG_MISC_STATUS_0B 0x0BU 345 #define REG_MISC_CONFIG_0C 0x0CU 346 #define REG_MISC_STATUS_0D 0x0DU 347 #define REG_MISC_STATUS_0E 0x0EU 348 #define REG_MISC_STATUS_0F 0x0FU 349 #define REG_MISC_CONFIG_17 0x17U 350 #define REG_MISC_CONFIG_1B 0x1BU 351 #define REG_MISC_CONFIG_1C 0x1CU 352 #define REG_MISC_CONFIG_1D 0x1DU 353 #define REG_MISC_CONFIG_1E 0x1EU 354 #define REG_MISC_CONFIG_1F 0x1FU 355 #define REG_MISC_CONFIG_20 0x20U 356 #define REG_MISC_CONFIG_21 0x21U 357 #define REG_MISC_CONFIG_22 0x22U 358 #define REG_MISC_CONFIG_23 0x23U 359 #define REG_MISC_CONFIG_24 0x24U 360 #define REG_MISC_CONFIG_25 0x25U 361 #define REG_MISC_CONFIG_26 0x26U 362 #define REG_MISC_CONFIG_27 0x27U 363 #define REG_MISC_CONFIG_2A 0x2AU 364 #define REG_MISC_CONFIG_2B 0x2BU 365 #define REG_MISC_CONFIG_2C 0x2CU 366 #define REG_MISC_CONFIG_2D 0x2DU 367 #define REG_MISC_CONFIG_2E 0x2EU 368 #define REG_MISC_CONFIG_2F 0x2FU 369 #define REG_MISC_CONFIG_33 0x33U 370 #define REG_MISC_CONFIG_34 0x34U 371 #define REG_MISC_CONFIG_36 0x36U 372 #define REG_MISC_CONFIG_38 0x38U 373 #define REG_MISC_CONFIG_40 0x40U 374 #define REG_MISC_CONFIG_41 0x41U 375 #define REG_MISC_CONFIG_45 0x45U 376 #define REG_MISC_CONFIG_48 0x48U 377 #define REG_MISC_CONFIG_4D 0x4DU 378 #define REG_MISC_CONFIG_52 0x52U 379 #define REG_MISC_CONFIG_58 0x58U 380 #define REG_MISC_CONFIG_59 0x59U 381 #define REG_MISC_CONFIG_5D 0x5DU 382 383 384 //***** Bank 172B - HDCP *****// 385 #define REG_HDCP_TX_RI_00 0x00U 386 #define REG_HDCP_TX_MODE_01 0x01U // Pj[7:0] : 61h[7:0]; Tx_mode[7:0] : 61h[15:8] 387 #define REG_HDCP_TX_COMMAND_02 0x02U 388 #define REG_HDCP_TX_RI127_03 0x03U // RI[15:0] 127th frame : 63[15:0] 389 #define REG_HDCP_TX_LN_04 0x04U // Ln[55:0] : 64h[7:0] ~ 67h[7:0] 390 #define REG_HDCP_TX_LN_SEED_07 0x07U // Ln seed[7:0] : 67h[15:8] 391 #define REG_HDCP_TX_AN_08 0x08U // An[63:0] : 68[7:0] ~ 6B[15:8] 392 #define REG_HDCP_TX_MI_0C 0x0CU // Mi[63:0] : 6C[7:0] ~ 6F[15:8] 393 394 //***** Bank 1730 - HDMI PHY *****// 395 #define REG_HDMITxPHY_CONFIG_01 0x01U 396 #define REG_HDMITxPHY_CONFIG_02 0x02U 397 #define REG_HDMITxPHY_CONFIG_03 0x03U 398 #define REG_HDMITxPHY_CONFIG_05 0x05U 399 #define REG_HDMITxPHY_CONFIG_06 0x06U 400 #define REG_HDMITxPHY_CONFIG_07 0x07U 401 #define REG_HDMITxPHY_CONFIG_0F 0x0FU 402 #define REG_HDMITxPHY_CONFIG_10 0x10U 403 #define REG_HDMITxPHY_CONFIG_11 0x11U 404 #define REG_HDMITxPHY_CONFIG_15 0x15U 405 #define REG_HDMITxPHY_CONFIG_16 0x16U 406 #define REG_HDMITxPHY_CONFIG_17 0x17U 407 #define REG_HDMITxPHY_CONFIG_18 0x18U 408 #define REG_HDMITxPHY_CONFIG_19 0x19U 409 #define REG_HDMITxPHY_CONFIG_26 0x26U 410 #define REG_HDMITxPHY_CONFIG_2E 0x2EU 411 #define REG_HDMITxPHY_CONFIG_30 0x30U 412 #define REG_HDMITxPHY_CONFIG_31 0x31U 413 #define REG_HDMITxPHY_CONFIG_32 0x32U 414 #define REG_HDMITxPHY_CONFIG_33 0x33U 415 #define REG_HDMITxPHY_CONFIG_34 0x34U 416 #define REG_HDMITxPHY_CONFIG_35 0x35U 417 #define REG_HDMITxPHY_CONFIG_36 0x36U 418 #define REG_HDMITxPHY_CONFIG_37 0x37U 419 #define REG_HDMITxPHY_CONFIG_38 0x38U 420 #define REG_HDMITxPHY_CONFIG_39 0x39U 421 #define REG_HDMITxPHY_CONFIG_3A 0x3AU 422 #define REG_HDMITxPHY_CONFIG_3C 0x3CU 423 #define REG_HDMITxPHY_CONFIG_3D 0x3DU 424 #define REG_HDMITxPHY_CONFIG_3F 0x3FU 425 #define REG_HDMITxPHY_CONFIG_40 0x40U 426 #define REG_HDMITxPHY_CONFIG_41 0x41U 427 #define REG_HDMITxPHY_CONFIG_42 0x42U 428 #define REG_HDMITxPHY_CONFIG_46 0x46U 429 #define REG_HDMITxPHY_CONFIG_60 0x60U 430 #define REG_HDMITxPHY_CONFIG_79 0x79U 431 #define REG_HDMITxPHY_CONFIG_7A 0x7AU 432 #define REG_HDMITxPHY_CONFIG_7E 0x7EU 433 434 //***** Bank 1738 - HDMITX 2 *****// 435 #define REG_HDMI_2_CONFIG_00 0x00U 436 #define REG_HDMI_2_CONFIG_10 0x10U 437 #define REG_HDMI_2_CONFIG_1D 0x1DU 438 #define REG_HDMI_2_CONFIG_1E 0x1EU 439 #define REG_HDMI_2_CONFIG_1F 0x1FU 440 441 //***** Bank 0E - PM_SLEEP *****// 442 #define REG_PM_SLP_0F 0x0FU 443 #define REG_PM_SLP_10 0x10U 444 #define REG_PM_SLP_12 0x12U 445 #define REG_PM_SLP_20 0x20U 446 #define REG_PM_SLP_27 0x27U 447 #define REG_PM_SLP_4A 0x4AU 448 #define REG_PM_SLP_4B 0x4BU 449 #define REG_PM_SLP_4C 0x4CU 450 #define REG_PM_SLP_57 0x57U 451 #define REG_PM_SLP_62 0x62U 452 453 //***** Bank 14 - PM_SAR *****// 454 #define REG_PM_SAR_11 0x11U 455 #define REG_PM_SAR_12 0x12U 456 457 //***** Bank 21 - TX_PM *****// 458 #define REG_PM_HDMITX_03 0x03U 459 #define REG_PM_HDMITX_1C 0x1CU 460 #define REG_PM_HDMITX_2B 0x2BU 461 #define REG_PM_HDMITX_2C 0x2CU 462 #define REG_PM_HDMITX_2E 0x2EU 463 #define REG_PM_HDMITX_2F 0x2FU 464 #define REG_PM_HDMITX_33 0x33U 465 #define REG_PM_HDMITX_34 0x34U 466 #define REG_PM_HDMITX_38 0x38U 467 468 //***** Bank 22 - RX_PM *****// 469 #define REG_PM_HDMIRX_ATOP_06 0x06U 470 #define REG_PM_HDMIRX_ATOP_60 0x60U 471 #define REG_PM_HDMIRX_ATOP_7F 0x7FU 472 473 //------------------------------------------------------------------------------------------------- 474 // Type and Structure 475 //------------------------------------------------------------------------------------------------- 476 477 #endif // _REG_HDMITX_H_ 478 479