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Searched refs:L_CLKGEN1 (Results 1 – 25 of 49) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_sc.c5585 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x000C); // 345MHz in MHal_CLKGEN_FRC_Init()
5586 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
5587 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x0001); // Enable clock in MHal_CLKGEN_FRC_Init()
5590 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0C00); // 172MHz in MHal_CLKGEN_FRC_Init()
5591 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
5592 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
5619 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x000C); // 216 MHz in MHal_CLKGEN_FRC_Init()
5620 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
5621 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0101); // Enable clock in MHal_CLKGEN_FRC_Init()
5624 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0C00); // 216 MHz in MHal_CLKGEN_FRC_Init()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_sc.c4986 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x000C); // 216 MHz in MHal_CLKGEN_FRC_Init()
4987 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
4988 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0101); // Enable clock in MHal_CLKGEN_FRC_Init()
4991 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0C00); // 216 MHz in MHal_CLKGEN_FRC_Init()
4992 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
4993 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
4996 W2BYTEMSK(L_CLKGEN1(0x31), 0x0000, 0x0C00); // CLK_LPLL in MHal_CLKGEN_FRC_Init()
4997 W2BYTEMSK(L_CLKGEN1(0x31), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
4998 W2BYTEMSK(L_CLKGEN1(0x31), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
5002 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x000C); // clk_odclk_frc in MHal_CLKGEN_FRC_Init()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_sc.c5646 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x000C); // 345MHz in MHal_CLKGEN_FRC_Init()
5647 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
5648 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x0001); // Enable clock in MHal_CLKGEN_FRC_Init()
5651 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0C00); // 172MHz in MHal_CLKGEN_FRC_Init()
5652 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
5653 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
5680 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x000C); // 216 MHz in MHal_CLKGEN_FRC_Init()
5681 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
5682 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0101); // Enable clock in MHal_CLKGEN_FRC_Init()
5685 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0C00); // 216 MHz in MHal_CLKGEN_FRC_Init()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_sc.c6043 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x000C); // 345MHz in MHal_CLKGEN_FRC_Init()
6044 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
6045 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x0001); // Enable clock in MHal_CLKGEN_FRC_Init()
6048 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0C00); // 172MHz in MHal_CLKGEN_FRC_Init()
6049 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
6050 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
6094 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x000C); // 216 MHz in MHal_CLKGEN_FRC_Init()
6095 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
6096 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0101); // Enable clock in MHal_CLKGEN_FRC_Init()
6099 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0C00); // 216 MHz in MHal_CLKGEN_FRC_Init()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_sc.c6063 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x000C); // 345MHz in MHal_CLKGEN_FRC_Init()
6064 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
6065 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x0001); // Enable clock in MHal_CLKGEN_FRC_Init()
6068 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0C00); // 172MHz in MHal_CLKGEN_FRC_Init()
6069 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
6070 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
6114 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x000C); // 216 MHz in MHal_CLKGEN_FRC_Init()
6115 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
6116 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0101); // Enable clock in MHal_CLKGEN_FRC_Init()
6119 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0C00); // 216 MHz in MHal_CLKGEN_FRC_Init()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_sc.c6348 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x000C); // 345MHz in MHal_CLKGEN_FRC_Init()
6349 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
6350 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x0001); // Enable clock in MHal_CLKGEN_FRC_Init()
6353 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0C00); // 172MHz in MHal_CLKGEN_FRC_Init()
6354 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
6355 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
6405 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x000C); // 216 MHz in MHal_CLKGEN_FRC_Init()
6406 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
6407 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0101); // Enable clock in MHal_CLKGEN_FRC_Init()
6410 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0C00); // 216 MHz in MHal_CLKGEN_FRC_Init()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_sc.c6348 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x000C); // 345MHz in MHal_CLKGEN_FRC_Init()
6349 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
6350 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x0001); // Enable clock in MHal_CLKGEN_FRC_Init()
6353 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0C00); // 172MHz in MHal_CLKGEN_FRC_Init()
6354 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
6355 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
6405 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x000C); // 216 MHz in MHal_CLKGEN_FRC_Init()
6406 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
6407 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0101); // Enable clock in MHal_CLKGEN_FRC_Init()
6410 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0C00); // 216 MHz in MHal_CLKGEN_FRC_Init()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmdrv_frc.c524 W2BYTEMSK(L_CLKGEN1(0x35), 0x0004, 0x0004); // clk_idclk_frc in MDrv_XC_SendCmdToFRC()
525 W2BYTEMSK(L_CLKGEN1(0x35), 0x0000, 0x0002); // Not Invert in MDrv_XC_SendCmdToFRC()
526 W2BYTEMSK(L_CLKGEN1(0x35), 0x0000, 0x0001); // Enable clock in MDrv_XC_SendCmdToFRC()
530 W2BYTEMSK(L_CLKGEN1(0x35), 0x0000, 0x0004); // clk_fdclk_frc in MDrv_XC_SendCmdToFRC()
531 W2BYTEMSK(L_CLKGEN1(0x35), 0x0000, 0x0002); // Not Invert in MDrv_XC_SendCmdToFRC()
532 W2BYTEMSK(L_CLKGEN1(0x35), 0x0000, 0x0001); // Enable clock in MDrv_XC_SendCmdToFRC()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_sc.c4062 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0xFFFF); // turn-on clk_mcu_frc in MHal_CLKGEN_FRC_Bypass_Enable()
4064 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x01); // Disable clock in MHal_CLKGEN_FRC_Bypass_Enable()
4071 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0x0C); // 216 MHz in MHal_CLKGEN_FRC_Bypass_Enable()
4072 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0x02); // Not Invert in MHal_CLKGEN_FRC_Bypass_Enable()
4073 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0x01); // Enable clock in MHal_CLKGEN_FRC_Bypass_Enable()
4075 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x1C); // 27 MHz in MHal_CLKGEN_FRC_Bypass_Enable()
4076 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x02); // Not Invert in MHal_CLKGEN_FRC_Bypass_Enable()
4077 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x01); // Enable clock in MHal_CLKGEN_FRC_Bypass_Enable()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_sc.c4198 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0xFFFF); // turn-on clk_mcu_frc in MHal_CLKGEN_FRC_Bypass_Enable()
4200 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x01); // Disable clock in MHal_CLKGEN_FRC_Bypass_Enable()
4207 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0x0C); // 216 MHz in MHal_CLKGEN_FRC_Bypass_Enable()
4208 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0x02); // Not Invert in MHal_CLKGEN_FRC_Bypass_Enable()
4209 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0x01); // Enable clock in MHal_CLKGEN_FRC_Bypass_Enable()
4211 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x1C); // 27 MHz in MHal_CLKGEN_FRC_Bypass_Enable()
4212 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x02); // Not Invert in MHal_CLKGEN_FRC_Bypass_Enable()
4213 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x01); // Enable clock in MHal_CLKGEN_FRC_Bypass_Enable()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A DhalPNL.h197 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A DhalPNL.h197 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A DhalPNL.h205 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A DhalPNL.h207 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A DhalPNL.h198 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A DhalPNL.h207 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A DhalPNL.h195 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A DhalPNL.h195 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A DhalPNL.h200 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A DhalPNL.h193 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A DhalPNL.h205 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_xc_chip_config.h451 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_xc_chip_config.h451 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_xc_chip_config.h577 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_xc_chip_config.h575 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) macro

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