Home
last modified time | relevance | path

Searched refs:INTERN_DVBS_DEMOD_WAIT_TIMEOUT (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBS.c150 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000) macro
2540 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_Config()
5729 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5742 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5817 …}while(((u8Data!=17)||(u8Data2!=0xff))&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));//E_DMD_S2_… in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
5827 if (u16WaitCount>=INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
6236 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_DiSEqC_SendCmd()
6238 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
6290 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)) ; in INTERN_DVBS_DiSEqC_SendCmd()
6292 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBS.c150 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000) macro
2540 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_Config()
5729 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5742 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5817 …}while(((u8Data!=17)||(u8Data2!=0xff))&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));//E_DMD_S2_… in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
5827 if (u16WaitCount>=INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
6236 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_DiSEqC_SendCmd()
6238 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
6290 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)) ; in INTERN_DVBS_DiSEqC_SendCmd()
6292 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DVBS.c150 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000) macro
2385 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_Config()
5574 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5587 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5662 …}while(((u8Data!=17)||(u8Data2!=0xff))&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));//E_DMD_S2_… in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
5672 if (u16WaitCount>=INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
6079 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_DiSEqC_SendCmd()
6081 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
6133 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)) ; in INTERN_DVBS_DiSEqC_SendCmd()
6135 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_DVBS.c150 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000) macro
2528 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_Config()
5717 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5730 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5805 …}while(((u8Data!=17)||(u8Data2!=0xff))&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));//E_DMD_S2_… in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
5815 if (u16WaitCount>=INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
6222 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_DiSEqC_SendCmd()
6224 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
6276 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)) ; in INTERN_DVBS_DiSEqC_SendCmd()
6278 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_DVBS.c150 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000) macro
2528 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_Config()
5717 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5730 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5805 …}while(((u8Data!=17)||(u8Data2!=0xff))&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));//E_DMD_S2_… in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
5815 if (u16WaitCount>=INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
6222 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_DiSEqC_SendCmd()
6224 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
6276 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)) ; in INTERN_DVBS_DiSEqC_SendCmd()
6278 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DVBS.c150 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000) macro
2385 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_Config()
5574 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5587 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5662 …}while(((u8Data!=17)||(u8Data2!=0xff))&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));//E_DMD_S2_… in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
5672 if (u16WaitCount>=INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
6079 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_DiSEqC_SendCmd()
6081 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
6133 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)) ; in INTERN_DVBS_DiSEqC_SendCmd()
6135 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DVBS.c150 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000) macro
2385 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_Config()
5574 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5587 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5662 …}while(((u8Data!=17)||(u8Data2!=0xff))&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));//E_DMD_S2_… in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
5672 if (u16WaitCount>=INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
6079 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_DiSEqC_SendCmd()
6081 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
6133 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)) ; in INTERN_DVBS_DiSEqC_SendCmd()
6135 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_DVBS.c147 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000) macro
2373 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_Config()
5512 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5525 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5604 …}while(((u8Data!=17)||(u8Data2!=0xff))&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));//E_DMD_S2_… in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
5614 if (u16WaitCount>=INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
6016 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_DiSEqC_SendCmd()
6018 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
6070 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)) ; in INTERN_DVBS_DiSEqC_SendCmd()
6072 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_DVBS.c147 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000) macro
2541 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_Config()
5694 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5707 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5782 …}while(((u8Data!=17)||(u8Data2!=0xff))&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));//E_DMD_S2_… in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
5792 if (u16WaitCount>=INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
6194 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_DiSEqC_SendCmd()
6196 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
6248 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)) ; in INTERN_DVBS_DiSEqC_SendCmd()
6250 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBS.c147 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000) macro
2572 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_Config()
5715 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5728 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
5806 …}while(((u8Data!=17)||(u8Data2!=0xff))&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));//E_DMD_S2_… in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
5816 if (u16WaitCount>=INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
6218 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_DiSEqC_SendCmd()
6220 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
6272 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)) ; in INTERN_DVBS_DiSEqC_SendCmd()
6274 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBS.c148 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000) macro
2410 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_Config()
6300 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
6313 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_BlindScan_GetTunerFreq()
6391 …}while(((u8Data!=17)||(u8Data2!=0xff))&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));//E_DMD_S2_… in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
6401 if (u16WaitCount>=INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_BlindScan_WaitCurFreqFinished()
6809 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)); in INTERN_DVBS_DiSEqC_SendCmd()
6811 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
6863 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)) ; in INTERN_DVBS_DiSEqC_SendCmd()
6865 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT) in INTERN_DVBS_DiSEqC_SendCmd()
/utopia/UTPA2-700.0.x/modules/demodulator/drv/demod/
H A DdrvDMD_INTERN_DVBS_v2.c227 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000) macro