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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102 //0312
103
104 #define _INTERN_DVBS_C_
105 #ifdef MSOS_TYPE_LINUX
106 #include <math.h>
107 #endif
108 #include "ULog.h"
109 #include "MsCommon.h"
110 #include "MsIRQ.h"
111 #include "MsOS.h"
112 //#include "apiPWS.h"
113
114 #include "MsTypes.h"
115 #include "drvBDMA.h"
116 //#include "drvIIC.h"
117 //#include "msAPI_Tuner.h"
118 //#include "msAPI_MIU.h"
119 //#include "BinInfo.h"
120 //#include "halVif.h"
121 #include "drvDMD_INTERN_DVBS.h"
122 #include "halDMD_INTERN_DVBS.h"
123 #include "halDMD_INTERN_common.h"
124
125 #include "drvMMIO.h"
126 //#include "TDAG4D01A_SSI_DVBT.c"
127 #include "drvDMD_VD_MBX.h"
128 //-----------------------------------------------------------------------
129 #define BIN_ID_INTERN_DVBS_DEMOD BIN_ID_INTERN_DVBS
130
131 //For DVBS
132 //#define DVBT2FEC_REG_BASE 0x3300
133 #define DVBS2OPPRO_REG_BASE 0x3E00
134 #define TOP_REG_BASE 0x2000 //DMDTOP
135 #define REG_BACKEND 0x1F00//_REG_BACKEND
136 #define DVBSFEC_REG_BASE 0x3F00
137 #define DVBS2FEC_REG_BASE 0x3300
138 #define DVBS2_REG_BASE 0x3A00
139 #define DVBS2_INNER_REG_BASE 0x3B00
140 #define DVBS2_INNER_EXT_REG_BASE 0x3C00
141 #define DVBS2_INNER_EXT2_REG_BASE 0x3D00
142 //#define DVBSTFEC_REG_BASE 0x2300 //DVBTFEC
143 #define FRONTEND_REG_BASE 0x2800
144 #define FRONTENDEXT_REG_BASE 0x2900
145 #define FRONTENDEXT2_REG_BASE 0x2A00
146 #define DMDANA_REG_BASE 0x2E00 //DMDDTOP//reg_dmdana.xls
147 #define DVBTM_REG_BASE 0x3400
148
149 #define SAMPLING_RATE_FS (144000)//(108000)//(96000)
150 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000)
151 #define INTERN_DVBS_TUNER_WAIT_TIMEOUT (50)
152
153 //#define DVBS2_Function (1)
154 //#define MSB131X_ADCPLL_IQ_SWAP 0
155 //#define INTERN_DVBS_TS_DATA_SWAP 0
156
157 //#define MS_DEBUG //enable debug dump
158
159 #ifdef MS_DEBUG
160 #define DBG_INTERN_DVBS(x) x
161 #define DBG_GET_SIGNAL_DVBS(x) x
162 #define DBG_INTERN_DVBS_TIME(x) x
163 #define DBG_INTERN_DVBS_LOCK(x) x
164 #define INTERN_DVBS_INTERNAL_DEBUG 1
165 #else
166 #define DBG_INTERN_DVBS(x) //x
167 #define DBG_GET_SIGNAL_DVBS(x) //x
168 #define DBG_INTERN_DVBS_TIME(x) //x
169 #define DBG_INTERN_DVBS_LOCK(x) //x
170 #define INTERN_DVBS_INTERNAL_DEBUG 0
171 #endif
172 //----------------------------------------------------------
173 #define DBG_DUMP_LOAD_DSP_TIME 0
174
175
176 #define SIGNAL_LEVEL_OFFSET 0.00f
177 #define TAKEOVERPOINT -60.0f
178 #define TAKEOVERRANGE 0.5f
179 #define LOG10_OFFSET -0.21f
180 #define INTERN_DVBS_USE_SAR_3_ENABLE 0
181 //extern MS_U32 msAPI_Timer_GetTime0(void);
182 //#define INTERN_DVBS_GET_TIME msAPI_Timer_GetTime0()
183
184
185 //Debug Info
186 //Lock/Done Flag
187 #define AGC_LOCK 0x28170100
188 #define DAGC0_LOCK 0x283B0001
189 #define DAGC1_LOCK 0x285B0001
190 #define DAGC2_LOCK 0x28620001 //ACIDAGC 1 2
191 #define DAGC3_LOCK 0x286E0001
192 #define DCR_LOCK 0x28220100
193 #define COARSE_SYMBOL_RATE_DONE 0x2A200001 //CSRD 1 2
194 #define FINE_SYMBOL_RATE_DONE 0x2A200008 //FSRD 1 2
195 #define POWER4CFO_DONE 0x29280100 //POWER4CFO 1 2
196 //#define CLOSE_COARSE_CFO_LOCK 0x244E0001
197 #define TR_LOCK 0x3B0E0100 //TR 1 2
198 #define PR_LOCK 0x3B401000
199 #define FRAME_SYNC_ACQUIRE 0x3B300001
200 #define EQ_LOCK 0x3B5A1000
201 #define P_SYNC_LOCK 0x22160002
202 #define IN_SYNC_LOCK 0x3F0D8000
203
204 //AGC / DAGC
205 #define DEBUG_SEL_IF_AGC_GAIN 0x28260003
206 #define DEBUG_SEL_AGC_ERR 0x28260004
207 #define DEBUG_OUT_AGC 0x2828
208
209 #define DEBUG_SEL_DAGC0_GAIN 0x28E80003
210 #define DEBUG_SEL_DAGC0_ERR 0x28E80001
211 #define DEBUG_SEL_DAGC0_PEAK_MEAN 0x28E80005
212 #define DEBUG_OUT_DAGC0 0x2878
213
214 #define DEBUG_SEL_DAGC1_GAIN 0x28E80003//???
215 #define DEBUG_SEL_DAGC1_ERR 0x28E80001
216 #define DEBUG_SEL_DAGC1_PEAK_MEAN 0x28E80005
217 #define DEBUG_OUT_DAGC1 0x28B8
218
219 #define DEBUG_SEL_DAGC2_GAIN 0x28E80003
220 #define DEBUG_SEL_DAGC2_ERR 0x28E80001
221 #define DEBUG_SEL_DAGC2_PEAK_MEAN 0x28E80005
222 #define DEBUG_OUT_DAGC2 0x28C4
223
224 #define DEBUG_SEL_DAGC3_GAIN 0x29DA0003
225 #define DEBUG_SEL_DAGC3_ERR 0x29DA0001
226 #define DEBUG_SEL_DAGC3_PEAK_MEAN 0x29DA0005
227 #define DEBUG_OUT_DAGC3 0x29DC
228
229 #define INNER_DEBUG_SEL_TR 0x24080D00 //TR
230 #define DEBUG_SEL_TR_SFO_CONVERGE 0x24080B00
231 #define DEBUG_SEL_TR_INPUT 0x24080F00
232
233 #define FRONTEND_FREEZE_DUMP 0x27028000
234 #define INNER_FREEZE_DUMP 0x24080010
235
236 #define DCR_OFFSET 0x2740
237 #define INNER_DEBUG_SEL 0x2408
238 #define INNEREXT_FINEFE_DBG_OUT0 0x2550
239 #define INNEREXT_FINEFE_DBG_OUT2 0x2552
240 #define INNEREXT_FINEFE_KI_FF0 0x2556
241 #define INNEREXT_FINEFE_KI_FF2 0x2558
242 #define INNEREXT_FINEFE_KI_FF4 0x255A
243 #define INNER_PR_DEBUG_OUT0 0x2486
244 #define INNER_PR_DEBUG_OUT2 0x2488
245
246 #define IIS_COUNT0 0x2746
247 #define IIS_COUNT2 0x2748
248 #define IQB_PHASE 0x2766
249 #define IQB_GAIN 0x2768
250 #define TR_INDICATOR_FF0 0x2454
251 #define TR_INDICATOR_FF2 0x2456
252 #define INNER_TR_LOPF_VALUE_DEBUG0 0x2444
253 #define INNER_TR_LOPF_VALUE_DEBUG2 0x2446
254 #define INNER_TR_LOPF_VALUE_DEBUG4 0x2448
255 //------------------------------------------------------------
256 //Init Mailbox parameter.
257 #define INTERN_DVBS_TS_SERIAL_INVERSION 0
258 //For Parameter Init Setting
259 #define A_S2_ZIF_EN 0x01 //[0]
260 #define A_S2_RF_AGC_EN 0x00 //[0]
261 #define A_S2_DCR_EN 0x00 //[0] 0=Auto :1=Force
262 #define A_S2_IQB_EN 0x01 //[2]
263 #define A_S2_IIS_EN 0x00 //[0]
264 #define A_S2_CCI_EN 0x00 //[0] 0:1=Enable
265 #define A_S2_FORCE_ACI_SELECT 0xFF //[3:0] 0xFF=OFF(internal default)
266 #define A_S2_IQ_SWAP 0x01 //[0]
267 #define A_S2_AGC_REF_EXT_0 0x00 //[7:0] //0x00 0x90
268 #define A_S2_AGC_REF_EXT_1 0x02 //[11:8] //0x02 0x07
269 #define A_S2_AGC_K 0x07 //[15:12]
270 #define A_S2_ADCI_GAIN 0x0F //[4:0]
271 #define A_S2_ADCQ_GAIN 0x0F //[12:8]
272 #define A_S2_SRD_SIG_SRCH_RNG 0x6A //[7:0]
273 #define A_S2_SRD_DC_EXC_RNG 0x16 //[7:0]
274 //FRONTENDEXT_SRD_FRC_CFO
275 #define A_S2_FORCE_CFO_0 0x00 //[7:0]
276 #define A_S2_FORCE_CFO_1 0x00 //[11:8]
277 #define A_S2_DECIMATION_NUM 0x00 //[3:0] 00=(Internal Default)
278 #define A_S2_PSD_SMTH_TAP 0x29 //[6:0] Bit7 no define.
279 //CCI Parameter
280 //Set_Tuner_BW=(((U16)REG_BASE[DIG_SWUSE1FH]<<8)|REG_BASE[DIG_SWUSE1FL]);
281 #define A_S2_CCI_FREQN_0_L 0x00 //[7:0]
282 #define A_S2_CCI_FREQN_0_H 0x00 //[11:8]
283 #define A_S2_CCI_FREQN_1_L 0x00 //[7:0]
284 #define A_S2_CCI_FREQN_1_H 0x00 //[11:8]
285 #define A_S2_CCI_FREQN_2_L 0x00 //[7:0]
286 #define A_S2_CCI_FREQN_2_H 0x00 //[11:8]
287 //Inner TR Parameter
288 #define A_S2_TR_LOPF_KP 0x00 //[4:0] 00=(Internal Default)
289 #define A_S2_TR_LOPF_KI 0x00 //[4:0] 00=(Internal Default)
290 //Inner FineFE Parameter
291 #define A_S2_FINEFE_KI_SWITCH_0 0x00 //[15:12] 00=(Internal Default)
292 #define A_S2_FINEFE_KI_SWITCH_1 0x00 //[3:0] 00=(Internal Default)
293 #define A_S2_FINEFE_KI_SWITCH_2 0x00 //[7:4] 00=(Internal Default)
294 #define A_S2_FINEFE_KI_SWITCH_3 0x00 //[11:8] 00=(Internal Default)
295 #define A_S2_FINEFE_KI_SWITCH_4 0x00 //[15:12] 00=(Internal Default)
296 //Inner PR KP Parameter
297 #define A_S2_PR_KP_SWITCH_0 0x00 //[11:8] 00=(Internal Default)
298 #define A_S2_PR_KP_SWITCH_1 0x00 //[15:12] 00=(Internal Default)
299 #define A_S2_PR_KP_SWITCH_2 0x00 //[3:0] 00=(Internal Default)
300 #define A_S2_PR_KP_SWITCH_3 0x00 //[7:4] 00=(Internal Default)
301 #define A_S2_PR_KP_SWITCH_4 0x00 //[11:8] 00=(Internal Default)
302 //Inner FS Parameter
303 #define A_S2_FS_GAMMA 0x10 //[7:0]
304 #define A_S2_FS_ALPHA0 0x10 //[7:0]
305 #define A_S2_FS_ALPHA1 0x10 //[7:0]
306 #define A_S2_FS_ALPHA2 0x10 //[7:0]
307 #define A_S2_FS_ALPHA3 0x10 //[7:0]
308
309 #define A_S2_FS_H_MODE_SEL 0x01 //[0]
310 #define A_S2_FS_OBSWIN 0x08 //[12:8]
311 #define A_S2_FS_PEAK_DET_TH_L 0x00 //[7:0]
312 #define A_S2_FS_PEAK_DET_TH_H 0x01 //[15:8]
313 #define A_S2_FS_CONFIRM_NUM 0x01 //[3:0]
314 //Inner EQ Parameter
315 #define A_S2_EQ_MU_FFE_DA 0x00 //[3:0] 00=(Internal Default)
316 #define A_S2_EQ_MU_FFE_DD 0x00 //[7:4] 00=(Internal Default)
317 #define A_S2_EQ_ALPHA_SNR_DA 0x00 //[7:4] 00=(Internal Default)
318 #define A_S2_EQ_ALPHA_SNR_DD 0x00 //[11:8] 00=(Internal Default)
319 //Outer FEC Parameter
320 #define A_S2_FEC_ALFA 0x00 //[12:8]
321 #define A_S2_FEC_BETA 0x01 //[7:4]
322 #define A_S2_FEC_SCALING_LLR 0x00 //[7:0] 00=(Internal Default)
323 //TS Parameter
324 #if INTERN_DVBS_TS_SERIAL_INVERSION
325 #define A_S2_TS_SERIAL 0x01 //[0]
326 #else
327 #define A_S2_TS_SERIAL 0x00 //[0]
328 #endif
329 #define A_S2_TS_CLK_RATE 0x00
330 #define A_S2_TS_OUT_INV 0x00 //[5]
331 #define A_S2_TS_DATA_SWAP 0x00 //[5]
332 //Rev Parameter
333
334 #define A_S2_FW_VERSION_L 0x00 //From FW
335 #define A_S2_FW_VERSION_H 0x00 //From FW
336 #define A_S2_CHIP_VERSION 0x01
337 #define A_S2_FS_L 0x00
338 #define A_S2_FS_H 0x00
339 #define A_S2_MANUAL_TUNE_SYMBOLRATE_L 0x20
340 #define A_S2_MANUAL_TUNE_SYMBOLRATE_H 0x4E
341
342 MS_U8 INTERN_DVBS_DSPREG[] =
343 {
344 A_S2_ZIF_EN, A_S2_RF_AGC_EN, A_S2_DCR_EN, A_S2_IQB_EN, A_S2_IIS_EN, A_S2_CCI_EN, A_S2_FORCE_ACI_SELECT, A_S2_IQ_SWAP, // 00H ~ 07H
345 A_S2_AGC_REF_EXT_0, A_S2_AGC_REF_EXT_1, A_S2_AGC_K, A_S2_ADCI_GAIN, A_S2_ADCQ_GAIN, A_S2_SRD_SIG_SRCH_RNG, A_S2_SRD_DC_EXC_RNG, A_S2_FORCE_CFO_0, // 08H ~ 0FH
346 A_S2_FORCE_CFO_1, A_S2_DECIMATION_NUM, A_S2_PSD_SMTH_TAP, A_S2_CCI_FREQN_0_L, A_S2_CCI_FREQN_0_H, A_S2_CCI_FREQN_1_L, A_S2_CCI_FREQN_1_H, A_S2_CCI_FREQN_2_L, // 10H ~ 17H
347 A_S2_CCI_FREQN_2_H, A_S2_TR_LOPF_KP, A_S2_TR_LOPF_KI, A_S2_FINEFE_KI_SWITCH_0, A_S2_FINEFE_KI_SWITCH_1, A_S2_FINEFE_KI_SWITCH_2, A_S2_FINEFE_KI_SWITCH_3, A_S2_FINEFE_KI_SWITCH_4, // 18H ~ 1FH
348 A_S2_PR_KP_SWITCH_0, A_S2_PR_KP_SWITCH_1, A_S2_PR_KP_SWITCH_2, A_S2_PR_KP_SWITCH_3, A_S2_PR_KP_SWITCH_4, A_S2_FS_GAMMA, A_S2_FS_ALPHA0, A_S2_FS_ALPHA1, // 20H ~ 27H
349 A_S2_FS_ALPHA2, A_S2_FS_ALPHA3, A_S2_FS_H_MODE_SEL, A_S2_FS_OBSWIN, A_S2_FS_PEAK_DET_TH_L, A_S2_FS_PEAK_DET_TH_H, A_S2_FS_CONFIRM_NUM, A_S2_EQ_MU_FFE_DA, // 28h ~ 2FH
350 A_S2_EQ_MU_FFE_DD, A_S2_EQ_ALPHA_SNR_DA, A_S2_EQ_ALPHA_SNR_DD, A_S2_FEC_ALFA, A_S2_FEC_BETA, A_S2_FEC_SCALING_LLR, A_S2_TS_SERIAL, A_S2_TS_CLK_RATE, // 30H ~ 37H
351 A_S2_TS_OUT_INV, A_S2_TS_DATA_SWAP, A_S2_FW_VERSION_L, A_S2_FW_VERSION_H, A_S2_CHIP_VERSION, A_S2_FS_L, A_S2_FS_H, A_S2_MANUAL_TUNE_SYMBOLRATE_L, // 38H ~ 3CH
352 A_S2_MANUAL_TUNE_SYMBOLRATE_H,
353 };
354
355 /****************************************************************
356 *Local Variables *
357 ****************************************************************/
358
359 /*
360 static MS_U16 _u16SignalLevel[185][2]=
361 {//AV2028 SR=22M, 2/3 CN=5.9
362 {32100, 920},{32200, 915},{32350, 910},{32390, 905},{32480, 900},{32550, 895},{32620, 890},{32680, 885},{32750, 880},{32830, 875},
363 {32930, 870},{33010, 865},{33100, 860},{33200, 855},{33310, 850},{33410, 845},{33520, 840},{33640, 835},{33770, 830},{33900, 825},
364 {34030, 820},{34150, 815},{34290, 810},{34390, 805},{34490, 800},{34580, 795},{34700, 790},{34800, 785},{34880, 780},{34940, 775},
365 {35030, 770},{35130, 765},{35180, 760},{35260, 755},{35310, 750},{35340, 745},{35380, 740},{35400, 735},{35450, 730},{35550, 725},
366 {35620, 720},{35700, 715},{35800, 710},{35890, 705},{36000, 700},{36120, 695},{36180, 690},{36280, 685},{36400, 680},{36570, 675},
367 {36730, 670},{36910, 665},{37060, 660},{37100, 655},{37260, 650},{37340, 645},{37410, 640},{37580, 635},{37670, 630},{37700, 625},
368 {37750, 620},{37800, 615},{37860, 610},{37980, 605},{38050, 600},{38170, 595},{38370, 590},{38540, 585},{38710, 580},{38870, 575},
369 {39020, 570},{39070, 565},{39100, 560},{39180, 555},{39280, 550},{39460, 545},{39510, 540},{39600, 535},{39620, 530},{39680, 525},
370 {39720, 520},{39830, 515},{39880, 510},{39930, 505},{39960, 500},{40000, 495},{40200, 490},{40360, 485},{40540, 480},{40730, 475},
371 {40880, 470},{41020, 465},{41150, 460},{41280, 455},{41410, 450},{41520, 445},{41620, 440},{41730, 435},{41840, 430},{41930, 425},
372 {42010, 420},{42100, 415},{42180, 410},{42260, 405},{42350, 400},{42440, 395},{42520, 390},{42580, 385},{42660, 380},{42730, 375},
373 {42800, 370},{42870, 365},{42940, 360},{43000, 355},{43060, 350},{43130, 345},{43180, 340},{43250, 335},{43310, 330},{43370, 325},
374 {43420, 320},{43460, 315},{43520, 310},{43570, 305},{43620, 300},{43660, 295},{43710, 290},{43750, 285},{43810, 280},{43860, 275},
375 {43910, 270},{43940, 265},{43990, 260},{44020, 255},{44060, 250},{44110, 245},{44140, 240},{44190, 235},{44230, 230},{44270, 225},
376 {44320, 220},{44370, 215},{44400, 210},{44450, 205},{44490, 200},{44530, 195},{44590, 190},{44630, 185},{44660, 180},{44720, 175},
377 {44750, 170},{44790, 165},{44830, 160},{44880, 155},{44910, 150},{44960, 145},{45000, 140},{45030, 135},{45070, 130},{45100, 125},
378 {45130, 120},{45160, 115},{45200, 110},{45240, 105},{45270, 100},{45300, 95},{45330, 90},{45360, 85},{45400, 80},{45430, 75},
379 {45460, 70},{45490, 65},{45530, 60},{45560, 55},{45590, 50},{45630, 45},{45670, 40},{45690, 35},{45740, 30},{45760, 25},
380 {45800, 20},{45830, 15},{45860, 10},{45880, 5},{45920, 0}
381 };
382 */
383 MS_U8 u8DemodLockFlag;
384 MS_U8 modulation_order;
385 MS_BOOL _bDemodType=FALSE;//DVBS:FALSE ; S2:TRUE
386 //static MS_BOOL TPSLock = 0;
387 static MS_U32 u32ChkScanTimeStartDVBS = 0;
388 MS_U8 g_dvbs_lock = 0;
389 //static float intern_dvb_s_qam_ref[] = {3.0, 0.0, 0.0, 0.0, 0.0, 80.0}; //16q,32q,64q,128q,256q, and others
390 static MS_U8 _u8_DVBS2_CurrentCodeRate;
391 static MS_U8 _u8ToneBurstFlag=0;
392
393 //static float _fPostBer=0;
394 //static float _f_DVBS_CurrentSNR=0;
395 static MS_U16 _u16BlindScanStartFreq=0;
396 static MS_U16 _u16BlindScanEndFreq=0;
397 static MS_U16 _u16TunerCenterFreq=0;
398 MS_U16 _u16ChannelInfoIndex=0;
399 //Debug Only+
400 static MS_U16 _u16NextCenterFreq=0;
401 MS_U16 _u16LockedSymbolRate=0;
402 MS_U16 _u16LockedCenterFreq=0;
403 static MS_U16 _u16PreLockedHB=0;
404 static MS_U16 _u16PreLockedLB=0;
405 static MS_U16 _u16CurrentSymbolRate=0;
406 MS_S16 _s16CurrentCFO=0;
407 static MS_U16 _u16CurrentStepSize=0;
408 //Debug Only-
409 MS_U16 _u16ChannelInfoArray[2][1000];
410
411 //static MS_U32 _u32CurrentSR=0;
412 static MS_BOOL _bSerialTS=FALSE;
413 static MS_BOOL _bTSDataSwap=FALSE;
414
415 //Global Variables
416 S_CMDPKTREG gsCmdPacketDVBS;
417 //MS_U8 gCalIdacCh0, gCalIdacCh1;
418 static MS_BOOL bDMD_DVBS_NoChannelDetectedWithRFPower = FALSE;
419 static MS_U32 u32DMD_DVBS_NoChannelTimeAccWithRFPower = 0;
420 extern MS_U32 u32DMD_DVBS2_DJB_START_ADDR;
421 #ifdef INTERN_DVBS_LOAD_FW_FROM_CODE_MEMORY
422 MS_U8 INTERN_DVBS_table[] =
423 {
424 #include "fwDMD_INTERN_DVBS.dat"
425 };
426
427 #endif
428
429 MS_BOOL INTERN_DVBS_Show_Demod_Version(void);
430 MS_BOOL INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE *pQAMMode);
431 MS_BOOL INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE *pDemodType);
432 MS_BOOL INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE *pCodeRate);
433 MS_BOOL INTERN_DVBS_GetCurrentSymbolRate(MS_U32 *u32SymbolRate);
434 MS_BOOL INTERN_DVBS_GetCurrentSymbolRateOffset(MS_U16 *pData);
435
436 #if (INTERN_DVBS_INTERNAL_DEBUG)
437 void INTERN_DVBS_info(void);
438 MS_BOOL INTERN_DVBS_Show_AGC_Info(void);
439 #endif
440
441 //------------------------------------------------------------------
442 // System Info Function
443 //------------------------------------------------------------------
444 //=====================================================================================
INTERN_DVBS_DSPReg_Init(const MS_U8 * u8DVBS_DSPReg,MS_U8 u8Size)445 MS_U16 INTERN_DVBS_DSPReg_Init(const MS_U8 *u8DVBS_DSPReg, MS_U8 u8Size)
446 {
447 #if 0
448 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
449 #endif
450 MS_U8 status = true;
451 #if 0
452 MS_U16 u16DspAddr = 0;
453 #endif
454 DBG_INTERN_DVBS(printf("INTERN_DVBS_DSPReg_Init\n"));
455
456 #if 0//def MS_DEBUG
457 {
458 MS_U8 u8buffer[256];
459 printf("INTERN_DVBS_DSPReg_Init Reset\n");
460 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
461 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, 0);
462
463 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
464 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
465 printf("INTERN_DVBS_DSPReg_Init ReadBack, should be all 0\n");
466 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
467 printf("%x ", u8buffer[idx]);
468 printf("\n");
469
470 printf("INTERN_DVBS_DSPReg_Init Value\n");
471 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
472 printf("%x ", INTERN_DVBS_DSPREG[idx]);
473 printf("\n");
474 }
475 #endif
476
477 //for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
478 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBS_DSPREG[idx]);
479
480 // readback to confirm.
481 // ~read this to check mailbox initial values
482 #if 0
483 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
484 {
485 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &u8RegRead);
486 if (u8RegRead != INTERN_DVBS_DSPREG[idx])
487 {
488 DBG_INTERN_DVBS(printf("[Error]INTERN_DVBS_DSPReg_Init, idx=%d, drv_val=0x%x, firmware_val=0x%x\n",idx,INTERN_DVBS_DSPREG[idx],u8RegRead));
489 }
490 }
491 #endif
492 #if 0
493 if (u8DVBS_DSPReg != NULL)
494 {
495 if (1 == u8DVBS_DSPReg[0])
496 {
497 u8DVBS_DSPReg+=2;
498 for (idx = 0; idx<u8Size; idx++)
499 {
500 u16DspAddr = *u8DVBS_DSPReg;
501 u8DVBS_DSPReg++;
502 u16DspAddr = (u16DspAddr) + ((*u8DVBS_DSPReg)<<8);
503 u8DVBS_DSPReg++;
504 u8Mask = *u8DVBS_DSPReg;
505 u8DVBS_DSPReg++;
506 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
507 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBS_DSPReg) & (u8Mask));
508 u8DVBS_DSPReg++;
509 DBG_INTERN_DVBS(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
510 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
511 }
512 }
513 else
514 {
515 DBG_INTERN_DVBS(printf("FATAL: parameter version incorrect\n"));
516 }
517 }
518 #endif
519 #if 0//def MS_DEBUG
520 {
521 MS_U8 u8buffer[256];
522 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
523 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
524 printf("INTERN_DVBC_DSPReg_Init ReadBack\n");
525 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
526 printf("%x ", u8buffer[idx]);
527 printf("\n");
528 }
529 #endif
530
531 #if 0//def MS_DEBUG
532 {
533 MS_U8 u8buffer[256];
534 for (idx = 0; idx<128; idx++)
535 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2380+idx, &(u8buffer[idx]));
536 printf("INTERN_DVBS_DSPReg_Init ReadReg 0x2000~0x207F\n");
537 for (idx = 0; idx<128; idx++)
538 {
539 printf("%x ", u8buffer[idx]);
540 if ((idx & 0xF) == 0xF) printf("\n");
541 }
542 printf("\n");
543 }
544 #endif
545 return status;
546 }
547
548 /***********************************************************************************
549 Subject: Command Packet Interface
550 Function: INTERN_DVBS_Cmd_Packet_Send
551 Parmeter:
552 Return: MS_BOOL
553 Remark:
554 ************************************************************************************/
INTERN_DVBS_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)555 MS_BOOL INTERN_DVBS_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
556 {
557 MS_U8 status = true, indx;
558 MS_U8 reg_val, timeout = 0;
559 return true;
560
561 // ==== Command Phase ===================
562 DBG_INTERN_DVBS(ULOGD("DEMOD","--->INTERN_DVBS (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
563 pCmdPacket->param[0],pCmdPacket->param[1],
564 pCmdPacket->param[2],pCmdPacket->param[3],
565 pCmdPacket->param[4],pCmdPacket->param[5] ));
566
567 // wait _BIT_END clear
568 do
569 {
570 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
571 if((reg_val & _BIT_END) != _BIT_END)
572 {
573 break;
574 }
575 MsOS_DelayTask(5);
576 if (timeout > 200)
577 {
578 DBG_INTERN_DVBS(ULOGD("DEMOD","---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n"));
579 return false;
580 }
581 timeout++;
582 } while (1);
583
584 // set cmd_3:0 and _BIT_START
585 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
586 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
587 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
588
589
590 //DBG_INTERN_DVBS(printf("demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
591 // wait _BIT_START clear
592 do
593 {
594 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
595 if((reg_val & _BIT_START) != _BIT_START)
596 {
597 break;
598 }
599 MsOS_DelayTask(10);
600 if (timeout > 200)
601 {
602 DBG_INTERN_DVBS(ULOGD("DEMOD","---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n"));
603 return false;
604 }
605 timeout++;
606 } while (1);
607
608 // ==== Data Phase ======================
609
610 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
611
612 for (indx = 0; indx < param_cnt; indx++)
613 {
614 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
615 //DBG_INTERN_DVBS(printf("demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
616
617 // set param[indx] and _BIT_DRQ
618 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
619 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
620 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
621
622 // wait _BIT_DRQ clear
623 do
624 {
625 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
626 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
627 {
628 break;
629 }
630 MsOS_DelayTask(5);
631 if (timeout > 200)
632 {
633 DBG_INTERN_DVBS(ULOGD("DEMOD","---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n"));
634 return false;
635 }
636 timeout++;
637 } while (1);
638 }
639
640 // ==== End Phase =======================
641
642 // set _BIT_END to finish command
643 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
644 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
645
646 return status;
647 }
648
649 /***********************************************************************************
650 Subject: Command Packet Interface
651 Function: INTERN_DVBS_Cmd_Packet_Exe_Check
652 Parmeter:
653 Return: MS_BOOL
654 Remark:
655 ************************************************************************************/
INTERN_DVBS_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)656 MS_BOOL INTERN_DVBS_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
657 {
658 return TRUE;
659 }
660
661 /***********************************************************************************
662 Subject: SoftStop
663 Function: INTERN_DVBS_SoftStop
664 Parmeter:
665 Return: MS_BOOL
666 Remark:
667 ************************************************************************************/
INTERN_DVBS_SoftStop(void)668 MS_BOOL INTERN_DVBS_SoftStop ( void )
669 {
670 #if 1
671 MS_U16 u16WaitCnt=0;
672
673 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
674 {
675 DBG_INTERN_DVBS(ULOGD("DEMOD",">> MB Busy!\n"));
676 return FALSE;
677 }
678
679 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
680
681 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
682 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
683
684 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
685 {
686 if (u16WaitCnt++ >= 0xFFF)// 0xFF)
687 {
688 DBG_INTERN_DVBS(ULOGD("DEMOD",">> DVBT SoftStop Fail!\n"));
689 return FALSE;
690 }
691 }
692
693 //HAL_DMD_RIU_WriteByte(0x103460, 0x01); // reset VD_MCU
694 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
695 #endif
696 return TRUE;
697 }
698
699 /***********************************************************************************
700 Subject: Reset
701 Function: INTERN_DVBC_Reset
702 Parmeter:
703 Return: MS_BOOL
704 Remark:
705 ************************************************************************************/
706 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
707
INTERN_DVBS_Reset(void)708 MS_BOOL INTERN_DVBS_Reset ( void )// no midify
709 {
710 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_reset\n"));
711
712 DBG_INTERN_DVBS_TIME(ULOGD("DEMOD","INTERN_DVBS_Reset, t = %d\n",MsOS_GetSystemTime()));
713
714 //INTERN_DVBS_SoftStop();
715
716
717 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
718
719 MsOS_DelayTask(1);
720 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
721
722 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
723 MsOS_DelayTask(5);
724
725 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
726 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
727
728 u32ChkScanTimeStartDVBS = MsOS_GetSystemTime();
729 g_dvbs_lock = 0;
730
731 return TRUE;
732 }
INTERN_DVBS_PowerSaving(void)733 MS_BOOL INTERN_DVBS_PowerSaving ( void )
734 {
735 MS_U8 i;
736
737 //---P2=0---/;
738 for( i = 0; i < 231; i++){
739 MDrv_SYS_DMD_VD_MBX_WriteReg(0x350A + i, 0x11);}
740 // `M3_RIU_W((`RIUBASE_DMD_CLKGEN>>1)+7'h40, 2'b01, 16'h0000);
741 MDrv_SYS_DMD_VD_MBX_WriteReg(0x3580, 0x00);
742
743 //---P2=1---/;
744 for( i = 0; i < 146; i++){
745 MDrv_SYS_DMD_VD_MBX_WriteReg(0xA202 + i, 0x11);}
746 // `M3_RIU_W((`RIUBASE_DMD_CLKGEN_EXT>>1)+7'h14, 2'b01, 16'h0003);
747 MDrv_SYS_DMD_VD_MBX_WriteReg(0xA228, 0x03);
748
749 // ================================================================
750 // DEMOD_1 CLOCK GATED
751 // ================================================================
752 //---P2=0---/;
753 for( i = 0; i <= 177; i++){
754 MDrv_SYS_DMD_VD_MBX_WriteReg(0x3635+ i, 0x11);}
755 // `M3_RIU_W((`RIUBASE_DMD_CLKGEN_1>>1)+7'h1b, 2'b01, 16'h000f);
756 MDrv_SYS_DMD_VD_MBX_WriteReg(0x3636, 0x0f);
757
758
759 // ================================================================
760 // SRAM Power Down
761 // ================================================================
762 // [ 0]reg_force_allsram_on = 1'b0
763 // [ 1]reg_force_allsram_on_demod_1 = 1'b0
764 // [ 2] = 1'b0
765 // [ 3]reg_demod_1_sram_sd_en = 1'b0
766 // [ 4]reg_manhattan_sram_share_sram_sd_en = 1'b0
767 // [ 5]reg_mulan_sram_share_sram_sd_en = 1'b0
768 // [ 6]reg_dvb_frontend_sram_sd_en = 1'b0
769 // [ 7]reg_dtmb_sram_sd_en = 1'b0
770 // [ 8]reg_dvbt_sram_sd_en = 1'b0
771 // [ 9]reg_atsc_sram_sd_en = 1'b0
772 // [10]reg_vif_sram_sd_en = 1'b0
773 // [11]reg_backend_sram_sd_en = 1'b0
774 // [12]reg_adcdma_sram_sd_en = 1'b0
775 // [13]reg_isdbt_sram_sd_en = 1'b0
776 // [14]reg_dvbt2_sram_sd_en = 1'b0
777 // [15]reg_dvbs2_sram_sd_en = 1'b0
778 // `M3_RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h48, 2'b11, 16'hfffc);
779 // `M3_RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h48, 2'b11, 16'hfffc);
780 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2091, 0xff);
781 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2090, 0xfc);
782
783 // all controlled by reg_mulan_sram_share_sram_sd_en
784 // reg_sram_pwr_ctrl_sel[15:0]
785 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h70, 2'b11, 16'h0000);
786 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h70, 2'b11, 16'h0000);
787 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e1, 0x00);
788 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e0, 0x00);
789 // reg_sram_pwr_ctrl_sel[31:16]
790 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h71, 2'b11, 16'h0000);
791 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h71, 2'b11, 16'h0000);
792 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e3, 0x00);
793 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e2, 0x00);
794 // reg_sram_pwr_ctrl_sel[47:32]
795 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h72, 2'b11, 16'h0000);
796 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h72, 2'b11, 16'h0000);
797 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e5, 0x00);
798 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e4, 0x00);
799 // reg_sram_pwr_ctrl_sel[63:48]
800 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h73, 2'b11, 16'h0000);
801 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h73, 2'b11, 16'h0000);
802 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e7, 0x00);
803 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e6, 0x00);
804 // reg_sram_pwr_ctrl_sel[79:64]
805 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h74, 2'b11, 16'h0000);
806 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h74, 2'b11, 16'h0000);
807 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e9, 0x00);
808 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e8, 0x00);
809
810 // $display("================================================================");
811 // $display("Reset");
812 // $display("================================================================");
813 // Release DVBT2 & dmd_ana_misc Reset
814 // [0] reg_atsc_on[0]
815 // [1] reg_dvbt_on[1]
816 // [2] reg_vif_on[2]
817 // [3] reg_isdbt_on[3]
818 // [4] reg_atsc_rst[4]
819 // [5] reg_dvbt_rst[5]
820 // [6] reg_vif_rst[6]
821 // [7] reg_get_adc[7]
822 // [8] reg_ce8x_gate[8]
823 // [9] reg_ce_gate[9]
824 // [10] reg_dac_clk_inv[10]
825 // [11] reg_vdmcu_clock_faster[11]
826 // [12] reg_vif_if_agc_sel[12]
827 // [13] reg_dmd_ana_misc_rst[13]
828 // [14] reg_adcd_wmask[14]
829 // [15] reg_sif_only[15]
830 // `M3_RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h01, 2'b11, 16'h2070);
831
832 // Release DTMB Reset & Enable Manhattan frontend Enable
833 // [0] reg_dtmb_on
834 // [1] reg_dtmb_rst
835 // [4] reg_manhattan_frontend_on //No used @ Maserati
836 // [5] reg_manhattan_dvb_srd_sw_rst (1'b1 for DTMB)
837 // `M3_RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h02, 2'b01, 16'h0022);
838
839 // ================================================================
840 // MPLL Power Down
841 // ================================================================
842 // Set MPLL_ADC_DIV_SE
843 // [0] : reg_mpll_adc_clk_cc_en
844 // [1] : reg_adc_clk_pd
845 // [2] : reg_mpll_div2_pd
846 // [3] : reg_mpll_div3_pd
847 // [4] : reg_mpll_div4_pd
848 // [5] : reg_mpll_div8_pd
849 // [6] : reg_mpll_div10_pd
850 // [7] : reg_mpll_div17_pd
851 // [13:8]: reg_mpll_adc_div_sel
852 // `M3_RIU_W((`RIUBASE_DMD_ANA_MISC_M3>>1)+7'h30, 2'b01, 16'h12fe);//Different
853 // `M3_RIU_W((`RIUBASE_DMD_ANA_MISC_M3>>1)+7'h30, 2'b01, 16'h12fe);//Different
854 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2e60, 0xfe);
855
856 // [2:0] : reg_mpll_ictrl set 3'h3
857 // [3] : reg_mpll_in_sel set 1'h0
858 // [4] : reg_mpll_xtal2adc_sel if 1'h1 ADC_CLK=XTAL.
859 // [5] : reg_mpll_xtal2next_pll_sel
860 // [6] : reg_mpll_vco_offset(T8), reg_mpll_adc_clk_cc_mode(T9)
861 // [7] : reg_mpll_pd set 1'b1
862 // [8] : reg_xtal_en set 1'b0
863 // [10:9]: reg_xtal_sel set 2'h3 XTAL strength
864 // [11] : reg_mpll_porst set 1'b1
865 // [12] : reg_mpll_reset set 1'b1
866 // [13] : reg_pd_dmpll_clk XTAL to MPLL clock reference power down
867 // [14] : reg_mpll_pdiv_clk_pd set 1'b0
868 // Set MPLL_RESET=MPLL_PORST=1
869 // `M3_RIU_W((`RIUBASE_DMD_ANA_MISC_M3>>1)+7'h35, 2'b11, 16'h1e83);//Different
870 // `M3_RIU_W((`RIUBASE_DMD_ANA_MISC_M3>>1)+7'h35, 2'b11, 16'h1e83);//Different
871 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2e6b, 0x1e);
872 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2e6a, 0x83);
873
874 return TRUE;
875 }
876 /***********************************************************************************
877 Subject: Exit
878 Function: INTERN_DVBC_Exit
879 Parmeter:
880 Return: MS_BOOL
881 Remark:
882 ************************************************************************************/
INTERN_DVBS_Exit(void)883 MS_BOOL INTERN_DVBS_Exit ( void )
884 {
885 MS_U8 u8Data=0;
886 MS_U8 u8Data_temp=0;
887
888 u8Data_temp=HAL_DMD_RIU_ReadByte(0x101E39);
889 HAL_DMD_RIU_WriteByte(0x101E39, 0);
890
891 u8Data=HAL_DMD_RIU_ReadByte(0x1128C0);
892 u8Data&=~(0x02);
893 HAL_DMD_RIU_WriteByte(0x1128C0, u8Data);//revert IQ Swap status
894
895 HAL_DMD_RIU_WriteByte(0x101E39, u8Data_temp);
896 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_Exit\n"));
897 INTERN_DVBS_SoftStop();
898 INTERN_DVBS_PowerSaving();
899
900 return TRUE;
901 }
902
903 /***********************************************************************************
904 Subject: Load DSP code to chip
905 Function: INTERN_DVBS_LoadDSPCode
906 Parmeter:
907 Return: MS_BOOL
908 Remark:
909 ************************************************************************************/
INTERN_DVBS_LoadDSPCode(void)910 static MS_BOOL INTERN_DVBS_LoadDSPCode(void)
911 {
912 MS_U8 udata = 0x00;
913 MS_U16 i;
914 MS_U16 fail_cnt=0;
915
916 #if (DBG_DUMP_LOAD_DSP_TIME==1)
917 MS_U32 u32Time;
918 #endif
919
920 //MDrv_Sys_DisableWatchDog();
921 /*
922 HAL_DMD_RIU_WriteByte(0x103480, 0x01);//reference GUI//reset
923 HAL_DMD_RIU_WriteByte(0x103481, 0x00);
924 HAL_DMD_RIU_WriteByte(0x103480, 0x00);
925 HAL_DMD_RIU_WriteByte(0x103483, 0x50);
926 HAL_DMD_RIU_WriteByte(0x103483, 0x51);
927 HAL_DMD_RIU_WriteByte(0x103484, 0x00);
928 HAL_DMD_RIU_WriteByte(0x103485, 0x00);
929 */
930 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
931 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
932 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
933 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
934 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
935 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
936
937 //// Load code thru VDMCU_IF ////
938 DBG_INTERN_DVBS(printf(">Load Code.....\n"));
939 for ( i = 0; i < sizeof(INTERN_DVBS_table); i++)
940 {
941 HAL_DMD_RIU_WriteByte(0x10348C, INTERN_DVBS_table[i]);
942 //HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBS_table[i]); // write data to VD MCU 51 code sram
943 }
944
945 //// Content verification ////
946 DBG_INTERN_DVBS(ULOGD("DEMOD",">Verify Code...\n"));
947
948 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
949 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
950
951 for ( i = 0; i < sizeof(INTERN_DVBS_table); i++)
952 {
953 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
954 if (udata != INTERN_DVBS_table[i])
955 {
956 ULOGD("DEMOD",">fail add = 0x%x\n", i);
957 ULOGD("DEMOD",">code = 0x%x\n", INTERN_DVBS_table[i]);
958 ULOGD("DEMOD",">data = 0x%x\n", udata);
959
960 if (fail_cnt > 10)
961 {
962 ULOGD("DEMOD",">DVB-S DSP Loadcode fail!");
963 return false;
964 }
965 fail_cnt++;
966 }
967 }
968
969 #if 0 //use for Kris DJB with VCM
970 //====================================================================
971 // add S2 DRAM bufer start address into fixed location
972 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x30); // sram address low byte; 0x30 is defined in FW
973 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
974
975 //0x30~0x33
976 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBS2_DJB_START_ADDR);
977 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBS2_DJB_START_ADDR >> 8));
978 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBS2_DJB_START_ADDR >> 16));
979 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBS2_DJB_START_ADDR >> 24));
980
981 printf("@@@@@ share dram address = 0x %x \n ",u32DMD_DVBS2_DJB_START_ADDR);
982 //=====================================================================
983 #endif
984
985 /*
986 HAL_DMD_RIU_WriteByte(0x103483, 0x50);
987 HAL_DMD_RIU_WriteByte(0x103483, 0x00);
988 HAL_DMD_RIU_WriteByte(0x103480, 0x01);
989 HAL_DMD_RIU_WriteByte(0x103481, 0x01);
990 HAL_DMD_RIU_WriteByte(0x103480, 0x00);
991 */
992
993 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
994 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
995 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
996 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
997
998
999 DBG_INTERN_DVBS(ULOGD("DEMOD",">DSP Loadcode done."));
1000 #if 0
1001 INTERN_DVBS_Config(6875, 128, 36125, 0,1);
1002 INTERN_DVBS_Active(ENABLE);
1003 while(1);
1004 #endif
1005 //HAL_DMD_RIU_WriteByte(0x101E3E, 0x04); // DVBT = BIT1 -> 0x02
1006
1007 return TRUE;
1008 }
1009
1010 /***********************************************************************************
1011 Subject: DVB-S CLKGEN initialized function
1012 Function: INTERN_DVBS_Power_On_Initialization
1013 Parmeter:
1014 Return: MS_BOOL
1015 Remark:
1016 ************************************************************************************/
INTERN_DVBS_InitClkgen(MS_BOOL bRFAGCTristateEnable)1017 void INTERN_DVBS_InitClkgen(MS_BOOL bRFAGCTristateEnable)
1018 {
1019 MS_U8 u8Temp=0;
1020 // This file is translated by Steven Hung's riu2script.pl
1021
1022 // ==============================================================
1023 // Start demod top initial setting by HK MCU ......
1024 // ==============================================================
1025 // [8] : reg_chiptop_dummy_0 (reg_dmdtop_dmd_sel)
1026 // 1'b0->reg_DMDTOP control by HK_MCU.
1027 // 1'b1->reg_DMDTOP control by DMD_MCU.
1028 // [9] : reg_chiptop_dummy_0 (reg_dmd_ana_regsel)
1029 // 1'b0->reg_DMDANA control by HK_MCU.
1030 // 1'b1->reg_DMDANA control by DMD_MCU.
1031 // select HK MCU ......
1032 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0000);
1033 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0000);
1034 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
1035
1036
1037 // ==============================================================
1038 // Start TOP CLKGEN initial setting ......
1039 // ==============================================================
1040 // CLK_DMDMCU clock setting
1041 // reg_ckg_dmdmcu@0x0f[4:0]
1042 // [0] : disable clock
1043 // [1] : invert clock
1044 // [4:2]:
1045 // 000:170 MHz(MPLL_DIV_BUF)
1046 // 001:160MHz
1047 // 010:144MHz
1048 // 011:123MHz
1049 // 100:108MHz (Kriti:DVBT2)
1050 // 101:mem_clcok
1051 // 110:mem_clock div 2
1052 // 111:select XTAL
1053 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
1054 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
1055 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1056 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1057
1058
1059 // set parallel ts clock
1060 // [11] : reg_ckg_demod_test_in_en = 0
1061 // 0: select internal ADC CLK
1062 // 1: select external test-in clock
1063 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
1064 // 0: select gated clock
1065 // 1: select free-run clock
1066 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
1067 // 0: normal phase to pad
1068 // 1: invert phase to pad
1069 // [8] : reg_ckg_atsc_dvb_div_sel = 1
1070 // 0: select clk_dmplldiv5
1071 // 1: select clk_dmplldiv3
1072 // [4:0]: reg_ckg_dvbtm_ts_divnum = 11
1073 // Demod TS output clock phase tuning number
1074 // If (reg_ckg_tsout_ph_tun_num == reg_ckg_dvbtm_ts_divnum),
1075 // Demod TS output clock is equal Demod TS internal working clock.
1076 // => TS clock = (864/3)/(2*(5+1)) = 24MHz
1077 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1078 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1079 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1080 HAL_DMD_RIU_WriteByte(0x103300, 0x05);
1081
1082
1083 // enable DVBTC ts clock
1084 // [11:8]: reg_ckg_dvbtc_ts
1085 // [8] : disable clock
1086 // [9] : invert clock
1087 // [11:10]: Select clock source
1088 // 00:clk_atsc_dvb_div
1089 // 01:62 MHz
1090 // 10:54 MHz
1091 // 11:reserved
1092 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
1093 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
1094 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1095 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1096
1097
1098 // enable dvbc adc clock
1099 // [3:0]: reg_ckg_dvbtc_adc
1100 // [0] : disable clock
1101 // [1] : invert clock
1102 // [3:2]: Select clock source => for demod clkgen clk_dvbtc_adc
1103 // 00: clk_dmdadc
1104 // 01: clk_dmdadc_div2
1105 // 10: clk_dmdadc_div4
1106 // 11: DFT_CLK
1107 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
1108 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
1109 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1110 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1111
1112
1113 // ==============================================================
1114 // Start demod_0 CLKGEN setting ......
1115 // ==============================================================
1116 // enable atsc_adcd_sync clock
1117 // [3:0] : reg_ckg_atsc_adcd_sync
1118 // [0] : disable clock
1119 // [1] : invert clock
1120 // [3:2]: Select clock source
1121 // 00: clk_dmdadc_sync
1122 // 01: 1'b0
1123 // 10: 1'b0
1124 // 11: DFT_CLK
1125 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
1126 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
1127 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1128 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1129
1130 // DVBS2
1131 // @0x350c
1132 // [3:0] : reg_ckg_dvbs_outer1x
1133 // [0] : disable clock
1134 // [1] : invert clock
1135 // [3:2]: Select clock source
1136 // 00: adc_clk_buf
1137 // 01: dvb_clk86_buf
1138 // 10: dvb_clk43_buf
1139 // 11: 1'b0
1140 // [6:4] : reg_ckg_dvbs_outer2x
1141 // [4] : disable clock
1142 // [5] : invert clock
1143 // [6] : Select clock source
1144 // 00: adc_clk_buf
1145 // 01: 1'b0
1146 // 10: 1'b0
1147 // 11: DFT_CLK
1148 // [10:8]: reg_ckg_dvbs2_inner
1149 // [8] : disable clock
1150 // [9] : invert clock
1151 // [10]: Select clock source
1152 // 00: adc_clk_buf
1153 // 01: 1'b0
1154 // 10: 1'b0
1155 // 11: DFT_CLK
1156 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1157 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1158 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1159 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1160
1161
1162 // DVBS2
1163 // @0x350d
1164 // [11:8]: reg_ckg_dvbs2_oppro
1165 // [8] : disable clock
1166 // [9] : invert clock
1167 // [11:10]: Select clock source
1168 // 00: mpll_clk144_buf
1169 // 01: mpll_clk96_buf
1170 // 10: mpll_clk72_buf
1171 // 11: mpll_clk48_buf
1172 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0d, 2'b11, 16'h0000);
1173 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0d, 2'b11, 16'h0000);
1174 HAL_DMD_RIU_WriteByte(0x111f1b, 0x00);
1175 HAL_DMD_RIU_WriteByte(0x111f1a, 0x00);
1176
1177
1178 // @0x3510
1179 // [3:0] : reg_ckg_dvbtm_adc
1180 // N/A
1181 // [6:4] : reg_ckg_dvbt_inner1x
1182 // [4] : disable clock
1183 // [5] : invert clock
1184 // [6] : Select clock source
1185 // 00: dvb_clk24_buf
1186 // 01: dvb_clk21p5_buf
1187 // 10: 1'b0
1188 // 11: DFT_CLK
1189 // [10:8] reg_ckg_dvbt_inner2x
1190 // [8] : disable clock
1191 // [9] : invert clock
1192 // [10]: Select clock source
1193 // 00: dvb_clk48_buf
1194 // 01: dvb_clk43_buf
1195 // 10: 1'b0
1196 // 11: DFT_CLK
1197 // [14:12] reg_ckg_dvbt_inner4x
1198 // [12]: disable clock
1199 // [13]: invert clock
1200 // [14]: Select clock source
1201 // 00: dvb_clk96_buf
1202 // 01: dvb_clk86_buf
1203 // 10: 1'b0
1204 // 11: DFT_CLK
1205 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h1110);
1206 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h1110);
1207 HAL_DMD_RIU_WriteByte(0x111f21, 0x11);
1208 HAL_DMD_RIU_WriteByte(0x111f20, 0x10);
1209
1210 // @0x3511
1211 // [2:0] : reg_ckg_dvbt_outer1x
1212 // [0] : disable clock
1213 // [1] : invert clock
1214 // [2] : Select clock source
1215 // 00: dvb_clk48_buf
1216 // 01: dvb_clk43_buf
1217 // 10: 1'b0
1218 // 11: DFT_CLK
1219 // [6:4] : reg_ckg_dvbt_outer2x
1220 // [4] : disable clock
1221 // [5] : invert clock
1222 // [6] : Select clock source
1223 // 00: dvb_clk96_buf
1224 // 01: dvb_clk86_buf
1225 // 10: 1'b0
1226 // 11: DFT_CLK
1227 // [11:8]: reg_ckg_dvbtc_outer2x
1228 // [8] : disable clock
1229 // [9] : invert clock
1230 // [11:10]: Select clock source
1231 // 00: mpll_clk57p6_buf
1232 // 01: dvb_clk43_buf
1233 // 10: dvb_clk86_buf
1234 // 11: dvb_clk96_buf
1235 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0c11);
1236 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0c11);
1237 HAL_DMD_RIU_WriteByte(0x111f23, 0x0c);
1238 HAL_DMD_RIU_WriteByte(0x111f22, 0x11);
1239
1240
1241 // @0x3512
1242 // [11:8]: reg_ckg_acifir
1243 // [8] : disable clock
1244 // [9] : invert clock
1245 // [11:10]: Select clock source
1246 // 000: 1'b0
1247 // 001: clk_dmdadc
1248 // 010: clk_vif_ssc_mux
1249 // 011: 1'b0
1250 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b10, 16'h0400);
1251 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b10, 16'h0400);
1252 HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1253
1254
1255 // @0x3514
1256 // [12:8]: reg_ckg_dvbtm_sram_t1o2x_t22x
1257 // [8] : disable clock
1258 // [9] : invert clock
1259 // [12:10]: Select clock source
1260 // 000: dvb_clk48_buf
1261 // 001: dvb_clk43_buf
1262 // 010: 1'b0
1263 // 011: 1'b0
1264 // 100: 1'b0
1265 // 101: 1'b0
1266 // 110: 1'b0
1267 // 111: 1'b0
1268 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b11, 16'h0000);
1269 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b11, 16'h0000);
1270 HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
1271 HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1272
1273
1274 // @0x3516
1275 // [8:4] : reg_ckg_dvbtm_sram_adc_t22x
1276 // [4] : disable clock
1277 // [5] : invert clock
1278 // [8:6]: Select clock source
1279 // 000: dvb_clk48_buf
1280 // 001: dvb_clk43_buf
1281 // 010: 1'b0
1282 // 011: 1'b0
1283 // 100: adc_clk_buf
1284 // 101: 1'b0
1285 // 110: 1'b0
1286 // 111: 1'b0
1287 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h16, 2'b11, 16'h0001);
1288 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h16, 2'b11, 16'h0001);
1289 HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
1290 HAL_DMD_RIU_WriteByte(0x111f2c, 0x01);
1291
1292
1293 // @0x3517
1294 // [4:0] : reg_ckg_dvbtm_sram_t12x_t22x
1295 // [0] : disable clock
1296 // [1] : invert clock
1297 // [4:2]: Select clock source
1298 // 000: dvb_clk48_buf
1299 // 001: dvb_clk43_buf
1300 // 010: 1'b0
1301 // 011: 1'b0
1302 // 100: 1'b0
1303 // 101: 1'b0
1304 // 110: 1'b0
1305 // 111: 1'b0
1306 // [12:8] reg_ckg_dvbtm_sram_t12x_t24x
1307 // [8] : disable clock
1308 // [9] : invert clock
1309 // [12:10]: Select clock source
1310 // 000: dvb_clk96_buf
1311 // 001: dvb_clk86_buf
1312 // 010: dvb_clk48_buf
1313 // 011: dvb_clk43_buf
1314 // 100: 1'b0
1315 // 101: 1'b0
1316 // 110: 1'b0
1317 // 111: 1'b0
1318 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h17, 2'b11, 16'h0000);
1319 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h17, 2'b11, 16'h0000);
1320 HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
1321 HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
1322
1323
1324 // @0x3518
1325 // [4:0] : reg_ckg_dvbtm_sram_t14x_t24x
1326 // [0] : disable clock
1327 // [1] : invert clock
1328 // [4:2]: Select clock source
1329 // 000: dvb_clk96_buf
1330 // 001: dvb_clk96_buf
1331 // 010: 1'b0
1332 // 011: 1'b0
1333 // 100: 1'b0
1334 // 101: 1'b0
1335 // 110: 1'b0
1336 // 111: 1'b0
1337 // [12:8]: reg_ckg_dvbtm_ts_in
1338 // [8] : disable clock
1339 // [9] : invert clock
1340 // [12:10]: Select clock source
1341 // 000: clk_dvbtc_rs_p
1342 // 001: dvb_clk48_buf
1343 // 010: dvb_clk43_buf
1344 // 011: clk_dvbs_outer1x_pre_mux4
1345 // 100: clk_dvbs2_oppro_pre_mux4
1346 // 101: 1'b0
1347 // 110: 1'b0
1348 // 111: 1'b0
1349 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b11, 16'h0001);
1350 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b11, 16'h0001);
1351 HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1352 HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1353
1354
1355 // @0x3519
1356 // [2:0] : reg_ckg_tdp_jl_inner1x
1357 // [0] : disable clock
1358 // [1] : invert clock
1359 // [2] : Select clock source
1360 // 00: dvb_clk24_buf
1361 // 01: dvb_clk21p5_buf
1362 // 10: 1'b0
1363 // 11: DFT_CLK
1364 // [6:4] : reg_ckg_tdp_jl_inner4x
1365 // [4] : disable clock
1366 // [5] : invert clock
1367 // [6] : Select clock source
1368 // 00: dvb_clk96_buf
1369 // 01: dvb_clk86_buf
1370 // 10: 1'b0
1371 // 11: DFT_CLK
1372 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h19, 2'b11, 16'h3c00);
1373 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h19, 2'b11, 16'h3c00);
1374 HAL_DMD_RIU_WriteByte(0x111f33, 0x3c);
1375 HAL_DMD_RIU_WriteByte(0x111f32, 0x00);
1376
1377
1378 // @0x351a
1379 // [6:4] : reg_ckg_dvbt2_inner1x
1380 // [4] : disable clock
1381 // [5] : invert clock
1382 // [6] : Select clock source
1383 // 00: dvb_clk96_buf
1384 // 01: dvb_clk86_buf
1385 // 10: 1'b0
1386 // 11: DFT_CLK
1387 // [10:8]: reg_ckg_dvbt2_inner2x
1388 // [8] : disable clock
1389 // [9] : invert clock
1390 // [10]: Select clock source
1391 // 00: dvb_clk48_buf
1392 // 01: dvb_clk43_buf
1393 // 10: 1'b0
1394 // 11: DFT_CLK
1395 // [14:12]:reg_ckg_dvbt2_inner4x
1396 // [12] : disable clock
1397 // [13] : invert clock
1398 // [14] : Select clock source
1399 // 00: dvb_clk96_buf
1400 // 01: dvb_clk86_buf
1401 // 10: 1'b0
1402 // 11: DFT_CLK
1403 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1a, 2'b11, 16'h0000);
1404 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1a, 2'b11, 16'h0000);
1405 HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
1406 HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
1407
1408
1409 // @0x351b
1410 // [1:0] : reg_ckg_dvbt2_ldpc
1411 // DVBT2 LDPC gated clock control register
1412 // [0] = 1:clock enable.
1413 // [1] = 1:manual mode.
1414 // [3:2] : reg_ckg_dvbt2_bch
1415 // DVBT2 BCH gated clock control register;
1416 // [0] = 1:clock enable
1417 // [1] = 1:manual mode.
1418 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1b, 2'b11, 16'h0011);
1419 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1b, 2'b11, 16'h0011);
1420 HAL_DMD_RIU_WriteByte(0x111f37, 0x00);
1421 HAL_DMD_RIU_WriteByte(0x111f36, 0x11);
1422
1423
1424 // @0x351d
1425 // [4:0] : reg_ckg_dvbtm_adc_eq_1x
1426 // [0] : disable clock
1427 // [1] : invert clock
1428 // [2] : Select clock source
1429 // 00: adc_clk_buf
1430 // 01: 1'b0
1431 // 10: 1'b0
1432 // 11: DFT_CLK
1433 // [12:8]: reg_ckg_dvbtm_adc_eq_0p5x
1434 // [4] : disable clock
1435 // [5] : invert clock
1436 // [6]: Select clock source
1437 // 00: clk_adc_div2_buf
1438 // 01: 1'b0
1439 // 10: 1'b0
1440 // 11: DFT_CLK
1441 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1d, 2'b11, 16'h0000);
1442 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1d, 2'b11, 16'h0000);
1443 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1444 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1445
1446
1447 // @0x351e
1448 // [4:0] : reg_ckg_dvbtm_sram_t11x_t22x
1449 // [0] : disable clock
1450 // [1] : invert clock
1451 // [4:2]: Select clock source
1452 // 000: dvb_clk48_buf
1453 // 001: dvb_clk43_buf
1454 // 010: dvb_clk24_buf
1455 // 011: dvb_clk21p5_buf
1456 // 100: 1'b0
1457 // 101: 1'b0
1458 // 110: 1'b0
1459 // 111: 1'b0
1460 // [12:8]: reg_ckg_dvbtm_sram_t11x_t24x
1461 // [8] : disable clock
1462 // [9] : invert clock
1463 // [:2]: Select clock source
1464 // 000: dvb_clk48_buf
1465 // 001: dvb_clk43_buf
1466 // 010: dvb_clk24_buf
1467 // 011: dvb_clk21p5_buf
1468 // 100: 1'b0
1469 // 101: 1'b0
1470 // 110: 1'b0
1471 // 111: 1'b0
1472 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1e, 2'b11, 16'h0c04);
1473 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1e, 2'b11, 16'h0000);
1474 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1e, 2'b11, 16'h0000);
1475 HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
1476 HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
1477
1478
1479 // @0x3522
1480 // [3:0] : reg_ckg_dvbt_t2_inner0p5x_dvbc_eq1x
1481 // [0] : disable clock
1482 // [1] : invert clock
1483 // [2] : Select clock source
1484 // 00: dvb_clk12_buf
1485 // 01: dvb_clk10p75_buf
1486 // 10: 1'b0
1487 // 11: DFT_CLK
1488 // [7:4] : reg_ckg_dvbt_t2_inner2x_dvbc_eq4x
1489 // [4] : disable clock
1490 // [5] : invert clock
1491 // [6] : Select clock source
1492 // 00: dvb_clk48_buf
1493 // 01: dvb_clk43_buf
1494 // 10: 1'b0
1495 // 11: DFT_CLK
1496 // [11:8]: reg_ckg_dvbt_t2_inner1x
1497 // [8] : disable clock
1498 // [9] : invert clock
1499 // [11:10]: Select clock source
1500 // 00: dvb_clk24_buf
1501 // 01: dvb_clk21p5_buf
1502 // 10: 1'b0
1503 // 11: DFT_CLK
1504 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0111);
1505 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0111);
1506 HAL_DMD_RIU_WriteByte(0x111f45, 0x01);
1507 HAL_DMD_RIU_WriteByte(0x111f44, 0x11);
1508
1509 // @0x353a
1510 // [2:0] : reg_ckg_dvbtm_sram_t12x_t24x_srd1x_isdbt_inner2x
1511 // [0] : disable clock
1512 // [1] : invert clock
1513 // [2] : Select clock source
1514 // 00: clk_dvbtm_sram_t12x_t24x_srd1x_p
1515 // 01: clk_isdbt_inner2x_p
1516 // 10: 1'b0
1517 // 11: DFT_CLK
1518 // [6:4] : reg_ckg_dvbtm_sram_t12x_t24x_isdbt_inner2x
1519 // [4] : disable clock
1520 // [5] : invert clock
1521 // [6] : Select clock source
1522 // 00: clk_dvbtm_sram_t12x_t24x_p
1523 // 01: clk_isdbt_inner2x_p
1524 // 10: 1'b0
1525 // 11: DFT_CLK
1526 // [10:8]: reg_ckg_dvbtm_sram_t24x_isdbt_inner2x
1527 // [8] : disable clock
1528 // [9] : invert clock
1529 // [10]: Select clock source
1530 // 00: clk_dvbtm_sram_t14x_t24x_p
1531 // 01: clk_isdbt_inner2x_p
1532 // 10: 1'b0
1533 // 11: DFT_CLK
1534 // [14:12]: reg_ckg_dvbtm_sram_t12x_t24x_s2inner_isdbt_inner4x
1535 // [12] : disable clock
1536 // [13] : invert clock
1537 // [14] : Select clock source
1538 // 00: clk_dvbtm_sram_t12x_t24x_s2inner_p
1539 // 01: clk_isdbt_inner4x_p
1540 // 10: 1'b0
1541 // 11: DFT_CLK
1542 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3a, 2'b11, 16'h0110);
1543 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3a, 2'b11, 16'h0110);
1544 HAL_DMD_RIU_WriteByte(0x111f75, 0x01);
1545 HAL_DMD_RIU_WriteByte(0x111f74, 0x10);
1546
1547 // @0x353b
1548 // [2:0] : reg_ckg_dvbtm_sram_t12x_t24x_s2inner_isdbt_inner2x
1549 // [0] : disable clock
1550 // [1] : invert clock
1551 // [2] : Select clock source
1552 // 00: clk_dvbtm_sram_t12x_t24x_s2inner_p
1553 // 01: clk_isdbt_inner2x_p
1554 // 10: 1'b0
1555 // 11: DFT_CLK
1556 // [6:4] : reg_ckg_dvbtm_sram_t22x_isdbt_inner2x
1557 // [4] : disable clock
1558 // [5] : invert clock
1559 // [6] : Select clock source
1560 // 00: clk_dvbtm_sram_t12x_t22x_p
1561 // 01: clk_isdbt_inner2x_p
1562 // 10: 1'b0
1563 // 11: DFT_CLK
1564 // [10:8]: reg_ckg_dvbtm_sram_t14x_t24x_s2inner_isdbt_inner2x
1565 // [8] : disable clock
1566 // [9] : invert clock
1567 // [10]: Select clock source
1568 // 00: clk_dvbtm_sram_t14x_t24x_s2inner_p
1569 // 01: clk_isdbt_inner2x_p
1570 // 10: 1'b0
1571 // 11: DFT_CLK
1572 // [14:12]: reg_ckg_dvbtm_sram_t12x_t24x_srd1x_isdbt_inner4x
1573 // [12] : disable clock
1574 // [13] : invert clock
1575 // [14]: Select clock source
1576 // 00: clk_dvbtm_sram_t12x_t24x_srd1x_p
1577 // 01: clk_isdbt_inner4x_p
1578 // 10: 1'b0
1579 // 11: DFT_CLK
1580 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0010);
1581 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0010);
1582 HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
1583 HAL_DMD_RIU_WriteByte(0x111f76, 0x10);
1584
1585 // @0x353c
1586 // [2:0] : reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifssc_isdbt_inner4x
1587 // [0] : disable clock
1588 // [1] : invert clock
1589 // [2] : Select clock source
1590 // 00: clk_dvbtm_sram_t14x_t24x_srd1x_vifssc_p
1591 // 01: clk_isdbt_inner4x_p
1592 // 10: 1'b0
1593 // 11: DFT_CLK
1594 // [6:4] : reg_ckg_dvbtm_sram_t12x_t22x_isdbt_inner2x
1595 // [4] : disable clock
1596 // [5] : invert clock
1597 // [6] : Select clock source
1598 // 00: clk_dvbtm_sram_t12x_t22x_p
1599 // 01: clk_isdbt_inner2x_p
1600 // 10: 1'b0
1601 // 11: DFT_CLK
1602 // [10:8]: reg_ckg_dvbtm_sram_t11x_t22x_isdbt_inner2x
1603 // [8] : disable clock
1604 // [9] : invert clock
1605 // [10]: Select clock source
1606 // 00: clk_dvbtm_sram_t11x_t22x_p
1607 // 01: clk_isdbt_inner2x_p
1608 // 10: 1'b0
1609 // 11: DFT_CLK
1610 // [14:12]: reg_ckg_dvbtm_sram_t12x_t24x_isdbt_outer6x
1611 // [12] : disable clock
1612 // [13] : invert clock
1613 // [14]: Select clock source
1614 // 00: clk_dvbtm_sram_t12x_t24x_p
1615 // 01: clk_isdbt_outer6x_dvbt_outer2x_c_mux
1616 // 10: 1'b0
1617 // 11: DFT_CLK
1618 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3c, 2'b11, 16'h0110);
1619 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3c, 2'b11, 16'h0110);
1620 HAL_DMD_RIU_WriteByte(0x111f79, 0x01);
1621 HAL_DMD_RIU_WriteByte(0x111f78, 0x10);
1622
1623 // @0x353e
1624 // [2:0] : reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_isdbt_outer6x
1625 // [0] : disable clock
1626 // [1] : invert clock
1627 // [2] : Select clock source
1628 // 00: clk_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_mux8
1629 // 01: clk_isdbt_outer6x_p
1630 // 10: 1'b0
1631 // 11: DFT_CLK
1632 // [6:4] : reg_ckg_dvbtm_sram_t22x_miu
1633 // [4] : disable clock
1634 // [5] : invert clock
1635 // [6] : Select clock source
1636 // 00: clk_dvbt2_inner2x_p
1637 // 01: clk_miu_p
1638 // 10: 1'b0
1639 // 11: DFT_CLK
1640 // [10:8]: reg_ckg_dvbtm_sram_adc_t22x_isdbt_inner2x
1641 // [8] : disable clock
1642 // [9] : invert clock
1643 // [10]: Select clock source
1644 // 00: clk_dvbtm_sram_adc_t22x_p
1645 // 01: clk_isdbt_inner2x_p
1646 // 10: 1'b0
1647 // 11: DFT_CLK
1648 // [14:12]: reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_miu
1649 // [12] : disable clock
1650 // [13] : invert clock
1651 // [14]: Select clock source
1652 // 00: clk_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_mux8
1653 // 01: clk_miu_p
1654 // 10: 1'b0
1655 // 11: DFT_CLK
1656 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3e, 2'b11, 16'h1111);
1657 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3e, 2'b11, 16'h1111);
1658 HAL_DMD_RIU_WriteByte(0x111f7d, 0x11);
1659 HAL_DMD_RIU_WriteByte(0x111f7c, 0x11);
1660
1661 // @0x353f
1662 // [2:0] : reg_ckg_dvbs_outer2x_dvbt_outer2x_miu_isdbt_outer6x
1663 // [0] : disable clock
1664 // [1] : invert clock
1665 // [2] : Select clock source
1666 // 00: clk_dvbs_outer2x_dvbt_outer2x_miu_mux8
1667 // 01: clk_isdbt_outer6x_p
1668 // 10: 1'b0
1669 // 11: DFT_CLK
1670 // [6:4] : reg_ckg_dvbtm_sram_t22x_dvbtc_rs
1671 // [4] : disable clock
1672 // [5] : invert clock
1673 // [6] : Select clock source
1674 // 00: clk_dvbt2_inner2x_p
1675 // 01: clk_dvbtc_rs_p
1676 // 10: 1'b0
1677 // 11: DFT_CLK
1678 // [10:8]: reg_ckg_dvbtc_outer2x_isdbt_outer_rs
1679 // [8] : disable clock
1680 // [9] : invert clock
1681 // [10]: Select clock source
1682 // 00: clk_dvbtc_outer2x_p
1683 // 01: clk_isdbt_outer_rs_p
1684 // 10: 1'b0
1685 // 11: DFT_CLK
1686 // [14:12]: reg_ckg_dvbtm_sram_t22x_isdbt_outer6x_dvbt_outer2x
1687 // [12] : disable clock
1688 // [13] : invert clock
1689 // [14]: Select clock source
1690 // 00: clk_dvbtm_sram_t12x_t22x_p
1691 // 01: clk_isdbt_outer6x_dvbt_outer2x_mux
1692 // 10: 1'b0
1693 // 11: DFT_CLK
1694 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3f, 2'b11, 16'h1041);
1695 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3f, 2'b11, 16'h1041);
1696 HAL_DMD_RIU_WriteByte(0x111f7f, 0x10);
1697 HAL_DMD_RIU_WriteByte(0x111f7e, 0x41);
1698
1699
1700 // @0x3570
1701 // [4:0] : reg_ckg_dvbt_inner2x_srd0p5x
1702 // [0] : disable clock
1703 // [1] : invert clock
1704 // [3:2]: Select clock source
1705 // 00: dvb_clk48_buf
1706 // 01: dvb_clk43_buf
1707 // 10: clk_adc_div2_buf
1708 // 11: 1'b0
1709 // 11: 1'b0
1710 // [13:8]: reg_ckg_dvbtm_sram_t1outer1x_t24x
1711 // [8] : disable clock
1712 // [9] : invert clock
1713 // [12:10]: Select clock source
1714 // 000: dvb_clk96_buf
1715 // 001: dvb_clk86_buf
1716 // 010: dvb_clk48_buf
1717 // 011: dvb_clk43_buf
1718 // 100: 1'b0
1719 // 101: 1'b0
1720 // 110: 1'b0
1721 // 111: 1'b0
1722 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h70, 2'b11, 16'h0008);
1723 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h70, 2'b11, 16'h0008);
1724 HAL_DMD_RIU_WriteByte(0x111fe1, 0x00);
1725 HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1726
1727
1728 // @0x3571
1729 // [4:0] : reg_ckg_dvbtm_sram_t12x_t24x_srd1x
1730 // [0] : disable clock
1731 // [1] : invert clock
1732 // [3:2]: Select clock source
1733 // 000: dvb_clk96_buf
1734 // 001: dvb_clk86_buf
1735 // 010: dvb_clk48_buf
1736 // 011: dvb_clk43_buf
1737 // 100: adc_clk_buf
1738 // 101: 1'b0
1739 // 110: 1'b0
1740 // 111: 1'b0
1741 // [12:8]: reg_ckg_dvbtm_sram_t14x_t24x_srd1x
1742 // [8] : disable clock
1743 // [9] : invert clock
1744 // [12:10]: Select clock source
1745 // 000: dvb_clk96_buf
1746 // 001: dvb_clk86_buf
1747 // 010: adc_clk_buf
1748 // 011: 1'b0
1749 // 100: 1'b0
1750 // 101: 1'b0
1751 // 110: 1'b0
1752 // 111: 1'b0
1753 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h71, 2'b11, 16'h0810);
1754 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h71, 2'b11, 16'h0810);
1755 HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1756 HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1757
1758
1759 // @0x3572
1760 // [6:0] : reg_ckg_dvbt2_s2_bch_out
1761 // [0] : disable clock
1762 // [1] : invert clock
1763 // [2] : Select clock source
1764 // 00: dvb_clk48_buf
1765 // 01: dvb_clk43_buf
1766 // 10: 1'b0
1767 // 11: DFT_CLK
1768 // [12:8]: reg_ckg_dvbt2_outer2x
1769 // [8] : disable clock
1770 // [9] : invert clock
1771 // [12:10]: Select clock source
1772 // 000: mpll_clk144_buf
1773 // 001: mpll_clk108_buf
1774 // 010: mpll_clk96_buf
1775 // 011: mpll_clk72_buf
1776 // 100: mpll_clk54_buf
1777 // 101: mpll_clk48_buf
1778 // 110: mpll_clk36_buf
1779 // 111: mpll_clk24_buf
1780 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h72, 2'b11, 16'h0008);
1781 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h72, 2'b11, 16'h0008);
1782 HAL_DMD_RIU_WriteByte(0x111fe5, 0x00);
1783 HAL_DMD_RIU_WriteByte(0x111fe4, 0x08);
1784
1785
1786 // @0x3573
1787 // [3:0] : reg_ckg_dvbt2_inner4x_s2_inner
1788 // [0] : disable clock
1789 // [1] : invert clock
1790 // [2] : Select clock source
1791 // 00: dvb_clk96_buf
1792 // 01: dvb_clk86_buf
1793 // 10: 1'b0
1794 // 11: DFT_CLK
1795 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h73, 2'b11, 16'h0008);
1796 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h73, 2'b11, 16'h0008);
1797 HAL_DMD_RIU_WriteByte(0x111fe7, 0x00);
1798 HAL_DMD_RIU_WriteByte(0x111fe6, 0x08);
1799
1800
1801 // @0x3574
1802 // [4:0] reg_ckg_dvbtm_sram_t12x_t24x_s2inner
1803 // [0] : disable clock
1804 // [1] : invert clock
1805 // [4:2]:Select clock source
1806 // 000: dvb_clk96_buf
1807 // 001: dvb_clk86_buf
1808 // 010: dvb_clk48_buf
1809 // 011: dvb_clk43_buf
1810 // 100: adc_clk_buf
1811 // 101: 1'b0
1812 // 110: 1'b0
1813 // 111: 1'b0
1814 // [12:8] reg_ckg_dvbtm_sram_t14x_t24x_s2inner
1815 // [8] : disable clock
1816 // [9] : invert clock
1817 // [12:10]: Select clock source
1818 // 000: dvb_clk96_buf
1819 // 001: dvb_clk86_buf
1820 // 010: adc_clk_buf
1821 // 011: dvb_clk24_buf //JL SRAM Share (Windermere U02 ECO)
1822 // 100: dvb_clk21p5_buf //JL SRAM Share (Windermere U02 ECO)
1823 // 101: 1'b0
1824 // 110: 1'b0
1825 // 111: 1'b0
1826 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h74, 2'b11, 16'h0810);
1827 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h74, 2'b11, 16'h0810);
1828 HAL_DMD_RIU_WriteByte(0x111fe9, 0x08);
1829 HAL_DMD_RIU_WriteByte(0x111fe8, 0x10);
1830
1831
1832 // @0x3575
1833 // [4:0] : reg_ckg_dvbtc_rs
1834 // [0] : disable clock
1835 // [1] : invert clock
1836 // [4:2]:Select clock source
1837 // 000: mpll_clk216_buf
1838 // 001: mpll_clk172p8_buf
1839 // 010: mpll_clk144_buf
1840 // 011: mpll_clk288_buf
1841 // 100: dvb_clk96_buf
1842 // 101: dvb_clk86_buf
1843 // 110: mpll_clk57p6_buf
1844 // 111: dvb_clk43_buf
1845 // [11:8] : reg_ckg_dvbs_outer2x_dvbt_outer2x (N/A)
1846 // [15:12]: reg_ckg_dvbs_outer2x_dvbt_outer2x_miu
1847 // [12] : disable clock
1848 // [13] : invert clock
1849 // [15:14]:Select clock source
1850 // 000: 1'b0
1851 // 001: dvb_clk96_buf
1852 // 010: dvb_clk86_buf
1853 // 011: clk_miu
1854 // 100: 1'b0
1855 // 101: 1'b0
1856 // 110: 1'b0
1857 // 111: 1'b0
1858 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h75, 2'b11, 16'h0000);
1859 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h75, 2'b11, 16'h0000);
1860 HAL_DMD_RIU_WriteByte(0x111feb, 0x00);
1861 HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1862
1863
1864 // @0x3576
1865 // [4:0] : reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x
1866 // [0] : disable clock
1867 // [1] : invert clock
1868 // [4:2]:Select clock source
1869 // 000: 1'b0
1870 // 001: dvb_clk96_buf
1871 // 010: dvb_clk86_buf
1872 // 011: dvb_clk48_buf
1873 // 100: dvb_clk43_buf
1874 // 101: 1'b0
1875 // 110: 1'b0
1876 // 111: 1'b0
1877 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h76, 2'b11, 16'h0000);
1878 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h76, 2'b11, 16'h0000);
1879 HAL_DMD_RIU_WriteByte(0x111fed, 0x00);
1880 HAL_DMD_RIU_WriteByte(0x111fec, 0x00);
1881
1882
1883 // @0x3577
1884 // [3:0] : reg_ckg_dvbt2_inner4x_dvbtc_rs
1885 // [0] : disable clock
1886 // [1] : invert clock
1887 // [3:2]: Select clock source
1888 // 00: dvb_clk96_buf
1889 // 01: dvb_clk86_buf
1890 // 10: clk_dvbtc_rs_p
1891 // 11: 1'b0
1892 // [8:4] : reg_ckg_dvbtm_sram_adc_t22x_dvbtc_rs
1893 // [4] : disable clock
1894 // [5] : invert clock
1895 // [6] : Select clock source
1896 // 000: dvb_clk48_buf
1897 // 001: dvb_clk43_buf
1898 // 010: 1'b0
1899 // 011: adc_clk_buf
1900 // 100: 1'b0
1901 // 101: 1'b0
1902 // 110: 1'b0
1903 // 111: 1'b0
1904 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h77, 2'b11, 16'h0088);
1905 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h77, 2'b11, 16'h0088);
1906 HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1907 HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1908
1909
1910 // Maserati
1911 // @0x3578
1912 // [4:0] : reg_ckg_dvbt2_inner2x_srd0p5x
1913 // [0] : disable clock
1914 // [1] : invert clock
1915 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h78, 2'b01, 16'h0008);
1916 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h78, 2'b01, 16'h0008);
1917 HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1918
1919 // [3:0] : reg_ckg_sram_t22x_isdbt_inn2x_dtmb_inn2x
1920 // [0] : disable clock
1921 // [1] : invert clock
1922 // [3:2]:Select clock source
1923 // 000: clk_dvbtm_sram_t12x_t22x_p
1924 // 001: clk_isdbt_inner2x_p
1925 // 010: clk_share_dtmb_inner2x_isdbt_sram4_mux
1926 // 011:
1927 // [7:4] : reg_ckg_sram_t14x_t24x_s2inn_isdbt_inn2x_dtmb_inn6x
1928 // [4] : disable clock
1929 // [5] : invert clock
1930 // [7:6]:Select clock source
1931 // 000: clk_dvbtm_sram_t14x_t24x_s2inner_p
1932 // 001: clk_isdbt_inner2x_p
1933 // 010: clk_share_dtmb_inner6x_isdbt_sram3_mux
1934 // 011:
1935 // [11:8] : reg_ckg_sram_t14x_t24x_s2inn_isdbt_inn2x_dtmb_eq2x
1936 // [4] : disable clock
1937 // [5] : invert clock
1938 // [7:6]:Select clock source
1939 // 000: clk_dvbtm_sram_t14x_t24x_s2inner_p
1940 // 001: clk_isdbt_inner2x_p
1941 // 010: clk_share_dtmb_eq2x_isdbt_sram3_mux
1942 // 011:
1943 // [15:12]: reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifssc_isdbt_inner4x_dtmb_inner12x
1944 // [12] : disable clock
1945 // [13] : invert clock
1946 // [15:14]:Select clock source
1947 // 000: clk_dvbtm_sram_t14x_t24x_srd1x_vifssc_p
1948 // 001: clk_isdbt_inner4x_p
1949 // 010: clk_dvbtc_sram2_p
1950 // 011: clk_dtmb_eq2x_inner2x_12x_mux
1951 // `RIU_W((`RIUBASE_DEMOD_8>>1)+7'h48, 2'b11, 16'h0001);
1952 // `RIU_W((`RIUBASE_DEMOD_8>>1)+7'h48, 2'b11, 16'h0001);
1953 HAL_DMD_RIU_WriteByte(0x152991, 0x00);
1954 HAL_DMD_RIU_WriteByte(0x152990, 0x01);
1955 // ==============================================================
1956 // End demod top initial setting by HK MCU ......
1957 // ==============================================================
1958 //wriu 0x101e39 0x03
1959 HAL_DMD_RIU_WriteByte(0x101e39, 0x03);
1960
1961 //==========================================================
1962 //diseqc_out : PAD_GPIO15_I
1963 //swich to Diseqc out pin from GPIO
1964 //==========================================================
1965 //Bank: Reg_CHIP_TOP(0x101e)
1966 //reg_test_out_mode : addr h¡¦12, [6:4] = 3¡¦h0
1967 //reg_ts4config : addr h¡¦40, [11:10] = 2¡¦h0
1968 //reg_ts5config : addr h¡¦40, [13:12] = 2¡¦h0
1969 //reg_i2smutemode : addr h¡¦2, [15:14] = 2¡¦h0
1970 //reg_fifthuartmode : h¡¦4, [3:2] = 2¡¦h0
1971 //reg_od5thuart : h¡¦55, [5:4] = 2¡¦h0
1972 //reg_diseqc_out_config : ¡¥h68, [5] = 1¡¦b1
1973 u8Temp = HAL_DMD_RIU_ReadByte(0x101ED0);
1974 u8Temp|=0x10;
1975 HAL_DMD_RIU_WriteByte(0x101ED0, u8Temp);
1976
1977 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1978
1979 // SRAM allocation 64K avoid change souce from T2 failed.
1980 HAL_DMD_RIU_WriteByte(0x111701,0x00);
1981 HAL_DMD_RIU_WriteByte(0x111700,0x00);
1982
1983 HAL_DMD_RIU_WriteByte(0x111705,0x00);
1984 HAL_DMD_RIU_WriteByte(0x111704,0x00);
1985
1986 HAL_DMD_RIU_WriteByte(0x111703,0xff);
1987 HAL_DMD_RIU_WriteByte(0x111702,0xff);
1988
1989 HAL_DMD_RIU_WriteByte(0x111707,0xff);
1990 HAL_DMD_RIU_WriteByte(0x111706,0xff);
1991
1992 //Diff from TV tool
1993 HAL_DMD_RIU_WriteByte(0x111708,0x01);
1994 HAL_DMD_RIU_WriteByte(0x111709,0x00);
1995
1996 HAL_DMD_RIU_WriteByte(0x11170a,0x0f);
1997 HAL_DMD_RIU_WriteByte(0x11170b,0x00);
1998
1999 HAL_DMD_RIU_WriteByte(0x111718,0x02);
2000 HAL_DMD_RIU_WriteByte(0x111719,0x00);
2001
2002 HAL_DMD_RIU_WriteByte(0x11171a,0x00);
2003 HAL_DMD_RIU_WriteByte(0x11171b,0x00);
2004
2005 HAL_DMD_RIU_WriteByte(0x1117e0,0x14);
2006 HAL_DMD_RIU_WriteByte(0x1117e1,0x14);
2007
2008 HAL_DMD_RIU_WriteByte(0x1117e4,0x00);
2009 HAL_DMD_RIU_WriteByte(0x1117e5,0x00);
2010
2011 HAL_DMD_RIU_WriteByte(0x1117e6,0x00);
2012 HAL_DMD_RIU_WriteByte(0x1117e7,0x00);
2013
2014 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_InitClkgen\n"));
2015 }
2016
2017 /***********************************************************************************
2018 Subject: Power on initialized function
2019 Function: INTERN_DVBS_Power_On_Initialization
2020 Parmeter:
2021 Return: MS_BOOL
2022 Remark:
2023 ************************************************************************************/
INTERN_DVBS_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBS_DSPRegInitExt,MS_U8 u8DMD_DVBS_DSPRegInitSize)2024 MS_BOOL INTERN_DVBS_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBS_DSPRegInitExt, MS_U8 u8DMD_DVBS_DSPRegInitSize)
2025 {
2026 MS_U8 status = true;
2027 //MS_U8 u8ChipVersion;
2028
2029 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_Power_On_Initialization\n"));
2030
2031 #if defined(PWS_ENABLE)
2032 Mapi_PWS_Stop_VDMCU();
2033 #endif
2034 INTERN_DVBS_InitClkgen(bRFAGCTristateEnable);//~~ no modify
2035 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);//~~ no modify
2036
2037 DBG_INTERN_DVBS(ULOGD("DEMOD","@@@@@INTERN_DVBS_Power_On_Initialization1:bRFAGCTristateEnable=%d ;u8ADCIQMode=%d \n",bRFAGCTristateEnable,u8ADCIQMode));
2038 DBG_INTERN_DVBS(ULOGD("DEMOD","@@@@@INTERN_DVBS_Power_On_Initialization2:u8PadSel=%d ;bPGAEnable=%d \n",u8PadSel,bPGAEnable));
2039 DBG_INTERN_DVBS(ULOGD("DEMOD","@@@@@INTERN_DVBS_Power_On_Initialization2:u8PGAGain=%d \n",u8PGAGain));
2040
2041 //// Firmware download //////////
2042 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS Load DSP...\n"));
2043 //MsOS_DelayTask(100);
2044
2045 {
2046 if (INTERN_DVBS_LoadDSPCode() == FALSE)
2047 {
2048 DBG_INTERN_DVBS(ULOGD("DEMOD","DVB-S Load DSP Code Fail\n"));
2049 return FALSE;
2050 }
2051 else
2052 {
2053 DBG_INTERN_DVBS(ULOGD("DEMOD","DVB-S Load DSP Code OK\n"));
2054 }
2055 }
2056
2057 //// MCU Reset //////////
2058 if (INTERN_DVBS_Reset() == FALSE)
2059 {
2060 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS Reset...Fail\n"));
2061 return FALSE;
2062 }
2063 else
2064 {
2065 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS Reset...OK\n"));
2066 }
2067
2068
2069 status &= INTERN_DVBS_DSPReg_Init(u8DMD_DVBS_DSPRegInitExt, u8DMD_DVBS_DSPRegInitSize);
2070 //status &= INTERN_DVBS_Active(ENABLE);//enable this
2071
2072 //Read Demod FW Version.
2073 INTERN_DVBS_Show_Demod_Version();
2074
2075 return status;
2076 }
2077 /************************************************************************************************
2078 Subject: Driving control
2079 Function: INTERN_DVBC_Driving_Control
2080 Parmeter: bInversionEnable : TRUE For High
2081 Return: void
2082 Remark:
2083 *************************************************************************************************/
INTERN_DVBS_Driving_Control(MS_BOOL bEnable)2084 void INTERN_DVBS_Driving_Control(MS_BOOL bEnable)
2085 {
2086 MS_U8 u8Temp;
2087
2088 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
2089
2090 if (bEnable)
2091 {
2092 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
2093 }
2094 else
2095 {
2096 u8Temp = u8Temp & (~0x01);
2097 }
2098
2099 DBG_INTERN_DVBS(ULOGD("DEMOD","---> INTERN_DVBS_Driving_Control(Bit0) = 0x%x \n",u8Temp));
2100 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
2101 }
2102
2103 /************************************************************************************************
2104 Subject: Clk Inversion control
2105 Function: INTERN_DVBS_Clk_Inversion_Control
2106 Parmeter: bInversionEnable : TRUE For Inversion Action
2107 Return: void
2108 Remark:
2109 *************************************************************************************************/
INTERN_DVBS_Clk_Inversion_Control(MS_BOOL bInversionEnable)2110 void INTERN_DVBS_Clk_Inversion_Control(MS_BOOL bInversionEnable)
2111 {
2112 MS_U8 u8Temp;
2113
2114 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
2115
2116 if (bInversionEnable)
2117 {
2118 u8Temp = u8Temp | 0x02; //bit 9: clk inv
2119 }
2120 else
2121 {
2122 u8Temp = u8Temp & (~0x02);
2123 }
2124
2125 DBG_INTERN_DVBS(ULOGD("DEMOD","---> Inversion(Bit9) = 0x%x \n",u8Temp));
2126 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
2127 }
2128
2129 /************************************************************************************************
2130 Subject: Transport stream serial/parallel control
2131 Function: INTERN_DVBS_Serial_Control
2132 Parmeter: bEnable : TRUE For serial
2133 Return: MS_BOOL :
2134 Remark:
2135 *************************************************************************************************/
INTERN_DVBS_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)2136 MS_BOOL INTERN_DVBS_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
2137 {
2138 MS_U8 status = true;
2139 MS_U8 temp_val;
2140 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_ts... u8TSClk=%d\n", u8TSClk));
2141
2142 if (u8TSClk == 0xFF) u8TSClk=0x13;
2143 if (bEnable) //Serial mode for TS pad
2144 {
2145 // serial
2146 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
2147 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2148
2149 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
2150 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2151 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
2152 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2153 temp_val|=0x04;
2154 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2155 #else
2156 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
2157 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2158 temp_val|=0x07;
2159 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2160 #endif
2161 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
2162 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
2163
2164 //// INTERN_DVBS TS Control: Serial //////////
2165
2166 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, TS_SERIAL);
2167
2168 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2169 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 0);
2170 #else
2171 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 1);
2172 #endif
2173 gsCmdPacketDVBS.cmd_code = CMD_TS_CTRL;
2174
2175 gsCmdPacketDVBS.param[0] = TS_SERIAL;
2176 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2177 gsCmdPacketDVBS.param[1] = 0;//TS_CLK_NO_INV;
2178 #else
2179 gsCmdPacketDVBS.param[1] = 1;//TS_CLK_INVERSE;
2180 #endif
2181 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 2);
2182 }
2183 else
2184 {
2185 //parallel
2186 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
2187 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2188
2189 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2190 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2191 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2192 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
2193 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2194 temp_val|=0x05;
2195 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2196 #else
2197 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
2198 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2199 temp_val|=0x07;
2200 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2201 #endif
2202
2203 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
2204 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
2205
2206 //// INTERN_DVBS TS Control: Parallel //////////
2207
2208 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, TS_PARALLEL);
2209
2210 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2211 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 0);
2212 #else
2213 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 1);
2214 #endif
2215 //// INTERN_DVBC TS Control: Parallel //////////
2216 gsCmdPacketDVBS.cmd_code = CMD_TS_CTRL;
2217
2218 gsCmdPacketDVBS.param[0] = TS_PARALLEL;
2219 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2220 gsCmdPacketDVBS.param[1] = 0;//TS_CLK_NO_INV;
2221 #else
2222 gsCmdPacketDVBS.param[1] = 1;//TS_CLK_INVERSE;
2223 #endif
2224 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 2);
2225 }
2226
2227 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2228 DBG_INTERN_DVBS(ULOGD("DEMOD","---> Inversion(Bit5) = %d \n",0 ));
2229 #else
2230 DBG_INTERN_DVBS(ULOGD("DEMOD","---> Inversion(Bit5) = %d \n",1 ));
2231 #endif
2232
2233 INTERN_DVBS_Driving_Control(INTERN_DVBS_DTV_DRIVING_LEVEL);
2234 return status;
2235 }
2236
2237 /************************************************************************************************
2238 Subject: TS1 output control
2239 Function: INTERN_DVBS_PAD_TS1_Enable
2240 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
2241 Return: void
2242 Remark:
2243 *************************************************************************************************/
INTERN_DVBS_PAD_TS1_Enable(MS_BOOL flag)2244 void INTERN_DVBS_PAD_TS1_Enable(MS_BOOL flag)
2245 {
2246 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_TS1_Enable... \n"));
2247
2248 if(flag) // PAD_TS1 Enable TS CLK PAD
2249 {
2250 //printf("=== TS1_Enable ===\n");
2251 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
2252 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
2253 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
2254 }
2255 else // PAD_TS1 Disable TS CLK PAD
2256 {
2257 //printf("=== TS1_Disable ===\n");
2258 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
2259 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
2260 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
2261 }
2262 }
2263
2264 /************************************************************************************************
2265 Subject: channel change config
2266 Function: INTERN_DVBC_Config
2267 Parmeter: BW: bandwidth
2268 Return: MS_BOOL :
2269 Remark:
2270 *************************************************************************************************/
INTERN_DVBS_Config(MS_U32 u32SymbolRate,DMD_DVBS_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)2271 MS_BOOL INTERN_DVBS_Config(MS_U32 u32SymbolRate, DMD_DVBS_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
2272 {
2273
2274 MS_BOOL status= true;
2275 MS_U16 u16CenterFreq;
2276 // MS_U16 u16Fc = 0;
2277 MS_U8 temp_val;
2278 MS_U8 u8Data =0;
2279 MS_U8 u8counter = 0;
2280 //MS_U32 u32CurrentSR;
2281
2282 //u32CurrentSR = u32SymbolRate/1000; //KHz
2283
2284 //u32SymbolRate= u32SymbolRate/1000;//to match fw format
2285 u16CenterFreq =u32IFFreq;
2286 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_config+, QAM=%d, u32IFFreq=%d, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n", eQamMode, u32IFFreq, bSpecInv, bSerialTS, u8TSClk));
2287 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_Config, t = %d\n",MsOS_GetSystemTime()));
2288
2289 u8TSClk=0x05;//if (u8TSClk == 0xFF) u8TSClk=0x13;//set a fater speed for initial condition
2290 status &= INTERN_DVBS_Reset();
2291
2292 u8DemodLockFlag=0;
2293 /*
2294 // Symbol Rate
2295 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, u32CurrentSR&0xff);
2296 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, (u32CurrentSR>>8)&0xff);
2297 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, (u32CurrentSR>>16)&0xff);
2298 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config u32SymbolRate %d<<<\n", u32CurrentSR));
2299 */
2300 #if 0
2301 //======== check SR is right or not ===========
2302 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &u8Data);
2303 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L,u8Data));
2304 u32SR =u8Data;
2305 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &u8Data);
2306 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H,u8Data));
2307 u32SR =((U32)u8Data<<8)|u32SR ;
2308 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &u8Data);
2309 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MB_DMDTOP_DBG_5 addr=%d mailbox value=%d<<<\n", E_DMD_S2_MB_DMDTOP_DBG_5,u8Data));
2310 u32SR =((U32)u8Data<<16)|u32SR;
2311 //=================================================
2312 #endif
2313
2314 // IQ Swap ,ADCPLL IQ swap / DMDANA_IQ_SWAP
2315 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_IQ_SWAP, bSpecInv? 0x01:0x00);
2316 if(bSpecInv)
2317 {
2318 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DMDANA_REG_BASE+0xC0, &u8Data);//Demod\reg_dmdana.xls
2319 u8Data|=(0x02);
2320 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DMDANA_REG_BASE+0xC0, u8Data);
2321 }
2322
2323 // TS mode
2324 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, bSerialTS? 0x01:0x00);
2325 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Config TS Serial %d<<<\n", bSerialTS));
2326 _bSerialTS = bSerialTS;
2327
2328 if (bSerialTS)
2329 {
2330 // serial
2331 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2332 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2333
2334 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
2335 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2336 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2337 temp_val|=0x04;
2338 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2339 #else
2340 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2341 temp_val|=0x07;
2342 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2343 #endif
2344 }
2345 else
2346 {
2347 //parallel
2348 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2349 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2350
2351 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2352 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2353 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2354 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2355 temp_val|=0x05;
2356 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2357 #else
2358 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2359 temp_val|=0x07;
2360 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2361 #endif
2362 }
2363 #if (INTERN_DVBS_INTERNAL_DEBUG == 1)
2364 INTERN_DVBS_Show_Demod_Version();
2365 #endif
2366
2367 //-----------------------------------------------------------
2368 //From INTERN_DVBS_Demod_Restart function.
2369
2370 //FW sw reset
2371 //[0]: 0: SW Reset, 1: Start state machine
2372 //[1]: 1: Blind scan enable, 0: manual scan
2373 //[2]: 1: Code flow track enable
2374 //[3]: 1: go to AGC state
2375 //[4]: 1: set DiSEqC
2376 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2377 u8Data = (u8Data&0xF0)|0x01;
2378 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2379 //DBG_INTERN_DVBS(printf(">>>REG write check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2380 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2381 //DBG_INTERN_DVBS(printf(">>>REG read check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2382
2383 u8counter = 20;
2384 while( ((u8Data&0x01) == 0x00) && (u8counter != 0) )
2385 {
2386 MsOS_DelayTask(1);
2387 ULOGD("DEMOD","TOP_WR_DBG_90=0x%x, status=%d, u8counter=%d\n", u8Data, status, u8counter);
2388 u8Data|=0x01;
2389 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
2390 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
2391 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>(while)REG read check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2392 u8counter--;
2393 }
2394
2395 if((u8Data & 0x01)==0x00)
2396 {
2397 status = FALSE;
2398 }
2399
2400 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_config done\n"));
2401 return status;
2402 }
2403 /************************************************************************************************
2404 Subject: channel change config
2405 Function: INTERN_DVBS_Blind_Scan_Config
2406 Parmeter: BW: bandwidth
2407 Return: MS_BOOL :
2408 Remark:
2409 *************************************************************************************************/
INTERN_DVBS_BlindScan_Config(MS_U32 u32SymbolRate,DMD_DVBS_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)2410 MS_BOOL INTERN_DVBS_BlindScan_Config(MS_U32 u32SymbolRate, DMD_DVBS_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
2411 {
2412
2413 MS_BOOL status= true;
2414 MS_U16 u16CenterFreq;
2415 // MS_U16 u16Fc = 0;
2416 MS_U8 temp_val;
2417 MS_U8 u8Data=0;
2418 MS_U16 u16WaitCount = 0;
2419
2420 //MS_U32 u32CurrentSR;
2421
2422 //u32CurrentSR = u32SymbolRate/1000; //KHz
2423
2424 //u32SymbolRate= u32SymbolRate/1000;//to match fw format
2425 u16CenterFreq =u32IFFreq;
2426
2427 //DBG_INTERN_DVBS(printf(" @INTERN_DVBS_blindScan_Config+, SR=%d, QAM=%d, u32IFFreq=%d, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n", u32CurrentSR, eQamMode, u32IFFreq, bSpecInv, bSerialTS, u8TSClk));
2428 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_blindScan_Config, t = %d\n",MsOS_GetSystemTime()));
2429
2430 //status &= INTERN_DVBS_Reset();
2431 /*
2432 g_dvbs_lock = 0;
2433 u8DemodLockFlag=0;
2434 // Symbol Rate
2435 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, u32CurrentSR&0xff);
2436 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, (u32CurrentSR>>8)&0xff);
2437 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, (u32CurrentSR>>16)&0xff);
2438 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config u32SymbolRate %d<<<\n", u32CurrentSR));
2439 */
2440 #if 0
2441 //======== check SR is right or not ===========
2442 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &u8Data);
2443 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L,u8Data));
2444 u32SR =u8Data;
2445 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &u8Data);
2446 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H,u8Data));
2447 u32SR =((U32)u8Data<<8)|u32SR ;
2448 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &u8Data);
2449 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MB_DMDTOP_DBG_5 addr=%d mailbox value=%d<<<\n", E_DMD_S2_MB_DMDTOP_DBG_5,u8Data));
2450 u32SR =((U32)u8Data<<16)|u32SR;
2451 //=================================================
2452 #endif
2453
2454 // IQ Swap ,ADCPLL IQ swap / DMDANA_IQ_SWAP
2455 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_IQ_SWAP, bSpecInv? 0x01:0x00);
2456 if(bSpecInv)
2457 {
2458 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DMDANA_REG_BASE+0xC0, &u8Data);//Demod\reg_dmdana.xls
2459 u8Data|=(0x02);
2460 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DMDANA_REG_BASE+0xC0, u8Data);
2461 }
2462
2463 // TS mode
2464 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, bSerialTS? 0x01:0x00);
2465 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Config TS Serial %d<<<\n", bSerialTS));
2466 _bSerialTS = bSerialTS;
2467 u8TSClk=0x05;//if (u8TSClk == 0xFF) u8TSClk=0x13;//set a fater speed for initial condition
2468
2469 if (bSerialTS)
2470 {
2471 // serial
2472 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2473 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2474
2475 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
2476 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2477 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2478 temp_val|=0x04;
2479 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2480 #else
2481 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2482 temp_val|=0x07;
2483 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2484 #endif
2485 }
2486 else
2487 {
2488 //parallel
2489 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2490 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2491
2492 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2493 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2494 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2495 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2496 temp_val|=0x05;
2497 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2498 #else
2499 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2500 temp_val|=0x07;
2501 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2502 #endif
2503 }
2504 #if (INTERN_DVBS_INTERNAL_DEBUG == 1)
2505 INTERN_DVBS_Show_Demod_Version();
2506 #endif
2507
2508 //-----------------------------------------------------------
2509 //From INTERN_DVBS_Demod_Restart function.
2510
2511 //enable send DiSEqC
2512 //[0]: 0: SW Reset, 1: Start state machine
2513 //[1]: 1: Blind scan enable, 0: manual scan
2514 //[2]: 1: Code flow track enable
2515 //[3]: 1: go to AGC state
2516 //[4]: 1: set DiSEqC
2517 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2518 u8Data |= 0x08;
2519 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2520
2521 u16WaitCount=0;
2522 do
2523 {
2524 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
2525 u16WaitCount++;
2526 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
2527 MsOS_DelayTask(1);
2528 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
2529
2530 // disable blind scan
2531 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2532 u8Data&=~(0x02);
2533 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2534
2535 //disble send DiSEqC
2536 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2537 u8Data&=~(0x08);
2538 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2539
2540
2541 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_blindScan_Config done\n"));
2542 return status;
2543 }
2544
INTERN_DVBS_Power_ON_OFF(MS_U8 bPowerOn)2545 void INTERN_DVBS_Power_ON_OFF(MS_U8 bPowerOn)
2546 {
2547 bPowerOn = bPowerOn;
2548 }
2549
INTERN_DVBS_Power_Save(void)2550 MS_BOOL INTERN_DVBS_Power_Save(void)
2551 {
2552 return TRUE;
2553 }
2554 //------------------------------------------------------------------
2555 // END System Info Function
2556 //------------------------------------------------------------------
2557
2558 //------------------------------------------------------------------
2559 // Get And Show Info Function
2560 //------------------------------------------------------------------
2561 /************************************************************************************************
2562 Subject: enable hw to lock channel
2563 Function: INTERN_DVBS_Active
2564 Parmeter: bEnable
2565 Return: MS_BOOL
2566 Remark:
2567 *************************************************************************************************/
INTERN_DVBS_Active(MS_BOOL bEnable)2568 MS_BOOL INTERN_DVBS_Active(MS_BOOL bEnable)
2569 {
2570 MS_U8 status = TRUE;
2571 //MS_U8 u8Data;
2572
2573 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_Active\n"));
2574
2575 //// INTERN_DVBS Finite State Machine on/off //////////
2576 #if 0
2577 gsCmdPacketDVBC.cmd_code = CMD_FSM_CTRL;
2578
2579 gsCmdPacketDVBS.param[0] = (MS_U8)bEnable;
2580 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 1);
2581 #else
2582
2583 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
2584 #endif
2585
2586 bDMD_DVBS_NoChannelDetectedWithRFPower = FALSE;
2587 u32DMD_DVBS_NoChannelTimeAccWithRFPower = 0;
2588 return status;
2589 }
2590
INTERN_DVBS_GetTsDivNum(MS_U32 * u32SymbolRate,MS_U8 * system_type_reg,MS_U8 * code_rate_idx,MS_U8 * fec_type_idx,MS_U8 * pilot_flag,MS_U32 * u32temp,MS_U8 * code_rate_reg)2591 MS_BOOL INTERN_DVBS_GetTsDivNum(MS_U32 *u32SymbolRate, MS_U8* system_type_reg, MS_U8 *code_rate_idx, MS_U8 *fec_type_idx, MS_U8 *pilot_flag, MS_U32 *u32temp, MS_U8 *code_rate_reg)
2592 {
2593 MS_U8 u8Data = 0;
2594 MS_BOOL status = true;
2595 //MS_U32 u32SymbolRate=0;
2596 //float fSymbolRate;
2597 //MS_U8 ISSY_EN = 0;
2598 //MS_U8 code_rate_idx = 0;
2599 //MS_U8 pilot_flag = 0;
2600 // MS_U8 fec_type_idx = 0;
2601 MS_U8 mod_type_idx = 0;
2602 //MS_U16 k_bch_array[2][11] ={
2603 // {16008, 21408, 25728, 32208, 38688, 43040, 48408, 51648, 53840, 57472, 58192},
2604 // { 3072, 5232, 6312, 7032, 9552, 10632, 11712, 12432, 13152, 14232, 0}};
2605 //MS_U16 n_ldpc_array[2] = {64800, 16200};
2606 //MS_FLOAT pilot_term = 0;
2607 //MS_FLOAT k_bch;
2608 //MS_FLOAT n_ldpc;
2609 //MS_FLOAT ts_div_num_offset = 2.0;
2610 //MS_U32 u32Time_start,u32Time_end;
2611 //MS_U32 u32temp;
2612 //MS_FLOAT pkt_interval;
2613 //MS_U8 time_counter=0;
2614
2615 INTERN_DVBS_GetCurrentSymbolRate(u32SymbolRate);
2616 //fSymbolRate=u32SymbolRate+0.0;///1000.0;//Symbol Rate(KHz)
2617 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum u32SymbolRate=%d\n", *u32SymbolRate));
2618 // DMD_DVBS_MODULATION_TYPE pQAMMode;
2619
2620 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//V
2621 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum GetCurrentDemodType E_DMD_S2_SYSTEM_TYPE=%d\n", u8Data));//u8Data:0 is S2; 1 is DVBS
2622 *system_type_reg=u8Data;
2623 if(!u8Data)//DVBS2
2624 {
2625 /*
2626 //Get DVBS2 Code Rate
2627 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);//V
2628 printf("[S2]INTERN_DVBS_GetTsDivNum DVBS2 E_DMD_S2_CODERATE=0x%x\n", u8Data);
2629 switch (u8Data)
2630 {
2631 case 0x03: //CR 1/2
2632 k_bch=32208.0;
2633 _u8_DVBS2_CurrentCodeRate = 5;
2634 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_2\n"));
2635 break;
2636 case 0x01: //CR 1/3
2637 k_bch=21408.0; //8PSK???
2638 _u8_DVBS2_CurrentCodeRate = 6;
2639 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_3\n"));
2640 break;
2641 case 0x05: //CR 2/3
2642 k_bch=43040.0;
2643 _u8_DVBS2_CurrentCodeRate = 7;
2644 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=2_3\n"));
2645 break;
2646 case 0x00: //CR 1/4
2647 k_bch=16008.0; //8PSK???
2648 _u8_DVBS2_CurrentCodeRate = 8;
2649 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_4\n"));
2650 break;
2651 case 0x06: //CR 3/4
2652 k_bch=48408.0;
2653 _u8_DVBS2_CurrentCodeRate = 9;
2654 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=3_4\n"));
2655 break;
2656 case 0x02: //CR 2/5
2657 k_bch=25728.0; //8PSK???
2658 _u8_DVBS2_CurrentCodeRate = 10;
2659 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=2_5\n"));
2660 break;
2661 case 0x04: //CR 3/5
2662 k_bch=38688.0;
2663 _u8_DVBS2_CurrentCodeRate = 11;
2664 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=3_5\n"));
2665 break;
2666 case 0x07: //CR 4/5
2667 k_bch=51648.0;
2668 _u8_DVBS2_CurrentCodeRate = 12;
2669 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=4_5\n"));
2670 break;
2671 case 0x08: //CR 5/6
2672 k_bch=53840.0;
2673 _u8_DVBS2_CurrentCodeRate = 13;
2674 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=5_6\n"));
2675 break;
2676 case 0x09: //CR 8/9
2677 k_bch=57472.0;
2678 _u8_DVBS2_CurrentCodeRate = 14;
2679 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=8_9\n"));
2680 break;
2681 case 0x0A: //CR 9/10
2682 k_bch=58192.0;
2683 _u8_DVBS2_CurrentCodeRate = 15;
2684 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=9_10\n"));
2685 break;
2686 default:
2687 k_bch=58192.0;
2688 _u8_DVBS2_CurrentCodeRate = 15;
2689 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate= default 9_10\n"));
2690 break;
2691 } //printf("INTERN_DVBS_GetTsDivNum k_bch=%ld\n", (MS_U32)k_bch);
2692 */
2693 //INTERN_DVBS_GetCurrentModulationType(&pQAMMode); //V
2694 //printf("INTERN_DVBS_GetTsDivNum Mod_order=%d\n", modulation_order);
2695
2696 // pilot_flag => 0 : off 1 : on
2697 // fec_type_idx => 0 : normal 1 : short
2698 // mod_type_idx => 0 : QPSK 1 : 8PSK 2 : 16APSK 3 : 32APSK
2699 // code_rate_idx => d0: 1/4, d1: 1/3, d2: 2/5, d3: 1/2, d4: 3/5, d5: 2/3, d6: 3/4, d7: 4/5, d8: 5/6, d9: 8/9, d10: 9/10
2700 //set TS clock rate
2701 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, code_rate_idx);
2702 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FEC_TYPE, fec_type_idx);
2703 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MOD_TYPE, &mod_type_idx);
2704 modulation_order = mod_type_idx;
2705 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_PILOT_FLAG, pilot_flag);
2706 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_PILOT_FLAG, &u8Data);
2707
2708 /*
2709 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_ISSY_ACTIVE, ISSY_EN);
2710 if(*ISSY_EN==0)
2711 {
2712 k_bch = k_bch_array[fec_type_idx][code_rate_idx];
2713 n_ldpc = n_ldpc_array[fec_type_idx];
2714 pilot_term = ((float) n_ldpc / modulation_order / 1440 * 36) * pilot_flag;
2715 if(sDMD_DVBS_Info.bSerialTS)//serial mode
2716 {
2717 *fTSDivNum =(288000.0/(k_bch/((n_ldpc/modulation_order+90+pilot_term)/u32SymbolRate)) - ts_div_num_offset);
2718 *fTSDivNum = (*fTSDivNum-1)/2;// since 288/(2(fTSDivNum+1)) = 288/TS_RATE = A ==> fTSDivNum = (A-1)/2
2719 }
2720 else//parallel mode
2721 {
2722 *fTSDivNum = (288000.0/(k_bch/((n_ldpc/modulation_order+90+pilot_term)/u32SymbolRate)/8) - ts_div_num_offset);
2723 *fTSDivNum = (*fTSDivNum-1)/2;
2724 }
2725 }
2726 else if(*ISSY_EN==1)//ISSY = 1
2727 {
2728 //u32Time_start = msAPI_Timer_GetTime0();
2729 time_counter=0;
2730 do
2731 {
2732 MDrv_SYS_DMD_VD_MBX_ReadReg((0x3E00 + 0x4D*2), &u8Data);//DVBS2OPPRO_ISCR_CAL_DONE (_REG_DVBS2OPPRO(0x4D)+0)
2733 u8Data &= 0x01;
2734 // u32Time_end =msAPI_Timer_GetTime0();
2735 MsOS_DelayTask(1);
2736 time_counter = time_counter +1;
2737 }while( (u8Data!=0x01) && ( (time_counter )< 50) );
2738
2739 //read pkt interval
2740 MDrv_SYS_DMD_VD_MBX_ReadReg((0x3E00 + 0x70*2), &u8Data);
2741 *u32temp = u8Data;
2742 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x70*2+1), &u8Data);
2743 *u32temp |= (MS_U32)u8Data<<8;
2744 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x71*2), &u8Data);
2745 *u32temp |= (MS_U32)u8Data<<16;
2746 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x71*2+1), &u8Data);
2747 *u32temp |= (MS_U32)u8Data<<24;
2748
2749 pkt_interval = (MS_FLOAT) u32temp / 1024.0;
2750 if(sDMD_DVBS_Info.bSerialTS)//serial mode
2751 {
2752 *fTSDivNum=288000.0 / (188*8*u32SymbolRate/pkt_interval) - ts_div_num_offset;
2753 *fTSDivNum = (*fTSDivNum-1)/2;
2754 }
2755 else
2756 {
2757 *fTSDivNum=288000.0 / (188*u32SymbolRate/pkt_interval) - ts_div_num_offset;
2758 *fTSDivNum = (*fTSDivNum-1)/2;
2759 }
2760
2761 }
2762 else
2763 {
2764 // *fTSDivNum =0x0A;
2765 }
2766
2767 if(*fTSDivNum>255)
2768 *fTSDivNum=255;
2769 if(*fTSDivNum<1)
2770 *fTSDivNum=1;
2771 */
2772 #if 0
2773 //printf("INTERN_DVBS_GetTsDivNum Pilot E_DMD_S2_MB_DMDTOP_DBG_9=%d\n", u8Data);
2774 /*if(u8Data) // Pilot ON
2775 printf(">>>INTERN_DVBS_GetTsDivNum Pilot ON<<<\n");
2776 else //Pilot off
2777 printf(">>>INTERN_DVBS_GetTsDivNum Pilot off<<<\n");
2778 */
2779 if(_bSerialTS)
2780 {
2781 if(u8Data)//if pilot ON
2782 {
2783 if(modulation_order==2)
2784 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90+36*22)/u32SymbolRate)) - 3);
2785 else if(modulation_order==3)
2786 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90+36*15)/u32SymbolRate)) - 3);
2787 }
2788 else
2789 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90)/u32SymbolRate)) - 3);
2790 }
2791 else//Parallel mode
2792 {
2793 if(u8Data)
2794 {
2795 if(modulation_order==2)
2796 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0+36*22)/u32SymbolRate)/8.0) - 3);
2797 else if(modulation_order==3)
2798 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0+36*15)/u32SymbolRate)/8.0) - 3);
2799 }
2800 else
2801 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0)/u32SymbolRate)/8.0) - 3);
2802 }
2803 #endif
2804 }
2805 else //S
2806 {
2807 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE + 0x3A*2, &u8Data);
2808 //u8_gCodeRate = (u8Data & 0x70)>>4;
2809 //DVBS Code Rate
2810 //switch (u8_gCodeRate)
2811 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
2812 *code_rate_reg=u8Data;
2813 switch (u8Data)
2814 {
2815 case 0x00: //CR 1/2
2816 _u8_DVBS2_CurrentCodeRate = 0;
2817 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=1_2\n"));
2818 /*
2819 if(sDMD_DVBS_Info.bSerialTS)
2820 *fTSDivNum = (288000.0/((1.0/2.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2821 else
2822 *fTSDivNum = (288000.0/((1.0/2.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2823
2824 *fTSDivNum = (*fTSDivNum-1)/2;
2825 if(*fTSDivNum>255)
2826 *fTSDivNum=255;
2827 if(*fTSDivNum<1)
2828 *fTSDivNum=1;
2829 */
2830 break;
2831 case 0x01: //CR 2/3
2832 _u8_DVBS2_CurrentCodeRate = 1;
2833 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=2_3\n"));
2834 /*
2835 if(sDMD_DVBS_Info.bSerialTS)
2836 *fTSDivNum = (MS_U8)(288000.0/((2.0/3.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2837 else
2838 *fTSDivNum = (MS_U8)(288000.0/((2.0/3.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2839
2840 *fTSDivNum = (*fTSDivNum-1)/2;
2841 if(*fTSDivNum>255)
2842 *fTSDivNum=255;
2843 if(*fTSDivNum<1)
2844 *fTSDivNum=1;
2845 */
2846 break;
2847 case 0x02: //CR 3/4
2848 _u8_DVBS2_CurrentCodeRate = 2;
2849 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=3_4\n"));
2850 /*
2851 if(sDMD_DVBS_Info.bSerialTS)
2852 *fTSDivNum = (288000.0/((3.0/4.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2853 else
2854 *fTSDivNum = (288000.0/((3.0/4.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2855 *fTSDivNum = (*fTSDivNum-1)/2;
2856 if(*fTSDivNum>255)
2857 *fTSDivNum=255;
2858 if(*fTSDivNum<1)
2859 *fTSDivNum=1;
2860 */
2861 break;
2862 case 0x03: //CR 5/6
2863 _u8_DVBS2_CurrentCodeRate = 3;
2864 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=5_6\n"));
2865 /*
2866 if(sDMD_DVBS_Info.bSerialTS)
2867 *fTSDivNum = (288000.0/((5.0/6.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2868 else
2869 *fTSDivNum = (288000.0/((5.0/6.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2870
2871 *fTSDivNum = (*fTSDivNum-1)/2;
2872 if(*fTSDivNum>255)
2873 *fTSDivNum=255;
2874 if(*fTSDivNum<1)
2875 *fTSDivNum=1;
2876 */
2877 break;
2878 case 0x04: //CR 7/8
2879 _u8_DVBS2_CurrentCodeRate = 4;
2880 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=7_8\n"));
2881 /*
2882 if(sDMD_DVBS_Info.bSerialTS)
2883 *fTSDivNum =(288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2884 else
2885 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2886
2887 *fTSDivNum = (*fTSDivNum-1)/2;
2888 if(*fTSDivNum>255)
2889 *fTSDivNum=255;
2890 if(*fTSDivNum<1)
2891 *fTSDivNum=1;
2892 */
2893 break;
2894 default:
2895 _u8_DVBS2_CurrentCodeRate = 4;
2896 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate= default 7_8\n"));
2897 /*
2898 if(sDMD_DVBS_Info.bSerialTS)
2899 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2900 else
2901 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2902
2903 *fTSDivNum = (*fTSDivNum-1)/2;
2904 if(*fTSDivNum>255)
2905 *fTSDivNum=255;
2906 if(*fTSDivNum<1)
2907 *fTSDivNum=1;
2908 */
2909 break;
2910 }
2911 } //printf("INTERN_DVBS_GetTsDivNum u8TSClk = 0x%x\n", *u8TSDivNum);
2912 return status;
2913 }
2914
INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK_TYPE eType,MS_U16 fCurrRFPowerDbm,MS_U16 fNoChannelRFPowerDbm,MS_U32 u32TimeInterval)2915 MS_BOOL INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK_TYPE eType, MS_U16 fCurrRFPowerDbm, MS_U16 fNoChannelRFPowerDbm, MS_U32 u32TimeInterval)
2916 {
2917 MS_U8 u8Data =0; //MS_U8 u8Data2 =0;
2918 MS_U8 bRet = TRUE;
2919 //MS_FLOAT fTSDivNum=0;
2920
2921 switch( eType )
2922 {
2923 case DMD_DVBS_GETLOCK:
2924 #if (INTERN_DVBS_INTERNAL_DEBUG)
2925 INTERN_DVBS_info();
2926 #endif
2927 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2928 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_GetLock manual tune=%d<<<\n", u8Data));
2929 if ((u8Data&0x02)==0x00)//manual mode
2930 {
2931 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);
2932 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_GetLock MailBox state=%d<<<\n", u8Data));
2933
2934 if((u8Data == 15) || (u8Data == 16))
2935 {
2936 if (u8Data==15)
2937 {
2938 _bDemodType=FALSE; //S
2939 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Demod DVBS Lock<<<\n"));
2940 }
2941 else if(u8Data==16)
2942 {
2943 _bDemodType=TRUE; //S2
2944 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Demod DVBS2 Lock<<<\n"));
2945 }
2946 if(g_dvbs_lock == 0)
2947 {
2948 g_dvbs_lock = 1;
2949 }
2950
2951 if(u8DemodLockFlag==0)
2952 {
2953 u8DemodLockFlag=1;
2954
2955 // caculate TS clock divider number
2956 /*
2957 INTERN_DVBS_GetTsDivNum(&fTSDivNum); //ts_div_num
2958 u8Data = (MS_U8)fTSDivNum;
2959 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_GetLock TsClkDivNum = 0x%x<<<\n", u8Data));
2960
2961 if (u8Data > 0x1F)
2962 u8Data=0x1F;
2963 //if (u8Data < 0x05) u8Data=0x05;
2964 HAL_DMD_RIU_WriteByte(0x103300, u8Data);
2965
2966 //Ts Output Enable
2967 HAL_DMD_RIU_WriteByte(0x101eaa,0x10);
2968 */
2969 }
2970 DBG_INTERN_DVBS(ULOGD("DEMOD","@INTERN_DVBS_Demod Lock+++\n"));
2971 bRet = TRUE;
2972 }
2973 else
2974 {
2975 if(g_dvbs_lock == 1)
2976 {
2977 g_dvbs_lock = 0;
2978 u8DemodLockFlag=0;
2979 }
2980 DBG_INTERN_DVBS(ULOGD("DEMOD","@INTERN_DVBS_Demod UnLock---\n"));
2981 bRet = FALSE;
2982 }
2983
2984 if(_bSerialTS==1)
2985 {
2986 if (bRet==FALSE)
2987 {
2988 _bTSDataSwap=FALSE;
2989 }
2990 else
2991 {
2992 if (_bTSDataSwap==FALSE)
2993 {
2994 _bTSDataSwap=TRUE;
2995 MDrv_SYS_DMD_VD_MBX_ReadReg( (DVBTM_REG_BASE + 0x20*2), &u8Data);//DVBTM_REG_BASE
2996 u8Data^=0x20;//h0020 h0020 5 5 reg_ts_data_reverse
2997 MDrv_SYS_DMD_VD_MBX_WriteReg( (DVBTM_REG_BASE + 0x20*2), u8Data);
2998 }
2999 }
3000 }
3001 }
3002 else
3003 {
3004 bRet = TRUE;
3005 }
3006 break;
3007
3008 default:
3009 bRet = FALSE;
3010 }
3011 return bRet;
3012 }
3013
INTERN_DVBS_GetTunrSignalLevel_PWR(MS_U16 * u16Data)3014 MS_BOOL INTERN_DVBS_GetTunrSignalLevel_PWR(MS_U16 *u16Data)// Need check debug out table
3015 {
3016 MS_BOOL status=TRUE;
3017 MS_U8 u8Data =0;
3018 //MS_U8 u8Index =0;
3019 //float fCableLess = 0.0;
3020 /*
3021 if (FALSE == INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0) )//Demod unlock
3022 {
3023 fCableLess = 0;
3024 }
3025 */
3026 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x11*2, &u8Data);//FRONTEND_AGC_DEBUG_SEL
3027 u8Data=(u8Data&0xF0)|0x03;
3028 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x11*2, u8Data);
3029
3030 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x02, &u8Data);//FRONTEND_LATCH
3031 u8Data|=0x80;
3032 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x02, u8Data);
3033
3034 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x12*2+1, &u8Data);//FRONTEND_AGC_DEBUG_OUT_R1
3035 *u16Data=u8Data;
3036 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x12*2, &u8Data);//FRONTEND_AGC_DEBUG_OUT_R0
3037 *u16Data=(*u16Data<<8)|u8Data;
3038 //printf("===========================Tuner 65535-u16Data = %d\n", (65535-u16Data));
3039 //MsOS_DelayTask(400);
3040
3041 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x02, &u8Data);//FRONTEND_LOAD0
3042 u8Data&=~(0x80);
3043 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x02, u8Data);
3044 /*
3045 if (status==FALSE)
3046 {
3047 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS GetSignalStrength fail!!! \n "));
3048 fCableLess = 0;
3049 }
3050 */
3051 // printf("#### INTERN_DVBS_GetTunrSignalLevel_PWR u16Data = %d\n", (int)u16Data);
3052 /*
3053 for (u8Index=0; u8Index < (sizeof(_u16SignalLevel)/sizeof(_u16SignalLevel[0])); u8Index++)
3054 {
3055 if ((65535 - u16Data) <= _u16SignalLevel[u8Index][0])
3056 {
3057 if (u8Index >=1)
3058 {
3059 fCableLess = (float)(_u16SignalLevel[u8Index][1])+((float)(_u16SignalLevel[u8Index][0] - (65535 - u16Data)) / (float)(_u16SignalLevel[u8Index][0] - _u16SignalLevel[u8Index-1][0]))*(float)(_u16SignalLevel[u8Index-1][1] - _u16SignalLevel[u8Index][1]);
3060 }
3061 else
3062 {
3063 fCableLess = _u16SignalLevel[u8Index][1];
3064 }
3065 }
3066 }
3067 //---------------------------------------------------
3068 if (fCableLess >= 350)
3069 fCableLess = fCableLess - 35;
3070 else if ((fCableLess < 350) && (fCableLess >= 250))
3071 fCableLess = fCableLess - 25;
3072 else
3073 fCableLess = fCableLess - 5;
3074
3075 if (fCableLess < 0)
3076 fCableLess = 0;
3077 if (fCableLess > 920)
3078 fCableLess = 920;
3079
3080 fCableLess = (-1.0)*(fCableLess/10.0);
3081
3082 //printf("===========================fCableLess2 = %.2f\n",fCableLess);
3083
3084 DBG_INTERN_DVBS(printf("INTERN_DVBS GetSignalStrength %f\n", fCableLess));
3085 */
3086 return status;
3087 }
3088
3089 /****************************************************************************
3090 Subject: To get the Post viterbi BER
3091 Function: INTERN_DVBS_GetPostViterbiBer
3092 Parmeter: Quility
3093 Return: E_RESULT_SUCCESS
3094 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBC_VIT_STATUS_NG
3095 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
3096 We will not read the Period, and have the "/256/8"
3097 *****************************************************************************/
3098
INTERN_DVBS_GetPostViterbiBer(MS_U32 * BitErr,MS_U16 * BitErrPeriod)3099 MS_BOOL INTERN_DVBS_GetPostViterbiBer(MS_U32 *BitErr, MS_U16 *BitErrPeriod)//POST BER //V
3100 {
3101 MS_BOOL status = true;
3102 MS_U8 reg = 0, reg_frz = 0;
3103 //MS_U16 BitErrPeriod;
3104 //MS_U32 BitErr;
3105
3106 /////////// Post-Viterbi BER /////////////After Viterbi
3107
3108 // freeze ,DVBSRS_BACKEND_BIT_ERR_NUM_FREEZE
3109 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1*2+1, ®_frz);//h0001 h0001 8 8 reg_ber_en
3110 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x1*2+1, reg_frz|0x01);
3111
3112 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0 ,DVBSFEC_BIT_ERR_SBLPRD_7_0
3113 // 0x47 [15:8] reg_bit_err_sblprd_15_8
3114 //KRIS register table
3115 //h0018 h0018 7 0 reg_bit_err_sblprd_7_0
3116 //h0018 h0018 15 8 reg_bit_err_sblprd_15_8
3117 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x18*2+1, ®);
3118 *BitErrPeriod = reg;
3119
3120 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x18*2, ®);
3121 *BitErrPeriod = (*BitErrPeriod << 8)|reg;
3122
3123
3124 //h001d h001d 7 0 reg_bit_err_num_7_0
3125 //h001d h001d 15 8 reg_bit_err_num_15_8
3126 //h001e h001e 7 0 reg_bit_err_num_23_16
3127 //h001e h001e 15 8 reg_bit_err_num_31_24
3128
3129 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1E*2+1, ®);
3130 *BitErr = reg;
3131 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1E*2, ®);
3132 *BitErr = (*BitErr << 8)|reg;
3133 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1D*2+1, ®);
3134 *BitErr = (*BitErr << 8)|reg;
3135 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1D*2, ®);
3136 *BitErr = (*BitErr << 8)|reg;
3137
3138 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
3139 reg_frz=reg_frz&(~0x01);
3140 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x1*2+1, reg_frz);
3141 /*
3142 if (BitErrPeriod == 0 ) //PRD
3143 BitErrPeriod = 1;
3144
3145 if (BitErr <= 0 )
3146 *postber = 0.5f / ((float)BitErrPeriod*128*188*8);
3147 else
3148 *postber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
3149
3150 if (*postber <= 0.0f)
3151 *postber = 1.0e-10f;
3152
3153 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS PostVitBER = %8.3e \n", *postber));
3154 */
3155 return status;
3156 }
3157
3158
INTERN_DVBS_GetPreViterbiBer(float * preber)3159 MS_BOOL INTERN_DVBS_GetPreViterbiBer(float *preber)//PER BER // not yet
3160 {
3161 MS_BOOL status = true;
3162 //MS_U8 reg = 0, reg_frz = 0;
3163 //MS_U16 BitErrPeriod;
3164 //MS_U32 BitErr;
3165
3166 #if 0
3167 /////////// Pre-Viterbi BER /////////////Before Viterbi
3168
3169 // freeze ,DVBSRS_BACKEND_BIT_ERR_NUM_FREEZE
3170 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x10, ®_frz);
3171 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSTFEC_REG_BASE+0x10, reg_frz|0x08);
3172
3173 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0 ,DVBSFEC_BIT_ERR_SBLPRD_7_0
3174 // 0x47 [15:8] reg_bit_err_sblprd_15_8
3175 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x19, ®);
3176 BitErrPeriod = reg;
3177
3178 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x18, ®);
3179 BitErrPeriod = (BitErrPeriod << 8)|reg;
3180
3181 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x17, ®);
3182 BitErrPeriod = (BitErrPeriod << 8)|reg;
3183
3184 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x16, ®);
3185 BitErrPeriod = (BitErrPeriod << 8)|reg;
3186 BitErrPeriod = (BitErrPeriod & 0x3FFF);
3187
3188 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
3189 // 0x6b [15:8] reg_bit_err_num_15_8
3190 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
3191 // 0x6d [15:8] reg_bit_err_num_31_24
3192 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x1F, ®);
3193 BitErr = reg;
3194
3195 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x1E, ®);
3196 BitErr = (BitErr << 8)|reg;
3197
3198 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
3199 reg_frz=reg_frz&(~0x08);
3200 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x10, reg_frz);
3201
3202 if (BitErrPeriod ==0 )//protect 0
3203 BitErrPeriod=1;
3204 if (BitErr <=0 )
3205 *perber=0.5f / (float)BitErrPeriod / 256;
3206 else
3207 *perber=(float)BitErr / (float)BitErrPeriod / 256;
3208
3209 if (*perber <= 0.0f)
3210 *perber = 1.0e-10f;
3211
3212 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS PerVitBER = %8.3e \n", *perber));
3213 #endif
3214
3215 return status;
3216 }
3217
3218 /****************************************************************************
3219 Subject: To get the Packet error
3220 Function: INTERN_DVBS_GetPacketErr
3221 Parmeter: pktErr
3222 Return: E_RESULT_SUCCESS
3223 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
3224 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
3225 We will not read the Period, and have the "/256/8"
3226 *****************************************************************************/
INTERN_DVBS_GetPacketErr(MS_U16 * pktErr)3227 MS_BOOL INTERN_DVBS_GetPacketErr(MS_U16 *pktErr)//V
3228 {
3229 MS_BOOL status = true;
3230 MS_U8 u8Data = 0;
3231 MS_U16 u16PktErr = 0;
3232
3233 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);
3234 if(!u8Data) //DVB-S2
3235 {
3236 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x02*2, &u8Data);//DVBS2FEC_OUTER_FREEZE (_REG_DVBS2FEC(0x02)+0) //[0]
3237 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE+0x02*2, u8Data|0x01);
3238
3239 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x26*2+1, &u8Data);//DVBS2FEC_BCH_EFLAG2_SUM1 (_REG_DVBS2FEC(0x2B)+1)
3240 u16PktErr = u8Data;
3241 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x26*2, &u8Data);
3242 u16PktErr = (u16PktErr << 8)|u8Data;
3243
3244 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x02*2, &u8Data);
3245 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE+0x02*2, u8Data&(~0x01));
3246 }
3247 else
3248 { //DVB-S
3249 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x19*2, &u8Data); //0x19 [7] reg_bit_err_num_freeze
3250 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x19*2, u8Data|0x80);
3251
3252 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(REG_BACKEND+0x33*2+1, &u8Data);// DVBSFEC_UNCRT_PKT_NUM_15_8 (_REG_DVBSFEC(0x1F)+1)
3253 u16PktErr = u8Data;
3254 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(REG_BACKEND+0x33*2, &u8Data);
3255 u16PktErr = (u16PktErr << 8)|u8Data;
3256
3257 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x19*2, &u8Data); //0x19 [7] reg_bit_err_num_freeze
3258 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x19*2, u8Data&(~0x80));
3259 }
3260 *pktErr = u16PktErr;
3261
3262 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS PktErr = %d \n", (int)u16PktErr));
3263
3264 return status;
3265 }
3266
3267 /****************************************************************************
3268 Subject: Read the signal to noise ratio (SNR)
3269 Function: INTERN_DVBS_GetSNR
3270 Parmeter: None
3271 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
3272 Remark:
3273 *****************************************************************************/
3274
INTERN_DVBS_GetSNR(MS_U32 * u32NDA_SNR_A,MS_U32 * u32NDA_SNR_AB)3275 MS_BOOL INTERN_DVBS_GetSNR(MS_U32 *u32NDA_SNR_A, MS_U32 *u32NDA_SNR_AB)//V
3276 {
3277 MS_BOOL status= TRUE;
3278 MS_U8 u8Data =0, reg_frz =0;
3279 //NDA SNR
3280 // MS_U32 u32NDA_SNR_A =0;
3281 //MS_U32 u32NDA_SNR_AB =0;
3282 //NDA SNR
3283 //float NDA_SNR_A =0.0;
3284 //float NDA_SNR_AB =0.0;
3285 //float NDA_SNR =0.0;
3286 //double NDA_SNR_LINEAR=0.0;
3287 //float snr_poly =0.0;
3288 //float Fixed_SNR =0.0;
3289 /*
3290 if (INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0)== FALSE)
3291 {
3292 return 0;
3293 }
3294 */
3295 // freeze
3296 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE+0x04*2, ®_frz);
3297 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_INNER_REG_BASE+0x04*2, reg_frz|0x10);//INNE_LATCH bit[4]
3298
3299 //NDA SNR_A
3300 // read Linear_SNR
3301 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x47*2, &u8Data);
3302 *u32NDA_SNR_A=(u8Data&0x03);
3303 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x46*2 + 1, &u8Data);
3304 *u32NDA_SNR_A=(*u32NDA_SNR_A<<8)|u8Data;
3305 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x46*2, &u8Data);
3306 *u32NDA_SNR_A=(*u32NDA_SNR_A<<8)|u8Data;
3307 //NDA SNR_AB
3308 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x49*2+1, &u8Data);
3309 *u32NDA_SNR_AB=(u8Data&0x3F);
3310 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x49*2, &u8Data);
3311 *u32NDA_SNR_AB = (*u32NDA_SNR_AB<<8)|u8Data;
3312 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x48*2 + 1, &u8Data);
3313 *u32NDA_SNR_AB=(*u32NDA_SNR_AB<<8)|u8Data;
3314 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x48*2, &u8Data);
3315 *u32NDA_SNR_AB=(*u32NDA_SNR_AB<<8)|u8Data;
3316
3317 //UN_freeze
3318 reg_frz=reg_frz&(~0x10);
3319 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_INNER_REG_BASE+0x08, reg_frz);
3320
3321 if (status== FALSE)
3322 {
3323 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetSNR Fail! \n"));
3324 return 0;
3325 }
3326
3327 //NDA SNR
3328 //NDA_SNR_A=(float)u32NDA_SNR_A/65536;
3329 //NDA_SNR_AB=(float)u32NDA_SNR_AB/4194304;
3330 //
3331 //since support 16,32APSK we need to add judgement
3332 /*
3333 if(modulation_order==4)
3334 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB/(2-1.252295758529242));//for 16APSK CR2/3
3335 else if(modulation_order==5)//(2-1.41333232789)
3336 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB/(2-1.41333232789));//for 32APSK CR3/4
3337 else
3338 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB);
3339
3340 NDA_SNR_LINEAR =(1/((NDA_SNR_A/NDA_SNR_AB)-1)) ;
3341
3342 if(NDA_SNR_LINEAR<=0)
3343 NDA_SNR=1.0;
3344 else
3345 NDA_SNR=10*log10(NDA_SNR_LINEAR);
3346
3347 //printf("[DVBS]: NDA_SNR ================================: %.1f\n", NDA_SNR);
3348 _f_DVBS_CurrentSNR = NDA_SNR;
3349 */
3350 /*
3351 //[DVBS/S2, QPSK/8PSK, 1/2~9/10 the same CN]
3352 snr_poly = 0.0; //use Polynomial curve fitting to fix SNR
3353 snr_poly = 0.005261367463671*pow(NDA_SNR, 3)-0.116517828301214*pow(NDA_SNR, 2)+0.744836970505452*pow(NDA_SNR, 1)-0.86727609780167;
3354 Fixed_SNR = NDA_SNR + snr_poly;
3355 //printf("[DVBS]: NDA_SNR + snr_poly =====================: %.1f\n", Fixed_SNR);
3356
3357 if (Fixed_SNR < 17.0)
3358 Fixed_SNR = Fixed_SNR;
3359 else if ((Fixed_SNR < 20.0) && (Fixed_SNR >= 17.0))
3360 Fixed_SNR = Fixed_SNR - 0.8;
3361 else if ((Fixed_SNR < 22.5) && (Fixed_SNR >= 20.0))
3362 Fixed_SNR = Fixed_SNR - 2.0;
3363 else if ((Fixed_SNR < 27.0) && (Fixed_SNR >= 22.5))
3364 Fixed_SNR = Fixed_SNR - 3.0;
3365 else if ((Fixed_SNR < 29.0) && (Fixed_SNR >= 27.0))
3366 Fixed_SNR = Fixed_SNR - 3.5;
3367 else if (Fixed_SNR >= 29.0)
3368 Fixed_SNR = Fixed_SNR - 3.0;
3369
3370 if (Fixed_SNR < 1.0)
3371 Fixed_SNR = 1.0;
3372 if (Fixed_SNR > 30.0)
3373 Fixed_SNR = 30.0;
3374 */
3375 //*f_snr = NDA_SNR;
3376 //printf("[DVBS]: NDA_SNR=============================: %.1f\n", NDA_SNR);
3377
3378 return status;
3379 }
3380
INTERN_DVBS_GetIFAGC(MS_U8 * ifagc_reg,MS_U8 * ifagc_reg_lsb,MS_U16 * ifagc_err)3381 MS_BOOL INTERN_DVBS_GetIFAGC(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err)
3382 {
3383 MS_BOOL status = true;
3384
3385 status = HAL_DMD_IFAGC_RegRead(ifagc_reg, ifagc_reg_lsb, ifagc_err);
3386
3387 return status;
3388 }
3389
3390 //SSI
INTERN_DVBS_GetSignalStrength(MS_U16 fRFPowerDbm,DMD_DVBS_DEMOD_TYPE * pDemodType,MS_U8 * u8_DVBS2_CurrentCodeRateLocal,MS_U8 * u8_DVBS2_CurrentConstellationLocal)3391 MS_BOOL INTERN_DVBS_GetSignalStrength(MS_U16 fRFPowerDbm, DMD_DVBS_DEMOD_TYPE *pDemodType, MS_U8 *u8_DVBS2_CurrentCodeRateLocal, MS_U8 *u8_DVBS2_CurrentConstellationLocal)
3392 {
3393 //-1.2~-92.2 dBm
3394 MS_BOOL status = true;
3395 MS_U8 u8Data =0;
3396 //MS_U8 _u8_DVBS2_CurrentCodeRateLocal = 0;
3397 //float ch_power_db=0.0f, ch_power_db_rel=0.0f;
3398 MS_U8 u8Data2 = 0;
3399 //MS_U8 _u8_DVBS2_CurrentConstellationLocal = 0;
3400 //DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3401
3402 //DBG_INTERN_DVBS_TIME(printf("INTERN_DVBS_GetSignalStrength, t=%ld, RF level=%f, Table=%lx\n",MsOS_GetSystemTime(), fRFPowerDbm, (MS_U32)(sDMD_DVBS_InitData->pTuner_RfagcSsi)));
3403
3404 // if (INTERN_DVBC_Lock(COFDM_TPS_LOCK))
3405 // if (INTERN_DVBC_Lock(COFDM_AGC_LOCK))
3406 // Actually, it's more reasonable, that signal level depended on cable input power level
3407 // thougth the signal isn't dvb-t signal.
3408 //
3409 // use pointer of IFAGC table to identify
3410 // case 1: RFAGC from SAR, IFAGC controlled by demod
3411 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
3412 //status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
3413 // sDMD_DVBS_InitData->pTuner_RfagcSsi, sDMD_DVBS_InitData->u16Tuner_RfagcSsi_Size,
3414 // sDMD_DVBS_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBS_InitData->u16Tuner_IfagcSsi_HiRef_Size,
3415 // sDMD_DVBS_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBS_InitData->u16Tuner_IfagcSsi_LoRef_Size,
3416 // sDMD_DVBS_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBS_InitData->u16Tuner_IfagcErr_HiRef_Size,
3417 // sDMD_DVBS_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBS_InitData->u16Tuner_IfagcErr_LoRef_Size);
3418 //ch_power_db = INTERN_DVBS_GetTunrSignalLevel_PWR();
3419 //printf("@@@@@@@@@ ch_power_db = %f \n", ch_power_db);
3420
3421
3422
3423
3424 status &= INTERN_DVBS_GetCurrentDemodType(pDemodType);
3425
3426 if((MS_U8)*pDemodType == (MS_U8)DMD_SAT_DVBS)//S
3427 {
3428 /*
3429 float fDVBS_SSI_Pref[]=
3430 {
3431 //0, 1, 2, 3, 4
3432 -78.9, -77.15, -76.14, -75.19, -74.57,//QPSK
3433 };
3434 */
3435 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE + 0x84, &u8Data);
3436 *u8_DVBS2_CurrentCodeRateLocal = (u8Data & 0x07);
3437 //ch_power_db_rel = ch_power_db - fDVBS_SSI_Pref[_u8_DVBS2_CurrentCodeRateLocal];
3438 }
3439 else
3440 {
3441 /*
3442 float fDVBS2_SSI_Pref[][11]=
3443 {
3444 // 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
3445 //1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10
3446 {-85.17, -84.08, -83.15, -81.86, -80.63, -79.77, -78.84, -78.19, -77.69, -76.68, -76.46}, //QPSK
3447 { 0.0, 0.0, 0.0, 0.0, -77.36, -76.24, -74.95, 0.0, -73.52, -72.18, -71.84} //8PSK
3448 };
3449 */
3450 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
3451 *u8_DVBS2_CurrentCodeRateLocal = (u8Data & 0x3C)>>2;
3452
3453 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
3454 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD6, &u8Data2);
3455
3456 if(((u8Data & 0x03)==0x01) && ((u8Data2 & 0x80)==0x00))
3457 {
3458 *u8_DVBS2_CurrentConstellationLocal = DMD_DVBS_QPSK;
3459 }
3460 else if (((u8Data & 0x03)==0x01) && ((u8Data2 & 0x80)==0x80))
3461 {
3462 *u8_DVBS2_CurrentConstellationLocal = DMD_DVBS_8PSK;//8PSK
3463 }
3464 //ch_power_db_rel = ch_power_db - fDVBS2_SSI_Pref[_u8_DVBS2_CurrentConstellationLocal][_u8_DVBS2_CurrentCodeRateLocal];
3465 }
3466 /*
3467 if(ch_power_db_rel <= -15.0f)
3468 {
3469 *pu16SignalBar = 0;
3470 }
3471 else if (ch_power_db_rel <= 0.0f)
3472 {
3473 *pu16SignalBar = (MS_U16)(2.0f/3 * (ch_power_db_rel+15.0f));
3474 }
3475 else if (ch_power_db_rel <= 20.0f)
3476 {
3477 *pu16SignalBar = (MS_U16)(4.0f * ch_power_db_rel + 10.0f);
3478 }
3479 else if (ch_power_db_rel <= 35.0f)
3480 {
3481 *pu16SignalBar = (MS_U16)(2.0f/3 * (ch_power_db_rel-20.0f) + 90.0);
3482 }
3483 else
3484 {
3485 *pu16SignalBar = 100;
3486 }
3487 */
3488 //printf("SSI_CH_PWR(dB) = %f \n", ch_power_db_rel);
3489 //DBG_INTERN_DVBS(printf(">>>>>Signal Strength(SSI) = %d\n", (int)*pu16SignalBar));
3490
3491 return status;
3492 }
3493
3494 //SQI
3495 /****************************************************************************
3496 Subject: To get the DVT Signal quility
3497 Function: INTERN_DVBS_GetSignalQuality
3498 Parmeter: Quility
3499 Return: E_RESULT_SUCCESS
3500 E_RESULT_FAILURE
3501 Remark: Here we have 4 level range
3502 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
3503 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
3504 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
3505 <4>.4th Range => Quality <10
3506 *****************************************************************************/
3507 #if (0)
INTERN_DVBS_GetSignalQuality(MS_U16 * quality,const DMD_DVBS_InitData * sDMD_DVBS_InitData,MS_U8 u8SarValue,float fRFPowerDbm)3508 MS_BOOL INTERN_DVBS_GetSignalQuality(MS_U16 *quality, const DMD_DVBS_InitData *sDMD_DVBS_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
3509 {
3510
3511 float fber = 0.0;
3512 //float log_ber;
3513 MS_BOOL status = TRUE;
3514 float f_snr = 0.0, ber_sqi = 0.0, cn_rel = 0.0;
3515 //MS_U8 u8Data =0;
3516 DMD_DVBS_CODE_RATE_TYPE _u8_DVBS2_CurrentCodeRateLocal ;
3517 MS_U16 bchpkt_error,BCH_Eflag2_Window;
3518 //fRFPowerDbm = fRFPowerDbm;
3519 float snr_poly =0.0;
3520 float Fixed_SNR =0.0;
3521 double eFlag_PER=0.0;
3522
3523 if (TRUE == INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0))
3524 {
3525 if(_bDemodType) //S2
3526 {
3527
3528 INTERN_DVBS_GetSNR(&f_snr);
3529 snr_poly = 0.005261367463671*pow(f_snr, 3)-0.116517828301214*pow(f_snr, 2)+0.744836970505452*pow(f_snr, 1)-0.86727609780167;
3530 Fixed_SNR = f_snr + snr_poly;
3531
3532 if (Fixed_SNR < 17.0)
3533 Fixed_SNR = Fixed_SNR;
3534 else if ((Fixed_SNR < 20.0) && (Fixed_SNR >= 17.0))
3535 Fixed_SNR = Fixed_SNR - 0.8;
3536 else if ((Fixed_SNR < 22.5) && (Fixed_SNR >= 20.0))
3537 Fixed_SNR = Fixed_SNR - 2.0;
3538 else if ((Fixed_SNR < 27.0) && (Fixed_SNR >= 22.5))
3539 Fixed_SNR = Fixed_SNR - 3.0;
3540 else if ((Fixed_SNR < 29.0) && (Fixed_SNR >= 27.0))
3541 Fixed_SNR = Fixed_SNR - 3.5;
3542 else if (Fixed_SNR >= 29.0)
3543 Fixed_SNR = Fixed_SNR - 3.0;
3544
3545
3546 if (Fixed_SNR < 1.0)
3547 Fixed_SNR = 1.0;
3548 if (Fixed_SNR > 30.0)
3549 Fixed_SNR = 30.0;
3550
3551 //BCH EFLAG2_Window, window size 0x2000
3552 BCH_Eflag2_Window=0x2000;
3553 MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE + 0x25*2 + 1, (BCH_Eflag2_Window>>8));
3554 MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE + 0x25*2 , (BCH_Eflag2_Window&0xff));
3555 INTERN_DVBS_GetPacketErr(&bchpkt_error);
3556 eFlag_PER = (float)(bchpkt_error)/(float)(BCH_Eflag2_Window);
3557 if(eFlag_PER>0)
3558 fber = 0.089267531133002*pow(eFlag_PER, 2) + 0.019640560289510*eFlag_PER + 0.0000001;
3559 else
3560 fber = 0;
3561
3562 #ifdef MSOS_TYPE_LINUX
3563 //log_ber = ( - 1) *log10f(1 / fber);
3564 if (fber > 1.0E-1)
3565 ber_sqi = (log10f(1.0f/fber))*20.0f + 8.0f;
3566 else if(fber > 8.5E-7)
3567 ber_sqi = (log10f(1.0f/fber))*20.0f - 30.0f;
3568 else
3569 ber_sqi = 100.0;
3570 #else
3571 //log_ber = ( - 1) *Log10Approx(1 / fber);
3572 if (fber > 1.0E-1)
3573 ber_sqi = (Log10Approx(1.0f/fber))*20.0f + 8.0f;
3574 else if(fber > 8.5E-7)
3575 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 30.0f;
3576 else
3577 ber_sqi = 100.0;
3578
3579 #endif
3580
3581 *quality = Fixed_SNR/30*ber_sqi;
3582 DBG_INTERN_DVBS(printf(" Fixed_SNR %f\n",Fixed_SNR));
3583 DBG_INTERN_DVBS(printf(" BCH_Eflag2_Window %d\n",BCH_Eflag2_Window));
3584 DBG_INTERN_DVBS(printf(" eFlag_PER [%f]\n fber [%8.3e]\n ber_sqi [%f]\n",eFlag_PER,fber,ber_sqi));
3585 }
3586 else //S
3587 {
3588 if (INTERN_DVBS_GetPostViterbiBer(&fber) == FALSE)//ViterbiBer
3589 {
3590 DBG_INTERN_DVBS(printf("\nGetPostViterbiBer Fail!"));
3591 return FALSE;
3592 }
3593 _fPostBer=fber;
3594
3595
3596 if (status==FALSE)
3597 {
3598 DBG_INTERN_DVBS(printf("MSB131X_DTV_GetSignalQuality GetPostViterbiBer Fail!\n"));
3599 return 0;
3600 }
3601 float fDVBS_SQI_CNref[]=
3602 { //0, 1, 2, 3, 4
3603 4.2, 5.9, 6, 6.9, 7.5,//QPSK
3604 };
3605
3606 INTERN_DVBS_GetCurrentDemodCodeRate(&_u8_DVBS2_CurrentCodeRateLocal);
3607 #if 0
3608 #ifdef MSOS_TYPE_LINUX
3609 log_ber = ( - 1.0f) *log10f(1.0f / fber); //BY modify
3610 #else
3611 log_ber = ( - 1.0f) *Log10Approx(1.0f / fber); //BY modify
3612 #endif
3613 DBG_INTERN_DVBS(printf("\nLog(BER) = %f\n",log_ber));
3614 #endif
3615 if (fber > 2.5E-2)
3616 ber_sqi = 0.0;
3617 else if(fber > 8.5E-7)
3618 #ifdef MSOS_TYPE_LINUX
3619 ber_sqi = (log10f(1.0f/fber))*20.0f - 32.0f; //40.0f;
3620 #else
3621 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 32.0f;//40.0f;
3622 #endif
3623 else
3624 ber_sqi = 100.0;
3625
3626 status &= INTERN_DVBS_GetSNR(&f_snr);
3627 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS GetSNR = %d \n", (int)f_snr));
3628
3629 cn_rel = f_snr - fDVBS_SQI_CNref[_u8_DVBS2_CurrentCodeRateLocal];
3630
3631 DBG_INTERN_DVBS(printf(" fber = %f\n",fber));
3632 DBG_INTERN_DVBS(printf(" f_snr = %f\n",f_snr));
3633 DBG_INTERN_DVBS(printf(" cn_nordig_s1 = %f\n",fDVBS_SQI_CNref[_u8_DVBS2_CurrentCodeRateLocal]));
3634 DBG_INTERN_DVBS(printf(" cn_rel = %f\n",cn_rel));
3635 DBG_INTERN_DVBS(printf(" ber_sqi = %f\n",ber_sqi));
3636
3637 if (cn_rel < -7.0f)
3638 {
3639 *quality = 0;
3640 }
3641 else if (cn_rel < 3.0)
3642 {
3643 *quality = (MS_U16)(ber_sqi*((cn_rel - 3.0)/10.0 + 1.0));
3644 }
3645 else
3646 {
3647 *quality = (MS_U16)ber_sqi;
3648 }
3649
3650
3651 }
3652 //INTERN_DVBS_GetTunrSignalLevel_PWR();//For Debug.
3653 DBG_INTERN_DVBS(printf(">>>>>Signal Quility(SQI) = %d\n", *quality));
3654 return TRUE;
3655 }
3656 else
3657 {
3658 *quality = 0;
3659 }
3660
3661 return TRUE;
3662 }
3663 #endif
3664 /****************************************************************************
3665 Subject: To get the Cell ID
3666 Function: INTERN_DVBS_Get_CELL_ID
3667 Parmeter: point to return parameter cell_id
3668
3669 Return: TRUE
3670 FALSE
3671 Remark:
3672 *****************************************************************************/
INTERN_DVBS_Get_CELL_ID(MS_U16 * cell_id)3673 MS_BOOL INTERN_DVBS_Get_CELL_ID(MS_U16 *cell_id)
3674 {
3675 MS_BOOL status = true;
3676 MS_U8 value1 = 0;
3677 MS_U8 value2 = 0;
3678
3679 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [15:8]
3680 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [7:0]
3681
3682 *cell_id = ((MS_U16)value1<<8)|value2;
3683 return status;
3684 }
3685
3686 /****************************************************************************
3687 Subject: To get the DVBC Carrier Freq Offset
3688 Function: INTERN_DVBS_Get_FreqOffset
3689 Parmeter: Frequency offset (in KHz), bandwidth
3690 Return: E_RESULT_SUCCESS
3691 E_RESULT_FAILURE
3692 Remark:
3693 *****************************************************************************/
INTERN_DVBS_Get_FreqOffset(MS_S16 * s16CFO)3694 MS_BOOL INTERN_DVBS_Get_FreqOffset(MS_S16 *s16CFO)
3695 {
3696 MS_U8 u8Data=0;
3697 MS_U16 u16Data;
3698 //MS_S16 s16CFO;
3699 //float FreqOffset;
3700 //MS_U32 u32FreqOffset = 0;
3701 //MS_U8 reg = 0;
3702 MS_BOOL status = TRUE;
3703
3704 DBG_INTERN_DVBS(ULOGD("DEMOD",">>> INTERN_DVBS_Get_FreqOffset DVBS_Estimated_CFO <<<\n"));
3705 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_97, &u8Data);
3706 u16Data=u8Data;
3707 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_96, &u8Data);
3708 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset
3709 if (u16Data >= 0x8000)
3710 {
3711 u16Data=0x10000- u16Data;
3712 *s16CFO=-1*u16Data;
3713 }
3714 else
3715 {
3716 *s16CFO=u16Data;
3717 }
3718 DBG_INTERN_DVBS(ULOGD("DEMOD",">>> INTERN_DVBS_Get_FreqOffset CFO = %d[KHz] <<<\n", *s16CFO));
3719 /*
3720 if(abs(s16CFO)%1000 >= 500)
3721 {
3722 if(s16CFO < 0)
3723 *pFreqOff=(s16CFO/1000)-1.0;
3724 else
3725 *pFreqOff=(s16CFO/1000)+1.0;
3726 }
3727 else
3728 *pFreqOff = s16CFO/1000;
3729 DBG_INTERN_DVBS(printf(">>> INTERN_DVBS_Get_FreqOffset *pFreqOff = %d[MHz] <<<\n", (MS_S16)*pFreqOff));
3730 */
3731 // no use.
3732 //u8BW = u8BW;
3733 /*
3734 printf("INTERN_DVBS_Get_FreqOffset\n");//DBG_INTERN_DVBS(printf("INTERN_DVBS_Get_FreqOffset\n"));
3735
3736 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x1C*2 + 1, 0x08);
3737
3738 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x05, ®);
3739 reg|=0x80;
3740 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x05, reg);
3741
3742 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x23*2, ®);
3743 u32FreqOffset=reg;
3744 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x22*2 + 1, ®);
3745 u32FreqOffset=(u32FreqOffset<<8)|reg;
3746 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x22*2, ®);
3747 u32FreqOffset=(u32FreqOffset<<8)|reg;
3748
3749 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x05, ®);
3750 reg&=~(0x80);
3751 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x05, reg);
3752
3753 FreqOffset=(float)u32FreqOffset;
3754 if (FreqOffset>=2048)
3755 {
3756 FreqOffset=FreqOffset-4096;
3757 }
3758 FreqOffset=(FreqOffset/4096)*SAMPLING_RATE_FS;
3759
3760 *pFreqOff = FreqOffset/1000; //KHz
3761 printf("INTERN_DVBS_Get_FreqOffset:%d[MHz]\n", (MS_S16)FreqOffset/1000);//DBG_INTERN_DVBS(printf("INTERN_DVBS_Get_FreqOffset:%f[MHz]\n", FreqOffset/1000));
3762 */
3763
3764 return status;
3765 }
3766
3767 /****************************************************************************
3768 Subject: To get the current modulation type at the DVB-S Demod
3769 Function: INTERN_DVBS_GetCurrentModulationType
3770 Parmeter: pointer for return QAM type
3771
3772 Return: TRUE
3773 FALSE
3774 Remark:
3775 *****************************************************************************/
INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE * pQAMMode)3776 MS_BOOL INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE *pQAMMode)
3777 {
3778 MS_U8 u8Data=0;
3779 MS_U16 u16tmp=0;
3780 MS_U8 MOD_type;
3781 MS_BOOL status = true;
3782 //DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3783
3784 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType\n"));
3785
3786 //status &= INTERN_DVBS_GetCurrentDemodType(&pDemodType);
3787
3788 // read code rate, pilot on/off, long/short FEC type, and modulation type for calculating TOP_DVBTM_TS_CLK_DIVNUM
3789 // pilot_flag => 0 : off 1 : on
3790 // fec_type_idx => 0 : normal 1 : short
3791 // mod_type_idx => 0 : QPSK 1 : 8PSK 2 : 16APSK
3792 // code_rate_idx => 0 : 1/4 1 : 1/3 2 : 2/5 3 : 1/2 4 : 3/5 5 : 2/3
3793 // 6 : 3/4 7 : 4/5 8 : 5/6 9 : 8/9 10 : 9/10
3794 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//V
3795 if(u8Data)
3796 {
3797 *pQAMMode = DMD_DVBS_QPSK;
3798 modulation_order=2;
3799 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs]ModulationType=DVBS_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS_QPSK\n"));
3800 //return TRUE;
3801 }
3802 else //S2
3803 {
3804 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x96, &u8Data);
3805 //printf(">>> INTERN_DVBS_GetCurrentModulationType INNER 0x4B = 0x%x <<<\n", u8Data);
3806 //if((u8Data & 0x0F)==0x02) //QPSK
3807 /*MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MOD_TYPE, &u8Data1);
3808 printf("@@@@@E_DMD_S2_MOD_TYPE = %d \n ",u8Data1);
3809 printf("@@@@@ E_DMD_S2_MOD_TYPE=%d \n",E_DMD_S2_MOD_TYPE);
3810
3811 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_IS_ID, &u8Data1);
3812 printf("@@@@@E_DMD_S2_IS_ID = %d \n ",u8Data1);
3813 printf("@@@@@ E_DMD_S2_IS_ID=%d \n",E_DMD_S2_IS_ID);*/
3814
3815 // INNER_DEBUG_SEL
3816 MDrv_SYS_DMD_VD_MBX_ReadReg(0x3b00+0x04*2+1, &u8Data);
3817 u8Data = u8Data & 0xc0;
3818 MDrv_SYS_DMD_VD_MBX_WriteReg(0x3b00+0x04*2+1, u8Data);
3819
3820 // reg_plscdec_debug_out
3821 // PLSCDEC info
3822 //[0:4] PLSC MODCOD
3823 //[5] dummy frame
3824 //[6] reserve frame
3825 //[7:9] modulation type
3826 //[10:13] code rate type
3827 //[14] FEC type
3828 //[15] pilot type
3829 MDrv_SYS_DMD_VD_MBX_ReadReg(0x3b00+0x6b*2 , &u8Data);
3830 u16tmp = (MS_U16)u8Data;
3831 MDrv_SYS_DMD_VD_MBX_ReadReg(0x3b00+0x6b*2+1 , &u8Data);
3832 u16tmp |= (MS_U16)u8Data << 8;
3833 MOD_type = ((MS_U8)(u16tmp>>7)&0x07); // 2:QPSK, 3:8PSK, 4:16APSK, 5:32APSK
3834
3835 if(MOD_type==2)
3836 {
3837 *pQAMMode = DMD_DVBS_QPSK;
3838 modulation_order=2;
3839 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS2_QPSK\n"));
3840 //return TRUE;
3841 }
3842 else if(MOD_type==3)
3843 {
3844 *pQAMMode = DMD_DVBS_8PSK;
3845 modulation_order=3;
3846 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_8PSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS2_8PSK\n"));
3847 //return TRUE;
3848 }
3849 else if(MOD_type==4)
3850 {
3851 *pQAMMode = DMD_DVBS_16APSK;
3852 modulation_order=4;
3853 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_16APSK\n");
3854 }
3855 else
3856 {
3857 *pQAMMode = DMD_DVBS_QPSK;
3858 modulation_order=2;
3859 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=NOT SUPPORT\n");
3860 return FALSE;
3861 }
3862
3863 }
3864
3865 return status;
3866 /*#else
3867 *pQAMMode = DMD_DVBS_QPSK;
3868 printf("[dvbs]ModulationType=DVBS_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS_QPSK\n"));
3869 //return true;
3870 #endif*/
3871 }
3872
3873 /****************************************************************************
3874 Subject: To get the current DemodType at the DVB-S Demod
3875 Function: INTERN_DVBS_GetCurrentDemodType
3876 Parmeter: pointer for return DVBS/DVBS2 type
3877
3878 Return: TRUE
3879 FALSE
3880 Remark:
3881 *****************************************************************************/
INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE * pDemodType)3882 MS_BOOL INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE *pDemodType)//V
3883 {
3884 MS_U8 u8Data=0;
3885 MS_BOOL status = true;
3886
3887 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentDemodType\n"));
3888
3889 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x80, &u8Data);//status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x80, &u8Data);
3890 //printf(">>> INTERN_DVBS_GetCurrentDemodType INNER 0x40 = 0x%x <<<\n", u8Data);
3891 //if ((u8Data & 0x01) == 0)
3892 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//E_DMD_S2_SYSTEM_TYPE 0: S2 ; 1 :S
3893 if(!u8Data) //S2
3894 {
3895 *pDemodType = DMD_SAT_DVBS2;
3896 DBG_INTERN_DVBS(ULOGD("DEMOD","[dvbs]DemodType=DVBS2\n"));
3897 }
3898 else //S
3899 {
3900 *pDemodType = DMD_SAT_DVBS;
3901 DBG_INTERN_DVBS(ULOGD("DEMOD","[dvbs]DemodType=DVBS\n"));
3902 }
3903 return status;
3904 }
3905 /****************************************************************************
3906 Subject: To get the current CodeRate at the DVB-S Demod
3907 Function: INTERN_DVBS_GetCurrentCodeRate
3908 Parmeter: pointer for return Code Rate type
3909
3910 Return: TRUE
3911 FALSE
3912 Remark:
3913 *****************************************************************************/
INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE * pCodeRate)3914 MS_BOOL INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE *pCodeRate)
3915 {
3916 MS_U8 u8Data = 0;//, u8_gCodeRate = 0;
3917 MS_BOOL status = true;
3918
3919 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate\n"));
3920 //DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3921 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);
3922 //status &= INTERN_DVBS_GetCurrentDemodType(&pDemodType);
3923 if(!u8Data)
3924 //if((MS_U8)pDemodType == (MS_U8)DMD_SAT_DVBS2 ) //S2
3925 {
3926 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
3927 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
3928 //u8_gCodeRate = (u8Data & 0x3C);
3929 //_u8_DVBS2_CurrentCodeRate = 0;
3930 switch (u8Data)
3931 //switch (u8_gCodeRate)
3932 {
3933 case 0x03:
3934 *pCodeRate = DMD_CONV_CODE_RATE_1_2;
3935 _u8_DVBS2_CurrentCodeRate = 5;//0;
3936 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=1_2\n"));
3937 break;
3938 case 0x01:
3939 *pCodeRate = DMD_CONV_CODE_RATE_1_3;
3940 _u8_DVBS2_CurrentCodeRate = 6;//1;
3941 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=1_3\n"));
3942 break;
3943 case 0x05:
3944 *pCodeRate = DMD_CONV_CODE_RATE_2_3;
3945 _u8_DVBS2_CurrentCodeRate = 7;//2;
3946 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=2_3\n"));
3947 break;
3948 case 0x00:
3949 *pCodeRate = DMD_CONV_CODE_RATE_1_4;
3950 _u8_DVBS2_CurrentCodeRate = 8;//3;
3951 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=1_4\n"));
3952 break;
3953 case 0x06:
3954 *pCodeRate = DMD_CONV_CODE_RATE_3_4;
3955 _u8_DVBS2_CurrentCodeRate = 9;//4;
3956 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=3_4\n"));
3957 break;
3958 case 0x02:
3959 *pCodeRate = DMD_CONV_CODE_RATE_2_5;
3960 _u8_DVBS2_CurrentCodeRate = 10;//5;
3961 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=2_5\n"));
3962 break;
3963 case 0x04:
3964 *pCodeRate = DMD_CONV_CODE_RATE_3_5;
3965 _u8_DVBS2_CurrentCodeRate = 11;//6;
3966 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=3_5\n"));
3967 break;
3968 case 0x07:
3969 *pCodeRate = DMD_CONV_CODE_RATE_4_5;
3970 _u8_DVBS2_CurrentCodeRate = 12;//7;
3971 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=4_5\n"));
3972 break;
3973 case 0x08:
3974 *pCodeRate = DMD_CONV_CODE_RATE_5_6;
3975 _u8_DVBS2_CurrentCodeRate = 13;//8;
3976 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=5_6\n"));
3977 break;
3978 case 0x09:
3979 *pCodeRate = DMD_CONV_CODE_RATE_8_9;
3980 _u8_DVBS2_CurrentCodeRate = 14;//9;
3981 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=8_9\n"));
3982 break;
3983 case 0x0a:
3984 *pCodeRate = DMD_CONV_CODE_RATE_9_10;
3985 _u8_DVBS2_CurrentCodeRate = 15;//10;
3986 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=9_10\n"));
3987 break;
3988 default:
3989 *pCodeRate = DMD_CONV_CODE_RATE_9_10;
3990 _u8_DVBS2_CurrentCodeRate = 15;//10;
3991 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=DVBS2_Default\n"));
3992 }
3993 }
3994 else //S
3995 {
3996 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
3997 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE + 0x3A*2, &u8Data);
3998 //u8_gCodeRate = (u8Data & 0x70)>>4;
3999 switch (u8Data)
4000 //switch (u8_gCodeRate)
4001 {
4002 case 0x00:
4003 *pCodeRate = DMD_CONV_CODE_RATE_1_2;
4004 _u8_DVBS2_CurrentCodeRate = 0;
4005 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=1_2\n"));
4006 break;
4007 case 0x01:
4008 *pCodeRate = DMD_CONV_CODE_RATE_2_3;
4009 _u8_DVBS2_CurrentCodeRate = 1;
4010 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=2_3\n"));
4011 break;
4012 case 0x02:
4013 *pCodeRate = DMD_CONV_CODE_RATE_3_4;
4014 _u8_DVBS2_CurrentCodeRate = 2;
4015 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=3_4\n"));
4016 break;
4017 case 0x03:
4018 *pCodeRate = DMD_CONV_CODE_RATE_5_6;
4019 _u8_DVBS2_CurrentCodeRate = 3;
4020 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=5_6\n"));
4021 break;
4022 case 0x04:
4023 *pCodeRate = DMD_CONV_CODE_RATE_7_8;
4024 _u8_DVBS2_CurrentCodeRate = 4;
4025 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=7_8\n"));
4026 break;
4027 default:
4028 *pCodeRate = DMD_CONV_CODE_RATE_7_8;
4029 _u8_DVBS2_CurrentCodeRate = 4;
4030 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=DVBS_Default\n"));
4031 }
4032 }
4033 return status;
4034 }
4035
4036 /****************************************************************************
4037 Subject: To get the current symbol rate at the DVB-S Demod
4038 Function: INTERN_DVBS_GetCurrentSymbolRate
4039 Parmeter: pointer pData for return Symbolrate
4040
4041 Return: TRUE
4042 FALSE
4043 Remark:
4044 *****************************************************************************/
INTERN_DVBS_GetCurrentSymbolRate(MS_U32 * u32SymbolRate)4045 MS_BOOL INTERN_DVBS_GetCurrentSymbolRate(MS_U32 *u32SymbolRate)
4046 {
4047 MS_U8 tmp = 0;
4048 MS_U16 u16SymbolRateTmp = 0;
4049
4050 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &tmp);
4051 u16SymbolRateTmp = tmp;
4052 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &tmp);
4053 u16SymbolRateTmp = (u16SymbolRateTmp<<8)|tmp;
4054
4055 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &tmp);
4056 *u32SymbolRate = (tmp<<16)|u16SymbolRateTmp;
4057
4058 DBG_INTERN_DVBS_LOCK(ULOGD("DEMOD","[dvbs]Symbol Rate=%d\n",*u32SymbolRate));
4059
4060 return TRUE;
4061 }
4062
INTERN_DVBS_Version(MS_U16 * ver)4063 MS_BOOL INTERN_DVBS_Version(MS_U16 *ver)
4064 {
4065 MS_U8 status = true;
4066 MS_U8 tmp = 0;
4067 MS_U16 u16_INTERN_DVBS_Version;
4068
4069 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FW_VERSION_L, &tmp);
4070 u16_INTERN_DVBS_Version = tmp;
4071 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FW_VERSION_H, &tmp);
4072 u16_INTERN_DVBS_Version = u16_INTERN_DVBS_Version<<8|tmp;
4073 *ver = u16_INTERN_DVBS_Version;
4074
4075 return status;
4076 }
4077
INTERN_DVBS_Show_Demod_Version(void)4078 MS_BOOL INTERN_DVBS_Show_Demod_Version(void)
4079 {
4080 MS_BOOL status = true;
4081 MS_U16 u16_INTERN_DVBS_Version;
4082
4083 status &= INTERN_DVBS_Version(&u16_INTERN_DVBS_Version);
4084
4085 ULOGD("DEMOD",">>> [Maserati]Demod FW Version: R%d.%d <<<\n", (u16_INTERN_DVBS_Version&0x00FF),((u16_INTERN_DVBS_Version>>8)&0x00FF));
4086
4087
4088 return status;
4089 }
4090
INTERN_DVBS_GetRollOff(MS_U8 * pRollOff)4091 MS_BOOL INTERN_DVBS_GetRollOff(MS_U8 *pRollOff)
4092 {
4093 MS_BOOL status=TRUE;
4094 MS_U8 u8Data=0;
4095
4096 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x1E, &u8Data);//#define INNER_TR_ROLLOFF (_REG_INNER(0x0F)+0)
4097 if ((u8Data&0x03)==0x00)
4098 *pRollOff = 0; //Rolloff 0.35
4099 else if (((u8Data&0x03)==0x01) || ((u8Data&0x03)==0x03))
4100 *pRollOff = 1; //Rolloff 0.25
4101 else
4102 *pRollOff = 2; //Rolloff 0.20
4103 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetRollOff:%d\n", *pRollOff));
4104
4105 return status;
4106 }
4107
INTERN_DVBS_Get_DTV_SQuality_BAR(MS_U8 * u8_gSQValue)4108 MS_BOOL INTERN_DVBS_Get_DTV_SQuality_BAR(MS_U8 *u8_gSQValue)
4109 {
4110 MS_BOOL status=TRUE;
4111 //MS_U16 u16_gSignalQualityValue;
4112 MS_U16 _u16_packetError;
4113
4114 // status = INTERN_DVBS_GetSignalQuality(&u16_gSignalQualityValue,0,0,0);
4115 status = INTERN_DVBS_GetPacketErr(&_u16_packetError);
4116 /*
4117 if ((_u16_packetError >= 1) && (u16_gSignalQualityValue > 30)) //Average
4118 {
4119 *u8_gSQValue = 30;
4120 }
4121 else if ((_u16_packetError >= 1) && (u16_gSignalQualityValue > 10)) //Poor
4122 {
4123 *u8_gSQValue = 10;
4124 }
4125 */
4126 return status;
4127 }
4128
4129 /****************************************************************************
4130 ** Function: Read demod related information
4131 ** Polling after demod lock
4132 ** GAIN & DCR /Fine CFO & PR & IIS & IQB & SNR /PacketErr & BER
4133 ****************************************************************************/
INTERN_DVBS_Show_AGC_Info(void)4134 MS_BOOL INTERN_DVBS_Show_AGC_Info(void)
4135 {
4136 MS_BOOL status = TRUE;
4137
4138 //MS_U8 tmp = 0;
4139 //MS_U8 agc_k = 0,d0_k = 0,d0_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0,d3_k = 0,d3_ref = 0;
4140 //MS_U16 if_agc_gain = 0,d0_gain = 0,d1_gain = 0,d2_gain = 0,d3_gain = 0, agc_ref = 0;
4141 //MS_U16 if_agc_err = 0;
4142 #if 0
4143 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x08*2 + 1,&agc_k);
4144 agc_k = ((agc_k & 0xF0)>>4);
4145 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x09*2 + 1,&tmp);
4146 agc_ref = tmp;
4147 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0xE8,&tmp);
4148 //agc_ref = (agc_ref<<8)|tmp;
4149 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x38*2,&d0_k);
4150 d0_k = ((d0_k & 0xF0)>>4);
4151 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x38*2 + 1,&d0_ref);
4152 d0_ref = (d0_ref & 0xFF);
4153 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x58*2,&d1_k);
4154 d1_k = (d1_k & 0xF0)>>4;
4155 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x58*2 + 1,&d1_ref);
4156 d1_ref = (d1_ref & 0xFF);
4157 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5E*2,&d2_k);
4158 d2_k = ((d2_k & 0xF0)>>4);
4159 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x5E*2 + 1,&d2_ref);
4160 d2_ref = (d2_ref & 0xFF);
4161 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6A*2,&d3_k);
4162 d3_k = ((d3_k & 0xF0)>>4);
4163 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref);
4164 d3_ref = (d3_ref & 0xFF);
4165
4166
4167 // select IF gain to read
4168 //Debug Select
4169 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x13*2, &tmp);
4170 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x13*2, (tmp&0xF0)|0x03);
4171 //IF_AGC_GAIN
4172 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2 + 1, &tmp);
4173 if_agc_gain = tmp;
4174 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2, &tmp);
4175 if_agc_gain = (if_agc_gain<<8)|tmp;
4176
4177
4178 // select d0 gain to read.
4179 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x74*2 + 1, &tmp);
4180 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x74*2 + 1, (tmp&0xF0)|0x03);
4181 //DAGC0_GAIN
4182 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3D*2, &tmp);
4183 d0_gain = tmp;
4184 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3C*2 + 1, &tmp);
4185 d0_gain = (d0_gain<<8)|tmp;
4186 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3C*2, &tmp);
4187 d0_gain = (d0_gain<<4)|(tmp>>4);
4188
4189
4190 // select d1 gain to read.
4191 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x8C, &tmp);
4192 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x8C, (tmp&0xF0)|0x00);
4193 //DAGC1_GAIN
4194 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5C*2 + 1, &tmp);
4195 d1_gain = tmp;
4196 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5C*2, &tmp);
4197 d1_gain = (d1_gain<<8)|tmp;
4198
4199
4200 // select d2 gain to read.
4201 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x06, &tmp);
4202 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT_REG_BASE + 0x06, (tmp&0xF0)|0x03);
4203 //DAGC2_GAIN
4204 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x62*2 + 1, &tmp);
4205 d2_gain = tmp;
4206 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x62*2, &tmp);
4207 d2_gain = (d2_gain<<8)|tmp;
4208
4209
4210 // select d3 gain to read.
4211 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp);
4212 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03);
4213 //DAGC3_GAIN
4214 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6F*2, &tmp);
4215 d3_gain = tmp;
4216 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6E*2 + 1, &tmp);
4217 d3_gain = (d3_gain<<8)|tmp;
4218 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6E*2, &tmp);
4219 d3_gain = (d3_gain<<4)|(tmp>>4);
4220
4221
4222 // select IF gain err to read
4223 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x13*2, &tmp);
4224 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x13*2, (tmp&0xF0)|0x00);
4225
4226 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2 + 1, &tmp);
4227 if_agc_err = tmp;
4228 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2, &tmp);
4229 if_agc_err = (if_agc_err<<8)|tmp;
4230
4231
4232 DBG_INTERN_DVBS(printf("[dvbs]agc_k=0x%x, agc_ref=0x%x, d0_k=0x%x, d0_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x, d3_k=0x%x, d3_ref=0x%x\n",
4233 agc_k, agc_ref, d0_k, d0_ref, d1_k, d1_ref, d2_k, d2_ref, d3_k, d3_ref));
4234
4235 DBG_INTERN_DVBS(printf("[dvbs]agc_g=0x%x, d0_g=0x%x, d1_g=0x%x, d2_g=0x%x, d3_g=0x%x, agc_err=0x%x\n", if_agc_gain, d0_gain, d1_gain, d2_gain, d3_gain, if_agc_err));
4236
4237 DBG_INTERN_DVBS(printf("[dvbs]agc_k=0x%x, agc_ref=0x%x, d0_k=0x%x, d0_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x, d3_k=0x%x, d3_ref=0x%x\n",
4238 agc_k, agc_ref, d0_k, d0_ref, d1_k, d1_ref, d2_k, d2_ref, d3_k, d3_ref));
4239
4240 DBG_INTERN_DVBS(printf("[dvbs]agc_g=0x%x, d0_g=0x%x, d1_g=0x%x, d2_g=0x%x, d3_g=0x%x, agc_err=0x%x\n", if_agc_gain, d0_gain, d1_gain, d2_gain, d3_gain, if_agc_err));
4241 #endif
4242 return status;
4243 }
4244
INTERN_DVBS_info(void)4245 void INTERN_DVBS_info(void)
4246 {
4247 //status &= INTERN_DVBS_Show_Demod_Version();
4248 //status &= INTERN_DVBS_Demod_Get_Debug_Info_get_once();
4249 //status &= INTERN_DVBS_Demod_Get_Debug_Info_polling();
4250 }
4251
INTERN_DVBS_Demod_Get_Debug_Info_get_once(void)4252 MS_BOOL INTERN_DVBS_Demod_Get_Debug_Info_get_once(void)
4253 {
4254 MS_BOOL status = TRUE;
4255 //MS_U8 u8Data = 0;
4256 //MS_U16 u16Data = 0, u16Address = 0;
4257 //float psd_smooth_factor;
4258 //float srd_right_bottom_value, srd_right_top_value, srd_left_bottom_value, srd_left_top_value;
4259 //MS_U16 u32temp5;
4260 //MS_U16 srd_left, srd_right, srd_left_top, srd_left_bottom, srd_right_top, srd_right_bottom;
4261
4262 #if 0
4263 //Lock Flag
4264 printf("========================================================================\n");
4265 printf("Debug Message Flag [Lock Flag]==========================================\n");
4266
4267 u16Address = (AGC_LOCK>>16)&0xffff;
4268 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4269 if ((u16Data&(AGC_LOCK&0xffff))!=(AGC_LOCK&0xffff))
4270 printf("[DVBS]: AGC LOCK ======================: Fail. \n");
4271 else
4272 printf("[DVBS]: AGC LOCK ======================: OK. \n");
4273
4274 u16Address = (DAGC0_LOCK>>16)&0xffff;
4275 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4276 if ((u16Data&(DAGC0_LOCK&0xffff))!=(DAGC0_LOCK&0xffff))
4277 printf("[DVBS]: DAGC0 LOCK ====================: Fail. \n");
4278 else
4279 printf("[DVBS]: DAGC0 LOCK ====================: OK. \n");
4280
4281 u16Address = (DAGC1_LOCK>>16)&0xffff;
4282 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4283 if ((u16Data&(DAGC1_LOCK&0xffff))!=(DAGC1_LOCK&0xffff))
4284 printf("[DVBS]: DAGC1 LOCK ====================: Fail. \n");
4285 else
4286 printf("[DVBS]: DAGC1 LOCK ====================: OK. \n");
4287
4288 u16Address = (DAGC2_LOCK>>16)&0xffff;
4289 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4290 if ((u16Data&(DAGC2_LOCK&0xffff))!=(DAGC2_LOCK&0xffff))
4291 printf("[DVBS]: DAGC2 LOCK ====================: Fail. \n");
4292 else
4293 printf("[DVBS]: DAGC2 LOCK ====================: OK. \n");
4294
4295 u16Address = (DAGC3_LOCK>>16)&0xffff;
4296 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4297 if ((u16Data&(DAGC3_LOCK&0xffff))!=(DAGC3_LOCK&0xffff))
4298 printf("[DVBS]: DAGC3 LOCK ====================: Fail. \n");
4299 else
4300 printf("[DVBS]: DAGC3 LOCK ====================: OK. \n");
4301
4302 u16Address = (DCR_LOCK>>16)&0xffff;
4303 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4304 if ((u16Data&(DCR_LOCK&0xffff))!=(DCR_LOCK&0xffff))
4305 printf("[DVBS]: DCR LOCK ======================: Fail. \n");
4306 else
4307 printf("[DVBS]: DCR LOCK ======================: OK. \n");
4308 //Mark Coarse SRD
4309 //Mark Fine SRD
4310 /*
4311 u16Address = (CLOSE_COARSE_CFO_LOCK>>16)&0xffff;
4312 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4313 if ((u16Data&(CLOSE_COARSE_CFO_LOCK&0xffff))!=(CLOSE_COARSE_CFO_LOCK&0xffff))
4314 printf("[DVBS]: Close CFO =====================: Fail. \n");
4315 else
4316 printf("[DVBS]: Close CFO =====================: OK. \n");
4317 */
4318 u16Address = (TR_LOCK>>16)&0xffff;
4319 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4320 if ((u16Data&(TR_LOCK&0xffff))!=(TR_LOCK&0xffff))
4321 printf("[DVBS]: TR LOCK =======================: Fail. \n");
4322 else
4323 printf("[DVBS]: TR LOCK =======================: OK. \n");
4324
4325 u16Address = (FRAME_SYNC_ACQUIRE>>16)&0xffff;
4326 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4327 if ((u16Data&(FRAME_SYNC_ACQUIRE&0xffff))!=(FRAME_SYNC_ACQUIRE&0xffff))
4328 printf("[DVBS]: FS Acquire ====================: Fail. \n");
4329 else
4330 printf("[DVBS]: FS Acquire ====================: OK. \n");
4331
4332 u16Address = (PR_LOCK>>16)&0xffff;
4333 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4334 if ((u16Data&(PR_LOCK&0xffff))!=(PR_LOCK&0xffff))
4335 printf("[DVBS]: PR LOCK =======================: Fail. \n");
4336 else
4337 printf("[DVBS]: PR LOCK =======================: OK. \n");
4338
4339 u16Address = (EQ_LOCK>>16)&0xffff;
4340 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4341 if ((u16Data&(EQ_LOCK&0xffff))!=(EQ_LOCK&0xffff))
4342 printf("[DVBS]: EQ LOCK =======================: Fail. \n");
4343 else
4344 printf("[DVBS]: EQ LOCK =======================: OK. \n");
4345
4346 u16Address = (P_SYNC_LOCK>>16)&0xffff;
4347 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4348 if ((u16Data&0x0002)!=0x0002)
4349 printf("[DVBS]: P_sync ========================: Fail. \n");
4350 else
4351 printf("[DVBS]: P_sync ========================: OK. \n");
4352
4353 u16Address = (IN_SYNC_LOCK>>16)&0xffff;
4354 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4355 if ((u16Data&0x8000)!=0x8000)
4356 printf("[DVBS]: In_sync =======================: Fail. \n");
4357 else
4358 printf("[DVBS]: In_sync =======================: OK. \n");
4359 //---------------------------------------------------------
4360 //Lock Time
4361 printf("------------------------------------------------------------------------\n");
4362 printf("Debug Message [Lock Time]===============================================\n");
4363
4364 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_05, &u8Data);
4365 printf("[DVBS]: AGC Lock Time =================: %d\n",u8Data&0x00FF);
4366 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_06, &u8Data);
4367 printf("[DVBS]: DCR Lock Time =================: %d\n",u8Data&0x00FF);
4368 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_2, &u8Data);
4369 printf("[DVBS]: TR Lock Time ==================: %d\n",u8Data&0x00FF);
4370 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_3, &u8Data);
4371 printf("[DVBS]: FS Lock Time ==================: %d\n",u8Data&0x00FF);
4372 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_4, &u8Data);
4373 printf("[DVBS]: PR Lock Time ==================: %d\n",u8Data&0x00FF);
4374 //printf("[DVBS]: PLSC Lock Time ================: %d\n",(u16Data>>8)&0x00FF);//No used
4375 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_6, &u8Data);
4376 printf("[DVBS]: EQ Lock Time ==================: %d\n",u8Data&0x00FF);
4377 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_7, &u8Data);
4378 printf("[DVBS]: FEC Lock Time =================: %d\n",u8Data&0x00FF);
4379
4380 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_0, &u8Data);
4381 printf("[DVBS]: CSRD ==========================: %d\n",u8Data&0x00FF);
4382 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_1, &u8Data);
4383 printf("[DVBS]: FSRD ==========================: %d\n",u8Data&0x00FF);
4384 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_01, &u8Data);
4385 printf("[DVBS]: CCFO ==========================: %d\n",u8Data&0x00FF);
4386 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_02, &u8Data);
4387 printf("[DVBS]: FCFO ==========================: %d\n",u8Data&0x00FF);
4388 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);
4389 printf("[DVBS]: State =========================: %d\n",u8Data&0x00FF);
4390 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SUBSTATE_FLAG, &u8Data);
4391 printf("[DVBS]: SubState ======================: %d\n",u8Data&0x00FF);
4392
4393 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00H, &u8Data);
4394 u16Data = u8Data;
4395 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00L, &u8Data);
4396 u16Data = (u16Data<<8)|u8Data;
4397 printf("[DVBS]: DBG1: =========================: 0x%x\n",u16Data);
4398 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01H, &u8Data);
4399 u16Data = u8Data;
4400 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01L, &u8Data);
4401 u16Data = (u16Data<<8)|u8Data;
4402 printf("[DVBS]: DBG2: =========================: 0x%x\n",u16Data);
4403 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE02H, &u8Data);
4404 u16Data = u8Data;
4405 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE02L, &u8Data);
4406 u16Data = (u16Data<<8)|u8Data;
4407 printf("[DVBS]: DBG3: =========================: 0x%x\n",u16Data);
4408 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE03H, &u8Data);
4409 u16Data = u8Data;
4410 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE03L, &u8Data);
4411 u16Data = (u16Data<<8)|u8Data;
4412 printf("[DVBS]: DBG4: =========================: 0x%x\n",u16Data);
4413 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE04H, &u8Data);
4414 u16Data = u8Data;
4415 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE04L, &u8Data);
4416 u16Data = (u16Data<<8)|u8Data;
4417 printf("[DVBS]: DBG5: =========================: 0x%x\n",u16Data);
4418 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE05H, &u8Data);
4419 u16Data = u8Data;
4420 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE05L, &u8Data);
4421 u16Data = (u16Data<<8)|u8Data;
4422 printf("[DVBS]: DBG6: =========================: 0x%x\n",u16Data);
4423 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE06H, &u8Data);
4424 u16Data = u8Data;
4425 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE06L, &u8Data);
4426 u16Data = (u16Data<<8)|u8Data;
4427 printf("[DVBS]: EQ Sum: =======================: 0x%x\n",u16Data);
4428 //---------------------------------------------------------
4429 //FIQ Status
4430 printf("------------------------------------------------------------------------\n");
4431 printf("Debug Message [FIQ Status]==============================================\n");
4432 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00H, &u8Data);
4433 u16Data = u8Data;
4434 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00L, &u8Data);
4435 u16Data = (u16Data<<8)|u8Data;
4436
4437 if ((u16Data&0x0001)==0x0000)
4438 printf("[DVBS]: AGC Lock ======================: Fail. \n");
4439 else
4440 printf("[DVBS]: AGC Lock ======================: OK. \n");
4441
4442 if ((u16Data&0x0002)==0x0000)
4443 printf("[DVBS]: Hum Detect ====================: Fail. \n");
4444 else
4445 printf("[DVBS]: Hum Detect ====================: OK. \n");
4446
4447 if ((u16Data&0x0004)==0x0000)
4448 printf("[DVBS]: DCR Lock ======================: Fail. \n");
4449 else
4450 printf("[DVBS]: DCR Lock ======================: OK. \n");
4451
4452 if ((u16Data&0x0008)==0x0000)
4453 printf("[DVBS]: IIS Detect ====================: Fail. \n");
4454 else
4455 printf("[DVBS]: IIS Detect ====================: OK. \n");
4456
4457 if ((u16Data&0x0010)==0x0000)
4458 printf("[DVBS]: DAGC0 Lock ====================: Fail. \n");
4459 else
4460 printf("[DVBS]: DAGC0 Lock ====================: OK. \n");
4461
4462 if ((u16Data&0x0020)==0x0000)
4463 printf("[DVBS]: DAGC1 Lock ====================: Fail. \n");
4464 else
4465 printf("[DVBS]: DAGC1 Lock ====================: OK. \n");
4466
4467 if ((u16Data&0x0040)==0x0000)
4468 printf("[DVBS]: DAGC2 Lock ====================: Fail. \n");
4469 else
4470 printf("[DVBS]: DAGC2 Lock ====================: OK. \n");
4471
4472 if ((u16Data&0x0080)==0x0000)
4473 printf("[DVBS]: CCI Detect ====================: Fail. \n");
4474 else
4475 printf("[DVBS]: CCI Detect ====================: OK. \n");
4476
4477 if ((u16Data&0x0100)==0x0000)
4478 printf("[DVBS]: SRD Coarse Done ===============: Fail. \n");
4479 else
4480 printf("[DVBS]: SRD Coarse Done ===============: OK. \n");
4481
4482 if ((u16Data&0x0200)==0x0000)
4483 printf("[DVBS]: SRD Fine Done =================: Fail. \n");
4484 else
4485 printf("[DVBS]: SRD Fine Done =================: OK. \n");
4486
4487 if ((u16Data&0x0400)==0x0000)
4488 printf("[DVBS]: EQ Lock =======================: Fail. \n");
4489 else
4490 printf("[DVBS]: EQ Lock =======================: OK. \n");
4491
4492 if ((u16Data&0x0800)==0x0000)
4493 printf("[DVBS]: FineFE Done ===================: Fail. \n");
4494 else
4495 printf("[DVBS]: FineFE Done ===================: OK. \n");
4496
4497 if ((u16Data&0x1000)==0x0000)
4498 printf("[DVBS]: PR Lock =======================: Fail. \n");
4499 else
4500 printf("[DVBS]: PR Lock =======================: OK. \n");
4501
4502 if ((u16Data&0x2000)==0x0000)
4503 printf("[DVBS]: Reserved Frame ================: Fail. \n");
4504 else
4505 printf("[DVBS]: Reserved Frame ================: OK. \n");
4506
4507 if ((u16Data&0x4000)==0x0000)
4508 printf("[DVBS]: Dummy Frame ===================: Fail. \n");
4509 else
4510 printf("[DVBS]: Dummy Frame ===================: OK. \n");
4511
4512 if ((u16Data&0x8000)==0x0000)
4513 printf("[DVBS]: PLSC Done =====================: Fail. \n");
4514 else
4515 printf("[DVBS]: PLSC Done =====================: OK. \n");
4516
4517 printf("------------------------------------------------------------------------\n");
4518 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01H, &u8Data);
4519 u16Data = u8Data;
4520 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01L, &u8Data);
4521 u16Data = (u16Data<<8)|u8Data;
4522 if ((u16Data&0x0001)==0x0000)
4523 printf("[DVBS]: FS Get Info From Len ==========: Fail. \n");
4524 else
4525 printf("[DVBS]: FS Get Info From Len ==========: OK. \n");
4526
4527 if ((u16Data&0x0002)==0x0000)
4528 printf("[DVBS]: IQ Swap Detect ================: Fail. \n");
4529 else
4530 printf("[DVBS]: IQ Swap Detect ================: OK. \n");
4531
4532 if ((u16Data&0x0004)==0x0000)
4533 printf("[DVBS]: FS Acquisition ================: Fail. \n");
4534 else
4535 printf("[DVBS]: FS Acquisition ================: OK. \n");
4536
4537 if ((u16Data&0x0008)==0x0000)
4538 printf("[DVBS]: TR Lock =======================: Fail. \n");
4539 else
4540 printf("[DVBS]: TR Lock =======================: OK. \n");
4541
4542 if ((u16Data&0x0010)==0x0000)
4543 printf("[DVBS]: CLCFE Lock ====================: Fail. \n");
4544 else
4545 printf("[DVBS]: CLCFE Lock ====================: OK. \n");
4546
4547 if ((u16Data&0x0020)==0x0000)
4548 printf("[DVBS]: OLCFE Lock ====================: Fail. \n");
4549 else
4550 printf("[DVBS]: OLCFE Lock ====================: OK. \n");
4551
4552 if ((u16Data&0x0040)==0x0000)
4553 printf("[DVBS]: Fsync Found ===================: Fail. \n");
4554 else
4555 printf("[DVBS]: Fsync Found ===================: OK. \n");
4556
4557 if ((u16Data&0x0080)==0x0000)
4558 printf("[DVBS]: Fsync Lock ====================: Fail. \n");
4559 else
4560 printf("[DVBS]: Fsync Lock ====================: OK. \n");
4561
4562 if ((u16Data&0x0100)==0x0000)
4563 printf("[DVBS]: Fsync Fail Search =============: Fail. \n");
4564 else
4565 printf("[DVBS]: Fsync Fail Search =============: OK. \n");
4566
4567 if ((u16Data&0x0200)==0x0000)
4568 printf("[DVBS]: Fsync Fail Lock ===============: Fail. \n");
4569 else
4570 printf("[DVBS]: Fsync Fail Lock ===============: OK. \n");
4571
4572 if ((u16Data&0x0400)==0x0000)
4573 printf("[DVBS]: False Alarm ===================: Fail. \n");
4574 else
4575 printf("[DVBS]: False Alarm ===================: OK. \n");
4576
4577 if ((u16Data&0x0800)==0x0000)
4578 printf("[DVBS]: Viterbi In Sync ===============: Fail. \n");
4579 else
4580 printf("[DVBS]: Viterbi In Sync ===============: OK. \n");
4581
4582 if ((u16Data&0x1000)==0x0000)
4583 printf("[DVBS]: Uncrt Over ====================: Fail. \n");
4584 else
4585 printf("[DVBS]: Uncrt Over ====================: OK. \n");
4586
4587 if ((u16Data&0x2000)==0x0000)
4588 printf("[DVBS]: CLK Cnt Over ==================: Fail. \n");
4589 else
4590 printf("[DVBS]: CLK Cnt Over ==================: OK. \n");
4591
4592 //if ((u16Data&0x4000)==0x0000)
4593 // printf("[DVBS]: Data In Ready FIFO ============: Fail. \n");
4594 //else
4595 // printf("[DVBS]: Data In Ready FIFO ============: OK. \n");
4596
4597 //if ((u16Data&0x8000)==0x0000)
4598 // printf("[DVBS]: IIR Buff Busy =================: Fail. \n");
4599 //else
4600 // printf("[DVBS]: IIR Buff Busy =================: OK. \n");
4601
4602 /*
4603 printf("------------------------------------------------------------------------\n");
4604 u16Address = 0x0B64;
4605 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address+1, &u8Data);
4606 u16Data = u8Data;
4607 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address , &u8Data);
4608 u16Data = (u16Data<<8)|u8Data;
4609 if ((u16Data&0x0001)==0x0000)
4610 printf("[DVBS]: IIR Busy LDPC =================: Fail. \n");
4611 else
4612 printf("[DVBS]: IIR Busy LDPC =================: OK. \n");
4613
4614 if ((u16Data&0x0002)==0x0000)
4615 printf("[DVBS]: BCH Busy ======================: Fail. \n");
4616 else
4617 printf("[DVBS]: BCH Busy ======================: OK. \n");
4618
4619 if ((u16Data&0x0004)==0x0000)
4620 printf("[DVBS]: Oppro Ready Out ===============: Fail. \n");
4621 else
4622 printf("[DVBS]: Oppro Ready Out ===============: OK. \n");
4623
4624 if ((u16Data&0x0008)==0x0000)
4625 printf("[DVBS]: LDPC Win ======================: Fail. \n");
4626 else
4627 printf("[DVBS]: LDPC Win ======================: OK. \n");
4628
4629 if ((u16Data&0x0010)==0x0000)
4630 printf("[DVBS]: LDPC Error ====================: Fail. \n");
4631 else
4632 printf("[DVBS]: LDPC Error ====================: OK. \n");
4633
4634 if ((u16Data&0x0020)==0x0000)
4635 printf("[DVBS]: Out BCH Error =================: Fail. \n");
4636 else
4637 printf("[DVBS]: Out BCH Error =================: OK. \n");
4638
4639 if ((u16Data&0x0040)==0x0000)
4640 printf("[DVBS]: Descr BCH FEC Num Error =======: Fail. \n");
4641 else
4642 printf("[DVBS]: Descr BCH FEC Num Error =======: OK. \n");
4643
4644 if ((u16Data&0x0080)==0x0000)
4645 printf("[DVBS]: Descr BCH Data Num Error ======: Fail. \n");
4646 else
4647 printf("[DVBS]: Descr BCH Data Num Error ======: OK. \n");
4648
4649 if ((u16Data&0x0100)==0x0000)
4650 printf("[DVBS]: Packet Error Out ==============: Fail. \n");
4651 else
4652 printf("[DVBS]: Packet Error Out ==============: OK. \n");
4653
4654 if ((u16Data&0x0200)==0x0000)
4655 printf("[DVBS]: BBH CRC Error =================: Fail. \n");
4656 else
4657 printf("[DVBS]: BBH CRC Error =================: OK. \n");
4658
4659 if ((u16Data&0x0400)==0x0000)
4660 printf("[DVBS]: BBH Decode Done ===============: Fail. \n");
4661 else
4662 printf("[DVBS]: BBH Decode Done ===============: OK. \n");
4663
4664 if ((u16Data&0x0800)==0x0000)
4665 printf("[DVBS]: ISRC Calculate Done ===========: Fail. \n");
4666 else
4667 printf("[DVBS]: ISRC Calculate Done ===========: OK. \n");
4668
4669 if ((u16Data&0x1000)==0x0000)
4670 printf("[DVBS]: Syncd Check Error =============: Fail. \n");
4671 else
4672 printf("[DVBS]: Syncd Check Error =============: OK. \n");
4673
4674 //if ((u16Data&0x2000)==0x0000)
4675 // printf("[DVBS]: Syncd Check Error======: Fail. \n");
4676 //else
4677 // printf("[DVBS]: Syncd Check Error======: OK. \n");
4678
4679 if ((u16Data&0x4000)==0x0000)
4680 printf("[DVBS]: Demap Init ====================: Fail. \n");
4681 else
4682 printf("[DVBS]: Demap Init ====================: OK. \n");
4683 */
4684 //Spectrum Information
4685 printf("------------------------------------------------------------------------\n");
4686
4687 u16Address = 0x2836;
4688 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4689 psd_smooth_factor=(u16Data>>8)&0x7F;
4690
4691 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
4692 u16Data = u8Data;
4693 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
4694 u16Data = (u16Data<<8)|u8Data;
4695 u32temp5=u16Data;
4696 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13H, &u8Data);
4697 u16Data = u8Data;
4698 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
4699 u16Data = (u16Data<<8)|u8Data;
4700 u32temp5|=(u16Data<<16);
4701 if (psd_smooth_factor!=0)
4702 srd_left_top_value=(float)u32temp5/256.0/psd_smooth_factor;
4703 else
4704 srd_left_top_value=0;
4705
4706 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
4707 u16Data = u8Data;
4708 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
4709 u16Data = (u16Data<<8)|u8Data;
4710 u32temp5=u16Data;
4711 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
4712 u16Data = u8Data;
4713 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
4714 u16Data = (u16Data<<8)|u8Data;
4715 u32temp5|=(u16Data<<16);
4716 if (psd_smooth_factor!=0)
4717 srd_left_bottom_value=(float)u32temp5/256.0/psd_smooth_factor;
4718 else
4719 srd_left_bottom_value=0;
4720
4721 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
4722 u16Data = u8Data;
4723 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
4724 u16Data = (u16Data<<8)|u8Data;
4725 u32temp5=u16Data;
4726 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE17H, &u8Data);
4727 u16Data = u8Data;
4728 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE17L, &u8Data);
4729 u16Data = (u16Data<<8)|u8Data;
4730 u32temp5|=(u16Data<<16);
4731 if (psd_smooth_factor!=0)
4732 srd_right_top_value=(float)u32temp5/256.0/psd_smooth_factor;
4733 else
4734 srd_right_top_value=0;
4735
4736 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18H, &u8Data);
4737 u16Data = u8Data;
4738 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18L, &u8Data);
4739 u16Data = (u16Data<<8)|u8Data;
4740 u32temp5=u16Data;
4741 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19H, &u8Data);
4742 u16Data = u8Data;
4743 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19L, &u8Data);
4744 u16Data = (u16Data<<8)|u8Data;
4745 u32temp5|=(u16Data<<16);
4746 if (psd_smooth_factor!=0)
4747 srd_right_bottom_value=(float)u32temp5/256.0/psd_smooth_factor;
4748 else
4749 srd_right_bottom_value=0;
4750
4751 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1AH, &u8Data);
4752 u16Data = u8Data;
4753 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1AL, &u8Data);
4754 u16Data = (u16Data<<8)|u8Data;
4755 srd_left=u16Data;
4756 printf("[DVBS]: FFT Left ======================: %d, %f\n", srd_left, srd_left_top_value - srd_left_bottom_value);
4757 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1BH, &u8Data);
4758 u16Data = u8Data;
4759 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1BL, &u8Data);
4760 u16Data = (u16Data<<8)|u8Data;
4761 srd_right=u16Data;
4762 printf("[DVBS]: FFT Right =====================: %d, %f\n", srd_right, srd_right_top_value - srd_right_bottom_value);
4763 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1CH, &u8Data);
4764 u16Data = u8Data;
4765 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1CL, &u8Data);
4766 u16Data = (u16Data<<8)|u8Data;
4767 srd_left_top=u16Data;
4768 printf("[DVBS]: FFT Left Top ==================: %d, %f\n", srd_left_top, srd_left_top_value);
4769 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1DH, &u8Data);
4770 u16Data = u8Data;
4771 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1DL, &u8Data);
4772 u16Data = (u16Data<<8)|u8Data;
4773 srd_left_bottom=u16Data;
4774 printf("[DVBS]: FFT Left Bottom ===============: %d, %f\n", srd_left_bottom, srd_left_bottom_value);
4775 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1EH, &u8Data);
4776 u16Data = u8Data;
4777 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1EL, &u8Data);
4778 u16Data = (u16Data<<8)|u8Data;
4779 srd_right_top=u16Data;
4780 printf("[DVBS]: FFT Right Top =================: %d, %f\n", srd_right_top, srd_right_top_value);
4781 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1FH, &u8Data);
4782 u16Data = u8Data;
4783 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1FL, &u8Data);
4784 u16Data = (u16Data<<8)|u8Data;
4785 srd_right_bottom=u16Data;
4786 printf("[DVBS]: FFT Right Bottom ==============: %d, %f\n", srd_right_bottom, srd_right_bottom_value);
4787
4788 printf("-----------------------------------------\n");
4789 printf("[DVBS]: Left-Bottom ===================: %d\n", srd_left-srd_left_bottom);
4790 printf("[DVBS]: Left-Top ======================: %d\n", srd_left_top - srd_left);
4791 printf("[DVBS]: Right-Top =====================: %d\n", srd_right - srd_right_top);
4792 printf("[DVBS]: Right-Bottom ==================: %d\n", srd_right_bottom - srd_right);
4793
4794 if (psd_smooth_factor!=0)
4795 {
4796 if ((srd_left_top-srd_left_bottom)!=0)
4797 printf("[DVBS]: Left Slope ====================: %f\n", (srd_left_top_value - srd_left_bottom_value)/(srd_left_top-srd_left_bottom));
4798 else
4799 printf("[DVBS]: Left Slope ====================: %f\n", 0.000000);
4800
4801 if((srd_right_bottom - srd_right_top)!=0)
4802 printf("[DVBS]: Right Slope ===================: %f\n", (srd_right_top_value - srd_right_bottom_value)/(srd_right_bottom - srd_right_top));
4803 else
4804 printf("[DVBS]: Right Slope ===================: %f\n", 0.000000);
4805
4806 if (((srd_right_top_value - srd_right_bottom_value)!=0)&&((srd_right_bottom - srd_right_top))!=0)
4807 printf("[DVBS]: Slope Ratio ===================: %f\n", ((srd_left_top_value - srd_left_bottom_value)/(srd_left_top-srd_left_bottom))/((srd_right_top_value - srd_right_bottom_value)/(srd_right_bottom - srd_right_top)));
4808 else
4809 printf("[DVBS]: Slope Ratio ===================: %f\n", 0.000000);
4810 }
4811 else
4812 {
4813 printf("[DVBS]: Left Slope ======================: %d\n", 0);
4814 printf("[DVBS]: Right Slope =====================: %d\n", 0);
4815 printf("[DVBS]: Slope Ratio =====================: %d\n", 0);
4816 }
4817 #endif
4818 return status;
4819 }
4820
INTERN_DVBS_Demod_Get_Debug_Info_polling(void)4821 MS_BOOL INTERN_DVBS_Demod_Get_Debug_Info_polling(void)
4822 {
4823 MS_BOOL bRet = FALSE;
4824 #if 0
4825 MS_U8 u8Data = 0;
4826 MS_U16 u16Data = 0;
4827 MS_U16 u16Address = 0;
4828 MS_U32 u32DebugInfo_Fb = 0; //Fb, SymbolRate
4829 MS_U32 u32DebugInfo_Fs = 96000; //Fs, 96000k
4830 float AGC_IF_Gain;
4831 float DAGC0_Gain, DAGC1_Gain, DAGC2_Gain, DAGC3_Gain, DAGC0_Peak_Mean, DAGC1_Peak_Mean, DAGC2_Peak_Mean, DAGC3_Peak_Mean;
4832 short AGC_Err, DAGC0_Err, DAGC1_Err, DAGC2_Err, DAGC3_Err;
4833 float DCR_Offset_I, DCR_Offset_Q;
4834 float FineCFO_loop_input_value, FineCFO_loop_out_value;
4835 double FineCFO_loop_ki_value, TR_loop_ki;
4836 float PR_in_value, PR_out_value, PR_loop_ki, PR_loopback_ki;
4837 float IQB_Phase, IQB_Gain;
4838 MS_U16 IIS_cnt, ConvegenceLen;
4839 float Linear_SNR_dd, SNR_dd_dB, Linear_SNR_da, SNR_da_dB, SNR_nda_dB, Linear_SNR;
4840 float Packet_Err, BER;
4841 float TR_Indicator_ff, TR_SFO_Converge, Fs_value, Fb_value;
4842 float TR_Loop_Output, TR_Loop_Ki, TR_loop_input, TR_tmp0, TR_tmp1, TR_tmp2;
4843 float Eq_variance_da, Eq_variance_dd;
4844 float ndasnr_ratio, ndasnr_a, ndasnr_ab;
4845 MS_U16 BitErr, BitErrPeriod;
4846 MS_BOOL BEROver;
4847
4848 //Fb
4849 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
4850 //bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
4851 if((u8Data&0x02)==0x00) //Manual Tune
4852 {
4853 u32DebugInfo_Fb = 0x0;//_u32CurrentSR;
4854 }
4855 else //Blind Scan
4856 {
4857 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
4858 u16Data = u8Data;
4859 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
4860 u16Data = (u16Data<<8)|u8Data;
4861 u32DebugInfo_Fb = u16Data;
4862 }
4863 printf("++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
4864 printf("Fs ====================================: %lu [kHz]\n",u32DebugInfo_Fs);
4865 printf("Fb ====================================: %lu [kHz]\n",u32DebugInfo_Fb);
4866 //---------------------------------------------------------
4867 //Page1-GAIN & DCR
4868 //---------------------------------------------------------
4869 //GAIN
4870 printf("\n");
4871 printf("========================================================================\n");
4872 printf("Debug Message [GAIN & DCR]==============================================\n");
4873
4874 //Debug select
4875 u16Address = (DEBUG_SEL_IF_AGC_GAIN>>16)&0xffff;
4876 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4877 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_IF_AGC_GAIN)&0xffff);
4878 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4879
4880 //Freeze and dump
4881 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4882 //AGC_IF_GAIN
4883 u16Address = (DEBUG_OUT_AGC)&0xffff;
4884 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4885 AGC_IF_Gain=u16Data;
4886 //Unfreeze
4887 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4888
4889 AGC_IF_Gain=AGC_IF_Gain/0x8000; //(16, 15)
4890 printf("[DVBS]: AGC_IF_Gain ===================: %f\n", AGC_IF_Gain);
4891 //---------------------------------------------------------
4892 //Debug select
4893 u16Address = (DEBUG_SEL_DAGC0_GAIN>>16)&0xffff;
4894 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4895 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_GAIN)&0xffff);
4896 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4897
4898 //Freeze and dump
4899 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4900 //DAGC0_GAIN
4901 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
4902 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4903 u16Data = (u16Data>>4);
4904 DAGC0_Gain=(u16Data&0x0fff);
4905 //Unfreeze
4906 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4907 //---------------------------------------------------------
4908 //Debug select
4909 u16Address = (DEBUG_SEL_DAGC1_GAIN>>16)&0xffff;
4910 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4911 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_GAIN)&0xffff);
4912 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4913
4914 //Freeze and dump
4915 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4916 //DAGC1_GAIN
4917 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
4918 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4919 DAGC1_Gain=(u16Data&0x07ff);
4920 //Unfreeze
4921 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4922 //---------------------------------------------------------
4923 //Debug select
4924 u16Address = (DEBUG_SEL_DAGC2_GAIN>>16)&0xffff;
4925 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4926 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_GAIN)&0xffff);
4927 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4928
4929 //Freeze and dump
4930 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4931 //DAGC2_GAIN
4932 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
4933 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4934 DAGC2_Gain=(u16Data&0x0fff);
4935 //Unfreeze
4936 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4937 //---------------------------------------------------------
4938 //Debug select
4939 u16Address = (DEBUG_SEL_DAGC3_GAIN>>16)&0xffff;
4940 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4941 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_GAIN)&0xffff);
4942 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4943
4944 //Freeze and dump
4945 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4946 //DAGC3_GAIN
4947 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
4948 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4949 u16Data = (u16Data>>4);
4950 DAGC3_Gain=(u16Data&0x0fff);
4951 //Unfreeze
4952 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4953 //---------------------------------------------------------
4954
4955 DAGC0_Gain=DAGC0_Gain/0x200; //<12,9>
4956 DAGC1_Gain=DAGC1_Gain/0x200; //<11,9>
4957 DAGC2_Gain=DAGC2_Gain/0x200; //<12,9>
4958 DAGC3_Gain=DAGC3_Gain/0x200; //<12,9>
4959 printf("[DVBS]: DAGC0_Gain ====================: %f\n", DAGC0_Gain);
4960 printf("[DVBS]: DAGC1_Gain ====================: %f\n", DAGC1_Gain);
4961 printf("[DVBS]: DAGC2_Gain ====================: %f\n", DAGC2_Gain);
4962 printf("[DVBS]: DAGC3_Gain ====================: %f\n", DAGC3_Gain);
4963
4964 //---------------------------------------------------------
4965 //ERROR
4966 //Debug select
4967 u16Address = (DEBUG_SEL_AGC_ERR>>16)&0xffff;
4968 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4969 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_AGC_ERR)&0xffff);
4970 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4971
4972 //Freeze and dump
4973 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4974 //AGC_ERR
4975 u16Address = (DEBUG_OUT_AGC)&0xffff;
4976 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4977 AGC_Err=(u16Data&0x03ff);
4978 //Unfreeze
4979 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4980
4981 //Debug select
4982 u16Address = (DEBUG_SEL_DAGC0_ERR>>16)&0xffff;
4983 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4984 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_ERR)&0xffff);
4985 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4986
4987 //Freeze and dump
4988 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4989 //DAGC0_ERR
4990 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
4991 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4992 u16Data = (u16Data>>4);
4993 DAGC0_Err=(u16Data&0x7fff);
4994 //Unfreeze
4995 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4996
4997 //Debug select
4998 u16Address = (DEBUG_SEL_DAGC1_ERR>>16)&0xffff;
4999 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5000 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_ERR)&0xffff);
5001 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5002
5003 //Freeze and dump
5004 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5005 //DAGC1_ERR
5006 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
5007 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5008 DAGC1_Err=(u16Data&0x7fff);
5009 //Unfreeze
5010 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5011
5012 //Debug select
5013 u16Address = (DEBUG_SEL_DAGC2_ERR>>16)&0xffff;
5014 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5015 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_ERR)&0xffff);
5016 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5017
5018 //Freeze and dump
5019 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5020 //DAGC2_ERR
5021 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
5022 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5023 DAGC2_Err=(u16Data&0x7fff);
5024 //Unfreeze
5025 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5026
5027 //Debug select
5028 u16Address = (DEBUG_SEL_DAGC3_ERR>>16)&0xffff;
5029 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5030 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_ERR)&0xffff);
5031 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5032
5033 //Freeze and dump
5034 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5035 //DAGC3_ERR
5036 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
5037 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5038 u16Data = (u16Data>>4);
5039 DAGC3_Err=(u16Data&0x7fff);
5040 //Unfreeze
5041 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5042
5043 if (AGC_Err>=0x200)
5044 AGC_Err=AGC_Err-0x400;
5045 if (DAGC0_Err>=0x4000)
5046 DAGC0_Err=DAGC0_Err-0x8000;
5047 if (DAGC1_Err>=0x4000)
5048 DAGC1_Err=DAGC1_Err-0x8000;
5049 if (DAGC2_Err>=0x4000)
5050 DAGC2_Err=DAGC2_Err-0x8000;
5051 if (DAGC3_Err>=0x4000)
5052 DAGC3_Err=DAGC3_Err-0x8000;
5053
5054 printf("[DVBS]: AGC_Err =========================: %.3f\n", (float)AGC_Err);
5055 printf("[DVBS]: DAGC0_Err =======================: %.3f\n", (float)DAGC0_Err);
5056 printf("[DVBS]: DAGC1_Err =======================: %.3f\n", (float)DAGC1_Err);
5057 printf("[DVBS]: DAGC2_Err =======================: %.3f\n", (float)DAGC2_Err);
5058 printf("[DVBS]: DAGC3_Err =======================: %.3f\n", (float)DAGC3_Err);
5059 //---------------------------------------------------------
5060 //PEAK_MEAN
5061 //Debug select
5062 u16Address = (DEBUG_SEL_DAGC0_PEAK_MEAN>>16)&0xffff;
5063 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5064 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_PEAK_MEAN)&0xffff);
5065 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5066
5067 //Freeze and dump
5068 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5069 //DAGC0_PEAK_MEAN
5070 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
5071 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5072 u16Data = (u16Data>>4);
5073 DAGC0_Peak_Mean=(u16Data&0x0fff);
5074 //Unfreeze
5075 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5076
5077 //Debug select
5078 u16Address = (DEBUG_SEL_DAGC1_PEAK_MEAN>>16)&0xffff;
5079 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5080 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_PEAK_MEAN)&0xffff);
5081 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5082
5083 //Freeze and dump
5084 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5085 //DAGC1_PEAK_MEAN
5086 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
5087 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5088 DAGC1_Peak_Mean=(u16Data&0x0fff);
5089 //Unfreeze
5090 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5091
5092 //Debug select
5093 u16Address = (DEBUG_SEL_DAGC2_PEAK_MEAN>>16)&0xffff;
5094 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5095 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_PEAK_MEAN)&0xffff);
5096 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5097
5098 //Freeze and dump
5099 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5100 //DAGC2_PEAK_MEAN
5101 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
5102 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5103 DAGC2_Peak_Mean=(u16Data&0x0fff);
5104 //Unfreeze
5105 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5106
5107 //Debug select
5108 u16Address = (DEBUG_SEL_DAGC3_PEAK_MEAN>>16)&0xffff;
5109 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5110 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_PEAK_MEAN)&0xffff);
5111 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5112
5113 //Freeze and dump
5114 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5115 //DAGC3_PEAK_MEAN
5116 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
5117 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5118 u16Data = (u16Data>>4);
5119 DAGC3_Peak_Mean=(u16Data&0x0fff);
5120 //Unfreeze
5121 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5122
5123
5124 DAGC0_Peak_Mean = DAGC0_Peak_Mean / 0x800; //<12,11>
5125 DAGC1_Peak_Mean = DAGC1_Peak_Mean / 0x800; //<12,11>
5126 DAGC2_Peak_Mean = DAGC2_Peak_Mean / 0x800; //<12,11>
5127 DAGC3_Peak_Mean = DAGC3_Peak_Mean / 0x800; //<12,11>
5128
5129 printf("[DVBS]: DAGC0_Peak_Mean ===============: %f\n", DAGC0_Peak_Mean);
5130 printf("[DVBS]: DAGC1_Peak_Mean ===============: %f\n", DAGC1_Peak_Mean);
5131 printf("[DVBS]: DAGC2_Peak_Mean ===============: %f\n", DAGC2_Peak_Mean);
5132 printf("[DVBS]: DAGC3_Peak_Mean ===============: %f\n", DAGC3_Peak_Mean);
5133 //---------------------------------------------------------
5134 //Freeze and dump
5135 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5136
5137 u16Address = (DCR_OFFSET)&0xffff;
5138 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5139
5140 DCR_Offset_I=(u16Data&0xff);
5141 if (DCR_Offset_I >= 0x80)
5142 DCR_Offset_I = DCR_Offset_I-0x100;
5143 DCR_Offset_I = DCR_Offset_I/0x80;
5144
5145 DCR_Offset_Q=(u16Data>>8)&0xff;
5146 if (DCR_Offset_Q >= 0x80)
5147 DCR_Offset_Q = DCR_Offset_Q-0x100;
5148 DCR_Offset_Q = DCR_Offset_Q/0x80;
5149
5150 //Unfreeze
5151 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5152
5153 printf("[DVBS]: DCR_Offset_I ==================: %f\n", DCR_Offset_I);
5154 printf("[DVBS]: DCR_Offset_Q ==================: %f\n", DCR_Offset_Q);
5155 //---------------------------------------------------------
5156 ////Page1-FineCFO & PR & IIS & IQB
5157 //---------------------------------------------------------
5158 //FineCFO
5159 printf("------------------------------------------------------------------------\n");
5160 printf("Debug Message [FineCFO & PR & IIS & IQB & SNR Status]===================\n");
5161 //Debug Select
5162 u16Address = INNER_DEBUG_SEL;
5163 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5164 u16Data=((u16Data&0xC0FF)|0x0400);
5165 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5166
5167 //Freeze and dump
5168 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5169
5170 u16Address = INNEREXT_FINEFE_DBG_OUT0;
5171 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5172 FineCFO_loop_out_value=u16Data;
5173 u16Address = INNEREXT_FINEFE_DBG_OUT2;
5174 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5175 FineCFO_loop_out_value=(FineCFO_loop_out_value+(float)u16Data*pow(2.0, 16));
5176
5177 //Too large.Use 10Bit
5178 u16Address = INNEREXT_FINEFE_KI_FF0;
5179 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5180 FineCFO_loop_ki_value=u16Data;
5181 u16Address = INNEREXT_FINEFE_KI_FF2;
5182 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5183 FineCFO_loop_ki_value=(FineCFO_loop_ki_value+(float)u16Data*pow(2.0, 16));
5184 u16Address = INNEREXT_FINEFE_KI_FF4;
5185 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5186 FineCFO_loop_ki_value=(FineCFO_loop_ki_value+(double)(u16Data&0x00FF)*pow(2.0, 32));
5187 //Unfreeze
5188 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5189
5190 //---------------------------------------------------------
5191 //Debug Select
5192 u16Address = INNER_DEBUG_SEL;
5193 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5194 u16Data=((u16Data&0xC0FF)|0x0100);
5195 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5196
5197 //Freeze and dump
5198 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5199
5200 u16Address = INNEREXT_FINEFE_DBG_OUT0;
5201 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5202 FineCFO_loop_input_value=u16Data;
5203 u16Address = INNEREXT_FINEFE_DBG_OUT2;
5204 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5205 FineCFO_loop_input_value=(FineCFO_loop_input_value+(float)u16Data*pow(2.0, 16));
5206
5207 //Unfreeze
5208 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5209
5210 FineCFO_loop_ki_value = FineCFO_loop_ki_value/1024;
5211
5212 if (FineCFO_loop_out_value > 8388608)
5213 FineCFO_loop_out_value=FineCFO_loop_out_value - 16777216;
5214 if (FineCFO_loop_ki_value > 536870912)//549755813888/1024)
5215 FineCFO_loop_ki_value=FineCFO_loop_ki_value - 1073741824;//1099511627776/1024;
5216 if (FineCFO_loop_input_value> 1048576)
5217 FineCFO_loop_input_value=FineCFO_loop_input_value - 2097152;
5218
5219 FineCFO_loop_out_value = ((float)FineCFO_loop_out_value/16777216);
5220 FineCFO_loop_ki_value = ((double)FineCFO_loop_ki_value/67108864*u32DebugInfo_Fb);//68719476736/1024*Fb
5221 FineCFO_loop_input_value = ((float)FineCFO_loop_input_value/2097152);
5222
5223 printf("[DVBS]: FineCFO_loop_out_value ========: %f \n", FineCFO_loop_out_value);
5224 printf("[DVBS]: FineCFO_loop_ki_value =========: %f \n", FineCFO_loop_ki_value);
5225 printf("[DVBS]: FineCFO_loop_input_value ======: %f \n", FineCFO_loop_input_value);
5226
5227 //---------------------------------------------------------
5228 //Phase Recovery
5229 //Debug select
5230 u16Address = INNER_DEBUG_SEL;
5231 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5232 u16Data=(((u16Data&0x00FF)|0x0600)&0xffff);
5233 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5234
5235 //Freeze and dump
5236 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5237
5238 u16Address = INNER_PR_DEBUG_OUT0;
5239 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5240 PR_out_value=u16Data;
5241 if (PR_out_value>=0x1000)
5242 PR_out_value=PR_out_value-0x2000;
5243
5244 //Unfreeze
5245 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5246 //---------------------------------------------------------
5247 //Debug select
5248 u16Address = INNER_DEBUG_SEL;
5249 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5250 u16Data=(((u16Data&0x00FF)|0x0100)&0xffff);
5251 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5252
5253 //Freeze and dump
5254 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5255
5256 u16Address = INNER_PR_DEBUG_OUT0;
5257 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5258 PR_in_value=u16Data;
5259 u16Address = INNER_PR_DEBUG_OUT2;
5260 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5261 PR_in_value=(((u16Data&0x000F)<<16)|(MS_U16)PR_in_value);
5262 if (PR_in_value>=0x80000)
5263 PR_in_value=PR_in_value-0x100000;
5264
5265 //Unfreeze
5266 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5267 //---------------------------------------------------------
5268 //Debug select
5269 u16Address = INNER_DEBUG_SEL;
5270 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5271 u16Data=(((u16Data&0xC0FF)|0x0400)&0xffff);
5272 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5273
5274 //Freeze and dump
5275 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5276
5277 u16Address = INNER_PR_DEBUG_OUT0;
5278 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5279 PR_loop_ki=u16Data;
5280 u16Address = INNER_PR_DEBUG_OUT2;
5281 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5282 PR_loop_ki=(((u16Data&0x00FF)<<16)+PR_loop_ki);
5283 if (PR_loop_ki>=0x800000)
5284 PR_loop_ki=PR_loop_ki-0x1000000;
5285
5286 //Unfreeze
5287 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5288 //---------------------------------------------------------
5289 //Debug select
5290 u16Address = INNER_DEBUG_SEL;
5291 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5292 u16Data=(((u16Data&0x00FF)|0x0500)&0xffff);
5293 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5294
5295 //Freeze and dump
5296 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5297
5298 u16Address = INNER_PR_DEBUG_OUT0;
5299 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5300 PR_loopback_ki=u16Data;
5301 u16Address = INNER_PR_DEBUG_OUT2;
5302 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5303 PR_loopback_ki=(((u16Data&0x00FF)<<16)+PR_loopback_ki);
5304 if (PR_loopback_ki>=0x800000)
5305 PR_loopback_ki=PR_loopback_ki-0x1000000;
5306
5307 //Unfreeze
5308 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5309
5310 PR_out_value = ((float)PR_out_value/4096);
5311 PR_in_value = ((float)PR_in_value/131072);
5312 PR_loop_ki = ((float)PR_loop_ki/67108864*u32DebugInfo_Fb);
5313 PR_loopback_ki = ((float)PR_loopback_ki/67108864*u32DebugInfo_Fb);
5314
5315 printf("[DVBS]: PR_out_value ==================: %f\n", PR_out_value);
5316 printf("[DVBS]: PR_in_value ===================: %f\n", PR_in_value);
5317 printf("[DVBS]: PR_loop_ki ====================: %f\n", PR_loop_ki);
5318 printf("[DVBS]: PR_loopback_ki ================: %f\n", PR_loopback_ki);
5319 //---------------------------------------------------------
5320 //IIS
5321 //Freeze and dump
5322 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5323
5324 u16Address = (IIS_COUNT0)&0xffff;
5325 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5326 IIS_cnt=u16Data;
5327 u16Address = (IIS_COUNT2)&0xffff;
5328 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5329 IIS_cnt=(u16Data&0x1f)<<16|IIS_cnt;
5330
5331 printf("[DVBS]: IIS_cnt =======================: %d\n", IIS_cnt);
5332
5333 //Unfreeze
5334 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5335 //IQB
5336 //Freeze and dump
5337 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5338
5339 u16Address = (IQB_PHASE)&0xffff;
5340 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5341 IQB_Phase=u16Data&0x3FF;
5342 if (IQB_Phase>=0x200)
5343 IQB_Phase=IQB_Phase-0x400;
5344 IQB_Phase=IQB_Phase/0x400*180;
5345
5346 u16Address = (IQB_GAIN)&0xffff;
5347 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5348 IQB_Gain=u16Data&0x7FF;
5349 IQB_Gain=IQB_Gain/0x400;
5350
5351 printf("[DVBS]: IQB_Phase =====================: %f\n", IQB_Phase);
5352 printf("[DVBS]: IQB_Gain ======================: %f\n", IQB_Gain);
5353
5354 //Unfreeze
5355 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5356 //---------------------------------------------------------
5357 //SNR
5358 //Freeze and dump
5359 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5360
5361 Eq_variance_da=0;
5362 u16Address = 0x249E;
5363 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5364 Eq_variance_da=u16Data;
5365 u16Address = 0x24A0;
5366 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5367 Eq_variance_da=((float)(u16Data&0x03fff)*pow(2.0, 16)+Eq_variance_da)/pow(2.0, 29);
5368
5369 if (Eq_variance_da==0)
5370 Eq_variance_da=1;
5371 Linear_SNR_da=1.0/Eq_variance_da;
5372 SNR_da_dB=10*log10(Linear_SNR_da);
5373
5374 Eq_variance_dd=0;
5375 u16Address = 0x24A2;
5376 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5377 Eq_variance_dd=u16Data;
5378 u16Address = 0x24A4;
5379 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5380 Eq_variance_dd=(((float)(u16Data&0x3fff)*65536)+Eq_variance_dd)/pow(2.0, 29);
5381
5382 if (Eq_variance_dd==0)
5383 Eq_variance_dd=1;
5384 Linear_SNR_dd=1.0/Eq_variance_dd;
5385 SNR_dd_dB=10*log10(Linear_SNR_dd);
5386
5387 ndasnr_a=0;
5388 u16Address = 0x248C;
5389 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5390 ndasnr_a=u16Data;
5391 u16Address = 0x248E;
5392 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5393 ndasnr_a=(((float)(u16Data&0x0003)*pow(2.0, 16))+ndasnr_a)/65536;
5394
5395 ndasnr_ab=0;
5396 u16Address = 0x2490;
5397 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5398 ndasnr_ab=u16Data;
5399 u16Address = 0x2492;
5400 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5401 ndasnr_ab=(((float)(u16Data&0x03ff)*pow(2.0, 16))+ndasnr_ab)/4194304;
5402
5403 ndasnr_ab=sqrt(ndasnr_ab);
5404 if (ndasnr_ab==0)
5405 ndasnr_ab=1;
5406 ndasnr_ratio=(float)ndasnr_a/ndasnr_ab;
5407 if (ndasnr_ratio> 1)
5408 SNR_nda_dB=10*log10(1/(ndasnr_ratio - 1));
5409 else
5410 SNR_nda_dB=0;
5411
5412 u16Address = 0x24BA;
5413 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5414 Linear_SNR=u16Data;
5415 u16Address = 0x24BC;
5416 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5417 Linear_SNR=(((float)(u16Data&0x0007)*pow(2.0, 16))+Linear_SNR)/64;
5418 if (Linear_SNR==0)
5419 Linear_SNR=1;
5420 Linear_SNR=10*log10(Linear_SNR);
5421
5422 //Unfreeze
5423 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5424 printf("[DVBS]: SNR ===========================: %.2f\n", Linear_SNR);
5425 printf("[DVBS]: SNR_DA_dB =====================: %.2f\n", SNR_da_dB);
5426 printf("[DVBS]: SNR_DD_dB =====================: %.2f\n", SNR_dd_dB);
5427 printf("[DVBS]: SNR_NDA_dB ====================: %.2f\n", SNR_nda_dB);
5428 //---------------------------------------------------------
5429 printf("------------------------------------------------------------------------\n");
5430 printf("Debug Message [DVBS - PacketErr & BER]==================================\n");
5431 //BER
5432 //freeze
5433 u16Address = 0x2103;
5434 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5435 u16Data=u16Data|0x0001;
5436 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5437
5438 // bank 17 0x18 [7:0] reg_bit_err_sblprd_7_0 [15:8] reg_bit_err_sblprd_15_8
5439 u16Address = 0x2166;
5440 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5441 Packet_Err=u16Data;
5442
5443 printf("[DVBS]: Packet Err ====================: %.3E\n", Packet_Err);
5444
5445 /////////// Post-Viterbi BER /////////////
5446 // bank 7 0x18 [7:0] reg_bit_err_sblprd_7_0
5447 // [15:8] reg_bit_err_sblprd_15_8
5448 u16Address = 0x2146;
5449 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5450 BitErrPeriod=u16Data;
5451
5452 // bank 17 0x1D [7:0] reg_bit_err_num_7_0 [15:8] reg_bit_err_num_15_8
5453 // bank 17 0x1E [7:0] reg_bit_err_num_23_16 [15:8] reg_bit_err_num_31_24
5454 u16Address = 0x216A;
5455 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5456 BitErr=u16Data;
5457 u16Address = 0x216C;
5458 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5459 BitErr=(u16Data<<16)|BitErr;
5460
5461 if (BitErrPeriod ==0 )//protect 0
5462 BitErrPeriod=1;
5463 if (BitErr <=0 )
5464 BER=0.5 / (float)(BitErrPeriod*128*188*8);
5465 else
5466 BER=(float)(BitErr) / (float)(BitErrPeriod*128*188*8);
5467
5468 printf("[DVBS]: Post-Viterbi BER ==============: %.3E\n", BER);
5469
5470 // bank 7 0x19 [7] reg_bit_err_num_freeze
5471 u16Address = 0x2103;
5472 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5473 u16Data=u16Data&(~0x0001);
5474 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5475
5476 /////////// Pre-Viterbi BER /////////////
5477 // bank 17 0x08 [3] reg_rd_freezeber
5478 u16Address = 0x2110;
5479 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5480 u16Data=u16Data|0x0008;
5481 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5482
5483 // bank 17 0x0b [7:0] reg_ber_timerl [15:8] reg_ber_timerm
5484 // bank 17 0x0c [5:0] reg_ber_timerh
5485 u16Address = 0x2116;
5486 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5487 BitErrPeriod=u16Data;
5488 u16Address = 0x2118;
5489 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5490 BitErrPeriod=((u16Data&0x3f)<<16)|BitErrPeriod;
5491
5492 // bank 17 0x0f [7:0] reg_ber_7_0 [15:8] reg_ber_15_8
5493 u16Address = 0x211E;
5494 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5495 BitErr=u16Data;
5496
5497 // bank 17 0x0D [13:8] reg_cor_intstat_reg
5498 u16Address = 0x211A;
5499 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5500 if (u16Data & 0x1000)
5501 {
5502 BEROver = true;
5503 }
5504 else
5505 {
5506 BEROver = false;
5507 }
5508
5509 if (BitErrPeriod ==0 )//protect 0
5510 BitErrPeriod=1;
5511 if (BitErr <=0 )
5512 BER=0.5 / (float)(BitErrPeriod) / 256;
5513 else
5514 BER=(float)(BitErr) / (float)(BitErrPeriod) / 256;
5515 printf("[DVBS]: Pre-Viterbi BER ===============: %.3E\n", BER);
5516
5517 // bank 17 0x08 [3] reg_rd_freezeber
5518 u16Address = 0x2110;
5519 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5520 u16Data=u16Data&(~0x0008);
5521 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5522
5523 u16Address = 0x2188;
5524 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5525 ConvegenceLen = ((u16Data>>8)&0xFF);
5526 printf("[DVBS]: ConvegenceLen =================: %d\n", ConvegenceLen);
5527
5528 //---------------------------------------------------------
5529 //Timing Recovery
5530 //Debug select
5531 u16Address = (INNER_DEBUG_SEL_TR>>16)&0xffff;
5532 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5533 u16Data=(((u16Data&0x00ff)|INNER_DEBUG_SEL_TR)&0xffff);
5534 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5535
5536 //Freeze and dump
5537 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5538
5539 u16Address = (TR_INDICATOR_FF0)&0xffff;
5540 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5541 TR_Indicator_ff=u16Data;
5542 u16Address = (TR_INDICATOR_FF0)&0xffff;
5543 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5544 TR_Indicator_ff=((u16Data<<16) | (MS_U16)TR_Indicator_ff)&0x7fffff;
5545 if (TR_Indicator_ff >= 0x400000)
5546 TR_Indicator_ff=TR_Indicator_ff - 0x800000;
5547
5548 //Unfreeze
5549 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5550
5551 //Debug select
5552 u16Address = (DEBUG_SEL_TR_SFO_CONVERGE>>16)&0xffff;
5553 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5554 u16Data=(((u16Data&0x00ff)|DEBUG_SEL_TR_SFO_CONVERGE)&0xffff);
5555 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5556
5557 //Freeze and dump
5558 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5559
5560 u16Address = (TR_INDICATOR_FF0)&0xffff;
5561 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5562 TR_SFO_Converge=u16Data;
5563 u16Address = (TR_INDICATOR_FF0)&0xffff;
5564 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5565 TR_SFO_Converge=((u16Data<<16) | (MS_U16)TR_SFO_Converge)&0x7fffff;
5566 if (TR_SFO_Converge >= 0x400000)
5567 TR_SFO_Converge=TR_SFO_Converge - 0x800000;
5568
5569 u16Address = INNER_TR_LOPF_VALUE_DEBUG0;
5570 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5571 TR_loop_ki=u16Data;
5572 u16Address = INNER_TR_LOPF_VALUE_DEBUG2;
5573 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5574 TR_loop_ki=((float)u16Data*pow(2.0, 16))+TR_loop_ki;
5575 u16Address = INNER_TR_LOPF_VALUE_DEBUG4;
5576 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5577 TR_loop_ki=(((double)(u16Data&0x01ff)*pow(2.0, 32))+ TR_loop_ki);
5578 if (TR_loop_ki>=pow(2.0, 40))
5579 TR_loop_ki=TR_loop_ki-pow(2.0, 41);
5580
5581 //Unfreeze
5582 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5583
5584 //Debug select
5585 u16Address = (DEBUG_SEL_TR_INPUT>>16)&0xffff;
5586 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5587 u16Data=(((u16Data&0x00ff)|DEBUG_SEL_TR_INPUT)&0xffff);
5588 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5589
5590 //Freeze and dump
5591 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5592
5593 u16Address = (TR_INDICATOR_FF0)&0xffff;
5594 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5595 TR_loop_input=u16Data;
5596 //banknum=(TR_INDICATOR_FF1>>8)&0xff;
5597 //addr=(TR_INDICATOR_FF1)&0xff;
5598 //if(InformRead(banknum, addr, &data)==FALSE) return;
5599 //TR_loop_input=((float)((data&0x00ff)<<16) + TR_loop_input);
5600 if (TR_loop_input >= 0x8000)
5601 TR_loop_input=TR_loop_input - 0x10000;
5602
5603 //Unfreeze
5604 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5605
5606 Fs_value=u32DebugInfo_Fs;
5607 Fb_value=u32DebugInfo_Fb;
5608 TR_tmp0=(float)TR_SFO_Converge/0x200000;
5609 TR_tmp2=TR_loop_ki/pow(2.0, 39);
5610 TR_tmp1=(float)Fs_value/2/Fb_value;
5611
5612 TR_Indicator_ff = (TR_Indicator_ff/0x400);
5613 TR_Loop_Output = (TR_tmp0/TR_tmp1*1000000);
5614 TR_Loop_Ki = (TR_tmp2/TR_tmp1*1000000);
5615 TR_loop_input = (TR_loop_input/0x8000);
5616
5617 printf("[DVBS]: TR_Indicator_ff================: %f \n", TR_Indicator_ff);
5618 printf("[DVBS]: TR_Loop_Output=================: %f [ppm]\n", TR_Loop_Output);
5619 printf("[DVBS]: TR_Loop_Ki=====================: %f [ppm]\n", TR_Loop_Ki);
5620 printf("[DVBS]: TR_loop_input==================: %f \n", TR_loop_input);
5621 #endif
5622 bRet=true;
5623 return bRet;
5624 }
5625
5626 //------------------------------------------------------------------
5627 // END Get And Show Info Function
5628 //------------------------------------------------------------------
5629
5630 //------------------------------------------------------------------
5631 // BlindScan Function
5632 //------------------------------------------------------------------
5633
INTERN_DVBS_BlindScan_Start(MS_U16 u16StartFreq,MS_U16 u16EndFreq)5634 MS_BOOL INTERN_DVBS_BlindScan_Start(MS_U16 u16StartFreq,MS_U16 u16EndFreq)
5635 {
5636 MS_BOOL status=TRUE;
5637 MS_U8 u8Data=0;
5638
5639 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_Start+\n"));
5640
5641 _u16BlindScanStartFreq=u16StartFreq;
5642 _u16BlindScanEndFreq=u16EndFreq;
5643 _u16TunerCenterFreq=0;
5644 _u16ChannelInfoIndex=0;
5645
5646 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5647 u8Data&=0xd0;
5648 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5649
5650 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)_u16BlindScanStartFreq&0x00ff);
5651 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(_u16BlindScanStartFreq>>8)&0x00ff);
5652
5653 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_Start- _u16BlindScanStartFreq%d u16StartFreq %d u16EndFreq %d\n", _u16BlindScanStartFreq, u16StartFreq, u16EndFreq));
5654
5655 return status;
5656 }
5657
INTERN_DVBS_BlindScan_NextFreq(MS_BOOL * bBlindScanEnd)5658 MS_BOOL INTERN_DVBS_BlindScan_NextFreq(MS_BOOL* bBlindScanEnd)
5659 {
5660 MS_BOOL status=TRUE;
5661 MS_U8 u8Data=0;
5662
5663 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_NextFreq+\n"));
5664
5665 * bBlindScanEnd=FALSE;
5666
5667 if (_u16TunerCenterFreq >=_u16BlindScanEndFreq)
5668 {
5669 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_NextFreq . _u16TunerCenterFreq %d _u16BlindScanEndFreq%d\n", _u16TunerCenterFreq, _u16BlindScanEndFreq));
5670 * bBlindScanEnd=TRUE;
5671
5672 return status;
5673 }
5674 //Set Tuner Frequency
5675 MsOS_DelayTask(10);
5676
5677 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5678 if ((u8Data&0x02)==0x00)//Manual Tune
5679 {
5680 u8Data&=~(0x28);
5681 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5682 u8Data|=0x02;
5683 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5684 u8Data|=0x01;
5685 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5686 }
5687 else
5688 {
5689 u8Data&=~(0x28);
5690 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5691 }
5692
5693 return status;
5694 }
5695
INTERN_DVBS_BlindScan_GetTunerFreq(MS_U16 * u16TunerCenterFreq,MS_U16 * u16TunerCutOffFreq)5696 MS_BOOL INTERN_DVBS_BlindScan_GetTunerFreq(MS_U16 *u16TunerCenterFreq, MS_U16 *u16TunerCutOffFreq)
5697 {
5698 MS_BOOL status=TRUE;
5699 MS_U8 u8Data=0;
5700 MS_U16 u16WaitCount;
5701 MS_U16 u16TunerCutOff;
5702
5703 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_SetTunerFreq+\n"));
5704
5705 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5706 if ((u8Data&0x02)==0x02)
5707 {
5708 u8Data|=0x08;
5709 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5710 u16WaitCount=0;
5711 do
5712 {
5713 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
5714 u16WaitCount++;
5715 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
5716 MsOS_DelayTask(1);
5717 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
5718 }
5719 else if((u8Data&0x01)==0x01)
5720 {
5721 u8Data|=0x20;
5722 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5723 u16WaitCount=0;
5724 do
5725 {
5726 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
5727 u16WaitCount++;
5728 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
5729 MsOS_DelayTask(1);
5730 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
5731 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5732 u8Data|=0x02;
5733 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5734 }
5735 u16WaitCount=0;
5736
5737 _u16TunerCenterFreq=0;
5738
5739 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, &u8Data);
5740 //printf("INTERN_DVBS_BlindScan_GetTunerFreq E_DMD_S2_BS_Tuner_Center_Freq_H=%d\n", u8Data);//RRRRR
5741 _u16TunerCenterFreq=u8Data;
5742 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, &u8Data);
5743 //printf("INTERN_DVBS_BlindScan_GetTunerFreq E_DMD_S2_BS_Tuner_Center_Freq_L=%d\n", u8Data);//RRRRR
5744 _u16TunerCenterFreq=(_u16TunerCenterFreq<<8)|u8Data;
5745
5746 *u16TunerCenterFreq = _u16TunerCenterFreq;
5747 //claire test
5748 u16TunerCutOff=44000;
5749 if(_u16TunerCenterFreq<=990)//980
5750 {
5751
5752 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_BALANCE_TRACK, &u8Data);
5753 if(u8Data==0x01)
5754 {
5755 if(_u16TunerCenterFreq<970)//970
5756 {
5757 u16TunerCutOff=10000;
5758 }
5759 else
5760 {
5761 u16TunerCutOff=20000;
5762 }
5763 u8Data=0x02;
5764 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_BALANCE_TRACK, u8Data);
5765 }
5766 else if(u8Data==0x02)
5767 {
5768 u8Data=0x00;
5769 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_BALANCE_TRACK, u8Data);
5770 }
5771 }
5772 *u16TunerCutOffFreq = u16TunerCutOff;
5773
5774 //end claire test
5775
5776 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_SetTunerFreq- _u16TunerCenterFreq:%d\n", _u16TunerCenterFreq));
5777
5778
5779 return status;
5780 }
5781
INTERN_DVBS_BlindScan_WaitCurFreqFinished(MS_U8 * u8Progress,MS_U8 * u8FindNum,MS_U8 * substate_reg,MS_U32 * u32Data,MS_U16 * symbolrate_reg,MS_U16 * CFO_reg)5782 MS_BOOL INTERN_DVBS_BlindScan_WaitCurFreqFinished(MS_U8* u8Progress,MS_U8 *u8FindNum, MS_U8 *substate_reg, MS_U32 *u32Data, MS_U16 *symbolrate_reg, MS_U16 *CFO_reg)
5783 {
5784 MS_BOOL status=TRUE;
5785 //MS_U32 u32Data=0;
5786 MS_U16 u16Data=0;
5787 MS_U8 u8Data=0, u8Data2=0;
5788 MS_U16 u16WaitCount;
5789
5790 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_WaitCurFreqFinished+\n"));
5791
5792 u16WaitCount=0;
5793 *u8FindNum=0;
5794 *u8Progress=0;
5795
5796 do
5797 {
5798 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data); //State=BlindScan
5799 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_BLINDSCAN_CHECK, &u8Data2); //SubState=BlindScan
5800 u16WaitCount++;
5801 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_BlindScan_WaitCurFreqFinished State: 0x%x Status: 0x%x u16WaitCount:%d\n", u8Data, u8Data2, u16WaitCount));
5802 //printf("INTERN_DVBS_BlindScan_WaitCurFreqFinished State: 0x%x Status: 0x%x u16WaitCount:%d\n", u8Data, u8Data2, u16WaitCount);
5803
5804 MsOS_DelayTask(1);
5805 }while(((u8Data!=17)||(u8Data2!=0xff))&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));//E_DMD_S2_STATE_FLAG
5806
5807
5808
5809 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DUMMY_REG_2, &u8Data);
5810 u16Data=u8Data;
5811
5812
5813 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_WaitCurFreqFinished OuterCheckStatus:0x%x\n", u16Data));
5814
5815 if (u16WaitCount>=INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
5816 {
5817 status=false;
5818 ULOGD("DEMOD","Debug blind scan wait finished time out!!!!\n");
5819 }
5820 else
5821 {
5822
5823 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SUBSTATE_FLAG, &u8Data);//SubState
5824 *substate_reg=u8Data;
5825 if (u8Data==0)
5826 {
5827
5828 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
5829 *u32Data=u8Data;
5830 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
5831 *u32Data=(*u32Data<<8)|u8Data;
5832 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
5833 *u32Data=(*u32Data<<8)|u8Data;
5834 //_u16ChannelInfoArray[0][_u16ChannelInfoIndex]=((*u32Data+500)/1000);
5835 //_u16LockedCenterFreq=((*u32Data+500)/1000); //Center Freq
5836
5837
5838 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
5839 u16Data=u8Data;
5840 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
5841 u16Data=(u16Data<<8)|u8Data;
5842 *symbolrate_reg=u16Data;
5843 //_u16ChannelInfoArray[1][_u16ChannelInfoIndex]=(u16Data);//Symbol Rate
5844 //_u16LockedSymbolRate=u16Data;
5845 //_u16ChannelInfoIndex++;
5846 //*u8FindNum=_u16ChannelInfoIndex;
5847 //printf("claire debug blind scan: find TP frequency %d SR %d index %d\n",_u16LockedCenterFreq,_u16LockedSymbolRate,_u16ChannelInfoIndex);
5848
5849
5850 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
5851 u16Data=u8Data;
5852 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
5853 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset_Locked
5854 *CFO_reg=u16Data;
5855 /*
5856 if (u16Data*1000 >= 0x8000)
5857 {
5858 u16Data=0x10000- u16Data*1000;
5859 _s16CurrentCFO=-1*u16Data/1000;
5860 }
5861 else
5862 {
5863 _s16CurrentCFO=u16Data;
5864 }
5865 */
5866 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
5867 u16Data=u8Data;
5868 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
5869 u16Data=(u16Data<<8)|u8Data;
5870 _u16CurrentStepSize=u16Data; //Tuner_Frequency_Step
5871
5872
5873 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18H, &u8Data);
5874 u16Data=u8Data;
5875 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18L, &u8Data);
5876 u16Data=(u16Data<<8)|u8Data;
5877 _u16PreLockedHB=u16Data; //Pre_Scanned_HB
5878
5879
5880 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19H, &u8Data);
5881 u16Data=u8Data;
5882 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19L, &u8Data);
5883 u16Data=(u16Data<<8)|u8Data;
5884 _u16PreLockedLB=u16Data; //Pre_Scanned_LB
5885
5886 DBG_INTERN_DVBS(ULOGD("DEMOD","Current Locked BWH:%d BWL:%d Step:%d\n ",_u16PreLockedHB, _u16PreLockedLB, _u16CurrentStepSize));
5887 }
5888 else if (u8Data==1)
5889 {
5890 //printf("claire debug blind scan: no find TP\n");
5891
5892
5893 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, &u8Data);
5894 u16Data=u8Data;
5895 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, &u8Data);
5896 u16Data=(u16Data<<8)|u8Data;
5897 _u16NextCenterFreq=u16Data;
5898
5899
5900 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
5901 u16Data=u8Data;
5902 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
5903 u16Data=(u16Data<<8)|u8Data;
5904 _u16PreLockedHB=u16Data; //Pre_Scanned_HB
5905
5906
5907
5908 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13H, &u8Data);
5909 u16Data=u8Data;
5910 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
5911 u16Data=(u16Data<<8)|u8Data;
5912 _u16PreLockedLB=u16Data; //Pre_Scanned_LB
5913
5914
5915 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
5916 u16Data=u8Data;
5917 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
5918 u16Data=(u16Data<<8)|u8Data;
5919 _u16CurrentSymbolRate=u16Data; //Fine_Symbol_Rate
5920
5921
5922 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
5923 u16Data=u8Data;
5924 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
5925 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset
5926 *CFO_reg=u16Data;
5927 /*
5928 if (u16Data*1000 >= 0x8000)
5929 {
5930 u16Data=0x1000- u16Data*1000;
5931 _s16CurrentCFO=-1*u16Data/1000;
5932 }
5933 else
5934 {
5935 _s16CurrentCFO=u16Data;
5936 }
5937 */
5938 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
5939 u16Data=u8Data;
5940 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
5941 u16Data=(u16Data<<8)|u8Data;
5942 _u16CurrentStepSize=u16Data; //Tuner_Frequency_Step
5943
5944 DBG_INTERN_DVBS(ULOGD("DEMOD","Pre Locked BWH:%d BWL:%d Step:%d\n ",_u16PreLockedHB, _u16PreLockedLB, _u16CurrentStepSize));
5945 }
5946 }
5947 *u8Progress=100;
5948
5949 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_WaitCurFreqFinished- u8Progress: %d u8FindNum %d\n", *u8Progress, *u8FindNum));
5950
5951 return status;
5952 }
5953
INTERN_DVBS_BlindScan_Cancel(void)5954 MS_BOOL INTERN_DVBS_BlindScan_Cancel(void)
5955 {
5956 MS_BOOL status=TRUE;
5957 MS_U8 u8Data=0;
5958 MS_U16 u16Data;
5959
5960 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_Cancel+\n"));
5961
5962 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5963 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
5964 u8Data&=0xF0;
5965 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5966 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
5967
5968 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E1, 0x00);
5969 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E0, 0x00);
5970 u16Data = 0x0000;
5971 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)u16Data&0x00ff);
5972 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(u16Data>>8)&0x00ff);
5973
5974 _u16TunerCenterFreq=0;
5975 _u16ChannelInfoIndex=0;
5976
5977 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_Cancel-\n"));
5978
5979 return status;
5980 }
5981
INTERN_DVBS_BlindScan_End(void)5982 MS_BOOL INTERN_DVBS_BlindScan_End(void)
5983 {
5984 MS_BOOL status=TRUE;
5985 MS_U8 u8Data=0;
5986 MS_U16 u16Data;
5987
5988 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_End+\n"));
5989
5990 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5991 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
5992 u8Data&=0xF0;
5993 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5994 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
5995
5996 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E1, 0x00);
5997 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E0, 0x00);
5998 u16Data = 0x0000;
5999 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)u16Data&0x00ff);
6000 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(u16Data>>8)&0x00ff);
6001
6002 _u16TunerCenterFreq=0;
6003 _u16ChannelInfoIndex=0;
6004
6005 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_End-\n"));
6006
6007 return status;
6008 }
6009
INTERN_DVBS_BlindScan_GetChannel(MS_U16 u16ReadStart,MS_U16 * u16TPNum,HAL_DEMOD_MS_FE_CARRIER_PARAM * pTable)6010 MS_BOOL INTERN_DVBS_BlindScan_GetChannel(MS_U16 u16ReadStart,MS_U16* u16TPNum,HAL_DEMOD_MS_FE_CARRIER_PARAM *pTable)
6011 {
6012 MS_BOOL status=TRUE;
6013 MS_U16 u16TableIndex;
6014
6015 *u16TPNum=_u16ChannelInfoIndex-u16ReadStart;
6016 for(u16TableIndex = 0; u16TableIndex < (*u16TPNum); u16TableIndex++)
6017 {
6018 pTable[u16TableIndex].u32Frequency = _u16ChannelInfoArray[0][_u16ChannelInfoIndex-1];
6019 pTable[u16TableIndex].SatParam.u32SymbolRate = _u16ChannelInfoArray[1][_u16ChannelInfoIndex-1];
6020 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_GetChannel Freq: %d SymbolRate: %d\n", pTable[u16TableIndex].u32Frequency, pTable[u16TableIndex].SatParam.u32SymbolRate));
6021 }
6022 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_u16TPNum:%d\n", *u16TPNum));
6023
6024 return status;
6025 }
6026
INTERN_DVBS_BlindScan_GetCurrentFreq(MS_U32 * u32CurrentFeq)6027 MS_BOOL INTERN_DVBS_BlindScan_GetCurrentFreq(MS_U32 *u32CurrentFeq)
6028 {
6029 MS_BOOL status=TRUE;
6030 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_BlindScan_GetCurrentFreq+\n"));
6031
6032 *u32CurrentFeq=_u16TunerCenterFreq;
6033 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_BlindScan_GetCurrentFreq-: %d\n", _u16TunerCenterFreq));
6034 return status;
6035 }
6036
6037 //------------------------------------------------------------------
6038 // END BlindScan Function
6039 //------------------------------------------------------------------
6040
6041 //------------------------------------------------------------------
6042 // DiSEqc Function
6043 //------------------------------------------------------------------
INTERN_DVBS_DiSEqC_Init(void)6044 MS_BOOL INTERN_DVBS_DiSEqC_Init(void)
6045 {
6046 MS_BOOL status = true;
6047 MS_U8 u8Data = 0;
6048
6049 //Clear status
6050 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6051 u8Data=(u8Data|0x3E)&(~0x3E);
6052 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6053
6054 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, 0x00);
6055 //Tone En
6056 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC0, &u8Data);
6057 u8Data=(u8Data&(~0x06))|(0x06);
6058 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, u8Data);
6059
6060 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_DiSEqC_Init\n"));
6061
6062 return status;
6063 }
6064
INTERN_DVBS_DiSEqC_SetTone(MS_BOOL bTone1)6065 MS_BOOL INTERN_DVBS_DiSEqC_SetTone(MS_BOOL bTone1)
6066 {
6067 MS_BOOL status=TRUE;
6068 MS_U8 u8Data=0;
6069 MS_U8 u8ReSet22k=0;
6070
6071 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC4, 0x01);//0x62;DVBS2_DISEQC_TX1
6072 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, 0x4E);//0x60
6073 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCC, 0x88);//0x66
6074
6075 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);//0x61
6076 u8ReSet22k=u8Data;
6077
6078 if (bTone1==TRUE)
6079 {
6080 //Tone burst 1
6081 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, 0x19);
6082 _u8ToneBurstFlag=1;
6083 }
6084 else
6085 {
6086 //Tone burst 0
6087 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, 0x11);
6088 _u8ToneBurstFlag=2;
6089 }
6090 //DIG_DISEQC_TX_EN
6091 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6092 //u8Data=u8Data&~(0x01);//Tx Disable
6093 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6094
6095 MsOS_DelayTask(1);
6096 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);//0x66 high byte DVBS2_DISEQC_TX_EN
6097 u8Data=u8Data|0x3E; //Status clear
6098 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6099 MsOS_DelayTask(10);
6100 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6101 u8Data=u8Data&~(0x3E);
6102 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6103 MsOS_DelayTask(1);
6104
6105 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6106 u8Data=u8Data|0x01; //Tx Enable
6107 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6108
6109 MsOS_DelayTask(30);//(100)
6110 //For ToneBurst 22k issue.
6111 u8Data=u8ReSet22k;
6112 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);//0x61
6113
6114 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_DiSEqC_SetTone:%d\n", bTone1));
6115 //MsOS_DelayTask(100);
6116 return status;
6117 }
6118
INTERN_DVBS_DiSEqC_SetLNBOut(MS_BOOL bLow)6119 MS_BOOL INTERN_DVBS_DiSEqC_SetLNBOut(MS_BOOL bLow)
6120 {
6121 MS_BOOL status=TRUE;
6122 MS_U8 u8Data=0;
6123
6124 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6125 if (bLow==TRUE)
6126 {
6127 u8Data=(u8Data|0x40); //13V
6128 }
6129 else
6130 {
6131 u8Data=(u8Data&(~0x40));//18V
6132 }
6133 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);
6134
6135 return status;
6136 }
6137
INTERN_DVBS_DiSEqC_GetLNBOut(MS_BOOL * bLNBOutLow)6138 MS_BOOL INTERN_DVBS_DiSEqC_GetLNBOut(MS_BOOL* bLNBOutLow)
6139 {
6140 MS_BOOL status=TRUE;
6141 MS_U8 u8Data=0;
6142
6143 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6144 if( (u8Data&0x40)==0x40)
6145 {
6146 * bLNBOutLow=TRUE;
6147 }
6148 else
6149 {
6150 * bLNBOutLow=FALSE;
6151 }
6152
6153 return status;
6154 }
6155
INTERN_DVBS_DiSEqC_Set22kOnOff(MS_BOOL b22kOn)6156 MS_BOOL INTERN_DVBS_DiSEqC_Set22kOnOff(MS_BOOL b22kOn)
6157 {
6158 MS_BOOL status=TRUE;
6159 MS_U8 u8Data=0;
6160
6161 //Set DiSeqC 22K
6162 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCC, 0x44); //Set 11K-->22K
6163
6164 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6165
6166 if (b22kOn==TRUE)
6167 {
6168 u8Data=(u8Data&0xc7);
6169 u8Data=(u8Data|0x08);
6170 }
6171 else
6172 {
6173 u8Data=(u8Data&0xc7);
6174 }
6175 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);
6176
6177 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_DiSEqC_Set22kOnOff:%d\n", b22kOn));
6178 return status;
6179 }
6180
INTERN_DVBS_DiSEqC_Get22kOnOff(MS_BOOL * b22kOn)6181 MS_BOOL INTERN_DVBS_DiSEqC_Get22kOnOff(MS_BOOL* b22kOn)
6182 {
6183 MS_BOOL status=TRUE;
6184 MS_U8 u8Data=0;
6185
6186 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6187 if ((u8Data&0x38)==0x08)
6188 {
6189 *b22kOn=TRUE;
6190 }
6191 else
6192 {
6193 *b22kOn=FALSE;
6194 }
6195
6196 return status;
6197 }
6198
INTERN_DVBS_DiSEqC_SendCmd(MS_U8 * pCmd,MS_U8 u8CmdSize)6199 MS_BOOL INTERN_DVBS_DiSEqC_SendCmd(MS_U8* pCmd,MS_U8 u8CmdSize)
6200 {
6201 MS_BOOL status=TRUE;
6202 MS_U8 u8Data;
6203 MS_U8 u8Index;
6204 MS_U16 u16WaitCount;
6205 /*
6206 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6207 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6208 u8Data=(u8Data&~(0x10));
6209 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6210 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6211 */
6212 #if 0 //For Unicable command timing
6213 u16WaitCount=0;
6214 do
6215 {
6216 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data);
6217 //printf(">>> INTERN_DVBS_DiSEqC_SendCmd DiSEqC Status = 0x%x <<<\n", u8Data);
6218 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6219 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6220 MsOS_DelayTask(1);
6221 u16WaitCount++;
6222 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
6223
6224 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
6225 {
6226 DBG_INTERN_DVBS(printf("INTERN_DVBS DiSEqC Send Command Busy!!!\n"));
6227 return FALSE;
6228 }
6229 #endif
6230
6231 //u16Address=0x0BC4;
6232 for (u8Index=0; u8Index < u8CmdSize; u8Index++)
6233 {
6234 u8Data=*(pCmd+u8Index);
6235 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC4 + u8Index, u8Data);//#define DVBS2_DISEQC_TX1 (_REG_DVBS2(0x62)+0)//[7:0]
6236 DBG_INTERN_DVBS(ULOGD("DEMOD","=============INTERN_DVBS_DiSEqC_SendCmd(Demod1) = 0x%X\n",u8Data));
6237 }
6238
6239 //set DiSEqC Tx Length, Odd Enable, Tone Burst Mode
6240 u8Data=((u8CmdSize-1)&0x07)|0x40;
6241 if (_u8ToneBurstFlag==1)
6242 {
6243 u8Data|=0x80;//0x20;
6244 }
6245 else if (_u8ToneBurstFlag==2)
6246 {
6247 u8Data|=0x20;//0x80;
6248 }
6249 _u8ToneBurstFlag=0;
6250 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_8, u8Data);
6251
6252 //add this only for check mailbox R/W
6253 #if 1
6254 DBG_INTERN_DVBS(ULOGD("DEMOD"," Write into E_DMD_S2_MB_DMDTOP_DBG_8 = 0x%X!!!\n",u8Data));
6255 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_8, &u8Data);
6256 DBG_INTERN_DVBS(ULOGD("DEMOD"," Read from E_DMD_S2_MB_DMDTOP_DBG_8 = 0x%X!!!\n",u8Data));
6257 #endif
6258
6259 MsOS_DelayTask(25);//MsOS_DelayTask(10);
6260 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);//#define TOP_WR_DBG_90 (_REG_DMDTOP(0x3A)+0)
6261 //u8Data=u8Data|0x10;
6262 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data|0x10);//enable DiSEqC_Data_Tx
6263 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); DBG_INTERN_DVBS(printf(">>>+++ INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X +++<<<\n",u8Data));
6264 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); DBG_INTERN_DVBS(printf(">>>+++ INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d +++<<<\n",u8Data));
6265
6266 #if 1 //For Unicable command timing???
6267 u16WaitCount=0;
6268 do
6269 {
6270 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); DBG_INTERN_DVBS(printf(">>>*** INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X ***<<<\n",u8Data));
6271 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); DBG_INTERN_DVBS(printf(">>>*** INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d ***<<<\n",u8Data));
6272 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6273 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6274 MsOS_DelayTask(1);
6275 u16WaitCount++;
6276 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)) ;
6277
6278 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
6279 {
6280 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS DiSEqC Send Command Busy!!!\n"));
6281 return FALSE;
6282 }
6283 else
6284 {
6285 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS DiSEqC Send Command Success!!!\n"));
6286 return TRUE;
6287 }
6288
6289
6290 #endif
6291 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); printf(">>>--- INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X ---<<<\n",u8Data);
6292 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); printf(">>>--- INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d ---<<<\n",u8Data+1);
6293
6294 return status;
6295 }
6296
INTERN_DVBS_DiSEqC_SetTxToneMode(MS_BOOL bTxTone22kOff)6297 MS_BOOL INTERN_DVBS_DiSEqC_SetTxToneMode(MS_BOOL bTxTone22kOff)
6298 {
6299 MS_BOOL status=TRUE;
6300 MS_U8 u8Data=0;
6301
6302 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xD7, &u8Data);//h006b h006b 15 15 reg_diseqc_tx_tone_mode
6303 if (bTxTone22kOff==TRUE)
6304 {
6305 u8Data=(u8Data|0x80); //1: without 22K.
6306 }
6307 else
6308 {
6309 u8Data=(u8Data&(~0x80)); //0: with 22K.
6310 }
6311 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xD7, u8Data);
6312
6313 return status;
6314 }
6315
INTERN_DVBS_UnicableAGCCheckPower(MS_BOOL pbAGCCheckPower)6316 MS_BOOL INTERN_DVBS_UnicableAGCCheckPower(MS_BOOL pbAGCCheckPower)
6317 {
6318 //MS_BOOL status = TRUE;
6319 MS_U8 u8Data=0;
6320
6321 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, 0x00);
6322
6323 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6324 u8Data &= 0xFE;//clean bit0
6325 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6326
6327 if (pbAGCCheckPower == FALSE)//0
6328 {
6329 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6330 u8Data &= 0xFE;//clean bit0
6331 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6332 //printf("CMD=MS_FALSE==============================\n");
6333 }
6334 else
6335 {
6336 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6337 u8Data |= 0x01; //bit1=1
6338 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6339 //printf("CMD=MS_TRUE==============================\n");
6340 }
6341
6342 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6343 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6344 u8Data &= 0xF0;
6345 u8Data |= 0x01;
6346 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6347 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6348 MsOS_DelayTask(500);
6349
6350 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6351 u8Data &= 0x80; //Read bit7
6352 if (u8Data == 0x80)
6353 {
6354 u8Data = 0x00;
6355 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6356 u8Data = 0x00;
6357 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6358 return TRUE;
6359 }
6360 else
6361 {
6362 u8Data = 0x00;
6363 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6364 u8Data = 0x00;
6365 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6366 return FALSE;
6367 }
6368 }
6369
6370 //------------------------------------------------------------------
6371 // END DiSEqc Function
6372 //------------------------------------------------------------------
6373 //------------------------------------------------------------------
6374 // R/W Function
6375 //------------------------------------------------------------------
INTERN_DVBS_WriteReg2bytes(MS_U16 u16Addr,MS_U16 u16Data)6376 MS_BOOL INTERN_DVBS_WriteReg2bytes(MS_U16 u16Addr, MS_U16 u16Data)
6377 {
6378 MS_BOOL bRet= TRUE;
6379 bRet &= MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr, (MS_U8)u16Data&0x00ff);
6380 bRet &= MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr + 0x0001, (MS_U8)(u16Data>>8)&0x00ff);
6381 return bRet;
6382 }
6383
INTERN_DVBS_ReadReg2bytes(MS_U16 u16Addr,MS_U16 * pu16Data)6384 MS_BOOL INTERN_DVBS_ReadReg2bytes(MS_U16 u16Addr, MS_U16 *pu16Data)
6385 {
6386 MS_BOOL bRet= TRUE;
6387 MS_U8 u8Data =0;
6388 MS_U16 u16Data =0;
6389
6390 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr + 0x0001, &u8Data);
6391 u16Data = u8Data;
6392 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr, &u8Data);
6393 *pu16Data = (u16Data<<8)|u8Data;
6394
6395 return bRet;
6396 }
6397
6398 //Frontend Freeze
INTERN_DVBS_DTV_FrontendSetFreeze(void)6399 MS_BOOL INTERN_DVBS_DTV_FrontendSetFreeze(void)
6400 {
6401 MS_BOOL bRet= TRUE;
6402 MS_U16 u16Address;
6403 MS_U16 u16Data=0;
6404
6405 u16Address = (FRONTEND_FREEZE_DUMP>>16)&0xffff;
6406 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6407 u16Data|=(FRONTEND_FREEZE_DUMP&0xffff);
6408 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6409
6410 return bRet;
6411 }
6412
INTERN_DVBS_DTV_FrontendUnFreeze(void)6413 MS_BOOL INTERN_DVBS_DTV_FrontendUnFreeze(void)
6414 {
6415 MS_BOOL bRet= TRUE;
6416 MS_U16 u16Address;
6417 MS_U16 u16Data=0;
6418
6419 u16Address = (FRONTEND_FREEZE_DUMP>>16)&0xffff;
6420 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6421 u16Data&=~(FRONTEND_FREEZE_DUMP&0xffff);
6422 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6423
6424 return bRet;
6425 }
6426
6427 //Inner Freeze
INTERN_DVBS_DTV_InnerSetFreeze(void)6428 MS_BOOL INTERN_DVBS_DTV_InnerSetFreeze(void)
6429 {
6430 MS_BOOL bRet= TRUE;
6431 MS_U16 u16Address;
6432 MS_U16 u16Data=0;
6433
6434 u16Address = (INNER_FREEZE_DUMP>>16)&0xffff;
6435 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6436 u16Data|=(INNER_FREEZE_DUMP&0xffff);
6437 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6438
6439 return bRet;
6440 }
6441
INTERN_DVBS_DTV_InnerUnFreeze(void)6442 MS_BOOL INTERN_DVBS_DTV_InnerUnFreeze(void)
6443 {
6444 MS_BOOL bRet= TRUE;
6445 MS_U16 u16Address;
6446 MS_U16 u16Data=0;
6447
6448 u16Address = (INNER_FREEZE_DUMP>>16)&0xffff;
6449 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6450 u16Data&=~(INNER_FREEZE_DUMP&0xffff);
6451 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6452
6453 return bRet;
6454 }
6455 //------------------------------------------------------------------
6456 // END R/W Function
6457 //------------------------------------------------------------------
6458
6459
6460 /***********************************************************************************
6461 Subject: read register
6462 Function: MDrv_1210_IIC_Bypass_Mode
6463 Parmeter:
6464 Return:
6465 Remark:
6466 ************************************************************************************/
6467 //void MDrv_1210_IIC_Bypass_Mode(MS_BOOL enable)
6468 //{
6469 // UNUSED(enable);
6470 // if (enable)
6471 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x10); // IIC by-pass mode on
6472 // else
6473 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x00); // IIC by-pass mode off
6474 //}
6475
6476