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93 ////////////////////////////////////////////////////////////////////////////////
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95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102 //0312
103
104 #define _INTERN_DVBS_C_
105 #ifdef MSOS_TYPE_LINUX
106 #include <math.h>
107 #endif
108 #include "ULog.h"
109 #include "MsCommon.h"
110 #include "MsIRQ.h"
111 #include "MsOS.h"
112 //#include "apiPWS.h"
113
114 #include "MsTypes.h"
115 #include "drvBDMA.h"
116 //#include "drvIIC.h"
117 //#include "msAPI_Tuner.h"
118 //#include "msAPI_MIU.h"
119 //#include "BinInfo.h"
120 //#include "halVif.h"
121 #include "drvDMD_INTERN_DVBS.h"
122 #include "halDMD_INTERN_DVBS.h"
123 #include "halDMD_INTERN_common.h"
124
125 #include "drvMMIO.h"
126 //#include "TDAG4D01A_SSI_DVBT.c"
127 #include "drvDMD_VD_MBX.h"
128 //-----------------------------------------------------------------------
129 #define BIN_ID_INTERN_DVBS_DEMOD BIN_ID_INTERN_DVBS
130
131 //For DVBS
132 //#define DVBT2FEC_REG_BASE 0x3300
133 #define DVBS2OPPRO_REG_BASE 0x3E00
134 #define TOP_REG_BASE 0x2000 //DMDTOP
135 //#define REG_BACKEND 0x1F00//_REG_BACKEND
136 #define DVBS2FEC_REG_BASE 0x3D00
137 #define DVBS2_REG_BASE 0x1500
138 #define DVBS2_INNER_REG_BASE 0x1600
139 #define DVBS2_INNER_EXT_REG_BASE 0x1700
140 #define DVBS2_INNER_EXT2_REG_BASE 0x1800
141 //#define DVBSTFEC_REG_BASE 0x2300 //DVBTFEC
142 #define FRONTENDEXT_REG_BASE 0x2200
143 #define FRONTENDEXT2_REG_BASE 0x2300
144 #define DMDANA_REG_BASE 0x2E00 //DMDDTOP//reg_dmdana.xls
145 #define DVBTM_REG_BASE 0x1E00
146
147 #define SAMPLING_RATE_FS (144000)//(108000)//(96000)
148 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000)
149 #define INTERN_DVBS_TUNER_WAIT_TIMEOUT (50)
150
151 //#define DVBS2_Function (1)
152 //#define MSB131X_ADCPLL_IQ_SWAP 0
153 //#define INTERN_DVBS_TS_DATA_SWAP 0
154
155 //#define MS_DEBUG //enable debug dump
156
157 #ifdef MS_DEBUG
158 #define DBG_INTERN_DVBS(x) x
159 #define DBG_GET_SIGNAL_DVBS(x) x
160 #define DBG_INTERN_DVBS_TIME(x) x
161 #define DBG_INTERN_DVBS_LOCK(x) x
162 #define INTERN_DVBS_INTERNAL_DEBUG 1
163 #else
164 #define DBG_INTERN_DVBS(x) //x
165 #define DBG_GET_SIGNAL_DVBS(x) //x
166 #define DBG_INTERN_DVBS_TIME(x) //x
167 #define DBG_INTERN_DVBS_LOCK(x) //x
168 #define INTERN_DVBS_INTERNAL_DEBUG 0
169 #endif
170 //----------------------------------------------------------
171 #define DBG_DUMP_LOAD_DSP_TIME 0
172
173
174 #define SIGNAL_LEVEL_OFFSET 0.00f
175 #define TAKEOVERPOINT -60.0f
176 #define TAKEOVERRANGE 0.5f
177 #define LOG10_OFFSET -0.21f
178 #define INTERN_DVBS_USE_SAR_3_ENABLE 0
179 //extern MS_U32 msAPI_Timer_GetTime0(void);
180 //#define INTERN_DVBS_GET_TIME msAPI_Timer_GetTime0()
181
182
183 //Debug Info
184 //Lock/Done Flag
185 #define AGC_LOCK 0x28170100
186 #define DAGC0_LOCK 0x283B0001
187 #define DAGC1_LOCK 0x285B0001
188 #define DAGC2_LOCK 0x28620001 //ACIDAGC 1 2
189 #define DAGC3_LOCK 0x286E0001
190 #define DCR_LOCK 0x28220100
191 #define COARSE_SYMBOL_RATE_DONE 0x2A200001 //CSRD 1 2
192 #define FINE_SYMBOL_RATE_DONE 0x2A200008 //FSRD 1 2
193 #define POWER4CFO_DONE 0x29280100 //POWER4CFO 1 2
194 //#define CLOSE_COARSE_CFO_LOCK 0x244E0001
195 #define TR_LOCK 0x3B0E0100 //TR 1 2
196 #define PR_LOCK 0x3B401000
197 #define FRAME_SYNC_ACQUIRE 0x3B300001
198 #define EQ_LOCK 0x3B5A1000
199 #define P_SYNC_LOCK 0x22160002
200 #define IN_SYNC_LOCK 0x3F0D8000
201
202 //AGC / DAGC
203 #define DEBUG_SEL_IF_AGC_GAIN 0x28260003
204 #define DEBUG_SEL_AGC_ERR 0x28260004
205 #define DEBUG_OUT_AGC 0x2828
206
207 #define DEBUG_SEL_DAGC0_GAIN 0x28E80003
208 #define DEBUG_SEL_DAGC0_ERR 0x28E80001
209 #define DEBUG_SEL_DAGC0_PEAK_MEAN 0x28E80005
210 #define DEBUG_OUT_DAGC0 0x2878
211
212 #define DEBUG_SEL_DAGC1_GAIN 0x28E80003//???
213 #define DEBUG_SEL_DAGC1_ERR 0x28E80001
214 #define DEBUG_SEL_DAGC1_PEAK_MEAN 0x28E80005
215 #define DEBUG_OUT_DAGC1 0x28B8
216
217 #define DEBUG_SEL_DAGC2_GAIN 0x28E80003
218 #define DEBUG_SEL_DAGC2_ERR 0x28E80001
219 #define DEBUG_SEL_DAGC2_PEAK_MEAN 0x28E80005
220 #define DEBUG_OUT_DAGC2 0x28C4
221
222 #define DEBUG_SEL_DAGC3_GAIN 0x29DA0003
223 #define DEBUG_SEL_DAGC3_ERR 0x29DA0001
224 #define DEBUG_SEL_DAGC3_PEAK_MEAN 0x29DA0005
225 #define DEBUG_OUT_DAGC3 0x29DC
226
227 #define INNER_DEBUG_SEL_TR 0x24080D00 //TR
228 #define DEBUG_SEL_TR_SFO_CONVERGE 0x24080B00
229 #define DEBUG_SEL_TR_INPUT 0x24080F00
230
231 #define FRONTEND_FREEZE_DUMP 0x21028000
232 #define INNER_FREEZE_DUMP 0x16080010
233
234 #define DCR_OFFSET 0x2740
235
236 #define DMDTOP_REG_BASE 0x2000
237 #define _REG_DMDTOP(idx) (DMDTOP_REG_BASE + (idx)*2)
238 #define TOP_WR_DBG_90 (_REG_DMDTOP(0x60)+0)
239
240 #define FRONTEND_REG_BASE 0x2100
241 #define _REG_FRONTEND(idx) (FRONTEND_REG_BASE + (idx)*2)
242 #define FRONTEND_LATCH (_REG_FRONTEND(0x02)+1)//[15]
243
244 #define FRONTEND_AGC_DEBUG_SEL (_REG_FRONTEND(0x11)+0)//[3:0]
245
246 #define FRONTEND_AGC_DEBUG_OUT_R0 (_REG_FRONTEND(0x12)+0)
247 #define FRONTEND_AGC_DEBUG_OUT_R1 (_REG_FRONTEND(0x12)+1)
248 #define FRONTEND_AGC_DEBUG_OUT_R2 (_REG_FRONTEND(0x13)+0)
249
250 #define FRONTEND_IF_MUX (_REG_FRONTEND(0x15)+0)//[1]
251
252 #define FRONTEND_IF_AGC_MANUAL0 (_REG_FRONTEND(0x19)+0)
253 #define FRONTEND_IF_AGC_MANUAL1 (_REG_FRONTEND(0x19)+1)
254
255 #define FRONTEND_MIXER_IQ_SWAP_OUT (_REG_FRONTEND(0x2F)+0)//[1]
256 #define FRONTEND_INFO_07 (_REG_FRONTEND(0x7F)+0)
257
258
259 #define INNER_REG_BASE 0x1600
260 #define _REG_INNER(idx) (INNER_REG_BASE + (idx)*2)
261 #define INNER_LATCH (_REG_INNER(0x04)+0)//[4]
262 #define INNER_DEBUG_SEL (_REG_INNER(0x04)+1)
263 #define INNER_PLSCDEC_DEBUG_OUT0 (_REG_INNER(0x6B)+0)
264 #define INNER_PLSCDEC_DEBUG_OUT1 (_REG_INNER(0x6B)+1)
265 #define INNER_TR_ROLLOFF (_REG_INNER(0x0F)+0)//[1:0]
266
267 #define INNEREXT_FINEFE_DBG_OUT0 0x2550
268 #define INNEREXT_FINEFE_DBG_OUT2 0x2552
269 #define INNEREXT_FINEFE_KI_FF0 0x2556
270 #define INNEREXT_FINEFE_KI_FF2 0x2558
271 #define INNEREXT_FINEFE_KI_FF4 0x255A
272 #define INNER_PR_DEBUG_OUT0 0x2486
273 #define INNER_PR_DEBUG_OUT2 0x2488
274
275 // ********** DVBSFEC.XLS ********** //
276 #define DVBSFEC_REG_BASE 0x2800
277 #define _REG_DVBSFEC(idx) (DVBSFEC_REG_BASE + (idx)*2)
278 #define DVBSFEC_VITERBI_IQ_SWAP (_REG_DVBSFEC(0x41)+0) //[2]
279
280
281 // ********** DVBS2FEC.XLS ********** //
282 #define DVBS2FEC_REG_BASE 0x3D00//0x2600
283 #define _REG_DVBS2FEC(idx) (DVBS2FEC_REG_BASE + (idx)*2)
284 #define DVBS2FEC_OUTER_FREEZE (_REG_DVBS2FEC(0x02)+0) //[0]
285 #define DVBS2FEC_LDPC_ERROR_WINDOW0 (_REG_DVBS2FEC(0x12)+0)
286 #define DVBS2FEC_LDPC_ERROR_WINDOW1 (_REG_DVBS2FEC(0x12)+1)
287 #define DVBS2FEC_LDPC_BER_COUNT0 (_REG_DVBS2FEC(0x2C)+0)//(_REG_DVBS2FEC(0x32)+0)
288 #define DVBS2FEC_LDPC_BER_COUNT1 (_REG_DVBS2FEC(0x2C)+1)//(_REG_DVBS2FEC(0x32)+1)
289 #define DVBS2FEC_LDPC_BER_COUNT2 (_REG_DVBS2FEC(0x2D)+0)//(_REG_DVBS2FEC(0x33)+0)
290 #define DVBS2FEC_LDPC_BER_COUNT3 (_REG_DVBS2FEC(0x2D)+1)//(_REG_DVBS2FEC(0x33)+1)
291
292
293 // ********** DVBS2OPPRO.XLS ********** //
294 #define DVBS2OPPRO_REG_BASE 0x3E00
295 #define _REG_DVBS2OPPRO(idx) (DVBS2OPPRO_REG_BASE + (idx)*2)
296
297 #define DVBS2OPPRO_SIS_EN (_REG_DVBS2OPPRO(0x43)+0) //[2]
298 #define DVBS2OPPRO_OPPRO_ISID (_REG_DVBS2OPPRO(0x43)+1) //[15:8]
299 #define DVBS2OPPRO_OPPRO_ISID_SEL (_REG_DVBS2OPPRO(0x50)+0)
300 #define DVBS2OPPRO_ROLLOFF_DET_DONE (_REG_DVBS2OPPRO(0x74)+0) //[0]
301 #define DVBS2OPPRO_ROLLOFF_DET_VALUE (_REG_DVBS2OPPRO(0x74)+0) //[6:4]
302 #define DVBS2OPPRO_ROLLOFF_DET_ERR (_REG_DVBS2OPPRO(0x74)+1) //[8]
303
304 #define IIS_COUNT0 0x2746
305 #define IIS_COUNT2 0x2748
306 #define IQB_PHASE 0x2766
307 #define IQB_GAIN 0x2768
308 #define TR_INDICATOR_FF0 0x2454
309 #define TR_INDICATOR_FF2 0x2456
310 #define INNER_TR_LOPF_VALUE_DEBUG0 0x2444
311 #define INNER_TR_LOPF_VALUE_DEBUG2 0x2446
312 #define INNER_TR_LOPF_VALUE_DEBUG4 0x2448
313 //------------------------------------------------------------
314 //Init Mailbox parameter.
315 #define INTERN_DVBS_TS_SERIAL_INVERSION 0
316 //For Parameter Init Setting
317 #define A_S2_ZIF_EN 0x01 //[0]
318 #define A_S2_RF_AGC_EN 0x00 //[0]
319 #define A_S2_DCR_EN 0x00 //[0] 0=Auto :1=Force
320 #define A_S2_IQB_EN 0x01 //[2]
321 #define A_S2_IIS_EN 0x00 //[0]
322 #define A_S2_CCI_EN 0x00 //[0] 0:1=Enable
323 #define A_S2_FORCE_ACI_SELECT 0xFF //[3:0] 0xFF=OFF(internal default)
324 #define A_S2_IQ_SWAP 0x01 //[0]
325 #define A_S2_AGC_REF_EXT_0 0x00 //[7:0] //0x00 0x90
326 #define A_S2_AGC_REF_EXT_1 0x02 //[11:8] //0x02 0x07
327 #define A_S2_AGC_K 0x07 //[15:12]
328 #define A_S2_ADCI_GAIN 0x0F //[4:0]
329 #define A_S2_ADCQ_GAIN 0x0F //[12:8]
330 #define A_S2_SRD_SIG_SRCH_RNG 0x6A //[7:0]
331 #define A_S2_SRD_DC_EXC_RNG 0x16 //[7:0]
332 //FRONTENDEXT_SRD_FRC_CFO
333 #define A_S2_FORCE_CFO_0 0x00 //[7:0]
334 #define A_S2_FORCE_CFO_1 0x00 //[11:8]
335 #define A_S2_DECIMATION_NUM 0x00 //[3:0] 00=(Internal Default)
336 #define A_S2_PSD_SMTH_TAP 0x29 //[6:0] Bit7 no define.
337 //CCI Parameter
338 //Set_Tuner_BW=(((U16)REG_BASE[DIG_SWUSE1FH]<<8)|REG_BASE[DIG_SWUSE1FL]);
339 #define A_S2_CCI_FREQN_0_L 0x00 //[7:0]
340 #define A_S2_CCI_FREQN_0_H 0x00 //[11:8]
341 #define A_S2_CCI_FREQN_1_L 0x00 //[7:0]
342 #define A_S2_CCI_FREQN_1_H 0x00 //[11:8]
343 #define A_S2_CCI_FREQN_2_L 0x00 //[7:0]
344 #define A_S2_CCI_FREQN_2_H 0x00 //[11:8]
345 //Inner TR Parameter
346 #define A_S2_TR_LOPF_KP 0x00 //[4:0] 00=(Internal Default)
347 #define A_S2_TR_LOPF_KI 0x00 //[4:0] 00=(Internal Default)
348 //Inner FineFE Parameter
349 #define A_S2_FINEFE_KI_SWITCH_0 0x00 //[15:12] 00=(Internal Default)
350 #define A_S2_FINEFE_KI_SWITCH_1 0x00 //[3:0] 00=(Internal Default)
351 #define A_S2_FINEFE_KI_SWITCH_2 0x00 //[7:4] 00=(Internal Default)
352 #define A_S2_FINEFE_KI_SWITCH_3 0x00 //[11:8] 00=(Internal Default)
353 #define A_S2_FINEFE_KI_SWITCH_4 0x00 //[15:12] 00=(Internal Default)
354 //Inner PR KP Parameter
355 #define A_S2_PR_KP_SWITCH_0 0x00 //[11:8] 00=(Internal Default)
356 #define A_S2_PR_KP_SWITCH_1 0x00 //[15:12] 00=(Internal Default)
357 #define A_S2_PR_KP_SWITCH_2 0x00 //[3:0] 00=(Internal Default)
358 #define A_S2_PR_KP_SWITCH_3 0x00 //[7:4] 00=(Internal Default)
359 #define A_S2_PR_KP_SWITCH_4 0x00 //[11:8] 00=(Internal Default)
360 //Inner FS Parameter
361 #define A_S2_FS_GAMMA 0x10 //[7:0]
362 #define A_S2_FS_ALPHA0 0x10 //[7:0]
363 #define A_S2_FS_ALPHA1 0x10 //[7:0]
364 #define A_S2_FS_ALPHA2 0x10 //[7:0]
365 #define A_S2_FS_ALPHA3 0x10 //[7:0]
366
367 #define A_S2_FS_H_MODE_SEL 0x01 //[0]
368 #define A_S2_FS_OBSWIN 0x08 //[12:8]
369 #define A_S2_FS_PEAK_DET_TH_L 0x00 //[7:0]
370 #define A_S2_FS_PEAK_DET_TH_H 0x01 //[15:8]
371 #define A_S2_FS_CONFIRM_NUM 0x01 //[3:0]
372 //Inner EQ Parameter
373 #define A_S2_EQ_MU_FFE_DA 0x00 //[3:0] 00=(Internal Default)
374 #define A_S2_EQ_MU_FFE_DD 0x00 //[7:4] 00=(Internal Default)
375 #define A_S2_EQ_ALPHA_SNR_DA 0x00 //[7:4] 00=(Internal Default)
376 #define A_S2_EQ_ALPHA_SNR_DD 0x00 //[11:8] 00=(Internal Default)
377 //Outer FEC Parameter
378 #define A_S2_FEC_ALFA 0x00 //[12:8]
379 #define A_S2_FEC_BETA 0x01 //[7:4]
380 #define A_S2_FEC_SCALING_LLR 0x00 //[7:0] 00=(Internal Default)
381 //TS Parameter
382 #if INTERN_DVBS_TS_SERIAL_INVERSION
383 #define A_S2_TS_SERIAL 0x01 //[0]
384 #else
385 #define A_S2_TS_SERIAL 0x00 //[0]
386 #endif
387 #define A_S2_TS_CLK_RATE 0x00
388 #define A_S2_TS_OUT_INV 0x00 //[5]
389 #define A_S2_TS_DATA_SWAP 0x00 //[5]
390 //Rev Parameter
391
392 #define A_S2_FW_VERSION_L 0x00 //From FW
393 #define A_S2_FW_VERSION_H 0x00 //From FW
394 #define A_S2_CHIP_VERSION 0x01
395 #define A_S2_FS_L 0x00
396 #define A_S2_FS_H 0x00
397 #define A_S2_MANUAL_TUNE_SYMBOLRATE_L 0x20
398 #define A_S2_MANUAL_TUNE_SYMBOLRATE_H 0x4E
399
400 MS_U8 INTERN_DVBS_DSPREG[] =
401 {
402 A_S2_ZIF_EN, A_S2_RF_AGC_EN, A_S2_DCR_EN, A_S2_IQB_EN, A_S2_IIS_EN, A_S2_CCI_EN, A_S2_FORCE_ACI_SELECT, A_S2_IQ_SWAP, // 00H ~ 07H
403 A_S2_AGC_REF_EXT_0, A_S2_AGC_REF_EXT_1, A_S2_AGC_K, A_S2_ADCI_GAIN, A_S2_ADCQ_GAIN, A_S2_SRD_SIG_SRCH_RNG, A_S2_SRD_DC_EXC_RNG, A_S2_FORCE_CFO_0, // 08H ~ 0FH
404 A_S2_FORCE_CFO_1, A_S2_DECIMATION_NUM, A_S2_PSD_SMTH_TAP, A_S2_CCI_FREQN_0_L, A_S2_CCI_FREQN_0_H, A_S2_CCI_FREQN_1_L, A_S2_CCI_FREQN_1_H, A_S2_CCI_FREQN_2_L, // 10H ~ 17H
405 A_S2_CCI_FREQN_2_H, A_S2_TR_LOPF_KP, A_S2_TR_LOPF_KI, A_S2_FINEFE_KI_SWITCH_0, A_S2_FINEFE_KI_SWITCH_1, A_S2_FINEFE_KI_SWITCH_2, A_S2_FINEFE_KI_SWITCH_3, A_S2_FINEFE_KI_SWITCH_4, // 18H ~ 1FH
406 A_S2_PR_KP_SWITCH_0, A_S2_PR_KP_SWITCH_1, A_S2_PR_KP_SWITCH_2, A_S2_PR_KP_SWITCH_3, A_S2_PR_KP_SWITCH_4, A_S2_FS_GAMMA, A_S2_FS_ALPHA0, A_S2_FS_ALPHA1, // 20H ~ 27H
407 A_S2_FS_ALPHA2, A_S2_FS_ALPHA3, A_S2_FS_H_MODE_SEL, A_S2_FS_OBSWIN, A_S2_FS_PEAK_DET_TH_L, A_S2_FS_PEAK_DET_TH_H, A_S2_FS_CONFIRM_NUM, A_S2_EQ_MU_FFE_DA, // 28h ~ 2FH
408 A_S2_EQ_MU_FFE_DD, A_S2_EQ_ALPHA_SNR_DA, A_S2_EQ_ALPHA_SNR_DD, A_S2_FEC_ALFA, A_S2_FEC_BETA, A_S2_FEC_SCALING_LLR, A_S2_TS_SERIAL, A_S2_TS_CLK_RATE, // 30H ~ 37H
409 A_S2_TS_OUT_INV, A_S2_TS_DATA_SWAP, A_S2_FW_VERSION_L, A_S2_FW_VERSION_H, A_S2_CHIP_VERSION, A_S2_FS_L, A_S2_FS_H, A_S2_MANUAL_TUNE_SYMBOLRATE_L, // 38H ~ 3CH
410 A_S2_MANUAL_TUNE_SYMBOLRATE_H,
411 };
412
413 /****************************************************************
414 *Local Variables *
415 ****************************************************************/
416
417 /*
418 static MS_U16 _u16SignalLevel[185][2]=
419 {//AV2028 SR=22M, 2/3 CN=5.9
420 {32100, 920},{32200, 915},{32350, 910},{32390, 905},{32480, 900},{32550, 895},{32620, 890},{32680, 885},{32750, 880},{32830, 875},
421 {32930, 870},{33010, 865},{33100, 860},{33200, 855},{33310, 850},{33410, 845},{33520, 840},{33640, 835},{33770, 830},{33900, 825},
422 {34030, 820},{34150, 815},{34290, 810},{34390, 805},{34490, 800},{34580, 795},{34700, 790},{34800, 785},{34880, 780},{34940, 775},
423 {35030, 770},{35130, 765},{35180, 760},{35260, 755},{35310, 750},{35340, 745},{35380, 740},{35400, 735},{35450, 730},{35550, 725},
424 {35620, 720},{35700, 715},{35800, 710},{35890, 705},{36000, 700},{36120, 695},{36180, 690},{36280, 685},{36400, 680},{36570, 675},
425 {36730, 670},{36910, 665},{37060, 660},{37100, 655},{37260, 650},{37340, 645},{37410, 640},{37580, 635},{37670, 630},{37700, 625},
426 {37750, 620},{37800, 615},{37860, 610},{37980, 605},{38050, 600},{38170, 595},{38370, 590},{38540, 585},{38710, 580},{38870, 575},
427 {39020, 570},{39070, 565},{39100, 560},{39180, 555},{39280, 550},{39460, 545},{39510, 540},{39600, 535},{39620, 530},{39680, 525},
428 {39720, 520},{39830, 515},{39880, 510},{39930, 505},{39960, 500},{40000, 495},{40200, 490},{40360, 485},{40540, 480},{40730, 475},
429 {40880, 470},{41020, 465},{41150, 460},{41280, 455},{41410, 450},{41520, 445},{41620, 440},{41730, 435},{41840, 430},{41930, 425},
430 {42010, 420},{42100, 415},{42180, 410},{42260, 405},{42350, 400},{42440, 395},{42520, 390},{42580, 385},{42660, 380},{42730, 375},
431 {42800, 370},{42870, 365},{42940, 360},{43000, 355},{43060, 350},{43130, 345},{43180, 340},{43250, 335},{43310, 330},{43370, 325},
432 {43420, 320},{43460, 315},{43520, 310},{43570, 305},{43620, 300},{43660, 295},{43710, 290},{43750, 285},{43810, 280},{43860, 275},
433 {43910, 270},{43940, 265},{43990, 260},{44020, 255},{44060, 250},{44110, 245},{44140, 240},{44190, 235},{44230, 230},{44270, 225},
434 {44320, 220},{44370, 215},{44400, 210},{44450, 205},{44490, 200},{44530, 195},{44590, 190},{44630, 185},{44660, 180},{44720, 175},
435 {44750, 170},{44790, 165},{44830, 160},{44880, 155},{44910, 150},{44960, 145},{45000, 140},{45030, 135},{45070, 130},{45100, 125},
436 {45130, 120},{45160, 115},{45200, 110},{45240, 105},{45270, 100},{45300, 95},{45330, 90},{45360, 85},{45400, 80},{45430, 75},
437 {45460, 70},{45490, 65},{45530, 60},{45560, 55},{45590, 50},{45630, 45},{45670, 40},{45690, 35},{45740, 30},{45760, 25},
438 {45800, 20},{45830, 15},{45860, 10},{45880, 5},{45920, 0}
439 };
440 */
441 MS_U8 u8DemodLockFlag;
442 MS_U8 modulation_order;
443 MS_BOOL _bDemodType = FALSE;//DVBS:FALSE ; S2:TRUE
444 //static MS_BOOL TPSLock = 0;
445 static MS_U32 u32ChkScanTimeStartDVBS = 0;
446 MS_U8 g_dvbs_lock = 0;
447 //static float intern_dvb_s_qam_ref[] = {3.0, 0.0, 0.0, 0.0, 0.0, 80.0}; //16q,32q,64q,128q,256q, and others
448 //static MS_U8 _u8_DVBS2_CurrentCodeRate;
449 static MS_U8 _u8ToneBurstFlag=0;
450
451 //static float _fPostBer=0;
452 //static float _f_DVBS_CurrentSNR=0;
453 static MS_U16 _u16BlindScanStartFreq=0;
454 static MS_U16 _u16BlindScanEndFreq=0;
455 static MS_U16 _u16TunerCenterFreq=0;
456 MS_U16 _u16ChannelInfoIndex=0;
457 //Debug Only+
458 static MS_U16 _u16NextCenterFreq=0;
459 MS_U16 _u16LockedSymbolRate=0;
460 MS_U16 _u16LockedCenterFreq=0;
461 static MS_U16 _u16PreLockedHB=0;
462 static MS_U16 _u16PreLockedLB=0;
463 static MS_U16 _u16CurrentSymbolRate=0;
464 MS_S16 _s16CurrentCFO=0;
465 static MS_U16 _u16CurrentStepSize=0;
466 //Debug Only-
467 MS_U16 _u16ChannelInfoArray[2][1000];
468
469 //static MS_U32 _u32CurrentSR=0;
470 static MS_BOOL _bSerialTS=FALSE;
471 static MS_BOOL _bTSDataSwap=FALSE;
472
473 //Global Variables
474 S_CMDPKTREG gsCmdPacketDVBS;
475 //MS_U8 gCalIdacCh0, gCalIdacCh1;
476 static MS_BOOL bDMD_DVBS_NoChannelDetectedWithRFPower = FALSE;
477 static MS_U32 u32DMD_DVBS_NoChannelTimeAccWithRFPower = 0;
478
479 // For VCM
480 static MS_U32 u32DVBS2_DJB_START_ADDR = 0;
481 static DMD_DVBS_VCM_OPT u8VCM_Enabled_Opt = VCM_Disabled;
482 static MS_U8 u8Default_VCM_IS_ID = 0;
483
484 const MS_U8 modulation_order_array[12] = {2, 3, 4, 5, 3, 4, 5, 6, 6, 6, 7, 8};
485
486 #ifdef INTERN_DVBS_LOAD_FW_FROM_CODE_MEMORY
487 MS_U8 INTERN_DVBS_table[] =
488 {
489 #include "fwDMD_INTERN_DVBS.dat"
490 };
491
492 #endif
493
494 MS_BOOL INTERN_DVBS_Show_Demod_Version(void);
495 //MS_BOOL INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE *pQAMMode);
496 //MS_BOOL INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE *pDemodType);
497 //MS_BOOL INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE *pCodeRate);
498 //MS_BOOL INTERN_DVBS_GetCurrentSymbolRate(MS_U32 *u32SymbolRate);
499 //MS_BOOL INTERN_DVBS_GetCurrentSymbolRateOffset(MS_U16 *pData);
500
501 #if (INTERN_DVBS_INTERNAL_DEBUG)
502 void INTERN_DVBS_info(void);
503 MS_BOOL INTERN_DVBS_Show_AGC_Info(void);
504 #endif
505
506 //------------------------------------------------------------------
507 // System Info Function
508 //------------------------------------------------------------------
509 //=====================================================================================
INTERN_DVBS_DSPReg_Init(const MS_U8 * u8DVBS_DSPReg,MS_U8 u8Size)510 MS_U16 INTERN_DVBS_DSPReg_Init(const MS_U8 *u8DVBS_DSPReg, MS_U8 u8Size)
511 {
512 #if 0
513 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
514 #endif
515 MS_U8 status = true;
516 #if 0
517 MS_U16 u16DspAddr = 0;
518 #endif
519 DBG_INTERN_DVBS(printf("INTERN_DVBS_DSPReg_Init\n"));
520
521 #if 0//def MS_DEBUG
522 {
523 MS_U8 u8buffer[256];
524 printf("INTERN_DVBS_DSPReg_Init Reset\n");
525 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
526 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, 0);
527
528 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
529 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
530 printf("INTERN_DVBS_DSPReg_Init ReadBack, should be all 0\n");
531 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
532 printf("%x ", u8buffer[idx]);
533 printf("\n");
534
535 printf("INTERN_DVBS_DSPReg_Init Value\n");
536 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
537 printf("%x ", INTERN_DVBS_DSPREG[idx]);
538 printf("\n");
539 }
540 #endif
541
542 //for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
543 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBS_DSPREG[idx]);
544
545 // readback to confirm.
546 // ~read this to check mailbox initial values
547 #if 0
548 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
549 {
550 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &u8RegRead);
551 if (u8RegRead != INTERN_DVBS_DSPREG[idx])
552 {
553 DBG_INTERN_DVBS(printf("[Error]INTERN_DVBS_DSPReg_Init, idx=%d, drv_val=0x%x, firmware_val=0x%x\n",idx,INTERN_DVBS_DSPREG[idx],u8RegRead));
554 }
555 }
556 #endif
557 #if 0
558 if (u8DVBS_DSPReg != NULL)
559 {
560 if (1 == u8DVBS_DSPReg[0])
561 {
562 u8DVBS_DSPReg+=2;
563 for (idx = 0; idx<u8Size; idx++)
564 {
565 u16DspAddr = *u8DVBS_DSPReg;
566 u8DVBS_DSPReg++;
567 u16DspAddr = (u16DspAddr) + ((*u8DVBS_DSPReg)<<8);
568 u8DVBS_DSPReg++;
569 u8Mask = *u8DVBS_DSPReg;
570 u8DVBS_DSPReg++;
571 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
572 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBS_DSPReg) & (u8Mask));
573 u8DVBS_DSPReg++;
574 DBG_INTERN_DVBS(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
575 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
576 }
577 }
578 else
579 {
580 DBG_INTERN_DVBS(printf("FATAL: parameter version incorrect\n"));
581 }
582 }
583 #endif
584 #if 0//def MS_DEBUG
585 {
586 MS_U8 u8buffer[256];
587 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
588 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
589 printf("INTERN_DVBC_DSPReg_Init ReadBack\n");
590 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
591 printf("%x ", u8buffer[idx]);
592 printf("\n");
593 }
594 #endif
595
596 #if 0//def MS_DEBUG
597 {
598 MS_U8 u8buffer[256];
599 for (idx = 0; idx<128; idx++)
600 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2380+idx, &(u8buffer[idx]));
601 printf("INTERN_DVBS_DSPReg_Init ReadReg 0x2000~0x207F\n");
602 for (idx = 0; idx<128; idx++)
603 {
604 printf("%x ", u8buffer[idx]);
605 if ((idx & 0xF) == 0xF) printf("\n");
606 }
607 printf("\n");
608 }
609 #endif
610 return status;
611 }
612
613 /***********************************************************************************
614 Subject: Command Packet Interface
615 Function: INTERN_DVBS_Cmd_Packet_Send
616 Parmeter:
617 Return: MS_BOOL
618 Remark:
619 ************************************************************************************/
INTERN_DVBS_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)620 MS_BOOL INTERN_DVBS_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
621 {
622 MS_U8 status = true, indx;
623 MS_U8 reg_val, timeout = 0;
624 return true;
625
626 // ==== Command Phase ===================
627 DBG_INTERN_DVBS(ULOGD("DEMOD","--->INTERN_DVBS (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
628 pCmdPacket->param[0],pCmdPacket->param[1],
629 pCmdPacket->param[2],pCmdPacket->param[3],
630 pCmdPacket->param[4],pCmdPacket->param[5] ));
631
632 // wait _BIT_END clear
633 do
634 {
635 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
636 if((reg_val & _BIT_END) != _BIT_END)
637 {
638 break;
639 }
640 MsOS_DelayTask(5);
641 if (timeout > 200)
642 {
643 DBG_INTERN_DVBS(ULOGD("DEMOD","---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n"));
644 return false;
645 }
646 timeout++;
647 } while (1);
648
649 // set cmd_3:0 and _BIT_START
650 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
651 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
652 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
653
654
655 //DBG_INTERN_DVBS(printf("demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
656 // wait _BIT_START clear
657 do
658 {
659 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
660 if((reg_val & _BIT_START) != _BIT_START)
661 {
662 break;
663 }
664 MsOS_DelayTask(10);
665 if (timeout > 200)
666 {
667 DBG_INTERN_DVBS(ULOGD("DEMOD","---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n"));
668 return false;
669 }
670 timeout++;
671 } while (1);
672
673 // ==== Data Phase ======================
674
675 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
676
677 for (indx = 0; indx < param_cnt; indx++)
678 {
679 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
680 //DBG_INTERN_DVBS(printf("demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
681
682 // set param[indx] and _BIT_DRQ
683 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
684 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
685 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
686
687 // wait _BIT_DRQ clear
688 do
689 {
690 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
691 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
692 {
693 break;
694 }
695 MsOS_DelayTask(5);
696 if (timeout > 200)
697 {
698 DBG_INTERN_DVBS(ULOGD("DEMOD","---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n"));
699 return false;
700 }
701 timeout++;
702 } while (1);
703 }
704
705 // ==== End Phase =======================
706
707 // set _BIT_END to finish command
708 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
709 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
710
711 return status;
712 }
713
714 /***********************************************************************************
715 Subject: Command Packet Interface
716 Function: INTERN_DVBS_Cmd_Packet_Exe_Check
717 Parmeter:
718 Return: MS_BOOL
719 Remark:
720 ************************************************************************************/
INTERN_DVBS_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)721 MS_BOOL INTERN_DVBS_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
722 {
723 return TRUE;
724 }
725
726 /***********************************************************************************
727 Subject: SoftStop
728 Function: INTERN_DVBS_SoftStop
729 Parmeter:
730 Return: MS_BOOL
731 Remark:
732 ************************************************************************************/
INTERN_DVBS_SoftStop(void)733 MS_BOOL INTERN_DVBS_SoftStop ( void )
734 {
735 #if 1
736 MS_U16 u16WaitCnt=0;
737
738 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
739 {
740 DBG_INTERN_DVBS(ULOGD("DEMOD",">> MB Busy!\n"));
741 return FALSE;
742 }
743
744 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
745
746 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
747 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
748
749 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
750 {
751 if (u16WaitCnt++ >= 0xFFF)// 0xFF)
752 {
753 DBG_INTERN_DVBS(ULOGD("DEMOD",">> DVBT SoftStop Fail!\n"));
754 return FALSE;
755 }
756 }
757
758 //HAL_DMD_RIU_WriteByte(0x103460, 0x01); // reset VD_MCU
759 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
760 #endif
761 return TRUE;
762 }
763
764 /***********************************************************************************
765 Subject: Reset
766 Function: INTERN_DVBC_Reset
767 Parmeter:
768 Return: MS_BOOL
769 Remark:
770 ************************************************************************************/
771 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
772
INTERN_DVBS_Reset(void)773 MS_BOOL INTERN_DVBS_Reset ( void )// no midify
774 {
775 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_reset\n"));
776
777 DBG_INTERN_DVBS_TIME(ULOGD("DEMOD","INTERN_DVBS_Reset, t = %d\n",MsOS_GetSystemTime()));
778
779 //INTERN_DVBS_SoftStop();
780
781
782 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
783
784 MsOS_DelayTask(1);
785 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
786
787 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
788 MsOS_DelayTask(5);
789
790 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
791 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
792
793 u32ChkScanTimeStartDVBS = MsOS_GetSystemTime();
794 g_dvbs_lock = 0;
795
796 return TRUE;
797 }
798
799 /***********************************************************************************
800 Subject: Exit
801 Function: INTERN_DVBC_Exit
802 Parmeter:
803 Return: MS_BOOL
804 Remark:
805 ************************************************************************************/
INTERN_DVBS_Exit(void)806 MS_BOOL INTERN_DVBS_Exit ( void )
807 {
808
809 MS_BOOL status = TRUE;
810 #if 0
811 MS_U8 u8Data=0;
812 MS_U8 u8Data_temp=0;
813
814 u8Data_temp=HAL_DMD_RIU_ReadByte(0x101E39);
815 HAL_DMD_RIU_WriteByte(0x101E39, 0);
816
817 u8Data=HAL_DMD_RIU_ReadByte(0x1128C0);
818 u8Data&=~(0x02);
819 HAL_DMD_RIU_WriteByte(0x1128C0, u8Data);//revert IQ Swap status
820
821 HAL_DMD_RIU_WriteByte(0x101E39, u8Data_temp);
822 #endif
823
824 // This file is translated by Steven Hung's riu2script.pl
825
826 // ("==============================================================");
827 // ("Start demod top initial setting by HK MCU ......");
828 // ("==============================================================");
829 // [8] : reg_chiptop_dummy_0 (reg_dmdtop_dmd_sel)
830 // 1'b0->reg_DMDTOP control by HK_MCU.
831 // 1'b1->reg_DMDTOP control by DMD_MCU.
832 // [9] : reg_chiptop_dummy_0 (reg_dmd_ana_regsel)
833 // 1'b0->reg_DMDANA control by HK_MCU.
834 // 1'b1->reg_DMDANA control by DMD_MCU.
835 // ("select HK MCU ......");
836 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0000);
837 HAL_DMD_RIU_WriteByte(0x101e39, 0x00);
838
839 // enable DISEQC PAD
840 // [15] reg_allpad_in
841 // `RIU_W((`RIUBASE_CHIP>>1)+7'h50, 2'b10, 16'h0000);
842 // [0] reg_if_agc_en
843 // [1] reg_rf_agc_en
844 // [2] reg_diseq_in_en = 1'b1
845 // [3] reg_diseq_out_en = 1'b1
846 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1d, 2'b01, 16'h000c);
847
848
849 // ("==============================================================");
850 // ("Start TOP CLKGEN initial setting ......");
851 // ("==============================================================");
852 // CLK_DMDMCU clock setting
853 // reg_ckg_dmdmcu@0x0f[4:0]
854 // [0] : disable clock
855 // [1] : invert clock
856 // [4:2]:
857 // 000:170 MHz(MPLL_DIV_BUF)
858 // 001:160MHz
859 // 010:144MHz
860 // 011:123MHz
861 // 100:108MHz (Kriti:DVBT2)
862 // 101:mem_clcok
863 // 110:mem_clock div 2
864 // 111:select XTAL
865 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h0010);
866 HAL_DMD_RIU_WriteByte(0x10331e, 0x11);
867
868
869 // set parallel ts clock
870 // [11] : reg_ckg_demod_test_in_en = 0
871 // 0: select internal ADC CLK
872 // 1: select external test-in clock
873 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
874 // 0: select gated clock
875 // 1: select free-run clock
876 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
877 // 0: normal phase to pad
878 // 1: invert phase to pad
879 // [8] : reg_ckg_atsc_dvb_div_sel = 1
880 // 0: select clk_dmplldiv5
881 // 1: select clk_dmplldiv3
882 // [4:0]: reg_ckg_dvbtm_ts_divnum = 5
883 // Demod TS output clock phase tuning number
884 // If (reg_ckg_tsout_ph_tun_num == reg_ckg_dvbtm_ts_divnum),
885 // Demod TS output clock is equal Demod TS internal working clock.
886 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
887 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0505);
888 // wriu 0x103301 0x05
889 // wriu 0x103300 0x05
890
891
892 // enable DVBTC ts clock
893 // [11:8]: reg_ckg_dvbtc_ts0
894 // [8] : disable clock
895 // [9] : invert clock
896 // [11:10]: Select clock source
897 // 00:clk_atsc_dvb_div
898 // 01:62 MHz
899 // 10:54 MHz
900 // 11:reserved
901 // [15:12]: reg_ckg_dvbtc_ts1
902 // [12] : disable clock
903 // [13] : invert clock
904 // [15:14]: Select clock source
905 // 00:clk_atsc_dvb_div
906 // 01:62 MHz
907 // 10:54 MHz
908 // 11:reserved
909 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
910 HAL_DMD_RIU_WriteByte(0x103309, 0x11);
911
912
913 // enable dvbc adc clock
914 // [3:0]: reg_ckg_dvbtc_adc
915 // [0] : disable clock
916 // [1] : invert clock
917 // [3:2]: Select clock source => for demod clkgen clk_dvbtc_adc
918 // 00: clk_dmdadc
919 // 01: clk_dmdadc_div2
920 // 10: clk_dmdadc_div4
921 // 11: DFT_CLK
922 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
923 HAL_DMD_RIU_WriteByte(0x103314, 0x11);
924
925 // Reset TS divider
926 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h01, 2'b01, 16'h0001);
927 // wriu 0x103302 0x01
928
929 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h01, 2'b01, 16'h0000);
930 // wriu 0x103302 0x00
931
932 // ("==============================================================");
933 // ("Start demod CLKGEN setting ......");
934 // ("==============================================================");
935 // enable atsc_adcd_sync clock
936 // [3:0] : reg_ckg_atsc_adcd_sync
937 // [0] : disable clock
938 // [1] : invert clock
939 // [3:2]: Select clock source
940 // 00: clk_dmdadc_sync
941 // 01: 1'b0
942 // 10: 1'b0
943 // 11: DFT_CLK
944 // [11:8] : reg_ckg_dmd_dma
945 // [8] : disable clock
946 // [9] : invert clock
947 // [11:10]: Select clock source
948 // 00: clk_dmdadc
949 // 01: clk_dmdadc_div2_buf
950 // 10: 1'b0
951 // 11: DFT_CLK
952 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
953 HAL_DMD_RIU_WriteByte(0x10200b, 0x11);
954 HAL_DMD_RIU_WriteByte(0x10200a, 0x11);
955
956
957 // [7:4] : reg_ckg_dvbtm_adc0p5x
958 // [4] : disable clock
959 // [5] : invert clock
960 // [7:6]: Select clock source
961 // 00: adc_clk_div2_buf
962 // 01: mpll_clk9_buf
963 // 10: 1'b0
964 // 11: DFT_CLK
965 // [11:8] reg_ckg_dvbtm_adc1x_eq1x
966 // [8] : disable clock
967 // [9] : invert clock
968 // [11:10]: Select clock source
969 // 00: adc_clk_buf
970 // 01: mpll_clk18_buf
971 // 10: 1'b0
972 // 11: DFT_CLK
973 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
974 HAL_DMD_RIU_WriteByte(0x102021, 0x11);
975 HAL_DMD_RIU_WriteByte(0x102020, 0x11);
976
977
978 // DVBS2
979 // @0x3511
980 // [3:0] : reg_ckg_dvbs2_inner
981 // [0] : disable clock
982 // [1] : invert clock
983 // [3:2]: Select clock source
984 // 00: adc_clk_buf
985 // 01: 1'b0
986 // 10: 1'b0
987 // 11: 1'b0
988 // [7:4] : reg_ckg_dvbs_outer1x
989 // [4] : disable clock
990 // [5] : invert clock
991 // [7:6] : Select clock source
992 // 00: adc_clk_buf
993 // 01: clk_dvbtc_outer2x_c_p
994 // 10: 1'b0
995 // 11: DFT_CLK
996 // [11:8] : reg_ckg_dvbs_outer2x
997 // [8] : disable clock
998 // [9] : invert clock
999 // [11:10] : Select clock source
1000 // 00: adc_clk_buf
1001 // 01: 1'b0
1002 // 10: 1'b0
1003 // 11: DFT_CLK
1004 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0000);
1005 HAL_DMD_RIU_WriteByte(0x102023, 0x11);
1006 HAL_DMD_RIU_WriteByte(0x102022, 0x11);
1007
1008
1009 // @0x3512
1010 // [4:0] : reg_ckg_dvbs_rs
1011 // [0] : disable clock
1012 // [1] : invert clock
1013 // [4:2]: Select clock source
1014 // 000: mpll_clk216_buf
1015 // 001: 1'b0
1016 // 010: 1'b0
1017 // 011: 1'b0
1018 // [12:8] : reg_ckg_dvbs2_outer
1019 // [8] : disable clock
1020 // [9] : invert clock
1021 // [12:10] : Select clock source
1022 // 000: mpll_clk288_buf
1023 // 001: mpll_clk216_buf
1024 // 010: 1'b0
1025 // 011: 1'b0
1026 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b11, 16'h0000);
1027 HAL_DMD_RIU_WriteByte(0x102025, 0x11);
1028 HAL_DMD_RIU_WriteByte(0x102024, 0x11);
1029
1030
1031
1032 // @0x3514
1033 // [3:0] : reg_ckg_dvbs2_ldpc_inner_sram
1034 // [0] : disable clock
1035 // [1] : invert clock
1036 // [3:2]: Select clock source
1037 // 00: clk_dvbs2_outer_mux8
1038 // 01: adc_clk_buf
1039 // 10: mpll_clk18_buf
1040 // 11: clk_dvbtc_outer2x_c_p
1041 // [7:4] : reg_ckg_dvbs_viterbi_sram
1042 // [4] : disable clock
1043 // [5] : invert clock
1044 // [7:6] : Select clock source
1045 // 00: clk_dvbs2_outer_mux8
1046 // 01: adc_clk_buf
1047 // 10: mpll_clk18_buf
1048 // 11: DFT_CLK
1049 // [12:8] : reg_ckg_dvbs_rs_deint_sram
1050 // [8] : disable clock
1051 // [9] : invert clock
1052 // [12:10] : Select clock source
1053 // 000: clk_dvbs2_outer_mux8
1054 // 001: clk_dvbs_outer1x_pre_mux4
1055 // 010: adc_clk_buf
1056 // 011: mpll_clk18_buf
1057 // 100: clk_dvbtc_outer2x_c_p
1058 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b11, 16'h0844);
1059 HAL_DMD_RIU_WriteByte(0x102029, 0x11);
1060 HAL_DMD_RIU_WriteByte(0x102028, 0x11);
1061
1062 // @0x3518
1063 // [4:0]: reg_ckg_dvbs2_outer_rs_adc
1064 // [0] : disable clock
1065 // [1] : invert clock
1066 // [3:2]: Select clock source
1067 // 000: clk_dvbs2_outer_mux8
1068 // 001: clk_dvbs_rs_p
1069 // 010: adc_clk_buf
1070 // 011: mpll_clk18_buf
1071 // 100: clk_dvbtc_outer2x_c_p
1072 // [11:8] : reg_ckg_dvbs2_ldpc_inner_j83b_sram
1073 // [0] : disable clock
1074 // [1] : invert clock
1075 // [3:2]: Select clock source
1076 // 00: clk_dvbs2_outer_mux8
1077 // 01: adc_clk_buf
1078 // 10: mpll_clk18_buf
1079 // 11: clk_dvbtc_outer2x_c_p
1080 // [15:12] : reg_ckg_dvbs_viterbi_j83b_sram
1081 // [12] : disable clock
1082 // [13] : invert clock
1083 // [15:14] : Select clock source
1084 // 00: clk_dvbs2_outer_mux8
1085 // 01: adc_clk_buf
1086 // 10: mpll_clk18_buf
1087 // 11: DFT_CLK
1088 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b11, 16'h4408);
1089 HAL_DMD_RIU_WriteByte(0x102031, 0x11);
1090 HAL_DMD_RIU_WriteByte(0x102030, 0x11);
1091
1092 // @0x3519
1093 // [4:0]: reg_ckg_dvbs2_outer_rs_adc_j83b
1094 // [0] : disable clock
1095 // [1] : invert clock
1096 // [3:2]: Select clock source
1097 // 000: clk_dvbs2_outer_mux8
1098 // 001: clk_dvbs_rs_p
1099 // 010: adc_clk_buf
1100 // 011: mpll_clk18_buf
1101 // 100: clk_dvbtc_outer2x_c_p
1102 // [12:8] : reg_ckg_dvbs2_demap
1103 // DVBS2 demap clock control register;
1104 // [0]=1:gate clock,
1105 // [1]=1:invert clock.
1106 // [4:2]: clock rate sel.
1107 // 0: mpll_clk216_buf
1108 // 1: mpll_clk172p8_buf
1109 // 2: mpll_clk144_buf
1110 // 3: mpll_clk96_buf
1111 // 4: mpll_clk72_buf
1112 // 5: adc_clk_buf
1113 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h19, 2'b11, 16'h0008);
1114 HAL_DMD_RIU_WriteByte(0x102033, 0x11);
1115 HAL_DMD_RIU_WriteByte(0x102032, 0x11);
1116
1117 // [4:0]: reg_ckg_dvbs2_oppro
1118 // DVBS2 OPPRO clock control register;
1119 // [0]=1:gate clock,
1120 // [1]=1:invert clock.
1121 // [4:2]: clock rate sel.
1122 // 0: mpll_clk216_buf
1123 // 1: mpll_clk172p8_buf
1124 // 2: mpll_clk144_buf
1125 // 3: mpll_clk96_buf
1126 // 4: mpll_clk72_buf
1127 // 5: adc_clk_buf
1128 // [12:8]: reg_ckg_dvbtm_ts_in_adc
1129 // DVBTM ts_in sram share clock control register;
1130 // [0]=1:gate clock,
1131 // [1]=1:invert clock.
1132 // [4:2]: clock rate sel.
1133 // 0: clk_dvbs_rs_p
1134 // 1: mpll_clk48_buf
1135 // 2: mpll_clk43_buf
1136 // 3: clk_dvbs_outer1x_pre_mux4
1137 // 4: clk_dvbs2_oppro_pre_mux4
1138 // 5: clk_dvbtc_outer2x_c_p
1139 // 6: adc_clk_buf
1140 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1a, 2'b11, 16'h1800);
1141 HAL_DMD_RIU_WriteByte(0x102035, 0x11);
1142 HAL_DMD_RIU_WriteByte(0x102034, 0x11);
1143
1144 // @0x3515
1145 // [4:0] : reg_ckg_dvbs2_bch
1146 // DVBS2 BCH clock control register;
1147 // [0]=1:gate clock,
1148 // [1]=1:invert clock.
1149 // [4:2]: clock rate sel.
1150 // 0: mpll_clk216_buf
1151 // 1: mpll_clk172p8_buf
1152 // 2: mpll_clk144_buf
1153 // 3: mpll_clk96_bu4
1154 // 4: mpll_clk72_buf
1155 // 5: adc_clk_buf
1156 // [12:8] : reg_ckg_dvbs2_bch_rs_adc
1157 // [8] : disable clock
1158 // [9] : invert clock
1159 // [11:10] : Select clock source
1160 // 00: clk_dvbs2_bch_pre_mux4
1161 // 01: clk_dvbs_rs_p
1162 // 10: adc_clk_buf
1163 // 11:
1164 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h15, 2'b11, 16'h0800);
1165 HAL_DMD_RIU_WriteByte(0x10202b, 0x11);
1166 HAL_DMD_RIU_WriteByte(0x10202a, 0x11);
1167
1168
1169 // @0x3516
1170 // [4:0] : reg_ckg_dvbtc_outer2x_c
1171 // [0] : disable clock
1172 // [1] : invert clock
1173 // [4:2]: Select clock source
1174 // 000: clk_dmplldiv10_buf
1175 // 001: clk_dmplldiv10_div2_buf
1176 // 010: clk_dmdadc
1177 // 011: clk_dmdadc_div2_buf
1178 // 100: clk_dmplldiv2_div8_buf
1179 // 101: mpll_clk96_buf
1180 // 110: mpll_clk48_buf
1181 // 110: 1'b0
1182 // [11:8] : reg_ckg_adcd_dvbs_rs
1183 // [8] : disable clock
1184 // [9] : invert clock
1185 // [11:10] : Select clock source
1186 // 00: adc_clk_buf
1187 // 01: clk_dvbs_rs_p
1188 // 10: mpll_clk18_buf
1189 // 11:
1190 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h16, 2'b10, 16'h0001);
1191 HAL_DMD_RIU_WriteByte(0x10202d, 0x11);
1192
1193 // 0 reg_force_allsram_on
1194 // 1 reg_adcdma_sram_sd_en = 1
1195 // 2 reg_dvbs2_inner_sram_sd_en = 1
1196 // 4 reg_dvbs2_outer_sram_sd_en = 1
1197 // 5 reg_dvbs_outer_sram_sd_en = 1
1198 // 6 reg_dvbc_outer_sram_sd_en = 1
1199 // 7 reg_dvbc_inner_0_sram_sd_en = 1
1200 // 8 reg_dvbc_inner_1_sram_sd_en = 1
1201 // 9 reg_dvbt_t2_ts_0_sram_sd_en = 1
1202 // 10 reg_dvbt_t2_ts_1_sram_sd_en = 1
1203 // 11 reg_sram_share_sram_sd_en = 1
1204 HAL_DMD_RIU_WriteByte(0x102104, 0xf6);
1205 HAL_DMD_RIU_WriteByte(0x102105, 0x0f);
1206
1207 // ("==============================================================");
1208 // ("End demod top initial setting by HK MCU ......");
1209 // ("==============================================================");
1210
1211 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_Exit\n"));
1212 status &= INTERN_DVBS_SoftStop();
1213
1214 return status;
1215 }
1216
1217 /***********************************************************************************
1218 Subject: Load DSP code to chip
1219 Function: INTERN_DVBS_LoadDSPCode
1220 Parmeter:
1221 Return: MS_BOOL
1222 Remark:
1223 ************************************************************************************/
INTERN_DVBS_LoadDSPCode(void)1224 static MS_BOOL INTERN_DVBS_LoadDSPCode(void)
1225 {
1226 MS_U8 udata = 0x00;
1227 MS_U16 i;
1228 MS_U16 fail_cnt=0;
1229
1230 #if (DBG_DUMP_LOAD_DSP_TIME==1)
1231 MS_U32 u32Time;
1232 #endif
1233
1234 //MDrv_Sys_DisableWatchDog();
1235 /*
1236 HAL_DMD_RIU_WriteByte(0x103480, 0x01);//reference GUI//reset
1237 HAL_DMD_RIU_WriteByte(0x103481, 0x00);
1238 HAL_DMD_RIU_WriteByte(0x103480, 0x00);
1239 HAL_DMD_RIU_WriteByte(0x103483, 0x50);
1240 HAL_DMD_RIU_WriteByte(0x103483, 0x51);
1241 HAL_DMD_RIU_WriteByte(0x103484, 0x00);
1242 HAL_DMD_RIU_WriteByte(0x103485, 0x00);
1243 */
1244 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
1245 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
1246 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
1247 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
1248 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
1249 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
1250
1251 //// Load code thru VDMCU_IF ////
1252 DBG_INTERN_DVBS(printf(">Load Code.....\n"));
1253 for ( i = 0; i < sizeof(INTERN_DVBS_table); i++)
1254 {
1255 HAL_DMD_RIU_WriteByte(0x10348C, INTERN_DVBS_table[i]);
1256 //HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBS_table[i]); // write data to VD MCU 51 code sram
1257 }
1258
1259 //// Content verification ////
1260 DBG_INTERN_DVBS(ULOGD("DEMOD",">Verify Code...\n"));
1261
1262 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
1263 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
1264
1265 for ( i = 0; i < sizeof(INTERN_DVBS_table); i++)
1266 {
1267 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
1268 if (udata != INTERN_DVBS_table[i])
1269 {
1270 ULOGD("DEMOD",">fail add = 0x%x\n", i);
1271 ULOGD("DEMOD",">code = 0x%x\n", INTERN_DVBS_table[i]);
1272 ULOGD("DEMOD",">data = 0x%x\n", udata);
1273
1274 if (fail_cnt > 10)
1275 {
1276 ULOGD("DEMOD",">DVB-S DSP Loadcode fail!");
1277 return false;
1278 }
1279 fail_cnt++;
1280 }
1281 }
1282
1283 #if 1 // Kyoto for VCM DJB
1284 //====================================================================
1285 // add S2 DRAM bufer start address into fixed location
1286 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x30); // sram address low byte; 0x30 is defined in FW
1287 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
1288
1289 //0x30~0x33
1290 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DVBS2_DJB_START_ADDR);
1291 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DVBS2_DJB_START_ADDR >> 8));
1292 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DVBS2_DJB_START_ADDR >> 16));
1293 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DVBS2_DJB_START_ADDR >> 24));
1294
1295 DBG_INTERN_DVBS( ULOGD("DEMOD", "@@@@@ share dram address = 0x %x \n ",u32DVBS2_DJB_START_ADDR) );
1296 //=====================================================================
1297 #endif
1298 /*
1299 //0x30~0x33
1300 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(0x11) );
1301 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(0x22) );
1302 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(0x33) );
1303 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(0x44) );
1304 */
1305
1306 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
1307 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
1308 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
1309 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
1310
1311
1312 DBG_INTERN_DVBS(ULOGD("DEMOD",">DSP Loadcode done."));
1313 #if 0
1314 INTERN_DVBS_Config(6875, 128, 36125, 0,1);
1315 INTERN_DVBS_Active(ENABLE);
1316 while(1);
1317 #endif
1318 //HAL_DMD_RIU_WriteByte(0x101E3E, 0x04); // DVBT = BIT1 -> 0x02
1319
1320 return TRUE;
1321 }
1322
1323 /***********************************************************************************
1324 Subject: DVB-S CLKGEN initialized function
1325 Function: INTERN_DVBS_Power_On_Initialization
1326 Parmeter:
1327 Return: MS_BOOL
1328 Remark:
1329 ************************************************************************************/
INTERN_DVBS_InitClkgen(MS_BOOL bRFAGCTristateEnable)1330 void INTERN_DVBS_InitClkgen(MS_BOOL bRFAGCTristateEnable)
1331 {
1332 //MS_U8 u8Temp=0;
1333 // This file is translated by Steven Hung's riu2script.pl
1334
1335 // ==============================================================
1336 // Start demod top initial setting by HK MCU ......
1337 // ==============================================================
1338 // [8] : reg_chiptop_dummy_0 (reg_dmdtop_dmd_sel)
1339 // 1'b0->reg_DMDTOP control by HK_MCU.
1340 // 1'b1->reg_DMDTOP control by DMD_MCU.
1341 // [9] : reg_chiptop_dummy_0 (reg_dmd_ana_regsel)
1342 // 1'b0->reg_DMDANA control by HK_MCU.
1343 // 1'b1->reg_DMDANA control by DMD_MCU.
1344 // select HK MCU ......
1345 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0000);
1346 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0000);
1347 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
1348
1349
1350 // ==============================================================
1351 // Start TOP CLKGEN initial setting ......
1352 // ==============================================================
1353 // CLK_DMDMCU clock setting
1354 // reg_ckg_dmdmcu@0x0f[4:0]
1355 // [0] : disable clock
1356 // [1] : invert clock
1357 // [4:2]:
1358 // 000:170 MHz(MPLL_DIV_BUF)
1359 // 001:160MHz
1360 // 010:144MHz
1361 // 011:123MHz
1362 // 100:108MHz (Kriti:DVBT2)
1363 // 101:mem_clcok
1364 // 110:mem_clock div 2
1365 // 111:select XTAL
1366 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
1367 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
1368 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1369 HAL_DMD_RIU_WriteByte(0x10331e, 0x30);
1370
1371
1372 // set parallel ts clock
1373 // [12] : reg_ckg_atsc_dvb_div_sel = 1
1374 // 0: select clk_dmplldiv5
1375 // 1: select clk_dmplldiv3
1376 // [11] : reg_ckg_demod_test_in_en = 0
1377 // 0: select internal ADC CLK
1378 // 1: select external test-in clock
1379 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
1380 // 0: select gated clock
1381 // 1: select free-run clock
1382 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
1383 // 0: normal phase to pad
1384 // 1: invert phase to pad
1385 // [4:0]: reg_ckg_dvbtm_ts_divnum = 11
1386 // Demod TS output clock phase tuning number
1387 // If (reg_ckg_tsout_ph_tun_num == reg_ckg_dvbtm_ts_divnum),
1388 // Demod TS output clock is equal Demod TS internal working clock.
1389 // => TS clock = (864/3)/(2*(5+1)) = 24MHz
1390 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1391 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1392 HAL_DMD_RIU_WriteByte(0x103301, 0x14);
1393 HAL_DMD_RIU_WriteByte(0x103300, 0x05);
1394
1395
1396 // enable DVBTC ts clock
1397 // [11:8]: reg_ckg_dvbtc_ts
1398 // [8] : disable clock
1399 // [9] : invert clock
1400 // [11:10]: Select clock source
1401 // 00:clk_atsc_dvb_div
1402 // 01:62 MHz
1403 // 10:54 MHz
1404 // 11:reserved
1405 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
1406 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
1407 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1408 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1409
1410
1411 // enable dvbc adc clock
1412 // [3:0]: reg_ckg_dvbtc_adc
1413 // [0] : disable clock
1414 // [1] : invert clock
1415 // [3:2]: Select clock source => for demod clkgen clk_dvbtc_adc
1416 // 00: clk_dmdadc
1417 // 01: clk_dmdadc_div2
1418 // 10: clk_dmdadc_div4
1419 // 11: DFT_CLK
1420 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
1421 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
1422 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1423 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1424
1425 // Reset TS divider
1426 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h01, 2'b01, 16'h0001);
1427 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1428
1429 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h01, 2'b01, 16'h0000);
1430 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1431
1432
1433 // ("==============================================================");
1434 // ("Start demod CLKGEN setting ......");
1435 // ("==============================================================");
1436 // enable atsc_adcd_sync clock
1437 // [3:0] : reg_ckg_atsc_adcd_sync
1438 // [0] : disable clock
1439 // [1] : invert clock
1440 // [3:2]: Select clock source
1441 // 00: clk_dmdadc_sync
1442 // 01: 1'b0
1443 // 10: 1'b0
1444 // 11: DFT_CLK
1445 // [11:8] : reg_ckg_dmd_dma
1446 // [8] : disable clock
1447 // [9] : invert clock
1448 // [11:10]: Select clock source
1449 // 00: clk_dmdadc
1450 // 01: clk_dmdadc_div2_buf
1451 // 10: 1'b0
1452 // 11: DFT_CLK
1453 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
1454 HAL_DMD_RIU_WriteByte(0x10200b, 0x00);
1455 HAL_DMD_RIU_WriteByte(0x10200a, 0x00);
1456
1457 // [7:4] : reg_ckg_dvbtm_adc0p5x
1458 // [4] : disable clock
1459 // [5] : invert clock
1460 // [7:6]: Select clock source
1461 // 00: adc_clk_div2_buf
1462 // 01: mpll_clk9_buf
1463 // 10: 1'b0
1464 // 11: DFT_CLK
1465 // [11:8] reg_ckg_dvbtm_adc1x_eq1x
1466 // [8] : disable clock
1467 // [9] : invert clock
1468 // [11:10]: Select clock source
1469 // 00: adc_clk_buf
1470 // 01: mpll_clk18_buf
1471 // 10: 1'b0
1472 // 11: DFT_CLK
1473 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
1474 HAL_DMD_RIU_WriteByte(0x102021, 0x00);
1475 HAL_DMD_RIU_WriteByte(0x102020, 0x00);
1476
1477 // DVBS2
1478 // @0x3511
1479 // [3:0] : reg_ckg_dvbs2_inner
1480 // [0] : disable clock
1481 // [1] : invert clock
1482 // [3:2]: Select clock source
1483 // 00: adc_clk_buf
1484 // 01: 1'b0
1485 // 10: 1'b0
1486 // 11: 1'b0
1487 // [7:4] : reg_ckg_dvbs_outer1x
1488 // [4] : disable clock
1489 // [5] : invert clock
1490 // [7:6] : Select clock source
1491 // 00: adc_clk_buf
1492 // 01: clk_dvbtc_outer2x_c_p
1493 // 10: 1'b0
1494 // 11: DFT_CLK
1495 // [11:8] : reg_ckg_dvbs_outer2x
1496 // [8] : disable clock
1497 // [9] : invert clock
1498 // [11:10] : Select clock source
1499 // 00: adc_clk_buf
1500 // 01: 1'b0
1501 // 10: 1'b0
1502 // 11: DFT_CLK
1503 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0000);
1504 HAL_DMD_RIU_WriteByte(0x102023, 0x00);
1505 HAL_DMD_RIU_WriteByte(0x102022, 0x00);
1506
1507
1508 // @0x3512
1509 // [4:0] : reg_ckg_dvbs_rs
1510 // [0] : disable clock
1511 // [1] : invert clock
1512 // [4:2]: Select clock source
1513 // 000: mpll_clk216_buf
1514 // 001: 1'b0
1515 // 010: 1'b0
1516 // 011: 1'b0
1517 // [12:8] : reg_ckg_dvbs2_outer
1518 // [8] : disable clock
1519 // [9] : invert clock
1520 // [12:10] : Select clock source
1521 // 000: mpll_clk288_buf
1522 // 001: mpll_clk216_buf
1523 // 010: 1'b0
1524 // 011: 1'b0
1525 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b11, 16'h0000);
1526 HAL_DMD_RIU_WriteByte(0x102025, 0x00);
1527 HAL_DMD_RIU_WriteByte(0x102024, 0x00);
1528
1529
1530 // @0x3514
1531 // [3:0] : reg_ckg_dvbs2_ldpc_inner_sram
1532 // [0] : disable clock
1533 // [1] : invert clock
1534 // [3:2]: Select clock source
1535 // 00: clk_dvbs2_outer_mux8
1536 // 01: adc_clk_buf
1537 // 10: mpll_clk18_buf
1538 // 11: clk_dvbtc_outer2x_c_p
1539 // [7:4] : reg_ckg_dvbs_viterbi_sram
1540 // [4] : disable clock
1541 // [5] : invert clock
1542 // [7:6] : Select clock source
1543 // 00: clk_dvbs2_outer_mux8
1544 // 01: adc_clk_buf
1545 // 10: mpll_clk18_buf
1546 // 11: DFT_CLK
1547 // [12:8] : reg_ckg_dvbs_rs_deint_sram
1548 // [8] : disable clock
1549 // [9] : invert clock
1550 // [12:10] : Select clock source
1551 // 000: clk_dvbs2_outer_mux8
1552 // 001: clk_dvbs_outer1x_pre_mux4
1553 // 010: adc_clk_buf
1554 // 011: mpll_clk18_buf
1555 // 100: clk_dvbtc_outer2x_c_p
1556 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b11, 16'h0844);
1557 HAL_DMD_RIU_WriteByte(0x102029, 0x08);
1558 HAL_DMD_RIU_WriteByte(0x102028, 0x44);
1559
1560 // @0x3518
1561 // [4:0]: reg_ckg_dvbs2_outer_rs_adc
1562 // [0] : disable clock
1563 // [1] : invert clock
1564 // [3:2]: Select clock source
1565 // 000: clk_dvbs2_outer_mux8
1566 // 001: clk_dvbs_rs_p
1567 // 010: adc_clk_buf
1568 // 011: mpll_clk18_buf
1569 // 100: clk_dvbtc_outer2x_c_p
1570 // [11:8] : reg_ckg_dvbs2_ldpc_inner_j83b_sram
1571 // [0] : disable clock
1572 // [1] : invert clock
1573 // [3:2]: Select clock source
1574 // 00: clk_dvbs2_outer_mux8
1575 // 01: adc_clk_buf
1576 // 10: mpll_clk18_buf
1577 // 11: clk_dvbtc_outer2x_c_p
1578 // [15:12] : reg_ckg_dvbs_viterbi_j83b_sram
1579 // [12] : disable clock
1580 // [13] : invert clock
1581 // [15:14] : Select clock source
1582 // 00: clk_dvbs2_outer_mux8
1583 // 01: adc_clk_buf
1584 // 10: mpll_clk18_buf
1585 // 11: DFT_CLK
1586 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b11, 16'h4408);
1587 HAL_DMD_RIU_WriteByte(0x102031, 0x44);
1588 HAL_DMD_RIU_WriteByte(0x102030, 0x08);
1589
1590
1591 // @0x3519
1592 // [4:0]: reg_ckg_dvbs2_outer_rs_adc_j83b
1593 // [0] : disable clock
1594 // [1] : invert clock
1595 // [3:2]: Select clock source
1596 // 000: clk_dvbs2_outer_mux8
1597 // 001: clk_dvbs_rs_p
1598 // 010: adc_clk_buf
1599 // 011: mpll_clk18_buf
1600 // 100: clk_dvbtc_outer2x_c_p
1601 // [12:8] : reg_ckg_dvbs2_demap
1602 // DVBS2 demap clock control register;
1603 // [0]=1:gate clock,
1604 // [1]=1:invert clock.
1605 // [4:2]: clock rate sel.
1606 // 0: mpll_clk216_buf
1607 // 1: mpll_clk172p8_buf
1608 // 2: mpll_clk144_buf
1609 // 3: mpll_clk96_buf
1610 // 4: mpll_clk72_buf
1611 // 5: adc_clk_buf
1612 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h19, 2'b11, 16'h0008);
1613 HAL_DMD_RIU_WriteByte(0x102033, 0x00);
1614 HAL_DMD_RIU_WriteByte(0x102032, 0x08);
1615
1616
1617 // [4:0]: reg_ckg_dvbs2_oppro
1618 // DVBS2 OPPRO clock control register;
1619 // [0]=1:gate clock,
1620 // [1]=1:invert clock.
1621 // [4:2]: clock rate sel.
1622 // 0: mpll_clk216_buf
1623 // 1: mpll_clk172p8_buf
1624 // 2: mpll_clk144_buf
1625 // 3: mpll_clk96_buf
1626 // 4: mpll_clk72_buf
1627 // 5: adc_clk_buf
1628 // [12:8]: reg_ckg_dvbtm_ts_in_adc
1629 // DVBTM ts_in sram share clock control register;
1630 // [0]=1:gate clock,
1631 // [1]=1:invert clock.
1632 // [4:2]: clock rate sel.
1633 // 0: clk_dvbs_rs_p
1634 // 1: mpll_clk48_buf
1635 // 2: mpll_clk43_buf
1636 // 3: clk_dvbs_outer1x_pre_mux4
1637 // 4: clk_dvbs2_oppro_pre_mux4
1638 // 5: clk_dvbtc_outer2x_c_p
1639 // 6: adc_clk_buf
1640 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1a, 2'b11, 16'h1800);
1641 HAL_DMD_RIU_WriteByte(0x102035, 0x18);
1642 HAL_DMD_RIU_WriteByte(0x102034, 0x00);
1643
1644
1645 // @0x3515
1646 // [4:0] : reg_ckg_dvbs2_bch
1647 // DVBS2 BCH clock control register;
1648 // [0]=1:gate clock,
1649 // [1]=1:invert clock.
1650 // [4:2]: clock rate sel.
1651 // 0: mpll_clk216_buf
1652 // 1: mpll_clk172p8_buf
1653 // 2: mpll_clk144_buf
1654 // 3: mpll_clk96_bu4
1655 // 4: mpll_clk72_buf
1656 // 5: adc_clk_buf
1657 // [12:8] : reg_ckg_dvbs2_bch_rs_adc
1658 // [8] : disable clock
1659 // [9] : invert clock
1660 // [11:10] : Select clock source
1661 // 00: clk_dvbs2_bch_pre_mux4
1662 // 01: clk_dvbs_rs_p
1663 // 10: adc_clk_buf
1664 // 11:
1665 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h15, 2'b11, 16'h0800);
1666 HAL_DMD_RIU_WriteByte(0x10202b, 0x08);
1667 HAL_DMD_RIU_WriteByte(0x10202a, 0x00);
1668
1669
1670
1671 // @0x3516
1672 // [4:0] : reg_ckg_dvbtc_outer2x_c
1673 // [0] : disable clock
1674 // [1] : invert clock
1675 // [4:2]: Select clock source
1676 // 000: clk_dmplldiv10_buf
1677 // 001: clk_dmplldiv10_div2_buf
1678 // 010: clk_dmdadc
1679 // 011: clk_dmdadc_div2_buf
1680 // 100: clk_dmplldiv2_div8_buf
1681 // 101: mpll_clk96_buf
1682 // 110: mpll_clk48_buf
1683 // 110: 1'b0
1684 // [11:8] : reg_ckg_adcd_dvbs_rs
1685 // [8] : disable clock
1686 // [9] : invert clock
1687 // [11:10] : Select clock source
1688 // 00: adc_clk_buf
1689 // 01: clk_dvbs_rs_p
1690 // 10: mpll_clk18_buf
1691 // 11:
1692 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h16, 2'b10, 16'h0001);
1693 HAL_DMD_RIU_WriteByte(0x10202d, 0x00);
1694
1695 // @0x3513
1696 // [4:0] : reg_ckg_dvbtm_ts_in
1697 // [0] : disable clock
1698 // [1] : invert clock
1699 // [4:2]: Select clock source
1700 // 000: clk_dvbtc_rs_p
1701 // 001: dvb_clk48_buf
1702 // 010: dvb_clk43_buf
1703 // 011: clk_dvbs_outer1x_pre_mux4
1704 // 100: clk_dvbs2_oppro_pre_mux4
1705 // 101: 1'b0
1706 // 110: 1'b0
1707 // 111: 1'b0
1708 // [11:8] : reg_ckg_dvbs2_diseqc
1709 // [8] : disable clock
1710 // [9] : invert clock
1711 // [11:10] : Select clock source
1712 // 00: xtali_clk24_buf
1713 // 01: xtali_clk12_buf
1714 // 10: xtali_clk6_buf
1715 // 11: xtali_clk3
1716 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h13, 2'b11, 16'h0010);
1717 HAL_DMD_RIU_WriteByte(0x102027, 0x00);
1718 HAL_DMD_RIU_WriteByte(0x102026, 0x00);
1719
1720 // ("==============================================================");
1721 // ("End demod top initial setting by HK MCU ......");
1722 // ("==============================================================");
1723
1724 // ===============================================================
1725 // Select reg_DMDTOP and reg_DMDANA are controlled by DMD MCU
1726 // ===============================================================
1727 // [8] : reg_chiptop_dummy_0 (reg_dmdtop_dmd_sel)
1728 // 1'b0->reg_DMDTOP control by HK_MCU.
1729 // 1'b1->reg_DMDTOP control by DMD_MCU.
1730 // [9] : reg_chiptop_dummy_0 (reg_dmd_ana_regsel)
1731 // 1'b0->reg_DMDANA control by HK_MCU.
1732 // 1'b1->reg_DMDANA control by DMD_MCU.
1733 // ("select DMD MCU ......");
1734 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300); // select DMD MCU
1735 HAL_DMD_RIU_WriteByte(0x101e39, 0x03);
1736 HAL_DMD_RIU_WriteByte(0x103c0e, 0x01);
1737
1738 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_InitClkgen\n"));
1739 }
1740
1741 /***********************************************************************************
1742 Subject: Power on initialized function
1743 Function: INTERN_DVBS_Power_On_Initialization
1744 Parmeter:
1745 Return: MS_BOOL
1746 Remark:
1747 ************************************************************************************/
INTERN_DVBS_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBS_DSPRegInitExt,MS_U8 u8DMD_DVBS_DSPRegInitSize)1748 MS_BOOL INTERN_DVBS_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBS_DSPRegInitExt, MS_U8 u8DMD_DVBS_DSPRegInitSize)
1749 {
1750 MS_U8 status = true;
1751 //MS_U8 u8ChipVersion;
1752
1753 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_Power_On_Initialization\n"));
1754
1755 #if defined(PWS_ENABLE)
1756 Mapi_PWS_Stop_VDMCU();
1757 #endif
1758 INTERN_DVBS_InitClkgen(bRFAGCTristateEnable);//~~ no modify
1759 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);//~~ no modify
1760
1761 DBG_INTERN_DVBS(ULOGD("DEMOD","@@@@@INTERN_DVBS_Power_On_Initialization1:bRFAGCTristateEnable=%d ;u8ADCIQMode=%d \n",bRFAGCTristateEnable,u8ADCIQMode));
1762 DBG_INTERN_DVBS(ULOGD("DEMOD","@@@@@INTERN_DVBS_Power_On_Initialization2:u8PadSel=%d ;bPGAEnable=%d \n",u8PadSel,bPGAEnable));
1763 DBG_INTERN_DVBS(ULOGD("DEMOD","@@@@@INTERN_DVBS_Power_On_Initialization2:u8PGAGain=%d \n",u8PGAGain));
1764
1765 //// Firmware download //////////
1766 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS Load DSP...\n"));
1767 //MsOS_DelayTask(100);
1768
1769 {
1770 if (INTERN_DVBS_LoadDSPCode() == FALSE)
1771 {
1772 DBG_INTERN_DVBS(ULOGD("DEMOD","DVB-S Load DSP Code Fail\n"));
1773 return FALSE;
1774 }
1775 else
1776 {
1777 DBG_INTERN_DVBS(ULOGD("DEMOD","DVB-S Load DSP Code OK\n"));
1778 }
1779 }
1780
1781 // For VCM
1782
1783 // Set VCM option
1784 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_VCM_OPT, u8VCM_Enabled_Opt);
1785
1786 if(u8VCM_Enabled_Opt == VCM_Forced_Mode)
1787 {
1788 // assign IS-ID
1789 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_IS_ID, u8Default_VCM_IS_ID);
1790 }
1791
1792 //// MCU Reset //////////
1793 if (INTERN_DVBS_Reset() == FALSE)
1794 {
1795 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS Reset...Fail\n"));
1796 return FALSE;
1797 }
1798 else
1799 {
1800 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS Reset...OK\n"));
1801 }
1802
1803
1804 status &= INTERN_DVBS_DSPReg_Init(u8DMD_DVBS_DSPRegInitExt, u8DMD_DVBS_DSPRegInitSize);
1805 //status &= INTERN_DVBS_Active(ENABLE);//enable this
1806
1807 //Read Demod FW Version.
1808 INTERN_DVBS_Show_Demod_Version();
1809
1810
1811 return status;
1812 }
1813
1814 /************************************************************************************************
1815 Subject: Driving control
1816 Function: INTERN_DVBC_Driving_Control
1817 Parmeter: bInversionEnable : TRUE For High
1818 Return: void
1819 Remark:
1820 *************************************************************************************************/
INTERN_DVBS_Driving_Control(MS_BOOL bEnable)1821 void INTERN_DVBS_Driving_Control(MS_BOOL bEnable)
1822 {
1823 MS_U8 u8Temp;
1824
1825 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1826
1827 if (bEnable)
1828 {
1829 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1830 }
1831 else
1832 {
1833 u8Temp = u8Temp & (~0x01);
1834 }
1835
1836 DBG_INTERN_DVBS(ULOGD("DEMOD","---> INTERN_DVBS_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1837 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1838 }
1839
1840 /************************************************************************************************
1841 Subject: Interrupt mode
1842 Function: INTERN_DVBS_Demod_Interrupt_Monitor
1843 Parmeter:
1844 Return: MS_BOOL
1845 Remark:
1846 *************************************************************************************************/
1847
INTERN_DVBS_Demod_Interrupt_Monitor(MS_U8 * pu8IntType)1848 MS_BOOL INTERN_DVBS_Demod_Interrupt_Monitor(MS_U8* pu8IntType)
1849 {
1850 MS_U8 u8_interrupt_type = 0;
1851 MS_BOOL bRet= TRUE;
1852 MS_U8 u8Data = 0;
1853
1854 // For VCM
1855 MS_U8 IS_ID = 0;
1856 MS_U8 IS_ID_Table[32];
1857
1858 //MS_U8 u8TsDiv = 1;
1859 //MS_FLOAT temp = 0;
1860
1861 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_Demod_Interrupt_Monitor\n"));
1862
1863 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_LOCK_COUNT, &u8Data);
1864 //bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);
1865
1866 switch(u8Data)
1867 {
1868 case 0: // DVBS2
1869 {
1870 u8_interrupt_type = 1;
1871 _bDemodType = TRUE; //S2
1872
1873 if( u8VCM_Enabled_Opt == VCM_MODE && INTERN_DVBS2_VCM_CHECK() )
1874 {
1875 INTERN_DVBS2_Get_IS_ID_INFO(&IS_ID, IS_ID_Table);
1876 INTERN_DVBS2_Set_Default_IS_ID(&IS_ID, IS_ID_Table);
1877
1878 ULOGD("DEMOD",">>>INTERN_DVBS_Demod VCM Default IS ID = %d<<<\n", IS_ID);
1879 }
1880
1881 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Demod DVBS2 Interrupt Lock<<<\n"));
1882
1883 //For Auto Test
1884 DBG_INTERN_DVBS(ULOGD("DEMOD","@INTERN_DVBS_Demod Lock+++\n"));
1885 u8DemodLockFlag = 1;
1886 }
1887 break;
1888
1889 case 1: // DVBS
1890 {
1891 u8_interrupt_type = 1;
1892 _bDemodType = FALSE; //S
1893 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Demod DVBS Interrupt Lock<<<\n"));
1894 //For Auto Test
1895 DBG_INTERN_DVBS(ULOGD("DEMOD","@INTERN_DVBS_Demod Lock+++\n"));
1896 u8DemodLockFlag = 1;
1897 }
1898 break;
1899
1900 case 2:
1901 {
1902 u8_interrupt_type = 2;
1903 DBG_INTERN_DVBS(ULOGD("DEMOD","@INTERN_DVBS_Demod Interrupt UnLock---\n"));
1904 u8DemodLockFlag = 0;
1905 _bTSDataSwap = FALSE;
1906 }
1907 break;
1908
1909 default:
1910 {
1911 u8_interrupt_type = 0;
1912 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Demod_Interrupt_Monitor Error<<<\n"));
1913 }
1914 break;
1915 }
1916
1917 #if 0
1918 if((u8Data==0x00) || (u8Data==0x01))//lock
1919 {
1920 u8_interrupt_type = 1;
1921 if(u8Data==0x01)
1922 {
1923 _bDemodType=FALSE; //S
1924 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Demod DVBS Interrupt Lock<<<\n"));
1925 }
1926 else
1927 {
1928 _bDemodType=TRUE; //S2
1929 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Demod DVBS2 Interrupt Lock<<<\n"));
1930 }
1931
1932
1933 INTERN_DVBS_GetTsDivNum(&temp); //ts_div_num
1934 u8TsDiv = temp;
1935 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_GetLock TsClkDivNum = 0x%x<<<\n", u8TsDiv));
1936 if (u8TsDiv > 0x1F)
1937 u8TsDiv=0x1F;
1938 HAL_DMD_RIU_WriteByte(0x103300, u8TsDiv);
1939 //Ts Output Enable
1940 HAL_DMD_RIU_WriteByte(0x101eaa,0x10);
1941
1942
1943 //For Auto Test
1944 DBG_INTERN_DVBS(ULOGD("DEMOD","@INTERN_DVBS_Demod Lock+++\n"));
1945 u8DemodLockFlag=1;
1946
1947 if(_bSerialTS==1)
1948 {
1949 _bTSDataSwap=TRUE;
1950 MDrv_SYS_DMD_VD_MBX_ReadReg( (DVBTM_REG_BASE + 0x20*2), &u8Data);//DVBTM_REG_BASE
1951 u8Data^=0x20;//h0020 h0020 5 5 reg_ts_data_reverse
1952 MDrv_SYS_DMD_VD_MBX_WriteReg( (DVBTM_REG_BASE + 0x20*2), u8Data);
1953 }
1954 }
1955 else if(u8Data==0x02)//unlock
1956 {
1957 u8_interrupt_type = 2;
1958 DBG_INTERN_DVBS(ULOGD("DEMOD","@INTERN_DVBS_Demod Interrupt UnLock---\n"));
1959 u8DemodLockFlag=0;
1960 _bTSDataSwap=false;
1961 }
1962
1963 else if(u8Data==0x03)//update TS
1964 {
1965 u8_interrupt_type = 3;
1966 INTERN_DVBS_GetTsDivNum(&temp); //ts_div_num
1967 u8TsDiv = temp;
1968 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Demod Interrupt TsClkDivNum = 0x%x<<<\n", u8TsDiv));
1969 if (u8TsDiv > 0x1F)
1970 u8TsDiv=0x1F;
1971 HAL_DMD_RIU_WriteByte(0x103300, u8TsDiv);
1972 }
1973 else
1974 {
1975 u8_interrupt_type = 0;
1976 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Demod_Interrupt_Monitor Error<<<\n"));
1977 }
1978 #endif
1979
1980 *pu8IntType = u8_interrupt_type;
1981
1982 return bRet;
1983 }
1984
1985 /************************************************************************************************
1986 Subject: Clk Inversion control
1987 Function: INTERN_DVBS_Clk_Inversion_Control
1988 Parmeter: bInversionEnable : TRUE For Inversion Action
1989 Return: void
1990 Remark:
1991 *************************************************************************************************/
INTERN_DVBS_Clk_Inversion_Control(MS_BOOL bInversionEnable)1992 void INTERN_DVBS_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1993 {
1994 MS_U8 u8Temp;
1995
1996 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1997
1998 if (bInversionEnable)
1999 {
2000 u8Temp = u8Temp | 0x02; //bit 9: clk inv
2001 }
2002 else
2003 {
2004 u8Temp = u8Temp & (~0x02);
2005 }
2006
2007 DBG_INTERN_DVBS(ULOGD("DEMOD","---> Inversion(Bit9) = 0x%x \n",u8Temp));
2008 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
2009 }
2010
2011 /************************************************************************************************
2012 Subject: Transport stream serial/parallel control
2013 Function: INTERN_DVBS_Serial_Control
2014 Parmeter: bEnable : TRUE For serial
2015 Return: MS_BOOL :
2016 Remark:
2017 *************************************************************************************************/
INTERN_DVBS_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)2018 MS_BOOL INTERN_DVBS_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
2019 {
2020 MS_U8 status = true;
2021 MS_U8 temp_val;
2022 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_ts... u8TSClk=%d\n", u8TSClk));
2023
2024 if (u8TSClk == 0xFF) u8TSClk=0x13;
2025 if (bEnable) //Serial mode for TS pad
2026 {
2027 // serial
2028 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
2029 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2030
2031 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
2032 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2033 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
2034 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2035 temp_val|=0x04;
2036 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2037 #else
2038 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
2039 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2040 temp_val|=0x07;
2041 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2042 #endif
2043 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
2044 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
2045
2046 //// INTERN_DVBS TS Control: Serial //////////
2047
2048 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, TS_SERIAL);
2049
2050 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2051 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 0);
2052 #else
2053 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 1);
2054 #endif
2055 gsCmdPacketDVBS.cmd_code = CMD_TS_CTRL;
2056
2057 gsCmdPacketDVBS.param[0] = TS_SERIAL;
2058 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2059 gsCmdPacketDVBS.param[1] = 0;//TS_CLK_NO_INV;
2060 #else
2061 gsCmdPacketDVBS.param[1] = 1;//TS_CLK_INVERSE;
2062 #endif
2063 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 2);
2064 }
2065 else
2066 {
2067 //parallel
2068 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
2069 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2070
2071 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2072 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2073 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2074 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
2075 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2076 temp_val|=0x05;
2077 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2078 #else
2079 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
2080 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2081 temp_val|=0x07;
2082 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2083 #endif
2084
2085 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
2086 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
2087
2088 //// INTERN_DVBS TS Control: Parallel //////////
2089
2090 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, TS_PARALLEL);
2091
2092 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2093 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 0);
2094 #else
2095 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 1);
2096 #endif
2097 //// INTERN_DVBC TS Control: Parallel //////////
2098 gsCmdPacketDVBS.cmd_code = CMD_TS_CTRL;
2099
2100 gsCmdPacketDVBS.param[0] = TS_PARALLEL;
2101 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2102 gsCmdPacketDVBS.param[1] = 0;//TS_CLK_NO_INV;
2103 #else
2104 gsCmdPacketDVBS.param[1] = 1;//TS_CLK_INVERSE;
2105 #endif
2106 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 2);
2107 }
2108
2109 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2110 DBG_INTERN_DVBS(ULOGD("DEMOD","---> Inversion(Bit5) = %d \n",0 ));
2111 #else
2112 DBG_INTERN_DVBS(ULOGD("DEMOD","---> Inversion(Bit5) = %d \n",1 ));
2113 #endif
2114
2115 INTERN_DVBS_Driving_Control(INTERN_DVBS_DTV_DRIVING_LEVEL);
2116 return status;
2117 }
2118
2119 /************************************************************************************************
2120 Subject: TS1 output control
2121 Function: INTERN_DVBS_PAD_TS1_Enable
2122 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
2123 Return: void
2124 Remark:
2125 *************************************************************************************************/
INTERN_DVBS_PAD_TS1_Enable(MS_BOOL flag)2126 void INTERN_DVBS_PAD_TS1_Enable(MS_BOOL flag)
2127 {
2128 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_TS1_Enable... \n"));
2129
2130 if(flag) // PAD_TS1 Enable TS CLK PAD
2131 {
2132 //printf("=== TS1_Enable ===\n");
2133 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
2134 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
2135 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
2136 }
2137 else // PAD_TS1 Disable TS CLK PAD
2138 {
2139 //printf("=== TS1_Disable ===\n");
2140 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
2141 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
2142 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
2143 }
2144 }
2145
2146 /************************************************************************************************
2147 Subject: channel change config
2148 Function: INTERN_DVBC_Config
2149 Parmeter: BW: bandwidth
2150 Return: MS_BOOL :
2151 Remark:
2152 *************************************************************************************************/
INTERN_DVBS_Config(MS_U32 u32SymbolRate,DMD_DVBS_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)2153 MS_BOOL INTERN_DVBS_Config(MS_U32 u32SymbolRate, DMD_DVBS_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
2154 {
2155
2156 MS_BOOL status= true;
2157 MS_U16 u16CenterFreq;
2158 // MS_U16 u16Fc = 0;
2159 MS_U8 temp_val;
2160 MS_U8 u8Data =0;
2161 MS_U8 u8counter = 0;
2162 //MS_U32 u32CurrentSR;
2163
2164 //u32CurrentSR = u32SymbolRate/1000; //KHz
2165
2166 //u32SymbolRate= u32SymbolRate/1000;//to match fw format
2167 u16CenterFreq =u32IFFreq;
2168 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_config+, QAM=%d, u32IFFreq=%d, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n", eQamMode, u32IFFreq, bSpecInv, bSerialTS, u8TSClk));
2169 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_Config, t = %d\n",MsOS_GetSystemTime()));
2170
2171 u8TSClk=0x05;//if (u8TSClk == 0xFF) u8TSClk=0x13;//set a fater speed for initial condition
2172 status &= INTERN_DVBS_Reset();
2173
2174 u8DemodLockFlag=0;
2175 /*
2176 // Symbol Rate
2177 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, u32CurrentSR&0xff);
2178 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, (u32CurrentSR>>8)&0xff);
2179 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, (u32CurrentSR>>16)&0xff);
2180 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config u32SymbolRate %d<<<\n", u32CurrentSR));
2181 */
2182 #if 0
2183 //======== check SR is right or not ===========
2184 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &u8Data);
2185 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L,u8Data));
2186 u32SR =u8Data;
2187 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &u8Data);
2188 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H,u8Data));
2189 u32SR =((U32)u8Data<<8)|u32SR ;
2190 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &u8Data);
2191 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MB_DMDTOP_DBG_5 addr=%d mailbox value=%d<<<\n", E_DMD_S2_MB_DMDTOP_DBG_5,u8Data));
2192 u32SR =((U32)u8Data<<16)|u32SR;
2193 //=================================================
2194 #endif
2195
2196 // IQ Swap ,ADCPLL IQ swap / DMDANA_IQ_SWAP
2197 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_IQ_SWAP, bSpecInv? 0x01:0x00);
2198 if(bSpecInv)
2199 {
2200 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DMDANA_REG_BASE+0xC0, &u8Data);//Demod\reg_dmdana.xls
2201 u8Data|=(0x02);
2202 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DMDANA_REG_BASE+0xC0, u8Data);
2203 }
2204
2205 // TS mode
2206 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, bSerialTS? 0x01:0x00);
2207 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Config TS Serial %d<<<\n", bSerialTS));
2208 _bSerialTS = bSerialTS;
2209
2210 if (bSerialTS)
2211 {
2212 // serial
2213 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2214 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2215
2216 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
2217 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2218 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2219 temp_val|=0x04;
2220 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2221 #else
2222 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2223 temp_val|=0x07;
2224 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2225 #endif
2226 }
2227 else
2228 {
2229 //parallel
2230 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2231 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2232
2233 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2234 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2235 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2236 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2237 temp_val|=0x05;
2238 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2239 #else
2240 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2241 temp_val|=0x07;
2242 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2243 #endif
2244 }
2245 #if (INTERN_DVBS_INTERNAL_DEBUG == 1)
2246 INTERN_DVBS_Show_Demod_Version();
2247 #endif
2248
2249 //-----------------------------------------------------------
2250 //From INTERN_DVBS_Demod_Restart function.
2251
2252 //FW sw reset
2253 //[0]: 0: SW Reset, 1: Start state machine
2254 //[1]: 1: Blind scan enable, 0: manual scan
2255 //[2]: 1: Code flow track enable
2256 //[3]: 1: go to AGC state
2257 //[4]: 1: set DiSEqC
2258 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2259 u8Data = (u8Data&0xF0)|0x01;
2260 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2261 //DBG_INTERN_DVBS(printf(">>>REG write check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2262 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2263 //DBG_INTERN_DVBS(printf(">>>REG read check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2264
2265 u8counter = 20;
2266 while( ((u8Data&0x01) == 0x00) && (u8counter != 0) )
2267 {
2268 MsOS_DelayTask(1);
2269 ULOGD("DEMOD","TOP_WR_DBG_90=0x%x, status=%d, u8counter=%d\n", u8Data, status, u8counter);
2270 u8Data|=0x01;
2271 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
2272 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
2273 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>(while)REG read check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2274 u8counter--;
2275 }
2276
2277 if((u8Data & 0x01)==0x00)
2278 {
2279 status = FALSE;
2280 }
2281
2282 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_config done\n"));
2283 return status;
2284 }
2285 /************************************************************************************************
2286 Subject: channel change config
2287 Function: INTERN_DVBS_Blind_Scan_Config
2288 Parmeter: BW: bandwidth
2289 Return: MS_BOOL :
2290 Remark:
2291 *************************************************************************************************/
INTERN_DVBS_BlindScan_Config(MS_U32 u32SymbolRate,DMD_DVBS_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)2292 MS_BOOL INTERN_DVBS_BlindScan_Config(MS_U32 u32SymbolRate, DMD_DVBS_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
2293 {
2294
2295 MS_BOOL status= true;
2296 MS_U16 u16CenterFreq;
2297 // MS_U16 u16Fc = 0;
2298 MS_U8 temp_val;
2299 MS_U8 u8Data=0;
2300 MS_U16 u16WaitCount = 0;
2301
2302 //MS_U32 u32CurrentSR;
2303
2304 //u32CurrentSR = u32SymbolRate/1000; //KHz
2305
2306 //u32SymbolRate= u32SymbolRate/1000;//to match fw format
2307 u16CenterFreq =u32IFFreq;
2308
2309 //DBG_INTERN_DVBS(printf(" @INTERN_DVBS_blindScan_Config+, SR=%d, QAM=%d, u32IFFreq=%d, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n", u32CurrentSR, eQamMode, u32IFFreq, bSpecInv, bSerialTS, u8TSClk));
2310 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_blindScan_Config, t = %d\n",MsOS_GetSystemTime()));
2311
2312 //status &= INTERN_DVBS_Reset();
2313 /*
2314 g_dvbs_lock = 0;
2315 u8DemodLockFlag=0;
2316 // Symbol Rate
2317 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, u32CurrentSR&0xff);
2318 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, (u32CurrentSR>>8)&0xff);
2319 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, (u32CurrentSR>>16)&0xff);
2320 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config u32SymbolRate %d<<<\n", u32CurrentSR));
2321 */
2322 #if 0
2323 //======== check SR is right or not ===========
2324 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &u8Data);
2325 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L,u8Data));
2326 u32SR =u8Data;
2327 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &u8Data);
2328 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H,u8Data));
2329 u32SR =((U32)u8Data<<8)|u32SR ;
2330 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &u8Data);
2331 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MB_DMDTOP_DBG_5 addr=%d mailbox value=%d<<<\n", E_DMD_S2_MB_DMDTOP_DBG_5,u8Data));
2332 u32SR =((U32)u8Data<<16)|u32SR;
2333 //=================================================
2334 #endif
2335
2336 // IQ Swap ,ADCPLL IQ swap / DMDANA_IQ_SWAP
2337 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_IQ_SWAP, bSpecInv? 0x01:0x00);
2338 if(bSpecInv)
2339 {
2340 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DMDANA_REG_BASE+0xC0, &u8Data);//Demod\reg_dmdana.xls
2341 u8Data|=(0x02);
2342 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DMDANA_REG_BASE+0xC0, u8Data);
2343 }
2344
2345 // TS mode
2346 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, bSerialTS? 0x01:0x00);
2347 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Config TS Serial %d<<<\n", bSerialTS));
2348 _bSerialTS = bSerialTS;
2349 u8TSClk=0x05;//if (u8TSClk == 0xFF) u8TSClk=0x13;//set a fater speed for initial condition
2350
2351 if (bSerialTS)
2352 {
2353 // serial
2354 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2355 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2356
2357 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
2358 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2359 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2360 temp_val|=0x04;
2361 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2362 #else
2363 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2364 temp_val|=0x07;
2365 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2366 #endif
2367 }
2368 else
2369 {
2370 //parallel
2371 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2372 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2373
2374 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2375 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2376 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2377 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2378 temp_val|=0x05;
2379 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2380 #else
2381 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2382 temp_val|=0x07;
2383 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2384 #endif
2385 }
2386 #if (INTERN_DVBS_INTERNAL_DEBUG == 1)
2387 INTERN_DVBS_Show_Demod_Version();
2388 #endif
2389
2390 //-----------------------------------------------------------
2391 //From INTERN_DVBS_Demod_Restart function.
2392
2393 //enable send DiSEqC
2394 //[0]: 0: SW Reset, 1: Start state machine
2395 //[1]: 1: Blind scan enable, 0: manual scan
2396 //[2]: 1: Code flow track enable
2397 //[3]: 1: go to AGC state
2398 //[4]: 1: set DiSEqC
2399 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2400 u8Data |= 0x08;
2401 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2402
2403 u16WaitCount=0;
2404 do
2405 {
2406 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
2407 u16WaitCount++;
2408 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
2409 MsOS_DelayTask(1);
2410 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
2411
2412 // disable blind scan
2413 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2414 u8Data&=~(0x02);
2415 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2416
2417 //disble send DiSEqC
2418 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2419 u8Data&=~(0x08);
2420 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2421
2422
2423 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_blindScan_Config done\n"));
2424 return status;
2425 }
2426
INTERN_DVBS_Power_ON_OFF(MS_U8 bPowerOn)2427 void INTERN_DVBS_Power_ON_OFF(MS_U8 bPowerOn)
2428 {
2429 bPowerOn = bPowerOn;
2430 }
2431
INTERN_DVBS_Power_Save(void)2432 MS_BOOL INTERN_DVBS_Power_Save(void)
2433 {
2434 return TRUE;
2435 }
2436 //------------------------------------------------------------------
2437 // END System Info Function
2438 //------------------------------------------------------------------
2439
2440 //------------------------------------------------------------------
2441 // Get And Show Info Function
2442 //------------------------------------------------------------------
2443 /************************************************************************************************
2444 Subject: enable hw to lock channel
2445 Function: INTERN_DVBS_Active
2446 Parmeter: bEnable
2447 Return: MS_BOOL
2448 Remark:
2449 *************************************************************************************************/
INTERN_DVBS_Active(MS_BOOL bEnable)2450 MS_BOOL INTERN_DVBS_Active(MS_BOOL bEnable)
2451 {
2452 MS_U8 status = TRUE;
2453 //MS_U8 u8Data;
2454
2455 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_Active\n"));
2456
2457 //// INTERN_DVBS Finite State Machine on/off //////////
2458 #if 0
2459 gsCmdPacketDVBC.cmd_code = CMD_FSM_CTRL;
2460
2461 gsCmdPacketDVBS.param[0] = (MS_U8)bEnable;
2462 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 1);
2463 #else
2464
2465 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
2466 #endif
2467
2468 bDMD_DVBS_NoChannelDetectedWithRFPower = FALSE;
2469 u32DMD_DVBS_NoChannelTimeAccWithRFPower = 0;
2470 return status;
2471 }
2472
INTERN_DVBS_GetTsDivNum(MS_U32 * u32SymbolRate,MS_U8 * system_type_reg,MS_U8 * code_rate_idx,MS_U8 * fec_type_idx,MS_U8 * pilot_flag,MS_U32 * u32temp,MS_U8 * code_rate_reg)2473 MS_BOOL INTERN_DVBS_GetTsDivNum(MS_U32 *u32SymbolRate, MS_U8* system_type_reg, MS_U8 *code_rate_idx, MS_U8 *fec_type_idx, MS_U8 *pilot_flag, MS_U32 *u32temp, MS_U8 *code_rate_reg)
2474 {
2475 MS_U8 u8Data = 0;
2476 MS_BOOL status = true;
2477 //MS_U32 u32SymbolRate=0;
2478 //float fSymbolRate;
2479 //MS_U8 ISSY_EN = 0;
2480 //MS_U8 code_rate_idx_temp = 0;
2481 //MS_U8 pilot_flag_temp = 0;
2482 //MS_U8 fec_type_idx_temp = 0;
2483 MS_U8 mod_type_idx = 0;
2484 //MS_U16 k_bch_array[2][11] ={
2485 // {16008, 21408, 25728, 32208, 38688, 43040, 48408, 51648, 53840, 57472, 58192},
2486 // { 3072, 5232, 6312, 7032, 9552, 10632, 11712, 12432, 13152, 14232, 0}};
2487 //MS_U16 n_ldpc_array[2] = {64800, 16200};
2488 //MS_FLOAT pilot_term = 0;
2489 //MS_FLOAT k_bch;
2490 //MS_FLOAT n_ldpc;
2491 //MS_FLOAT ts_div_num_offset = 2.0;
2492 //MS_U32 u32Time_start,u32Time_end;
2493 //MS_U32 u32temp;
2494 //MS_FLOAT pkt_interval;
2495 //MS_U8 time_counter=0;
2496
2497 MS_U32 current_time = 0;
2498 MS_U8 VCM_OPT = VCM_Disabled;
2499
2500 INTERN_DVBS_GetCurrentSymbolRate(u32SymbolRate);
2501 //fSymbolRate=u32SymbolRate+0.0;///1000.0;//Symbol Rate(KHz)
2502 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum u32SymbolRate=%d\n", *u32SymbolRate));
2503 // DMD_DVBS_MODULATION_TYPE pQAMMode;
2504
2505 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//V
2506 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum GetCurrentDemodType E_DMD_S2_SYSTEM_TYPE=%d\n", u8Data));//u8Data:0 is S2; 1 is DVBS
2507
2508 //ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum GetCurrentDemodType E_DMD_S2_SYSTEM_TYPE=%d\n", u8Data);
2509
2510 *system_type_reg = u8Data;
2511 if(!u8Data)//DVBS2
2512 {
2513 /*
2514 //Get DVBS2 Code Rate
2515 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);//V
2516 printf("[S2]INTERN_DVBS_GetTsDivNum DVBS2 E_DMD_S2_CODERATE=0x%x\n", u8Data);
2517 switch (u8Data)
2518 {
2519 case 0x03: //CR 1/2
2520 k_bch=32208.0;
2521 //_u8_DVBS2_CurrentCodeRate = 5;
2522 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_2\n"));
2523 break;
2524 case 0x01: //CR 1/3
2525 k_bch=21408.0; //8PSK???
2526 //_u8_DVBS2_CurrentCodeRate = 6;
2527 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_3\n"));
2528 break;
2529 case 0x05: //CR 2/3
2530 k_bch=43040.0;
2531 //_u8_DVBS2_CurrentCodeRate = 7;
2532 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=2_3\n"));
2533 break;
2534 case 0x00: //CR 1/4
2535 k_bch=16008.0; //8PSK???
2536 //_u8_DVBS2_CurrentCodeRate = 8;
2537 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_4\n"));
2538 break;
2539 case 0x06: //CR 3/4
2540 k_bch=48408.0;
2541 //_u8_DVBS2_CurrentCodeRate = 9;
2542 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=3_4\n"));
2543 break;
2544 case 0x02: //CR 2/5
2545 k_bch=25728.0; //8PSK???
2546 //_u8_DVBS2_CurrentCodeRate = 10;
2547 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=2_5\n"));
2548 break;
2549 case 0x04: //CR 3/5
2550 k_bch=38688.0;
2551 //_u8_DVBS2_CurrentCodeRate = 11;
2552 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=3_5\n"));
2553 break;
2554 case 0x07: //CR 4/5
2555 k_bch=51648.0;
2556 //_u8_DVBS2_CurrentCodeRate = 12;
2557 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=4_5\n"));
2558 break;
2559 case 0x08: //CR 5/6
2560 k_bch=53840.0;
2561 //_u8_DVBS2_CurrentCodeRate = 13;
2562 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=5_6\n"));
2563 break;
2564 case 0x09: //CR 8/9
2565 k_bch=57472.0;
2566 //_u8_DVBS2_CurrentCodeRate = 14;
2567 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=8_9\n"));
2568 break;
2569 case 0x0A: //CR 9/10
2570 k_bch=58192.0;
2571 //_u8_DVBS2_CurrentCodeRate = 15;
2572 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=9_10\n"));
2573 break;
2574 default:
2575 k_bch=58192.0;
2576 //_u8_DVBS2_CurrentCodeRate = 15;
2577 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate= default 9_10\n"));
2578 break;
2579 } //printf("INTERN_DVBS_GetTsDivNum k_bch=%ld\n", (MS_U32)k_bch);
2580 */
2581 //INTERN_DVBS_GetCurrentModulationType(&pQAMMode); //V
2582 //printf("INTERN_DVBS_GetTsDivNum Mod_order=%d\n", modulation_order);
2583
2584 // pilot_flag => 0 : off 1 : on
2585 // fec_type_idx => 0 : normal 1 : short
2586 // mod_type_idx => 0 : QPSK 1 : 8PSK 2 : 16APSK 3 : 32APSK
2587 // code_rate_idx => d0: 1/4, d1: 1/3, d2: 2/5, d3: 1/2, d4: 3/5, d5: 2/3, d6: 3/4, d7: 4/5, d8: 5/6, d9: 8/9, d10: 9/10
2588 //set TS clock rate
2589
2590 if( INTERN_DVBS2_VCM_CHECK() ) // VCM signal
2591 {
2592 // wait current IS ID which we want to get
2593 current_time = MsOS_GetSystemTime();
2594 do
2595 {
2596 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_VCM_OPT, &VCM_OPT);
2597 }
2598 while( VCM_OPT != VCM_Forced_Mode && (MsOS_GetSystemTime() - current_time) < 500);
2599 }
2600
2601 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, code_rate_idx);
2602 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FEC_TYPE, fec_type_idx);
2603 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MOD_TYPE, &mod_type_idx);
2604 modulation_order = modulation_order_array[mod_type_idx];
2605 //modulation_order = mod_type_idx;
2606 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_PILOT_FLAG, pilot_flag);
2607
2608 //ULOGD("DEMOD","FEC = : %x\n", *fec_type_idx);
2609 //ULOGD("DEMOD","cr = : %x\n", *code_rate_idx);
2610 //ULOGD("DEMOD","pilot = : %x\n", *pilot_flag);
2611 //ULOGD("DEMOD","MOD = : %x\n", mod_type_idx);
2612
2613 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_PILOT_FLAG, &u8Data);
2614
2615 /*
2616 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_ISSY_ACTIVE, ISSY_EN);
2617 if(*ISSY_EN==0)
2618 {
2619 k_bch = k_bch_array[fec_type_idx][code_rate_idx];
2620 n_ldpc = n_ldpc_array[fec_type_idx];
2621 pilot_term = ((float) n_ldpc / modulation_order / 1440 * 36) * pilot_flag;
2622 if(sDMD_DVBS_Info.bSerialTS)//serial mode
2623 {
2624 *fTSDivNum =(288000.0/(k_bch/((n_ldpc/modulation_order+90+pilot_term)/u32SymbolRate)) - ts_div_num_offset);
2625 *fTSDivNum = (*fTSDivNum-1)/2;// since 288/(2(fTSDivNum+1)) = 288/TS_RATE = A ==> fTSDivNum = (A-1)/2
2626 }
2627 else//parallel mode
2628 {
2629 *fTSDivNum = (288000.0/(k_bch/((n_ldpc/modulation_order+90+pilot_term)/u32SymbolRate)/8) - ts_div_num_offset);
2630 *fTSDivNum = (*fTSDivNum-1)/2;
2631 }
2632 }
2633 else if(*ISSY_EN==1)//ISSY = 1
2634 {
2635 //u32Time_start = msAPI_Timer_GetTime0();
2636 time_counter=0;
2637 do
2638 {
2639 MDrv_SYS_DMD_VD_MBX_ReadReg((0x3E00 + 0x4D*2), &u8Data);//DVBS2OPPRO_ISCR_CAL_DONE (_REG_DVBS2OPPRO(0x4D)+0)
2640 u8Data &= 0x01;
2641 // u32Time_end =msAPI_Timer_GetTime0();
2642 MsOS_DelayTask(1);
2643 time_counter = time_counter +1;
2644 }while( (u8Data!=0x01) && ( (time_counter )< 50) );
2645
2646 //read pkt interval
2647 MDrv_SYS_DMD_VD_MBX_ReadReg((0x3E00 + 0x70*2), &u8Data);
2648 *u32temp = u8Data;
2649 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x70*2+1), &u8Data);
2650 *u32temp |= (MS_U32)u8Data<<8;
2651 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x71*2), &u8Data);
2652 *u32temp |= (MS_U32)u8Data<<16;
2653 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x71*2+1), &u8Data);
2654 *u32temp |= (MS_U32)u8Data<<24;
2655
2656 pkt_interval = (MS_FLOAT) u32temp / 1024.0;
2657 if(sDMD_DVBS_Info.bSerialTS)//serial mode
2658 {
2659 *fTSDivNum=288000.0 / (188*8*u32SymbolRate/pkt_interval) - ts_div_num_offset;
2660 *fTSDivNum = (*fTSDivNum-1)/2;
2661 }
2662 else
2663 {
2664 *fTSDivNum=288000.0 / (188*u32SymbolRate/pkt_interval) - ts_div_num_offset;
2665 *fTSDivNum = (*fTSDivNum-1)/2;
2666 }
2667
2668 }
2669 else
2670 {
2671 // *fTSDivNum =0x0A;
2672 }
2673
2674 if(*fTSDivNum>255)
2675 *fTSDivNum=255;
2676 if(*fTSDivNum<1)
2677 *fTSDivNum=1;
2678 */
2679 #if 0
2680 //printf("INTERN_DVBS_GetTsDivNum Pilot E_DMD_S2_MB_DMDTOP_DBG_9=%d\n", u8Data);
2681 /*if(u8Data) // Pilot ON
2682 printf(">>>INTERN_DVBS_GetTsDivNum Pilot ON<<<\n");
2683 else //Pilot off
2684 printf(">>>INTERN_DVBS_GetTsDivNum Pilot off<<<\n");
2685 */
2686 if(_bSerialTS)
2687 {
2688 if(u8Data)//if pilot ON
2689 {
2690 if(modulation_order==2)
2691 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90+36*22)/u32SymbolRate)) - 3);
2692 else if(modulation_order==3)
2693 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90+36*15)/u32SymbolRate)) - 3);
2694 }
2695 else
2696 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90)/u32SymbolRate)) - 3);
2697 }
2698 else//Parallel mode
2699 {
2700 if(u8Data)
2701 {
2702 if(modulation_order==2)
2703 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0+36*22)/u32SymbolRate)/8.0) - 3);
2704 else if(modulation_order==3)
2705 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0+36*15)/u32SymbolRate)/8.0) - 3);
2706 }
2707 else
2708 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0)/u32SymbolRate)/8.0) - 3);
2709 }
2710 #endif
2711 }
2712 else //S
2713 {
2714 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE + 0x3A*2, &u8Data);
2715 //u8_gCodeRate = (u8Data & 0x70)>>4;
2716 //DVBS Code Rate
2717 //switch (u8_gCodeRate)
2718 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
2719 *code_rate_reg=u8Data;
2720 switch (u8Data)
2721 {
2722 case 0x00: //CR 1/2
2723 //_u8_DVBS2_CurrentCodeRate = 0;
2724 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=1_2\n"));
2725 /*
2726 if(sDMD_DVBS_Info.bSerialTS)
2727 *fTSDivNum = (288000.0/((1.0/2.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2728 else
2729 *fTSDivNum = (288000.0/((1.0/2.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2730
2731 *fTSDivNum = (*fTSDivNum-1)/2;
2732 if(*fTSDivNum>255)
2733 *fTSDivNum=255;
2734 if(*fTSDivNum<1)
2735 *fTSDivNum=1;
2736 */
2737 break;
2738 case 0x01: //CR 2/3
2739 //_u8_DVBS2_CurrentCodeRate = 1;
2740 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=2_3\n"));
2741 /*
2742 if(sDMD_DVBS_Info.bSerialTS)
2743 *fTSDivNum = (MS_U8)(288000.0/((2.0/3.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2744 else
2745 *fTSDivNum = (MS_U8)(288000.0/((2.0/3.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2746
2747 *fTSDivNum = (*fTSDivNum-1)/2;
2748 if(*fTSDivNum>255)
2749 *fTSDivNum=255;
2750 if(*fTSDivNum<1)
2751 *fTSDivNum=1;
2752 */
2753 break;
2754 case 0x02: //CR 3/4
2755 //_u8_DVBS2_CurrentCodeRate = 2;
2756 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=3_4\n"));
2757 /*
2758 if(sDMD_DVBS_Info.bSerialTS)
2759 *fTSDivNum = (288000.0/((3.0/4.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2760 else
2761 *fTSDivNum = (288000.0/((3.0/4.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2762 *fTSDivNum = (*fTSDivNum-1)/2;
2763 if(*fTSDivNum>255)
2764 *fTSDivNum=255;
2765 if(*fTSDivNum<1)
2766 *fTSDivNum=1;
2767 */
2768 break;
2769 case 0x03: //CR 5/6
2770 //_u8_DVBS2_CurrentCodeRate = 3;
2771 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=5_6\n"));
2772 /*
2773 if(sDMD_DVBS_Info.bSerialTS)
2774 *fTSDivNum = (288000.0/((5.0/6.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2775 else
2776 *fTSDivNum = (288000.0/((5.0/6.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2777
2778 *fTSDivNum = (*fTSDivNum-1)/2;
2779 if(*fTSDivNum>255)
2780 *fTSDivNum=255;
2781 if(*fTSDivNum<1)
2782 *fTSDivNum=1;
2783 */
2784 break;
2785 case 0x04: //CR 7/8
2786 //_u8_DVBS2_CurrentCodeRate = 4;
2787 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=7_8\n"));
2788 /*
2789 if(sDMD_DVBS_Info.bSerialTS)
2790 *fTSDivNum =(288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2791 else
2792 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2793
2794 *fTSDivNum = (*fTSDivNum-1)/2;
2795 if(*fTSDivNum>255)
2796 *fTSDivNum=255;
2797 if(*fTSDivNum<1)
2798 *fTSDivNum=1;
2799 */
2800 break;
2801 default:
2802 //_u8_DVBS2_CurrentCodeRate = 4;
2803 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate= default 7_8\n"));
2804 /*
2805 if(sDMD_DVBS_Info.bSerialTS)
2806 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2807 else
2808 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2809
2810 *fTSDivNum = (*fTSDivNum-1)/2;
2811 if(*fTSDivNum>255)
2812 *fTSDivNum=255;
2813 if(*fTSDivNum<1)
2814 *fTSDivNum=1;
2815 */
2816 break;
2817 }
2818 } //printf("INTERN_DVBS_GetTsDivNum u8TSClk = 0x%x\n", *u8TSDivNum);
2819 return status;
2820 }
2821
INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK_TYPE eType,MS_U16 fCurrRFPowerDbm,MS_U16 fNoChannelRFPowerDbm,MS_U32 u32TimeInterval)2822 MS_BOOL INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK_TYPE eType, MS_U16 fCurrRFPowerDbm, MS_U16 fNoChannelRFPowerDbm, MS_U32 u32TimeInterval)
2823 {
2824 MS_U8 u8Data =0; //MS_U8 u8Data2 =0;
2825 MS_U8 bRet = TRUE;
2826
2827 MS_U8 IS_ID = 0;
2828 MS_U8 IS_ID_Table[32];
2829
2830 switch( eType )
2831 {
2832 case DMD_DVBS_GETLOCK:
2833 #if (INTERN_DVBS_INTERNAL_DEBUG)
2834 INTERN_DVBS_info();
2835 #endif
2836 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_WR_DBG_90), &u8Data);
2837 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_GetLock manual tune=%d<<<\n", u8Data));
2838 if ((u8Data&0x02)==0x00)//manual mode
2839 {
2840 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);
2841 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_GetLock MailBox state=%d<<<\n", u8Data));
2842
2843 //ULOGD("DEMOD",">>>INTERN_DVBS_GetLock MailBox state=%d<<<\n", u8Data);
2844
2845 if((u8Data == 15) || (u8Data == 16))
2846 {
2847 if (u8Data==15)
2848 {
2849 _bDemodType = FALSE; //S
2850 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Demod DVBS Lock<<<\n"));
2851 }
2852 else if(u8Data==16)
2853 {
2854 _bDemodType = TRUE; //S2
2855 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Demod DVBS2 Lock<<<\n"));
2856
2857 if( u8VCM_Enabled_Opt == VCM_MODE && INTERN_DVBS2_VCM_CHECK() )
2858 {
2859 INTERN_DVBS2_Get_IS_ID_INFO(&IS_ID, IS_ID_Table);
2860 INTERN_DVBS2_Set_Default_IS_ID(&IS_ID, IS_ID_Table);
2861
2862 ULOGD("DEMOD",">>>INTERN_DVBS_Demod VCM Default IS ID = %d<<<\n", IS_ID);
2863 }
2864 }
2865 if(g_dvbs_lock == 0)
2866 {
2867 g_dvbs_lock = 1;
2868 }
2869
2870 if(u8DemodLockFlag==0)
2871 {
2872 u8DemodLockFlag=1;
2873
2874 // caculate TS clock divider number
2875 /*
2876 INTERN_DVBS_GetTsDivNum(&fTSDivNum); //ts_div_num
2877 u8Data = (MS_U8)fTSDivNum;
2878 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_GetLock TsClkDivNum = 0x%x<<<\n", u8Data));
2879
2880 if (u8Data > 0x1F)
2881 u8Data=0x1F;
2882 //if (u8Data < 0x05) u8Data=0x05;
2883 HAL_DMD_RIU_WriteByte(0x103300, u8Data);
2884
2885 //Ts Output Enable
2886 HAL_DMD_RIU_WriteByte(0x101eaa,0x10);
2887 */
2888 }
2889 DBG_INTERN_DVBS(ULOGD("DEMOD","@INTERN_DVBS_Demod Lock+++\n"));
2890 bRet = TRUE;
2891 }
2892 else
2893 {
2894 if(g_dvbs_lock == 1)
2895 {
2896 g_dvbs_lock = 0;
2897 u8DemodLockFlag=0;
2898 }
2899 DBG_INTERN_DVBS(ULOGD("DEMOD","@INTERN_DVBS_Demod UnLock---\n"));
2900 bRet = FALSE;
2901 }
2902
2903 if(_bSerialTS==1)
2904 {
2905 if (bRet==FALSE)
2906 {
2907 _bTSDataSwap=FALSE;
2908 }
2909 else
2910 {
2911 if (_bTSDataSwap==FALSE)
2912 {
2913 _bTSDataSwap=TRUE;
2914 MDrv_SYS_DMD_VD_MBX_ReadReg( (DVBTM_REG_BASE + 0x20*2), &u8Data);//DVBTM_REG_BASE
2915 u8Data^=0x20;//h0020 h0020 5 5 reg_ts_data_reverse
2916 MDrv_SYS_DMD_VD_MBX_WriteReg( (DVBTM_REG_BASE + 0x20*2), u8Data);
2917 }
2918 }
2919 }
2920 }
2921 else
2922 {
2923 bRet = TRUE;
2924 }
2925 break;
2926
2927 default:
2928 bRet = FALSE;
2929 }
2930 return bRet;
2931 }
2932
INTERN_DVBS2_Set_IS_ID(MS_U8 u8IS_ID)2933 MS_BOOL INTERN_DVBS2_Set_IS_ID(MS_U8 u8IS_ID)
2934 {
2935 MS_U8 VCM_OPT = 0;
2936 MS_U32 current_time = 0;
2937 MS_BOOL status = TRUE;
2938
2939 // assign IS-ID
2940 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_IS_ID, u8IS_ID);
2941
2942 // wait for VCM_OPT == 1 or time out
2943 current_time = MsOS_GetSystemTime();
2944 do
2945 {
2946 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_VCM_OPT, &VCM_OPT);
2947 }
2948 while(VCM_OPT != 1 && (MsOS_GetSystemTime() - current_time) < 100);
2949
2950 return status;
2951 }
2952
INTERN_DVBS2_Set_Default_IS_ID(MS_U8 * u8IS_ID,MS_U8 * u8IS_ID_table)2953 MS_BOOL INTERN_DVBS2_Set_Default_IS_ID(MS_U8 *u8IS_ID, MS_U8 *u8IS_ID_table)
2954 {
2955 MS_U8 VCM_OPT = 0;
2956 MS_U32 current_time = 0;
2957 MS_BOOL status = TRUE;
2958
2959 MS_U8 Default_IS_ID = 0;
2960 MS_U8 iter;
2961 MS_U8 temp, convert_counter;
2962
2963 // Find the smallest IS_ID in the table
2964
2965 for(iter = 0; iter < 0x0F;++iter)
2966 {
2967 // low byte
2968 temp = u8IS_ID_table[2*iter];
2969
2970 if( temp != 0)
2971 {
2972 for(convert_counter = 0; convert_counter < 8;++convert_counter)
2973 {
2974 if( temp > ( (temp >> 1) * 2) )
2975 break;
2976 else
2977 temp = temp >> 1;
2978 }
2979
2980 Default_IS_ID = iter*16 + convert_counter;
2981 }
2982
2983 // high byte
2984 temp = u8IS_ID_table[2*iter + 1];
2985
2986 if( temp != 0)
2987 {
2988 for(convert_counter = 0; convert_counter < 8;++convert_counter)
2989 {
2990 if( temp > ( (temp >> 1) * 2) )
2991 break;
2992 else
2993 temp = temp >> 1;
2994 }
2995
2996 Default_IS_ID = iter*16 + 8 + convert_counter;
2997 }
2998 }
2999
3000 // assign IS-ID
3001 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_IS_ID, Default_IS_ID);
3002
3003 *u8IS_ID = Default_IS_ID;
3004
3005 // wait for VCM_OPT == 1 or time out
3006 current_time = MsOS_GetSystemTime();
3007 do
3008 {
3009 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_VCM_OPT, &VCM_OPT);
3010 }
3011 while(VCM_OPT != 1 && (MsOS_GetSystemTime() - current_time) < 100);
3012
3013 return status;
3014 }
3015
3016
INTERN_DVBS2_Get_IS_ID_INFO(MS_U8 * u8IS_ID,MS_U8 * u8IS_ID_table)3017 MS_BOOL INTERN_DVBS2_Get_IS_ID_INFO(MS_U8 *u8IS_ID, MS_U8 *u8IS_ID_table)
3018 {
3019 MS_BOOL status = TRUE;
3020 MS_U8 iter;
3021
3022 // get IS-ID
3023 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_IS_ID, u8IS_ID);
3024 // get IS-ID table
3025 for(iter = 0; iter <= 0x0F;++iter)
3026 {
3027 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_IS_ID_TABLE + 2*iter, &u8IS_ID_table[2*iter]);
3028 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_IS_ID_TABLE + 2*iter + 1, &u8IS_ID_table[2*iter + 1]);
3029 }
3030
3031 return status;
3032 }
3033
INTERN_DVBS2_VCM_INIT(DMD_DVBS_VCM_OPT u8VCM_OPT,MS_U8 u8IS_ID,MS_U32 u32DMD_DVBS2_DJB_START_ADDR)3034 MS_BOOL INTERN_DVBS2_VCM_INIT(DMD_DVBS_VCM_OPT u8VCM_OPT, MS_U8 u8IS_ID, MS_U32 u32DMD_DVBS2_DJB_START_ADDR)
3035 {
3036 MS_BOOL status = TRUE;
3037
3038 // Enabled VCM mode
3039 u8VCM_Enabled_Opt = u8VCM_OPT;
3040
3041 if(u8VCM_OPT != 0)
3042 {
3043 // assign IS-ID
3044 u8Default_VCM_IS_ID = u8IS_ID;
3045 // assign DJB address
3046 u32DVBS2_DJB_START_ADDR = u32DMD_DVBS2_DJB_START_ADDR;
3047 }
3048
3049 DBG_INTERN_DVBS(ULOGD("DEMOD","-->VCM_OPT<--%d\n", u8VCM_OPT));
3050 DBG_INTERN_DVBS(ULOGD("DEMOD","-->VCM_ISID<--%d\n", u8IS_ID));
3051 DBG_INTERN_DVBS(ULOGD("DEMOD","-->VCM_DJB<--%d\n", u32DMD_DVBS2_DJB_START_ADDR));
3052
3053 return status;
3054 }
3055
INTERN_DVBS2_VCM_CHECK(void)3056 MS_BOOL INTERN_DVBS2_VCM_CHECK(void)
3057 {
3058 MS_U8 VCM_Check = 0;
3059 MS_BOOL status = TRUE;
3060
3061 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2OPPRO_SIS_EN, &VCM_Check);
3062
3063 if( (VCM_Check & 0x04) == 0x00) // VCM signal
3064 status = TRUE;
3065 else // CCM signal
3066 status = FALSE;
3067
3068 return status;
3069 }
3070
INTERN_DVBS2_VCM_ENABLED(MS_U8 u8VCM_ENABLED)3071 MS_BOOL INTERN_DVBS2_VCM_ENABLED(MS_U8 u8VCM_ENABLED)
3072 {
3073 MS_BOOL status = TRUE;
3074 // Enabled VCM mode
3075 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_VCM_OPT, u8VCM_ENABLED);
3076
3077 return status;
3078 }
3079
INTERN_DVBS2_VCM_MODE(DMD_DVBS_VCM_OPT u8VCM_OPT)3080 MS_BOOL INTERN_DVBS2_VCM_MODE(DMD_DVBS_VCM_OPT u8VCM_OPT)
3081 {
3082 MS_BOOL status = TRUE;
3083 u8VCM_Enabled_Opt = u8VCM_OPT;
3084 // Change VCM mode
3085 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_VCM_OPT, u8VCM_Enabled_Opt);
3086
3087 return status;
3088 }
3089
INTERN_DVBS_GetTunrSignalLevel_PWR(MS_U16 * u16Data)3090 MS_BOOL INTERN_DVBS_GetTunrSignalLevel_PWR(MS_U16 *u16Data)// Need check debug out table
3091 {
3092 MS_BOOL status=TRUE;
3093 MS_U8 u8Data =0;
3094 //MS_U8 u8Index =0;
3095 //float fCableLess = 0.0;
3096 /*
3097 if (FALSE == INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0) )//Demod unlock
3098 {
3099 fCableLess = 0;
3100 }
3101 */
3102 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x11*2, &u8Data);//FRONTEND_AGC_DEBUG_SEL
3103 u8Data=(u8Data&0xF0)|0x03;
3104 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x11*2, u8Data);
3105
3106 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x02, &u8Data);//FRONTEND_LATCH
3107 u8Data|=0x80;
3108 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x02, u8Data);
3109
3110 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x12*2+1, &u8Data);//FRONTEND_AGC_DEBUG_OUT_R1
3111 *u16Data=u8Data;
3112 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x12*2, &u8Data);//FRONTEND_AGC_DEBUG_OUT_R0
3113 *u16Data=(*u16Data<<8)|u8Data;
3114 //printf("===========================Tuner 65535-u16Data = %d\n", (65535-u16Data));
3115 //MsOS_DelayTask(400);
3116
3117 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x02, &u8Data);//FRONTEND_LOAD0
3118 u8Data&=~(0x80);
3119 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x02, u8Data);
3120 /*
3121 if (status==FALSE)
3122 {
3123 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS GetSignalStrength fail!!! \n "));
3124 fCableLess = 0;
3125 }
3126 */
3127 // printf("#### INTERN_DVBS_GetTunrSignalLevel_PWR u16Data = %d\n", (int)u16Data);
3128 /*
3129 for (u8Index=0; u8Index < (sizeof(_u16SignalLevel)/sizeof(_u16SignalLevel[0])); u8Index++)
3130 {
3131 if ((65535 - u16Data) <= _u16SignalLevel[u8Index][0])
3132 {
3133 if (u8Index >=1)
3134 {
3135 fCableLess = (float)(_u16SignalLevel[u8Index][1])+((float)(_u16SignalLevel[u8Index][0] - (65535 - u16Data)) / (float)(_u16SignalLevel[u8Index][0] - _u16SignalLevel[u8Index-1][0]))*(float)(_u16SignalLevel[u8Index-1][1] - _u16SignalLevel[u8Index][1]);
3136 }
3137 else
3138 {
3139 fCableLess = _u16SignalLevel[u8Index][1];
3140 }
3141 }
3142 }
3143 //---------------------------------------------------
3144 if (fCableLess >= 350)
3145 fCableLess = fCableLess - 35;
3146 else if ((fCableLess < 350) && (fCableLess >= 250))
3147 fCableLess = fCableLess - 25;
3148 else
3149 fCableLess = fCableLess - 5;
3150
3151 if (fCableLess < 0)
3152 fCableLess = 0;
3153 if (fCableLess > 920)
3154 fCableLess = 920;
3155
3156 fCableLess = (-1.0)*(fCableLess/10.0);
3157
3158 //printf("===========================fCableLess2 = %.2f\n",fCableLess);
3159
3160 DBG_INTERN_DVBS(printf("INTERN_DVBS GetSignalStrength %f\n", fCableLess));
3161 */
3162 return status;
3163 }
3164
3165 /****************************************************************************
3166 Subject: To get the Post viterbi BER
3167 Function: INTERN_DVBS_GetPostViterbiBer
3168 Parmeter: Quility
3169 Return: E_RESULT_SUCCESS
3170 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBC_VIT_STATUS_NG
3171 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
3172 We will not read the Period, and have the "/256/8"
3173 *****************************************************************************/
3174
INTERN_DVBS_GetPostViterbiBer(MS_U32 * BitErr,MS_U16 * BitErrPeriod)3175 MS_BOOL INTERN_DVBS_GetPostViterbiBer(MS_U32 *BitErr, MS_U16 *BitErrPeriod)//POST BER //V
3176 {
3177 MS_BOOL status = true;
3178 MS_U8 reg = 0, reg_frz = 0;
3179 MS_U32 current_time = 0;
3180 //MS_U16 u16BitErrPeriod;
3181 //MS_U32 u32BitErr;
3182
3183 /////////// Post-Viterbi BER /////////////After Viterbi
3184
3185 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, ®);
3186
3187 if(!reg) // DVBS2
3188 {
3189 // wait buffer is full
3190 current_time = MsOS_GetSystemTime();
3191
3192 do
3193 {
3194 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_LDPC_BER_COUNT3, ®);
3195 }while(reg == 0xFF && (MsOS_GetSystemTime() - current_time) < 1000);
3196
3197 // freeze outer
3198 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_OUTER_FREEZE, ®);
3199 reg |= 0x01;
3200 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_OUTER_FREEZE, reg);
3201
3202 // Get LDPC error window
3203
3204 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_LDPC_ERROR_WINDOW1, ®);
3205 *BitErrPeriod = reg;
3206 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_LDPC_ERROR_WINDOW0, ®);
3207 *BitErrPeriod = (*BitErrPeriod << 8) | reg;
3208
3209 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_LDPC_BER_COUNT3, ®);
3210 *BitErr = reg;
3211 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_LDPC_BER_COUNT2, ®);
3212 *BitErr = (*BitErr << 8) | reg;
3213 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_LDPC_BER_COUNT1, ®);
3214 *BitErr = (*BitErr << 8) | reg;
3215 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_LDPC_BER_COUNT0, ®);
3216 *BitErr = (*BitErr << 8) | reg;
3217
3218 // unfreeze outer
3219 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_OUTER_FREEZE, ®);
3220 reg &= ~(0x01);
3221 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_OUTER_FREEZE, reg);
3222
3223 //fber = (float)u32BitErr/(u16BitErrPeriod*64800);
3224 //*p_postBer = fber;
3225 }
3226 else //DVBS
3227 {
3228 // freeze ,DVBSRS_BACKEND_BIT_ERR_NUM_FREEZE
3229 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x08*2, ®_frz);//h0001 h0001 8 8 reg_ber_en
3230 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x08*2, reg_frz|0x08);
3231
3232 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0 ,DVBSFEC_BIT_ERR_SBLPRD_7_0
3233 // 0x47 [15:8] reg_bit_err_sblprd_15_8
3234 //KRIS register table
3235 //h0018 h0018 7 0 reg_bit_err_sblprd_7_0
3236 //h0018 h0018 15 8 reg_bit_err_sblprd_15_8
3237 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x18*2+1, ®);
3238 *BitErrPeriod = reg;
3239
3240 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x18*2, ®);
3241 *BitErrPeriod = (*BitErrPeriod << 8)|reg;
3242
3243
3244 //h001d h001d 7 0 reg_bit_err_num_7_0
3245 //h001d h001d 15 8 reg_bit_err_num_15_8
3246 //h001e h001e 7 0 reg_bit_err_num_23_16
3247 //h001e h001e 15 8 reg_bit_err_num_31_24
3248
3249 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1E*2+1, ®);
3250 *BitErr = reg;
3251 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1E*2, ®);
3252 *BitErr = (*BitErr << 8)|reg;
3253 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1D*2+1, ®);
3254 *BitErr = (*BitErr << 8)|reg;
3255 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1D*2, ®);
3256 *BitErr = (*BitErr << 8)|reg;
3257
3258 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
3259 reg_frz=reg_frz&(~0x08);
3260 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x08*2, reg_frz);
3261 }
3262
3263 /*
3264 if (BitErrPeriod == 0 ) //PRD
3265 BitErrPeriod = 1;
3266
3267 if (BitErr <= 0 )
3268 *postber = 0.5f / ((float)BitErrPeriod*128*188*8);
3269 else
3270 *postber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
3271
3272 if (*postber <= 0.0f)
3273 *postber = 1.0e-10f;
3274
3275 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS PostVitBER = %8.3e \n", *postber));
3276 */
3277
3278 return status;
3279 }
3280
3281
INTERN_DVBS_GetPreViterbiBer(float * preber)3282 MS_BOOL INTERN_DVBS_GetPreViterbiBer(float *preber)//PER BER // not yet
3283 {
3284 MS_BOOL status = true;
3285 //MS_U8 reg = 0, reg_frz = 0;
3286 //MS_U16 BitErrPeriod;
3287 //MS_U32 BitErr;
3288
3289 #if 0
3290 /////////// Pre-Viterbi BER /////////////Before Viterbi
3291
3292 // freeze ,DVBSRS_BACKEND_BIT_ERR_NUM_FREEZE
3293 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x10, ®_frz);
3294 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSTFEC_REG_BASE+0x10, reg_frz|0x08);
3295
3296 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0 ,DVBSFEC_BIT_ERR_SBLPRD_7_0
3297 // 0x47 [15:8] reg_bit_err_sblprd_15_8
3298 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x19, ®);
3299 BitErrPeriod = reg;
3300
3301 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x18, ®);
3302 BitErrPeriod = (BitErrPeriod << 8)|reg;
3303
3304 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x17, ®);
3305 BitErrPeriod = (BitErrPeriod << 8)|reg;
3306
3307 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x16, ®);
3308 BitErrPeriod = (BitErrPeriod << 8)|reg;
3309 BitErrPeriod = (BitErrPeriod & 0x3FFF);
3310
3311 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
3312 // 0x6b [15:8] reg_bit_err_num_15_8
3313 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
3314 // 0x6d [15:8] reg_bit_err_num_31_24
3315 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x1F, ®);
3316 BitErr = reg;
3317
3318 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x1E, ®);
3319 BitErr = (BitErr << 8)|reg;
3320
3321 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
3322 reg_frz=reg_frz&(~0x08);
3323 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x10, reg_frz);
3324
3325 if (BitErrPeriod ==0 )//protect 0
3326 BitErrPeriod=1;
3327 if (BitErr <=0 )
3328 *perber=0.5f / (float)BitErrPeriod / 256;
3329 else
3330 *perber=(float)BitErr / (float)BitErrPeriod / 256;
3331
3332 if (*perber <= 0.0f)
3333 *perber = 1.0e-10f;
3334
3335 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS PerVitBER = %8.3e \n", *perber));
3336 #endif
3337
3338 return status;
3339 }
3340
3341 /****************************************************************************
3342 Subject: To get the Packet error
3343 Function: INTERN_DVBS_GetPacketErr
3344 Parmeter: pktErr
3345 Return: E_RESULT_SUCCESS
3346 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
3347 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
3348 We will not read the Period, and have the "/256/8"
3349 *****************************************************************************/
INTERN_DVBS_GetPacketErr(MS_U16 * pktErr)3350 MS_BOOL INTERN_DVBS_GetPacketErr(MS_U16 *pktErr)//V
3351 {
3352 MS_BOOL status = true;
3353 MS_U8 u8Data = 0;
3354 MS_U16 u16PktErr = 0;
3355
3356 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);
3357 if(!u8Data) //DVB-S2
3358 {
3359 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x02*2, &u8Data);//DVBS2FEC_OUTER_FREEZE (_REG_DVBS2FEC(0x02)+0) //[0]
3360 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE+0x02*2, u8Data|0x01);
3361
3362 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x2B*2+1, &u8Data);//DVBS2FEC_BCH_EFLAG2_SUM1 (_REG_DVBS2FEC(0x2B)+1)
3363 u16PktErr = u8Data;
3364 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x2B*2, &u8Data);
3365 u16PktErr = (u16PktErr << 8)|u8Data;
3366
3367 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x02*2, &u8Data);
3368 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE+0x02*2, u8Data&(~0x01));
3369 }
3370 else
3371 {
3372 //DVB-S
3373 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x19*2, &u8Data); //0x19 [7] reg_bit_err_num_freeze
3374 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x19*2, u8Data|0x80);
3375
3376 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1F*2+1, &u8Data);// DVBSFEC_UNCRT_PKT_NUM_15_8 (_REG_DVBSFEC(0x1F)+1)
3377 u16PktErr = u8Data;
3378 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1F*2, &u8Data);
3379 u16PktErr = (u16PktErr << 8)|u8Data;
3380
3381 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x19*2, &u8Data); //0x19 [7] reg_bit_err_num_freeze
3382 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x19*2, u8Data&(~0x80));
3383 }
3384 *pktErr = u16PktErr;
3385
3386 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS PktErr = %d \n", (int)u16PktErr));
3387
3388 return status;
3389 }
3390
3391 /****************************************************************************
3392 Subject: Read the signal to noise ratio (SNR)
3393 Function: INTERN_DVBS_GetSNR
3394 Parmeter: None
3395 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
3396 Remark:
3397 *****************************************************************************/
3398
INTERN_DVBS_GetSNR(MS_U32 * u32NDA_SNR_A,MS_U32 * u32NDA_SNR_AB)3399 MS_BOOL INTERN_DVBS_GetSNR(MS_U32 *u32NDA_SNR_A, MS_U32 *u32NDA_SNR_AB)//V
3400 {
3401 MS_BOOL status= TRUE;
3402 MS_U8 u8Data =0;//, reg_frz =0;
3403 //NDA SNR
3404 // MS_U32 u32NDA_SNR_A =0;
3405 //MS_U32 u32NDA_SNR_AB =0;
3406 //NDA SNR
3407 //float NDA_SNR_A =0.0;
3408 //float NDA_SNR_AB =0.0;
3409 //float NDA_SNR =0.0;
3410 //double NDA_SNR_LINEAR=0.0;
3411 //float snr_poly =0.0;
3412 //float Fixed_SNR =0.0;
3413 /*
3414 if (INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0)== FALSE)
3415 {
3416 return 0;
3417 }
3418 */
3419 // freeze
3420 #if 0
3421 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE+0x04*2, ®_frz);
3422 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_INNER_REG_BASE+0x04*2, reg_frz|0x10);//INNE_LATCH bit[4]
3423
3424 //NDA SNR_A
3425 // read Linear_SNR
3426 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x47*2, &u8Data);
3427 *u32NDA_SNR_A=(u8Data&0x03);
3428 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x46*2 + 1, &u8Data);
3429 *u32NDA_SNR_A=(*u32NDA_SNR_A<<8)|u8Data;
3430 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x46*2, &u8Data);
3431 *u32NDA_SNR_A=(*u32NDA_SNR_A<<8)|u8Data;
3432 //NDA SNR_AB
3433 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x49*2+1, &u8Data);
3434 *u32NDA_SNR_AB=(u8Data&0x3F);
3435 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x49*2, &u8Data);
3436 *u32NDA_SNR_AB = (*u32NDA_SNR_AB<<8)|u8Data;
3437 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x48*2 + 1, &u8Data);
3438 *u32NDA_SNR_AB=(*u32NDA_SNR_AB<<8)|u8Data;
3439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x48*2, &u8Data);
3440 *u32NDA_SNR_AB=(*u32NDA_SNR_AB<<8)|u8Data;
3441
3442 //UN_freeze
3443 reg_frz=reg_frz&(~0x10);
3444 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_INNER_REG_BASE+0x08, reg_frz);
3445
3446 if (status== FALSE)
3447 {
3448 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetSNR Fail! \n"));
3449 return 0;
3450 }
3451
3452 //NDA SNR
3453 //NDA_SNR_A=(float)u32NDA_SNR_A/65536;
3454 //NDA_SNR_AB=(float)u32NDA_SNR_AB/4194304;
3455 //
3456 //since support 16,32APSK we need to add judgement
3457 /*
3458 if(modulation_order==4)
3459 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB/(2-1.252295758529242));//for 16APSK CR2/3
3460 else if(modulation_order==5)//(2-1.41333232789)
3461 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB/(2-1.41333232789));//for 32APSK CR3/4
3462 else
3463 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB);
3464
3465 NDA_SNR_LINEAR =(1/((NDA_SNR_A/NDA_SNR_AB)-1)) ;
3466
3467 if(NDA_SNR_LINEAR<=0)
3468 NDA_SNR=1.0;
3469 else
3470 NDA_SNR=10*log10(NDA_SNR_LINEAR);
3471
3472 //printf("[DVBS]: NDA_SNR ================================: %.1f\n", NDA_SNR);
3473 _f_DVBS_CurrentSNR = NDA_SNR;
3474 */
3475 /*
3476 //[DVBS/S2, QPSK/8PSK, 1/2~9/10 the same CN]
3477 snr_poly = 0.0; //use Polynomial curve fitting to fix SNR
3478 snr_poly = 0.005261367463671*pow(NDA_SNR, 3)-0.116517828301214*pow(NDA_SNR, 2)+0.744836970505452*pow(NDA_SNR, 1)-0.86727609780167;
3479 Fixed_SNR = NDA_SNR + snr_poly;
3480 //printf("[DVBS]: NDA_SNR + snr_poly =====================: %.1f\n", Fixed_SNR);
3481
3482 if (Fixed_SNR < 17.0)
3483 Fixed_SNR = Fixed_SNR;
3484 else if ((Fixed_SNR < 20.0) && (Fixed_SNR >= 17.0))
3485 Fixed_SNR = Fixed_SNR - 0.8;
3486 else if ((Fixed_SNR < 22.5) && (Fixed_SNR >= 20.0))
3487 Fixed_SNR = Fixed_SNR - 2.0;
3488 else if ((Fixed_SNR < 27.0) && (Fixed_SNR >= 22.5))
3489 Fixed_SNR = Fixed_SNR - 3.0;
3490 else if ((Fixed_SNR < 29.0) && (Fixed_SNR >= 27.0))
3491 Fixed_SNR = Fixed_SNR - 3.5;
3492 else if (Fixed_SNR >= 29.0)
3493 Fixed_SNR = Fixed_SNR - 3.0;
3494
3495 if (Fixed_SNR < 1.0)
3496 Fixed_SNR = 1.0;
3497 if (Fixed_SNR > 30.0)
3498 Fixed_SNR = 30.0;
3499 */
3500 //*f_snr = NDA_SNR;
3501 //printf("[DVBS]: NDA_SNR=============================: %.1f\n", NDA_SNR);
3502 #endif
3503
3504 // freeze FW write SNR
3505 MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_INFO_07, &u8Data);
3506 u8Data |= 0x01;
3507 MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_INFO_07, u8Data);
3508
3509 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_07, &u8Data);
3510 *u32NDA_SNR_A = u8Data;
3511
3512 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_08, &u8Data);
3513 *u32NDA_SNR_AB = u8Data;
3514
3515 // unfreeze FW write SNR
3516 MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_INFO_07, &u8Data);
3517 u8Data &= (~0x01);
3518 MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_INFO_07, u8Data);
3519
3520 return status;
3521 }
3522
INTERN_DVBS_GetIFAGC(MS_U8 * ifagc_reg,MS_U8 * ifagc_reg_lsb,MS_U16 * ifagc_err)3523 MS_BOOL INTERN_DVBS_GetIFAGC(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err)
3524 {
3525 MS_BOOL status = true;
3526
3527 status = HAL_DMD_IFAGC_RegRead(ifagc_reg, ifagc_reg_lsb, ifagc_err);
3528
3529 return status;
3530 }
3531
3532 //SSI
INTERN_DVBS_GetSignalStrength(MS_U16 fRFPowerDbm,DMD_DVBS_DEMOD_TYPE * pDemodType,MS_U8 * u8_DVBS2_CurrentCodeRateLocal,MS_U8 * u8_DVBS2_CurrentConstellationLocal)3533 MS_BOOL INTERN_DVBS_GetSignalStrength(MS_U16 fRFPowerDbm, DMD_DVBS_DEMOD_TYPE *pDemodType, MS_U8 *u8_DVBS2_CurrentCodeRateLocal, MS_U8 *u8_DVBS2_CurrentConstellationLocal)
3534 {
3535 //-1.2~-92.2 dBm
3536 MS_BOOL status = true;
3537 MS_U8 u8Data =0;
3538 //MS_U8 _u8_DVBS2_CurrentCodeRateLocal = 0;
3539 //float ch_power_db=0.0f, ch_power_db_rel=0.0f;
3540 //MS_U8 u8Data2 = 0;
3541 //MS_U8 _u8_DVBS2_CurrentConstellationLocal = 0;
3542 //DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3543
3544 //DBG_INTERN_DVBS_TIME(printf("INTERN_DVBS_GetSignalStrength, t=%ld, RF level=%f, Table=%lx\n",MsOS_GetSystemTime(), fRFPowerDbm, (MS_U32)(sDMD_DVBS_InitData->pTuner_RfagcSsi)));
3545
3546 // if (INTERN_DVBC_Lock(COFDM_TPS_LOCK))
3547 // if (INTERN_DVBC_Lock(COFDM_AGC_LOCK))
3548 // Actually, it's more reasonable, that signal level depended on cable input power level
3549 // thougth the signal isn't dvb-t signal.
3550 //
3551 // use pointer of IFAGC table to identify
3552 // case 1: RFAGC from SAR, IFAGC controlled by demod
3553 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
3554 //status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
3555 // sDMD_DVBS_InitData->pTuner_RfagcSsi, sDMD_DVBS_InitData->u16Tuner_RfagcSsi_Size,
3556 // sDMD_DVBS_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBS_InitData->u16Tuner_IfagcSsi_HiRef_Size,
3557 // sDMD_DVBS_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBS_InitData->u16Tuner_IfagcSsi_LoRef_Size,
3558 // sDMD_DVBS_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBS_InitData->u16Tuner_IfagcErr_HiRef_Size,
3559 // sDMD_DVBS_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBS_InitData->u16Tuner_IfagcErr_LoRef_Size);
3560 //ch_power_db = INTERN_DVBS_GetTunrSignalLevel_PWR();
3561 //printf("@@@@@@@@@ ch_power_db = %f \n", ch_power_db);
3562
3563
3564
3565
3566 status &= INTERN_DVBS_GetCurrentDemodType(pDemodType);
3567
3568 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
3569 *u8_DVBS2_CurrentCodeRateLocal = u8Data;
3570
3571
3572 if((MS_U8)*pDemodType == (MS_U8)DMD_SAT_DVBS) // DVBS
3573 {
3574 /*
3575 float fDVBS_SSI_Pref[]=
3576 {
3577 //0, 1, 2, 3, 4
3578 -78.9, -77.15, -76.14, -75.19, -74.57,//QPSK
3579 };
3580 */
3581 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE + 0x84, &u8Data);
3582 //ch_power_db_rel = ch_power_db - fDVBS_SSI_Pref[_u8_DVBS2_CurrentCodeRateLocal];
3583 }
3584 else // DVBS2
3585 {
3586 /*
3587 float fDVBS2_SSI_Pref[][11]=
3588 {
3589 // 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
3590 //1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10
3591 {-85.17, -84.08, -83.15, -81.86, -80.63, -79.77, -78.84, -78.19, -77.69, -76.68, -76.46}, //QPSK
3592 { 0.0, 0.0, 0.0, 0.0, -77.36, -76.24, -74.95, 0.0, -73.52, -72.18, -71.84} //8PSK
3593 };
3594 */
3595 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MOD_TYPE, &u8Data);
3596 *u8_DVBS2_CurrentConstellationLocal = u8Data;
3597 }
3598 //ch_power_db_rel = ch_power_db - fDVBS2_SSI_Pref[_u8_DVBS2_CurrentConstellationLocal][_u8_DVBS2_CurrentCodeRateLocal];
3599
3600 /*
3601 if(ch_power_db_rel <= -15.0f)
3602 {
3603 *pu16SignalBar = 0;
3604 }
3605 else if (ch_power_db_rel <= 0.0f)
3606 {
3607 *pu16SignalBar = (MS_U16)(2.0f/3 * (ch_power_db_rel+15.0f));
3608 }
3609 else if (ch_power_db_rel <= 20.0f)
3610 {
3611 *pu16SignalBar = (MS_U16)(4.0f * ch_power_db_rel + 10.0f);
3612 }
3613 else if (ch_power_db_rel <= 35.0f)
3614 {
3615 *pu16SignalBar = (MS_U16)(2.0f/3 * (ch_power_db_rel-20.0f) + 90.0);
3616 }
3617 else
3618 {
3619 *pu16SignalBar = 100;
3620 }
3621 */
3622 //printf("SSI_CH_PWR(dB) = %f \n", ch_power_db_rel);
3623 //DBG_INTERN_DVBS(printf(">>>>>Signal Strength(SSI) = %d\n", (int)*pu16SignalBar));
3624
3625 return status;
3626 }
3627
3628 //SQI
3629 /****************************************************************************
3630 Subject: To get the DVT Signal quility
3631 Function: INTERN_DVBS_GetSignalQuality
3632 Parmeter: Quility
3633 Return: E_RESULT_SUCCESS
3634 E_RESULT_FAILURE
3635 Remark: Here we have 4 level range
3636 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
3637 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
3638 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
3639 <4>.4th Range => Quality <10
3640 *****************************************************************************/
3641 #if (0)
INTERN_DVBS_GetSignalQuality(MS_U16 * quality,const DMD_DVBS_InitData * sDMD_DVBS_InitData,MS_U8 u8SarValue,float fRFPowerDbm)3642 MS_BOOL INTERN_DVBS_GetSignalQuality(MS_U16 *quality, const DMD_DVBS_InitData *sDMD_DVBS_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
3643 {
3644
3645 float fber = 0.0;
3646 //float log_ber;
3647 MS_BOOL status = TRUE;
3648 float f_snr = 0.0, ber_sqi = 0.0, cn_rel = 0.0;
3649 //MS_U8 u8Data =0;
3650 DMD_DVBS_CODE_RATE_TYPE _u8_DVBS2_CurrentCodeRateLocal ;
3651 MS_U16 bchpkt_error,BCH_Eflag2_Window;
3652 //fRFPowerDbm = fRFPowerDbm;
3653 float snr_poly =0.0;
3654 float Fixed_SNR =0.0;
3655 double eFlag_PER=0.0;
3656
3657 if (TRUE == INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0))
3658 {
3659 if(_bDemodType) //S2
3660 {
3661
3662 INTERN_DVBS_GetSNR(&f_snr);
3663 snr_poly = 0.005261367463671*pow(f_snr, 3)-0.116517828301214*pow(f_snr, 2)+0.744836970505452*pow(f_snr, 1)-0.86727609780167;
3664 Fixed_SNR = f_snr + snr_poly;
3665
3666 if (Fixed_SNR < 17.0)
3667 Fixed_SNR = Fixed_SNR;
3668 else if ((Fixed_SNR < 20.0) && (Fixed_SNR >= 17.0))
3669 Fixed_SNR = Fixed_SNR - 0.8;
3670 else if ((Fixed_SNR < 22.5) && (Fixed_SNR >= 20.0))
3671 Fixed_SNR = Fixed_SNR - 2.0;
3672 else if ((Fixed_SNR < 27.0) && (Fixed_SNR >= 22.5))
3673 Fixed_SNR = Fixed_SNR - 3.0;
3674 else if ((Fixed_SNR < 29.0) && (Fixed_SNR >= 27.0))
3675 Fixed_SNR = Fixed_SNR - 3.5;
3676 else if (Fixed_SNR >= 29.0)
3677 Fixed_SNR = Fixed_SNR - 3.0;
3678
3679
3680 if (Fixed_SNR < 1.0)
3681 Fixed_SNR = 1.0;
3682 if (Fixed_SNR > 30.0)
3683 Fixed_SNR = 30.0;
3684
3685 //BCH EFLAG2_Window, window size 0x2000
3686 BCH_Eflag2_Window=0x2000;
3687 MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE + 0x25*2 + 1, (BCH_Eflag2_Window>>8));
3688 MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE + 0x25*2 , (BCH_Eflag2_Window&0xff));
3689 INTERN_DVBS_GetPacketErr(&bchpkt_error);
3690 eFlag_PER = (float)(bchpkt_error)/(float)(BCH_Eflag2_Window);
3691 if(eFlag_PER>0)
3692 fber = 0.089267531133002*pow(eFlag_PER, 2) + 0.019640560289510*eFlag_PER + 0.0000001;
3693 else
3694 fber = 0;
3695
3696 #ifdef MSOS_TYPE_LINUX
3697 //log_ber = ( - 1) *log10f(1 / fber);
3698 if (fber > 1.0E-1)
3699 ber_sqi = (log10f(1.0f/fber))*20.0f + 8.0f;
3700 else if(fber > 8.5E-7)
3701 ber_sqi = (log10f(1.0f/fber))*20.0f - 30.0f;
3702 else
3703 ber_sqi = 100.0;
3704 #else
3705 //log_ber = ( - 1) *Log10Approx(1 / fber);
3706 if (fber > 1.0E-1)
3707 ber_sqi = (Log10Approx(1.0f/fber))*20.0f + 8.0f;
3708 else if(fber > 8.5E-7)
3709 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 30.0f;
3710 else
3711 ber_sqi = 100.0;
3712
3713 #endif
3714
3715 *quality = Fixed_SNR/30*ber_sqi;
3716 DBG_INTERN_DVBS(printf(" Fixed_SNR %f\n",Fixed_SNR));
3717 DBG_INTERN_DVBS(printf(" BCH_Eflag2_Window %d\n",BCH_Eflag2_Window));
3718 DBG_INTERN_DVBS(printf(" eFlag_PER [%f]\n fber [%8.3e]\n ber_sqi [%f]\n",eFlag_PER,fber,ber_sqi));
3719 }
3720 else //S
3721 {
3722 if (INTERN_DVBS_GetPostViterbiBer(&fber) == FALSE)//ViterbiBer
3723 {
3724 DBG_INTERN_DVBS(printf("\nGetPostViterbiBer Fail!"));
3725 return FALSE;
3726 }
3727 _fPostBer=fber;
3728
3729
3730 if (status==FALSE)
3731 {
3732 DBG_INTERN_DVBS(printf("MSB131X_DTV_GetSignalQuality GetPostViterbiBer Fail!\n"));
3733 return 0;
3734 }
3735 float fDVBS_SQI_CNref[]=
3736 { //0, 1, 2, 3, 4
3737 4.2, 5.9, 6, 6.9, 7.5,//QPSK
3738 };
3739
3740 INTERN_DVBS_GetCurrentDemodCodeRate(&_u8_DVBS2_CurrentCodeRateLocal);
3741 #if 0
3742 #ifdef MSOS_TYPE_LINUX
3743 log_ber = ( - 1.0f) *log10f(1.0f / fber); //BY modify
3744 #else
3745 log_ber = ( - 1.0f) *Log10Approx(1.0f / fber); //BY modify
3746 #endif
3747 DBG_INTERN_DVBS(printf("\nLog(BER) = %f\n",log_ber));
3748 #endif
3749 if (fber > 2.5E-2)
3750 ber_sqi = 0.0;
3751 else if(fber > 8.5E-7)
3752 #ifdef MSOS_TYPE_LINUX
3753 ber_sqi = (log10f(1.0f/fber))*20.0f - 32.0f; //40.0f;
3754 #else
3755 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 32.0f;//40.0f;
3756 #endif
3757 else
3758 ber_sqi = 100.0;
3759
3760 status &= INTERN_DVBS_GetSNR(&f_snr);
3761 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS GetSNR = %d \n", (int)f_snr));
3762
3763 cn_rel = f_snr - fDVBS_SQI_CNref[_u8_DVBS2_CurrentCodeRateLocal];
3764
3765 DBG_INTERN_DVBS(printf(" fber = %f\n",fber));
3766 DBG_INTERN_DVBS(printf(" f_snr = %f\n",f_snr));
3767 DBG_INTERN_DVBS(printf(" cn_nordig_s1 = %f\n",fDVBS_SQI_CNref[_u8_DVBS2_CurrentCodeRateLocal]));
3768 DBG_INTERN_DVBS(printf(" cn_rel = %f\n",cn_rel));
3769 DBG_INTERN_DVBS(printf(" ber_sqi = %f\n",ber_sqi));
3770
3771 if (cn_rel < -7.0f)
3772 {
3773 *quality = 0;
3774 }
3775 else if (cn_rel < 3.0)
3776 {
3777 *quality = (MS_U16)(ber_sqi*((cn_rel - 3.0)/10.0 + 1.0));
3778 }
3779 else
3780 {
3781 *quality = (MS_U16)ber_sqi;
3782 }
3783
3784
3785 }
3786 //INTERN_DVBS_GetTunrSignalLevel_PWR();//For Debug.
3787 DBG_INTERN_DVBS(printf(">>>>>Signal Quility(SQI) = %d\n", *quality));
3788 return TRUE;
3789 }
3790 else
3791 {
3792 *quality = 0;
3793 }
3794
3795 return TRUE;
3796 }
3797 #endif
3798 /****************************************************************************
3799 Subject: To get the Cell ID
3800 Function: INTERN_DVBS_Get_CELL_ID
3801 Parmeter: point to return parameter cell_id
3802
3803 Return: TRUE
3804 FALSE
3805 Remark:
3806 *****************************************************************************/
INTERN_DVBS_Get_CELL_ID(MS_U16 * cell_id)3807 MS_BOOL INTERN_DVBS_Get_CELL_ID(MS_U16 *cell_id)
3808 {
3809 MS_BOOL status = true;
3810 MS_U8 value1 = 0;
3811 MS_U8 value2 = 0;
3812
3813 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [15:8]
3814 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [7:0]
3815
3816 *cell_id = ((MS_U16)value1<<8)|value2;
3817 return status;
3818 }
3819
3820 /****************************************************************************
3821 Subject: To get the DVBC Carrier Freq Offset
3822 Function: INTERN_DVBS_Get_FreqOffset
3823 Parmeter: Frequency offset (in KHz), bandwidth
3824 Return: E_RESULT_SUCCESS
3825 E_RESULT_FAILURE
3826 Remark:
3827 *****************************************************************************/
INTERN_DVBS_Get_FreqOffset(MS_S16 * s16CFO)3828 MS_BOOL INTERN_DVBS_Get_FreqOffset(MS_S16 *s16CFO)
3829 {
3830 MS_U8 u8Data=0;
3831 MS_U16 u16Data;
3832 //MS_S16 s16CFO;
3833 //float FreqOffset;
3834 //MS_U32 u32FreqOffset = 0;
3835 //MS_U8 reg = 0;
3836 MS_BOOL status = TRUE;
3837
3838 DBG_INTERN_DVBS(ULOGD("DEMOD",">>> INTERN_DVBS_Get_FreqOffset DVBS_Estimated_CFO <<<\n"));
3839 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_97, &u8Data);
3840 u16Data=u8Data;
3841 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_96, &u8Data);
3842 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset
3843
3844 if (u16Data >= 0x8000)
3845 {
3846 u16Data = 0x10000- u16Data;
3847 *s16CFO = -1*u16Data;
3848 }
3849 else
3850 {
3851 *s16CFO=u16Data;
3852 }
3853
3854 DBG_INTERN_DVBS(ULOGD("DEMOD",">>> INTERN_DVBS_Get_FreqOffset CFO = %d[KHz] <<<\n", *s16CFO));
3855
3856 return status;
3857 }
3858
INTERN_DVBS_Get_IQ_MODE(HAL_DEMOD_EN_SAT_IQ_MODE * SAT_IQ_MODE)3859 MS_BOOL INTERN_DVBS_Get_IQ_MODE(HAL_DEMOD_EN_SAT_IQ_MODE *SAT_IQ_MODE)
3860 {
3861 MS_BOOL status = true;
3862 MS_U8 u8Data = 0;
3863
3864 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_Get_IQ_MODE\n"));
3865
3866 if(_bDemodType) // DVBS2
3867 {
3868 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_MIXER_IQ_SWAP_OUT, &u8Data);
3869
3870 if( (u8Data&0x02) == 0x00 )
3871 *SAT_IQ_MODE = HAL_DEMOD_SAT_IQ_NORMAL;
3872 else
3873 *SAT_IQ_MODE = HAL_DEMOD_SAT_IQ_INVERSE;
3874 }
3875 else // DVBS
3876 {
3877 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_VITERBI_IQ_SWAP, &u8Data);
3878
3879 if( (u8Data & 0x04) == 0)
3880 *SAT_IQ_MODE = HAL_DEMOD_SAT_IQ_NORMAL;
3881 else
3882 *SAT_IQ_MODE = HAL_DEMOD_SAT_IQ_INVERSE;
3883 }
3884
3885 return status;
3886 }
3887
3888 /****************************************************************************
3889 Subject: To get the current modulation type at the DVB-S Demod
3890 Function: INTERN_DVBS_GetCurrentModulationType
3891 Parmeter: pointer for return QAM type
3892
3893 Return: TRUE
3894 FALSE
3895 Remark:
3896 *****************************************************************************/
INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE * pQAMMode)3897 MS_BOOL INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE *pQAMMode)
3898 {
3899 MS_U8 u8Data=0;
3900 MS_U16 u16tmp=0;
3901 MS_U8 MOD_type;
3902 MS_BOOL status = true;
3903 //DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3904
3905 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType\n"));
3906
3907 //status &= INTERN_DVBS_GetCurrentDemodType(&pDemodType);
3908
3909 // read code rate, pilot on/off, long/short FEC type, and modulation type for calculating TOP_DVBTM_TS_CLK_DIVNUM
3910 // pilot_flag => 0 : off 1 : on
3911 // fec_type_idx => 0 : normal 1 : short
3912 // mod_type_idx => 0 : QPSK 1 : 8PSK 2 : 16APSK
3913 // code_rate_idx => 0 : 1/4 1 : 1/3 2 : 2/5 3 : 1/2 4 : 3/5 5 : 2/3
3914 // 6 : 3/4 7 : 4/5 8 : 5/6 9 : 8/9 10 : 9/10
3915 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//V
3916 if(u8Data)
3917 {
3918 *pQAMMode = DMD_DVBS_QPSK;
3919 modulation_order=2;
3920 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs]ModulationType=DVBS_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS_QPSK\n"));
3921 //return TRUE;
3922 }
3923 else //S2
3924 {
3925 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x96, &u8Data);
3926 //printf(">>> INTERN_DVBS_GetCurrentModulationType INNER 0x4B = 0x%x <<<\n", u8Data);
3927 //if((u8Data & 0x0F)==0x02) //QPSK
3928 /*MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MOD_TYPE, &u8Data1);
3929 printf("@@@@@E_DMD_S2_MOD_TYPE = %d \n ",u8Data1);
3930 printf("@@@@@ E_DMD_S2_MOD_TYPE=%d \n",E_DMD_S2_MOD_TYPE);
3931
3932 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_IS_ID, &u8Data1);
3933 printf("@@@@@E_DMD_S2_IS_ID = %d \n ",u8Data1);
3934 printf("@@@@@ E_DMD_S2_IS_ID=%d \n",E_DMD_S2_IS_ID);*/
3935
3936 // INNER_DEBUG_SEL
3937 MDrv_SYS_DMD_VD_MBX_ReadReg(INNER_DEBUG_SEL, &u8Data);
3938 u8Data &= 0xc0;
3939 MDrv_SYS_DMD_VD_MBX_WriteReg(INNER_DEBUG_SEL, u8Data);
3940 // reg_plscdec_debug_out
3941 // PLSCDEC info
3942 //[0:7] PLSC MODCOD
3943 //[8:12] modulation_type
3944 //[13] dummy frame
3945 //[14] reserved_frame
3946 //[15] is DVBS2X
3947 //[16:22] code rate
3948 //[23] FEC type
3949 //[24] pilot type
3950 MDrv_SYS_DMD_VD_MBX_ReadReg(INNER_PLSCDEC_DEBUG_OUT1, &u8Data);
3951 u16tmp = (MS_U16)(u8Data & 0x1F);
3952 MOD_type = u16tmp;
3953 switch(MOD_type)
3954 {
3955 case 2:
3956 {
3957 *pQAMMode = DMD_DVBS_QPSK;
3958 modulation_order=2;
3959 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS2_QPSK\n"));
3960 }
3961 break;
3962
3963 case 3:
3964 {
3965 *pQAMMode = DMD_DVBS_8PSK;
3966 modulation_order=3;
3967 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_8PSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS2_8PSK\n"));
3968 }
3969
3970 break;
3971
3972 case 4:
3973 {
3974 *pQAMMode = DMD_DVBS_16APSK;
3975 modulation_order=4;
3976 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_16APSK\n");
3977 }
3978 break;
3979
3980 case 5:
3981 {
3982 *pQAMMode = DMD_DVBS_32APSK;
3983 modulation_order=5;
3984 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_32APSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS2_QPSK\n"));
3985 }
3986 break;
3987
3988 case 6:
3989 {
3990 *pQAMMode = DMD_DVBS_8APSK;
3991 modulation_order=3;
3992 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_8APSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS2_QPSK\n"));
3993 }
3994 break;
3995
3996 case 7:
3997 {
3998 *pQAMMode = DMD_DVBS_8_8APSK;
3999 modulation_order=4;
4000 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_8+8APSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS2_QPSK\n"));
4001 }
4002 break;
4003
4004 case 8:
4005 {
4006 *pQAMMode = DMD_DVBS_4_8_4_16APSK;
4007 modulation_order=5;
4008 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_4+8+4+16APSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS2_QPSK\n"));
4009 }
4010 break;
4011
4012 default:
4013 {
4014 *pQAMMode = DMD_DVBS_QPSK;
4015 modulation_order=2;
4016 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=NOT SUPPORT\n");
4017 return FALSE;
4018 }
4019 break;
4020 }
4021 }
4022
4023 return status;
4024 }
4025
4026 /****************************************************************************
4027 Subject: To get the current DemodType at the DVB-S Demod
4028 Function: INTERN_DVBS_GetCurrentDemodType
4029 Parmeter: pointer for return DVBS/DVBS2 type
4030
4031 Return: TRUE
4032 FALSE
4033 Remark:
4034 *****************************************************************************/
INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE * pDemodType)4035 MS_BOOL INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE *pDemodType)//V
4036 {
4037 MS_U8 u8Data=0;
4038 MS_BOOL status = true;
4039
4040 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentDemodType\n"));
4041
4042 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x80, &u8Data);//status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x80, &u8Data);
4043 //printf(">>> INTERN_DVBS_GetCurrentDemodType INNER 0x40 = 0x%x <<<\n", u8Data);
4044 //if ((u8Data & 0x01) == 0)
4045 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//E_DMD_S2_SYSTEM_TYPE 0: S2 ; 1 :S
4046 if(!u8Data) //S2
4047 {
4048 *pDemodType = DMD_SAT_DVBS2;
4049 DBG_INTERN_DVBS(ULOGD("DEMOD","[dvbs]DemodType=DVBS2\n"));
4050 }
4051 else //S
4052 {
4053 *pDemodType = DMD_SAT_DVBS;
4054 DBG_INTERN_DVBS(ULOGD("DEMOD","[dvbs]DemodType=DVBS\n"));
4055 }
4056 return status;
4057 }
4058 /****************************************************************************
4059 Subject: To get the current CodeRate at the DVB-S Demod
4060 Function: INTERN_DVBS_GetCurrentCodeRate
4061 Parmeter: pointer for return Code Rate type
4062
4063 Return: TRUE
4064 FALSE
4065 Remark:
4066 *****************************************************************************/
INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE * pCodeRate)4067 MS_BOOL INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE *pCodeRate)
4068 {
4069 MS_U8 u8Data = 0;//, u8_gCodeRate = 0;
4070 MS_BOOL status = true;
4071
4072 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate\n"));
4073 //DMD_DVBS_DEMOD_TYPE pDemodType = 0;
4074 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);
4075 //status &= INTERN_DVBS_GetCurrentDemodType(&pDemodType);
4076 if(!u8Data)
4077 //if((MS_U8)pDemodType == (MS_U8)DMD_SAT_DVBS2 ) //S2
4078 {
4079 //d0: 1/4, d1: 1/3, d2: 2/5, d3: 1/2, d4: 3/5, d5: 2/3, d6: 3/4, d7: 4/5, d8: 5/6, d9: 8/9, d10: 9/10,
4080 //d11: 2/9, d12: 13/45, d13: 9/20, d14: 90/180, d15: 96/180, d16: 11/20, d17: 100/180, d18: 104/180, d19: 26/45
4081 //d20: 18/30, d21: 28/45, d22: 23/36, d23: 116/180, d24: 20/30, d25: 124/180, d26: 25/36, d27: 128/180,, d28: 13/18
4082 //d29: 132/180, d30: 22/30, d31: 135/180, d32: 140/180, d33: 7/9, d34: 154/180
4083 //d35: 11/45, d36: 4/15, d37: 14/45, d38: 7/15, d39: 8/15, d40: 26/45, d41: 32/45
4084
4085 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
4086 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
4087 //u8_gCodeRate = (u8Data & 0x3C);
4088 //_u8_DVBS2_CurrentCodeRate = 0;
4089 switch (u8Data)
4090 {
4091 case 0x00:
4092 {
4093 *pCodeRate = DMD_CONV_CODE_RATE_1_4;
4094 //_u8_DVBS2_CurrentCodeRate = 8;//3
4095 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=1_4\n"));
4096 }
4097 break;
4098
4099 case 0x01:
4100 {
4101 *pCodeRate = DMD_CONV_CODE_RATE_1_3;
4102 //_u8_DVBS2_CurrentCodeRate = 6;
4103 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=1_3\n"));
4104 }
4105 break;
4106 case 0x02:
4107 {
4108 *pCodeRate = DMD_CONV_CODE_RATE_2_5;
4109 //_u8_DVBS2_CurrentCodeRate = 10;//5;
4110 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=2_5\n"));
4111 }
4112 break;
4113 case 0x03:
4114 {
4115 *pCodeRate = DMD_CONV_CODE_RATE_1_2;
4116 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4117 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=1_2\n"));
4118 }
4119 break;
4120 case 0x04:
4121 {
4122 *pCodeRate = DMD_CONV_CODE_RATE_3_5;
4123 //_u8_DVBS2_CurrentCodeRate = 11;//6;
4124 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=3_5\n"));
4125 }
4126 break;
4127 case 0x05:
4128 {
4129 *pCodeRate = DMD_CONV_CODE_RATE_2_3;
4130 //_u8_DVBS2_CurrentCodeRate = 7;//2;
4131 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=2_3\n"));
4132 }
4133 break;
4134 case 0x06:
4135 {
4136 *pCodeRate = DMD_CONV_CODE_RATE_3_4;
4137 //_u8_DVBS2_CurrentCodeRate = 9;//4;
4138 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=3_4\n"));
4139 }
4140 break;
4141 case 0x07:
4142 {
4143 *pCodeRate = DMD_CONV_CODE_RATE_4_5;
4144 //_u8_DVBS2_CurrentCodeRate = 12;//7;
4145 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=4_5\n"));
4146 }
4147 break;
4148 case 0x08:
4149 {
4150 *pCodeRate = DMD_CONV_CODE_RATE_5_6;
4151 //_u8_DVBS2_CurrentCodeRate = 13;//8;
4152 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=5_6\n"));
4153 }
4154 break;
4155 case 0x09:
4156 {
4157 *pCodeRate = DMD_CONV_CODE_RATE_8_9;
4158 //_u8_DVBS2_CurrentCodeRate = 14;//9;
4159 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=8_9\n"));
4160 }
4161 break;
4162 case 0x0A:
4163 {
4164 *pCodeRate = DMD_CONV_CODE_RATE_9_10;
4165 //_u8_DVBS2_CurrentCodeRate = 15;//10;
4166 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=9_10\n"));
4167 }
4168 break;
4169 case 0x0B:
4170 {
4171 *pCodeRate = DMD_DVBS2_CODE_RATE_2_9;
4172 //_u8_DVBS2_CurrentCodeRate = 16;//0;
4173 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=2_9\n"));
4174 }
4175 break;
4176 case 0x0C:
4177 {
4178 *pCodeRate = DMD_DVBS2_CODE_RATE_13_45;
4179 //_u8_DVBS2_CurrentCodeRate = 17;//0;
4180 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=13_45\n"));
4181 }
4182 break;
4183 case 0x0D:
4184 {
4185 *pCodeRate = DMD_DVBS2_CODE_RATE_9_20;
4186 //_u8_DVBS2_CurrentCodeRate = 18;//0;
4187 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=9_20\n"));
4188 }
4189 break;
4190 case 0x0E:
4191 {
4192 *pCodeRate = DMD_DVBS2_CODE_RATE_90_180;
4193 //_u8_DVBS2_CurrentCodeRate = 19;//0;
4194 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=90_180\n"));
4195 }
4196 break;
4197 case 0x0F:
4198 {
4199 *pCodeRate = DMD_DVBS2_CODE_RATE_96_180;
4200 //_u8_DVBS2_CurrentCodeRate = 20;//0;
4201 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=96_180\n"));
4202 }
4203 break;
4204 case 0x10:
4205 {
4206 *pCodeRate = DMD_DVBS2_CODE_RATE_11_20;
4207 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4208 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=11_20\n"));
4209 }
4210 break;
4211 case 0x11:
4212 {
4213 *pCodeRate = DMD_DVBS2_CODE_RATE_100_180;
4214 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4215 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=100_180\n"));
4216 }
4217 break;
4218 case 0x12:
4219 {
4220 *pCodeRate = DMD_DVBS2_CODE_RATE_104_180;
4221 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4222 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=104_180\n"));
4223 }
4224 break;
4225 case 0x13:
4226 {
4227 *pCodeRate = DMD_DVBS2_CODE_RATE_26_45_L;
4228 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4229 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=26_45\n"));
4230 }
4231 break;
4232 case 0x14:
4233 {
4234 *pCodeRate = DMD_DVBS2_CODE_RATE_18_30;
4235 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4236 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=18_30\n"));
4237 }
4238 break;
4239 case 0x15:
4240 {
4241 *pCodeRate = DMD_DVBS2_CODE_RATE_28_45;
4242 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4243 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=28_45\n"));
4244 }
4245 break;
4246 case 0x16:
4247 {
4248 *pCodeRate = DMD_DVBS2_CODE_RATE_23_36;
4249 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4250 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=23_36\n"));
4251 }
4252 break;
4253 case 0x17:
4254 {
4255 *pCodeRate = DMD_DVBS2_CODE_RATE_116_180;
4256 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4257 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=116_180\n"));
4258 }
4259 break;
4260 case 0x18:
4261 {
4262 *pCodeRate = DMD_DVBS2_CODE_RATE_20_30;
4263 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4264 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=20_30\n"));
4265 }
4266 break;
4267
4268 case 0x19:
4269 {
4270 *pCodeRate = DMD_DVBS2_CODE_RATE_124_180;
4271 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4272 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=124_180\n"));
4273 }
4274 break;
4275 case 0x1A:
4276 {
4277 *pCodeRate = DMD_DVBS2_CODE_RATE_25_36;
4278 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4279 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=25_36\n"));
4280 }
4281 break;
4282
4283 case 0x1B:
4284 {
4285 *pCodeRate = DMD_DVBS2_CODE_RATE_128_180;
4286 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4287 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=128_180\n"));
4288 }
4289 break;
4290 case 0x1C:
4291 {
4292 *pCodeRate = DMD_DVBS2_CODE_RATE_13_18;
4293 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4294 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=13_18\n"));
4295 }
4296 break;
4297
4298 case 0x1D:
4299 {
4300 *pCodeRate = DMD_DVBS2_CODE_RATE_132_180;
4301 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4302 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=132_180\n"));
4303 }
4304 break;
4305 case 0x1E:
4306 {
4307 *pCodeRate = DMD_DVBS2_CODE_RATE_22_30;
4308 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4309 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=22_30\n"));
4310 }
4311 break;
4312
4313 case 0x1F:
4314 {
4315 *pCodeRate = DMD_DVBS2_CODE_RATE_135_180;
4316 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4317 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=135_180\n"));
4318 }
4319 break;
4320 case 0x20:
4321 {
4322 *pCodeRate = DMD_DVBS2_CODE_RATE_140_180;
4323 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4324 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=140_180\n"));
4325 }
4326 break;
4327
4328 case 0x21:
4329 {
4330 *pCodeRate = DMD_DVBS2_CODE_RATE_7_9;
4331 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4332 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=7_9\n"));
4333 }
4334 break;
4335 case 0x22:
4336 {
4337 *pCodeRate = DMD_DVBS2_CODE_RATE_154_180;
4338 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4339 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=154_180\n"));
4340 }
4341 break;
4342
4343 case 0x23:
4344 {
4345 *pCodeRate = DMD_DVBS2_CODE_RATE_11_45;
4346 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4347 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=11_45\n"));
4348 }
4349 break;
4350 case 0x24:
4351 {
4352 *pCodeRate = DMD_DVBS2_CODE_RATE_4_15;
4353 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4354 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=4_15\n"));
4355 }
4356 break;
4357
4358 case 0x25:
4359 {
4360 *pCodeRate = DMD_DVBS2_CODE_RATE_14_45;
4361 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4362 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=14_45\n"));
4363 }
4364 break;
4365 case 0x26:
4366 {
4367 *pCodeRate = DMD_DVBS2_CODE_RATE_7_15;
4368 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4369 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=7_15\n"));
4370 }
4371 break;
4372
4373 case 0x27:
4374 {
4375 *pCodeRate = DMD_DVBS2_CODE_RATE_8_15;
4376 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4377 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=8_15\n"));
4378 }
4379 break;
4380
4381 case 0x28:
4382 {
4383 *pCodeRate = DMD_DVBS2_CODE_RATE_26_45_S;
4384 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4385 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=26_45_S\n"));
4386 }
4387 break;
4388
4389 case 0x29:
4390 {
4391 *pCodeRate = DMD_DVBS2_CODE_RATE_32_45;
4392 //_u8_DVBS2_CurrentCodeRate = 5;//0;
4393 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=32_45\n"));
4394 }
4395 break;
4396
4397 default:
4398 *pCodeRate = DMD_CONV_CODE_RATE_9_10;
4399 //_u8_DVBS2_CurrentCodeRate = 15;//10;
4400 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=DVBS2_Default\n"));
4401 }
4402 }
4403 else //S
4404 {
4405 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
4406 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE + 0x3A*2, &u8Data);
4407 //u8_gCodeRate = (u8Data & 0x70)>>4;
4408 switch (u8Data)
4409 //switch (u8_gCodeRate)
4410 {
4411 case 0x00:
4412 *pCodeRate = DMD_CONV_CODE_RATE_1_2;
4413 //_u8_DVBS2_CurrentCodeRate = 0;
4414 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=1_2\n"));
4415 break;
4416 case 0x01:
4417 *pCodeRate = DMD_CONV_CODE_RATE_2_3;
4418 //_u8_DVBS2_CurrentCodeRate = 1;
4419 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=2_3\n"));
4420 break;
4421 case 0x02:
4422 *pCodeRate = DMD_CONV_CODE_RATE_3_4;
4423 //_u8_DVBS2_CurrentCodeRate = 2;
4424 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=3_4\n"));
4425 break;
4426 case 0x03:
4427 *pCodeRate = DMD_CONV_CODE_RATE_5_6;
4428 //_u8_DVBS2_CurrentCodeRate = 3;
4429 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=5_6\n"));
4430 break;
4431 case 0x04:
4432 *pCodeRate = DMD_CONV_CODE_RATE_7_8;
4433 //_u8_DVBS2_CurrentCodeRate = 4;
4434 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=7_8\n"));
4435 break;
4436 default:
4437 *pCodeRate = DMD_CONV_CODE_RATE_7_8;
4438 //_u8_DVBS2_CurrentCodeRate = 4;
4439 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=DVBS_Default\n"));
4440 }
4441 }
4442 return status;
4443 }
4444
4445 /****************************************************************************
4446 Subject: To get the current symbol rate at the DVB-S Demod
4447 Function: INTERN_DVBS_GetCurrentSymbolRate
4448 Parmeter: pointer pData for return Symbolrate
4449
4450 Return: TRUE
4451 FALSE
4452 Remark:
4453 *****************************************************************************/
INTERN_DVBS_GetCurrentSymbolRate(MS_U32 * u32SymbolRate)4454 MS_BOOL INTERN_DVBS_GetCurrentSymbolRate(MS_U32 *u32SymbolRate)
4455 {
4456 MS_U8 tmp = 0;
4457 MS_U16 u16SymbolRateTmp = 0;
4458
4459 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &tmp);
4460 u16SymbolRateTmp = tmp;
4461 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &tmp);
4462 u16SymbolRateTmp = (u16SymbolRateTmp<<8)|tmp;
4463
4464 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &tmp);
4465 *u32SymbolRate = (tmp<<16)|u16SymbolRateTmp;
4466
4467 DBG_INTERN_DVBS_LOCK(ULOGD("DEMOD","[dvbs]Symbol Rate=%d\n",*u32SymbolRate));
4468
4469 return TRUE;
4470 }
4471
INTERN_DVBS_Version(MS_U16 * ver)4472 MS_BOOL INTERN_DVBS_Version(MS_U16 *ver)
4473 {
4474 MS_U8 status = true;
4475 MS_U8 tmp = 0;
4476 MS_U16 u16_INTERN_DVBS_Version;
4477
4478 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FW_VERSION_L, &tmp);
4479 u16_INTERN_DVBS_Version = tmp;
4480 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FW_VERSION_H, &tmp);
4481 u16_INTERN_DVBS_Version = u16_INTERN_DVBS_Version<<8|tmp;
4482 *ver = u16_INTERN_DVBS_Version;
4483
4484 return status;
4485 }
4486
INTERN_DVBS_Show_Demod_Version(void)4487 MS_BOOL INTERN_DVBS_Show_Demod_Version(void)
4488 {
4489 MS_BOOL status = true;
4490 MS_U16 u16_INTERN_DVBS_Version;
4491
4492 status &= INTERN_DVBS_Version(&u16_INTERN_DVBS_Version);
4493
4494 ULOGD("DEMOD",">>> [UTPA-700]Demod FW Version: R0x%X.0x%X <<<\n", (u16_INTERN_DVBS_Version&0x00FF),((u16_INTERN_DVBS_Version>>8)&0x00FF));
4495
4496
4497 return status;
4498 }
4499
INTERN_DVBS_GetRollOff(MS_U8 * pRollOff)4500 MS_BOOL INTERN_DVBS_GetRollOff(MS_U8 *pRollOff)
4501 {
4502 MS_BOOL status=TRUE;
4503 MS_U8 u8Data=0;
4504
4505 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//V
4506
4507 if(u8Data == 1) // DVBS
4508 {
4509 *pRollOff = HAL_DEMOD_SAT_RO_35; //Rolloff 0.35
4510 }
4511 else // DVBS2
4512 {
4513 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2OPPRO_ROLLOFF_DET_DONE, &u8Data);
4514
4515 if(u8Data)
4516 {
4517 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2OPPRO_ROLLOFF_DET_VALUE, &u8Data);
4518
4519 u8Data = (u8Data & 0x30) >> 4;
4520
4521 if (u8Data==0x02)
4522 *pRollOff = HAL_DEMOD_SAT_RO_35; //Rolloff 0.35
4523 else if (u8Data==0x01)
4524 *pRollOff = HAL_DEMOD_SAT_RO_25; //Rolloff 0.25
4525 else
4526 *pRollOff = HAL_DEMOD_SAT_RO_20; //Rolloff 0.20
4527
4528 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetRollOff:%d\n", *pRollOff));
4529 }
4530 }
4531
4532 #if 0
4533 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNER_TR_ROLLOFF, &u8Data);//#define INNER_TR_ROLLOFF (_REG_INNER(0x0F)+0)
4534 if ((u8Data&0x03)==0x00)
4535 *pRollOff = 0; //Rolloff 0.35
4536 else if (((u8Data&0x03)==0x01) || ((u8Data&0x03)==0x03))
4537 *pRollOff = 1; //Rolloff 0.25
4538 else
4539 *pRollOff = 2; //Rolloff 0.20
4540
4541 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetRollOff:%d\n", *pRollOff));
4542 #endif
4543
4544 return status;
4545 }
4546
INTERN_DVBS_Get_DTV_SQuality_BAR(MS_U8 * u8_gSQValue)4547 MS_BOOL INTERN_DVBS_Get_DTV_SQuality_BAR(MS_U8 *u8_gSQValue)
4548 {
4549 MS_BOOL status=TRUE;
4550 //MS_U16 u16_gSignalQualityValue;
4551 MS_U16 _u16_packetError;
4552
4553 // status = INTERN_DVBS_GetSignalQuality(&u16_gSignalQualityValue,0,0,0);
4554 status = INTERN_DVBS_GetPacketErr(&_u16_packetError);
4555 /*
4556 if ((_u16_packetError >= 1) && (u16_gSignalQualityValue > 30)) //Average
4557 {
4558 *u8_gSQValue = 30;
4559 }
4560 else if ((_u16_packetError >= 1) && (u16_gSignalQualityValue > 10)) //Poor
4561 {
4562 *u8_gSQValue = 10;
4563 }
4564 */
4565 return status;
4566 }
4567
4568 /****************************************************************************
4569 ** Function: Read demod related information
4570 ** Polling after demod lock
4571 ** GAIN & DCR /Fine CFO & PR & IIS & IQB & SNR /PacketErr & BER
4572 ****************************************************************************/
INTERN_DVBS_Show_AGC_Info(void)4573 MS_BOOL INTERN_DVBS_Show_AGC_Info(void)
4574 {
4575 MS_BOOL status = TRUE;
4576
4577 //MS_U8 tmp = 0;
4578 //MS_U8 agc_k = 0,d0_k = 0,d0_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0,d3_k = 0,d3_ref = 0;
4579 //MS_U16 if_agc_gain = 0,d0_gain = 0,d1_gain = 0,d2_gain = 0,d3_gain = 0, agc_ref = 0;
4580 //MS_U16 if_agc_err = 0;
4581 #if 0
4582 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x08*2 + 1,&agc_k);
4583 agc_k = ((agc_k & 0xF0)>>4);
4584 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x09*2 + 1,&tmp);
4585 agc_ref = tmp;
4586 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0xE8,&tmp);
4587 //agc_ref = (agc_ref<<8)|tmp;
4588 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x38*2,&d0_k);
4589 d0_k = ((d0_k & 0xF0)>>4);
4590 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x38*2 + 1,&d0_ref);
4591 d0_ref = (d0_ref & 0xFF);
4592 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x58*2,&d1_k);
4593 d1_k = (d1_k & 0xF0)>>4;
4594 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x58*2 + 1,&d1_ref);
4595 d1_ref = (d1_ref & 0xFF);
4596 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5E*2,&d2_k);
4597 d2_k = ((d2_k & 0xF0)>>4);
4598 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x5E*2 + 1,&d2_ref);
4599 d2_ref = (d2_ref & 0xFF);
4600 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6A*2,&d3_k);
4601 d3_k = ((d3_k & 0xF0)>>4);
4602 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref);
4603 d3_ref = (d3_ref & 0xFF);
4604
4605
4606 // select IF gain to read
4607 //Debug Select
4608 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x13*2, &tmp);
4609 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x13*2, (tmp&0xF0)|0x03);
4610 //IF_AGC_GAIN
4611 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2 + 1, &tmp);
4612 if_agc_gain = tmp;
4613 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2, &tmp);
4614 if_agc_gain = (if_agc_gain<<8)|tmp;
4615
4616
4617 // select d0 gain to read.
4618 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x74*2 + 1, &tmp);
4619 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x74*2 + 1, (tmp&0xF0)|0x03);
4620 //DAGC0_GAIN
4621 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3D*2, &tmp);
4622 d0_gain = tmp;
4623 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3C*2 + 1, &tmp);
4624 d0_gain = (d0_gain<<8)|tmp;
4625 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3C*2, &tmp);
4626 d0_gain = (d0_gain<<4)|(tmp>>4);
4627
4628
4629 // select d1 gain to read.
4630 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x8C, &tmp);
4631 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x8C, (tmp&0xF0)|0x00);
4632 //DAGC1_GAIN
4633 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5C*2 + 1, &tmp);
4634 d1_gain = tmp;
4635 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5C*2, &tmp);
4636 d1_gain = (d1_gain<<8)|tmp;
4637
4638
4639 // select d2 gain to read.
4640 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x06, &tmp);
4641 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT_REG_BASE + 0x06, (tmp&0xF0)|0x03);
4642 //DAGC2_GAIN
4643 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x62*2 + 1, &tmp);
4644 d2_gain = tmp;
4645 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x62*2, &tmp);
4646 d2_gain = (d2_gain<<8)|tmp;
4647
4648
4649 // select d3 gain to read.
4650 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp);
4651 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03);
4652 //DAGC3_GAIN
4653 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6F*2, &tmp);
4654 d3_gain = tmp;
4655 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6E*2 + 1, &tmp);
4656 d3_gain = (d3_gain<<8)|tmp;
4657 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6E*2, &tmp);
4658 d3_gain = (d3_gain<<4)|(tmp>>4);
4659
4660
4661 // select IF gain err to read
4662 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x13*2, &tmp);
4663 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x13*2, (tmp&0xF0)|0x00);
4664
4665 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2 + 1, &tmp);
4666 if_agc_err = tmp;
4667 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2, &tmp);
4668 if_agc_err = (if_agc_err<<8)|tmp;
4669
4670
4671 DBG_INTERN_DVBS(printf("[dvbs]agc_k=0x%x, agc_ref=0x%x, d0_k=0x%x, d0_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x, d3_k=0x%x, d3_ref=0x%x\n",
4672 agc_k, agc_ref, d0_k, d0_ref, d1_k, d1_ref, d2_k, d2_ref, d3_k, d3_ref));
4673
4674 DBG_INTERN_DVBS(printf("[dvbs]agc_g=0x%x, d0_g=0x%x, d1_g=0x%x, d2_g=0x%x, d3_g=0x%x, agc_err=0x%x\n", if_agc_gain, d0_gain, d1_gain, d2_gain, d3_gain, if_agc_err));
4675
4676 DBG_INTERN_DVBS(printf("[dvbs]agc_k=0x%x, agc_ref=0x%x, d0_k=0x%x, d0_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x, d3_k=0x%x, d3_ref=0x%x\n",
4677 agc_k, agc_ref, d0_k, d0_ref, d1_k, d1_ref, d2_k, d2_ref, d3_k, d3_ref));
4678
4679 DBG_INTERN_DVBS(printf("[dvbs]agc_g=0x%x, d0_g=0x%x, d1_g=0x%x, d2_g=0x%x, d3_g=0x%x, agc_err=0x%x\n", if_agc_gain, d0_gain, d1_gain, d2_gain, d3_gain, if_agc_err));
4680 #endif
4681 return status;
4682 }
4683
4684 /****************************************************************************
4685 ** Function: Read demod related information
4686 ** Polling after demod lock
4687 ** GAIN & DCR /Fine CFO & PR & IIS & IQB & SNR /PacketErr & BER
4688 ****************************************************************************/
INTERN_DVBS_AGC_Info(MS_U8 u8dbg_mode,MS_U16 * pu16Data)4689 MS_BOOL INTERN_DVBS_AGC_Info(MS_U8 u8dbg_mode, MS_U16* pu16Data)
4690 {
4691 MS_BOOL status = true;
4692 MS_U8 u8Data;
4693 MS_U16 u16Data;
4694
4695 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_AGC_DEBUG_SEL,&u8Data);
4696 u8Data = (u8Data & 0xf0) | u8dbg_mode;
4697 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_AGC_DEBUG_SEL,u8Data);
4698
4699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_LATCH,&u8Data);
4700 u8Data = u8Data | 0x80;
4701 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_LATCH,u8Data);
4702
4703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_AGC_DEBUG_OUT_R1,&u8Data);
4704 u16Data = u8Data;
4705 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_AGC_DEBUG_OUT_R0,&u8Data);
4706 u16Data = (u16Data<<8) | u8Data;
4707
4708 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_LATCH,&u8Data);
4709 u8Data = u8Data & 0x7f;
4710 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_LATCH,u8Data);
4711
4712 *pu16Data=u16Data;
4713
4714 if (status==FALSE)
4715 {
4716 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_AGC_Info Error!!! \n"));
4717 }
4718
4719 return status;
4720
4721 //MS_U8 tmp = 0;
4722 //MS_U8 agc_k = 0,d0_k = 0,d0_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0,d3_k = 0,d3_ref = 0;
4723 //MS_U16 if_agc_gain = 0,d0_gain = 0,d1_gain = 0,d2_gain = 0,d3_gain = 0, agc_ref = 0;
4724 //MS_U16 if_agc_err = 0;
4725 #if 0
4726 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x08*2 + 1,&agc_k);
4727 agc_k = ((agc_k & 0xF0)>>4);
4728 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x09*2 + 1,&tmp);
4729 agc_ref = tmp;
4730 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0xE8,&tmp);
4731 //agc_ref = (agc_ref<<8)|tmp;
4732 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x38*2,&d0_k);
4733 d0_k = ((d0_k & 0xF0)>>4);
4734 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x38*2 + 1,&d0_ref);
4735 d0_ref = (d0_ref & 0xFF);
4736 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x58*2,&d1_k);
4737 d1_k = (d1_k & 0xF0)>>4;
4738 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x58*2 + 1,&d1_ref);
4739 d1_ref = (d1_ref & 0xFF);
4740 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5E*2,&d2_k);
4741 d2_k = ((d2_k & 0xF0)>>4);
4742 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x5E*2 + 1,&d2_ref);
4743 d2_ref = (d2_ref & 0xFF);
4744 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6A*2,&d3_k);
4745 d3_k = ((d3_k & 0xF0)>>4);
4746 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref);
4747 d3_ref = (d3_ref & 0xFF);
4748
4749
4750 // select IF gain to read
4751 //Debug Select
4752 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x13*2, &tmp);
4753 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x13*2, (tmp&0xF0)|0x03);
4754 //IF_AGC_GAIN
4755 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2 + 1, &tmp);
4756 if_agc_gain = tmp;
4757 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2, &tmp);
4758 if_agc_gain = (if_agc_gain<<8)|tmp;
4759
4760
4761 // select d0 gain to read.
4762 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x74*2 + 1, &tmp);
4763 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x74*2 + 1, (tmp&0xF0)|0x03);
4764 //DAGC0_GAIN
4765 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3D*2, &tmp);
4766 d0_gain = tmp;
4767 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3C*2 + 1, &tmp);
4768 d0_gain = (d0_gain<<8)|tmp;
4769 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3C*2, &tmp);
4770 d0_gain = (d0_gain<<4)|(tmp>>4);
4771
4772
4773 // select d1 gain to read.
4774 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x8C, &tmp);
4775 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x8C, (tmp&0xF0)|0x00);
4776 //DAGC1_GAIN
4777 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5C*2 + 1, &tmp);
4778 d1_gain = tmp;
4779 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5C*2, &tmp);
4780 d1_gain = (d1_gain<<8)|tmp;
4781
4782
4783 // select d2 gain to read.
4784 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x06, &tmp);
4785 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT_REG_BASE + 0x06, (tmp&0xF0)|0x03);
4786 //DAGC2_GAIN
4787 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x62*2 + 1, &tmp);
4788 d2_gain = tmp;
4789 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x62*2, &tmp);
4790 d2_gain = (d2_gain<<8)|tmp;
4791
4792
4793 // select d3 gain to read.
4794 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp);
4795 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03);
4796 //DAGC3_GAIN
4797 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6F*2, &tmp);
4798 d3_gain = tmp;
4799 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6E*2 + 1, &tmp);
4800 d3_gain = (d3_gain<<8)|tmp;
4801 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6E*2, &tmp);
4802 d3_gain = (d3_gain<<4)|(tmp>>4);
4803
4804
4805 // select IF gain err to read
4806 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x13*2, &tmp);
4807 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x13*2, (tmp&0xF0)|0x00);
4808
4809 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2 + 1, &tmp);
4810 if_agc_err = tmp;
4811 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2, &tmp);
4812 if_agc_err = (if_agc_err<<8)|tmp;
4813
4814
4815 DBG_INTERN_DVBS(printf("[dvbs]agc_k=0x%x, agc_ref=0x%x, d0_k=0x%x, d0_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x, d3_k=0x%x, d3_ref=0x%x\n",
4816 agc_k, agc_ref, d0_k, d0_ref, d1_k, d1_ref, d2_k, d2_ref, d3_k, d3_ref));
4817
4818 DBG_INTERN_DVBS(printf("[dvbs]agc_g=0x%x, d0_g=0x%x, d1_g=0x%x, d2_g=0x%x, d3_g=0x%x, agc_err=0x%x\n", if_agc_gain, d0_gain, d1_gain, d2_gain, d3_gain, if_agc_err));
4819
4820 DBG_INTERN_DVBS(printf("[dvbs]agc_k=0x%x, agc_ref=0x%x, d0_k=0x%x, d0_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x, d3_k=0x%x, d3_ref=0x%x\n",
4821 agc_k, agc_ref, d0_k, d0_ref, d1_k, d1_ref, d2_k, d2_ref, d3_k, d3_ref));
4822
4823 DBG_INTERN_DVBS(printf("[dvbs]agc_g=0x%x, d0_g=0x%x, d1_g=0x%x, d2_g=0x%x, d3_g=0x%x, agc_err=0x%x\n", if_agc_gain, d0_gain, d1_gain, d2_gain, d3_gain, if_agc_err));
4824 #endif
4825 return status;
4826 }
4827
INTERN_DVBS_info(void)4828 void INTERN_DVBS_info(void)
4829 {
4830 //status &= INTERN_DVBS_Show_Demod_Version();
4831 //status &= INTERN_DVBS_Demod_Get_Debug_Info_get_once();
4832 //status &= INTERN_DVBS_Demod_Get_Debug_Info_polling();
4833 }
4834
INTERN_DVBS_Demod_Get_Debug_Info_get_once(void)4835 MS_BOOL INTERN_DVBS_Demod_Get_Debug_Info_get_once(void)
4836 {
4837 MS_BOOL status = TRUE;
4838 //MS_U8 u8Data = 0;
4839 //MS_U16 u16Data = 0, u16Address = 0;
4840 //float psd_smooth_factor;
4841 //float srd_right_bottom_value, srd_right_top_value, srd_left_bottom_value, srd_left_top_value;
4842 //MS_U16 u32temp5;
4843 //MS_U16 srd_left, srd_right, srd_left_top, srd_left_bottom, srd_right_top, srd_right_bottom;
4844
4845 #if 0
4846 //Lock Flag
4847 printf("========================================================================\n");
4848 printf("Debug Message Flag [Lock Flag]==========================================\n");
4849
4850 u16Address = (AGC_LOCK>>16)&0xffff;
4851 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4852 if ((u16Data&(AGC_LOCK&0xffff))!=(AGC_LOCK&0xffff))
4853 printf("[DVBS]: AGC LOCK ======================: Fail. \n");
4854 else
4855 printf("[DVBS]: AGC LOCK ======================: OK. \n");
4856
4857 u16Address = (DAGC0_LOCK>>16)&0xffff;
4858 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4859 if ((u16Data&(DAGC0_LOCK&0xffff))!=(DAGC0_LOCK&0xffff))
4860 printf("[DVBS]: DAGC0 LOCK ====================: Fail. \n");
4861 else
4862 printf("[DVBS]: DAGC0 LOCK ====================: OK. \n");
4863
4864 u16Address = (DAGC1_LOCK>>16)&0xffff;
4865 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4866 if ((u16Data&(DAGC1_LOCK&0xffff))!=(DAGC1_LOCK&0xffff))
4867 printf("[DVBS]: DAGC1 LOCK ====================: Fail. \n");
4868 else
4869 printf("[DVBS]: DAGC1 LOCK ====================: OK. \n");
4870
4871 u16Address = (DAGC2_LOCK>>16)&0xffff;
4872 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4873 if ((u16Data&(DAGC2_LOCK&0xffff))!=(DAGC2_LOCK&0xffff))
4874 printf("[DVBS]: DAGC2 LOCK ====================: Fail. \n");
4875 else
4876 printf("[DVBS]: DAGC2 LOCK ====================: OK. \n");
4877
4878 u16Address = (DAGC3_LOCK>>16)&0xffff;
4879 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4880 if ((u16Data&(DAGC3_LOCK&0xffff))!=(DAGC3_LOCK&0xffff))
4881 printf("[DVBS]: DAGC3 LOCK ====================: Fail. \n");
4882 else
4883 printf("[DVBS]: DAGC3 LOCK ====================: OK. \n");
4884
4885 u16Address = (DCR_LOCK>>16)&0xffff;
4886 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4887 if ((u16Data&(DCR_LOCK&0xffff))!=(DCR_LOCK&0xffff))
4888 printf("[DVBS]: DCR LOCK ======================: Fail. \n");
4889 else
4890 printf("[DVBS]: DCR LOCK ======================: OK. \n");
4891 //Mark Coarse SRD
4892 //Mark Fine SRD
4893 /*
4894 u16Address = (CLOSE_COARSE_CFO_LOCK>>16)&0xffff;
4895 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4896 if ((u16Data&(CLOSE_COARSE_CFO_LOCK&0xffff))!=(CLOSE_COARSE_CFO_LOCK&0xffff))
4897 printf("[DVBS]: Close CFO =====================: Fail. \n");
4898 else
4899 printf("[DVBS]: Close CFO =====================: OK. \n");
4900 */
4901 u16Address = (TR_LOCK>>16)&0xffff;
4902 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4903 if ((u16Data&(TR_LOCK&0xffff))!=(TR_LOCK&0xffff))
4904 printf("[DVBS]: TR LOCK =======================: Fail. \n");
4905 else
4906 printf("[DVBS]: TR LOCK =======================: OK. \n");
4907
4908 u16Address = (FRAME_SYNC_ACQUIRE>>16)&0xffff;
4909 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4910 if ((u16Data&(FRAME_SYNC_ACQUIRE&0xffff))!=(FRAME_SYNC_ACQUIRE&0xffff))
4911 printf("[DVBS]: FS Acquire ====================: Fail. \n");
4912 else
4913 printf("[DVBS]: FS Acquire ====================: OK. \n");
4914
4915 u16Address = (PR_LOCK>>16)&0xffff;
4916 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4917 if ((u16Data&(PR_LOCK&0xffff))!=(PR_LOCK&0xffff))
4918 printf("[DVBS]: PR LOCK =======================: Fail. \n");
4919 else
4920 printf("[DVBS]: PR LOCK =======================: OK. \n");
4921
4922 u16Address = (EQ_LOCK>>16)&0xffff;
4923 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4924 if ((u16Data&(EQ_LOCK&0xffff))!=(EQ_LOCK&0xffff))
4925 printf("[DVBS]: EQ LOCK =======================: Fail. \n");
4926 else
4927 printf("[DVBS]: EQ LOCK =======================: OK. \n");
4928
4929 u16Address = (P_SYNC_LOCK>>16)&0xffff;
4930 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4931 if ((u16Data&0x0002)!=0x0002)
4932 printf("[DVBS]: P_sync ========================: Fail. \n");
4933 else
4934 printf("[DVBS]: P_sync ========================: OK. \n");
4935
4936 u16Address = (IN_SYNC_LOCK>>16)&0xffff;
4937 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4938 if ((u16Data&0x8000)!=0x8000)
4939 printf("[DVBS]: In_sync =======================: Fail. \n");
4940 else
4941 printf("[DVBS]: In_sync =======================: OK. \n");
4942 //---------------------------------------------------------
4943 //Lock Time
4944 printf("------------------------------------------------------------------------\n");
4945 printf("Debug Message [Lock Time]===============================================\n");
4946
4947 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_05, &u8Data);
4948 printf("[DVBS]: AGC Lock Time =================: %d\n",u8Data&0x00FF);
4949 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_06, &u8Data);
4950 printf("[DVBS]: DCR Lock Time =================: %d\n",u8Data&0x00FF);
4951 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_2, &u8Data);
4952 printf("[DVBS]: TR Lock Time ==================: %d\n",u8Data&0x00FF);
4953 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_3, &u8Data);
4954 printf("[DVBS]: FS Lock Time ==================: %d\n",u8Data&0x00FF);
4955 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_4, &u8Data);
4956 printf("[DVBS]: PR Lock Time ==================: %d\n",u8Data&0x00FF);
4957 //printf("[DVBS]: PLSC Lock Time ================: %d\n",(u16Data>>8)&0x00FF);//No used
4958 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_6, &u8Data);
4959 printf("[DVBS]: EQ Lock Time ==================: %d\n",u8Data&0x00FF);
4960 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_7, &u8Data);
4961 printf("[DVBS]: FEC Lock Time =================: %d\n",u8Data&0x00FF);
4962
4963 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_0, &u8Data);
4964 printf("[DVBS]: CSRD ==========================: %d\n",u8Data&0x00FF);
4965 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_1, &u8Data);
4966 printf("[DVBS]: FSRD ==========================: %d\n",u8Data&0x00FF);
4967 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_01, &u8Data);
4968 printf("[DVBS]: CCFO ==========================: %d\n",u8Data&0x00FF);
4969 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_02, &u8Data);
4970 printf("[DVBS]: FCFO ==========================: %d\n",u8Data&0x00FF);
4971 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);
4972 printf("[DVBS]: State =========================: %d\n",u8Data&0x00FF);
4973 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SUBSTATE_FLAG, &u8Data);
4974 printf("[DVBS]: SubState ======================: %d\n",u8Data&0x00FF);
4975
4976 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00H, &u8Data);
4977 u16Data = u8Data;
4978 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00L, &u8Data);
4979 u16Data = (u16Data<<8)|u8Data;
4980 printf("[DVBS]: DBG1: =========================: 0x%x\n",u16Data);
4981 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01H, &u8Data);
4982 u16Data = u8Data;
4983 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01L, &u8Data);
4984 u16Data = (u16Data<<8)|u8Data;
4985 printf("[DVBS]: DBG2: =========================: 0x%x\n",u16Data);
4986 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE02H, &u8Data);
4987 u16Data = u8Data;
4988 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE02L, &u8Data);
4989 u16Data = (u16Data<<8)|u8Data;
4990 printf("[DVBS]: DBG3: =========================: 0x%x\n",u16Data);
4991 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE03H, &u8Data);
4992 u16Data = u8Data;
4993 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE03L, &u8Data);
4994 u16Data = (u16Data<<8)|u8Data;
4995 printf("[DVBS]: DBG4: =========================: 0x%x\n",u16Data);
4996 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE04H, &u8Data);
4997 u16Data = u8Data;
4998 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE04L, &u8Data);
4999 u16Data = (u16Data<<8)|u8Data;
5000 printf("[DVBS]: DBG5: =========================: 0x%x\n",u16Data);
5001 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE05H, &u8Data);
5002 u16Data = u8Data;
5003 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE05L, &u8Data);
5004 u16Data = (u16Data<<8)|u8Data;
5005 printf("[DVBS]: DBG6: =========================: 0x%x\n",u16Data);
5006 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE06H, &u8Data);
5007 u16Data = u8Data;
5008 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE06L, &u8Data);
5009 u16Data = (u16Data<<8)|u8Data;
5010 printf("[DVBS]: EQ Sum: =======================: 0x%x\n",u16Data);
5011 //---------------------------------------------------------
5012 //FIQ Status
5013 printf("------------------------------------------------------------------------\n");
5014 printf("Debug Message [FIQ Status]==============================================\n");
5015 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00H, &u8Data);
5016 u16Data = u8Data;
5017 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00L, &u8Data);
5018 u16Data = (u16Data<<8)|u8Data;
5019
5020 if ((u16Data&0x0001)==0x0000)
5021 printf("[DVBS]: AGC Lock ======================: Fail. \n");
5022 else
5023 printf("[DVBS]: AGC Lock ======================: OK. \n");
5024
5025 if ((u16Data&0x0002)==0x0000)
5026 printf("[DVBS]: Hum Detect ====================: Fail. \n");
5027 else
5028 printf("[DVBS]: Hum Detect ====================: OK. \n");
5029
5030 if ((u16Data&0x0004)==0x0000)
5031 printf("[DVBS]: DCR Lock ======================: Fail. \n");
5032 else
5033 printf("[DVBS]: DCR Lock ======================: OK. \n");
5034
5035 if ((u16Data&0x0008)==0x0000)
5036 printf("[DVBS]: IIS Detect ====================: Fail. \n");
5037 else
5038 printf("[DVBS]: IIS Detect ====================: OK. \n");
5039
5040 if ((u16Data&0x0010)==0x0000)
5041 printf("[DVBS]: DAGC0 Lock ====================: Fail. \n");
5042 else
5043 printf("[DVBS]: DAGC0 Lock ====================: OK. \n");
5044
5045 if ((u16Data&0x0020)==0x0000)
5046 printf("[DVBS]: DAGC1 Lock ====================: Fail. \n");
5047 else
5048 printf("[DVBS]: DAGC1 Lock ====================: OK. \n");
5049
5050 if ((u16Data&0x0040)==0x0000)
5051 printf("[DVBS]: DAGC2 Lock ====================: Fail. \n");
5052 else
5053 printf("[DVBS]: DAGC2 Lock ====================: OK. \n");
5054
5055 if ((u16Data&0x0080)==0x0000)
5056 printf("[DVBS]: CCI Detect ====================: Fail. \n");
5057 else
5058 printf("[DVBS]: CCI Detect ====================: OK. \n");
5059
5060 if ((u16Data&0x0100)==0x0000)
5061 printf("[DVBS]: SRD Coarse Done ===============: Fail. \n");
5062 else
5063 printf("[DVBS]: SRD Coarse Done ===============: OK. \n");
5064
5065 if ((u16Data&0x0200)==0x0000)
5066 printf("[DVBS]: SRD Fine Done =================: Fail. \n");
5067 else
5068 printf("[DVBS]: SRD Fine Done =================: OK. \n");
5069
5070 if ((u16Data&0x0400)==0x0000)
5071 printf("[DVBS]: EQ Lock =======================: Fail. \n");
5072 else
5073 printf("[DVBS]: EQ Lock =======================: OK. \n");
5074
5075 if ((u16Data&0x0800)==0x0000)
5076 printf("[DVBS]: FineFE Done ===================: Fail. \n");
5077 else
5078 printf("[DVBS]: FineFE Done ===================: OK. \n");
5079
5080 if ((u16Data&0x1000)==0x0000)
5081 printf("[DVBS]: PR Lock =======================: Fail. \n");
5082 else
5083 printf("[DVBS]: PR Lock =======================: OK. \n");
5084
5085 if ((u16Data&0x2000)==0x0000)
5086 printf("[DVBS]: Reserved Frame ================: Fail. \n");
5087 else
5088 printf("[DVBS]: Reserved Frame ================: OK. \n");
5089
5090 if ((u16Data&0x4000)==0x0000)
5091 printf("[DVBS]: Dummy Frame ===================: Fail. \n");
5092 else
5093 printf("[DVBS]: Dummy Frame ===================: OK. \n");
5094
5095 if ((u16Data&0x8000)==0x0000)
5096 printf("[DVBS]: PLSC Done =====================: Fail. \n");
5097 else
5098 printf("[DVBS]: PLSC Done =====================: OK. \n");
5099
5100 printf("------------------------------------------------------------------------\n");
5101 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01H, &u8Data);
5102 u16Data = u8Data;
5103 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01L, &u8Data);
5104 u16Data = (u16Data<<8)|u8Data;
5105 if ((u16Data&0x0001)==0x0000)
5106 printf("[DVBS]: FS Get Info From Len ==========: Fail. \n");
5107 else
5108 printf("[DVBS]: FS Get Info From Len ==========: OK. \n");
5109
5110 if ((u16Data&0x0002)==0x0000)
5111 printf("[DVBS]: IQ Swap Detect ================: Fail. \n");
5112 else
5113 printf("[DVBS]: IQ Swap Detect ================: OK. \n");
5114
5115 if ((u16Data&0x0004)==0x0000)
5116 printf("[DVBS]: FS Acquisition ================: Fail. \n");
5117 else
5118 printf("[DVBS]: FS Acquisition ================: OK. \n");
5119
5120 if ((u16Data&0x0008)==0x0000)
5121 printf("[DVBS]: TR Lock =======================: Fail. \n");
5122 else
5123 printf("[DVBS]: TR Lock =======================: OK. \n");
5124
5125 if ((u16Data&0x0010)==0x0000)
5126 printf("[DVBS]: CLCFE Lock ====================: Fail. \n");
5127 else
5128 printf("[DVBS]: CLCFE Lock ====================: OK. \n");
5129
5130 if ((u16Data&0x0020)==0x0000)
5131 printf("[DVBS]: OLCFE Lock ====================: Fail. \n");
5132 else
5133 printf("[DVBS]: OLCFE Lock ====================: OK. \n");
5134
5135 if ((u16Data&0x0040)==0x0000)
5136 printf("[DVBS]: Fsync Found ===================: Fail. \n");
5137 else
5138 printf("[DVBS]: Fsync Found ===================: OK. \n");
5139
5140 if ((u16Data&0x0080)==0x0000)
5141 printf("[DVBS]: Fsync Lock ====================: Fail. \n");
5142 else
5143 printf("[DVBS]: Fsync Lock ====================: OK. \n");
5144
5145 if ((u16Data&0x0100)==0x0000)
5146 printf("[DVBS]: Fsync Fail Search =============: Fail. \n");
5147 else
5148 printf("[DVBS]: Fsync Fail Search =============: OK. \n");
5149
5150 if ((u16Data&0x0200)==0x0000)
5151 printf("[DVBS]: Fsync Fail Lock ===============: Fail. \n");
5152 else
5153 printf("[DVBS]: Fsync Fail Lock ===============: OK. \n");
5154
5155 if ((u16Data&0x0400)==0x0000)
5156 printf("[DVBS]: False Alarm ===================: Fail. \n");
5157 else
5158 printf("[DVBS]: False Alarm ===================: OK. \n");
5159
5160 if ((u16Data&0x0800)==0x0000)
5161 printf("[DVBS]: Viterbi In Sync ===============: Fail. \n");
5162 else
5163 printf("[DVBS]: Viterbi In Sync ===============: OK. \n");
5164
5165 if ((u16Data&0x1000)==0x0000)
5166 printf("[DVBS]: Uncrt Over ====================: Fail. \n");
5167 else
5168 printf("[DVBS]: Uncrt Over ====================: OK. \n");
5169
5170 if ((u16Data&0x2000)==0x0000)
5171 printf("[DVBS]: CLK Cnt Over ==================: Fail. \n");
5172 else
5173 printf("[DVBS]: CLK Cnt Over ==================: OK. \n");
5174
5175 //if ((u16Data&0x4000)==0x0000)
5176 // printf("[DVBS]: Data In Ready FIFO ============: Fail. \n");
5177 //else
5178 // printf("[DVBS]: Data In Ready FIFO ============: OK. \n");
5179
5180 //if ((u16Data&0x8000)==0x0000)
5181 // printf("[DVBS]: IIR Buff Busy =================: Fail. \n");
5182 //else
5183 // printf("[DVBS]: IIR Buff Busy =================: OK. \n");
5184
5185 /*
5186 printf("------------------------------------------------------------------------\n");
5187 u16Address = 0x0B64;
5188 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address+1, &u8Data);
5189 u16Data = u8Data;
5190 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address , &u8Data);
5191 u16Data = (u16Data<<8)|u8Data;
5192 if ((u16Data&0x0001)==0x0000)
5193 printf("[DVBS]: IIR Busy LDPC =================: Fail. \n");
5194 else
5195 printf("[DVBS]: IIR Busy LDPC =================: OK. \n");
5196
5197 if ((u16Data&0x0002)==0x0000)
5198 printf("[DVBS]: BCH Busy ======================: Fail. \n");
5199 else
5200 printf("[DVBS]: BCH Busy ======================: OK. \n");
5201
5202 if ((u16Data&0x0004)==0x0000)
5203 printf("[DVBS]: Oppro Ready Out ===============: Fail. \n");
5204 else
5205 printf("[DVBS]: Oppro Ready Out ===============: OK. \n");
5206
5207 if ((u16Data&0x0008)==0x0000)
5208 printf("[DVBS]: LDPC Win ======================: Fail. \n");
5209 else
5210 printf("[DVBS]: LDPC Win ======================: OK. \n");
5211
5212 if ((u16Data&0x0010)==0x0000)
5213 printf("[DVBS]: LDPC Error ====================: Fail. \n");
5214 else
5215 printf("[DVBS]: LDPC Error ====================: OK. \n");
5216
5217 if ((u16Data&0x0020)==0x0000)
5218 printf("[DVBS]: Out BCH Error =================: Fail. \n");
5219 else
5220 printf("[DVBS]: Out BCH Error =================: OK. \n");
5221
5222 if ((u16Data&0x0040)==0x0000)
5223 printf("[DVBS]: Descr BCH FEC Num Error =======: Fail. \n");
5224 else
5225 printf("[DVBS]: Descr BCH FEC Num Error =======: OK. \n");
5226
5227 if ((u16Data&0x0080)==0x0000)
5228 printf("[DVBS]: Descr BCH Data Num Error ======: Fail. \n");
5229 else
5230 printf("[DVBS]: Descr BCH Data Num Error ======: OK. \n");
5231
5232 if ((u16Data&0x0100)==0x0000)
5233 printf("[DVBS]: Packet Error Out ==============: Fail. \n");
5234 else
5235 printf("[DVBS]: Packet Error Out ==============: OK. \n");
5236
5237 if ((u16Data&0x0200)==0x0000)
5238 printf("[DVBS]: BBH CRC Error =================: Fail. \n");
5239 else
5240 printf("[DVBS]: BBH CRC Error =================: OK. \n");
5241
5242 if ((u16Data&0x0400)==0x0000)
5243 printf("[DVBS]: BBH Decode Done ===============: Fail. \n");
5244 else
5245 printf("[DVBS]: BBH Decode Done ===============: OK. \n");
5246
5247 if ((u16Data&0x0800)==0x0000)
5248 printf("[DVBS]: ISRC Calculate Done ===========: Fail. \n");
5249 else
5250 printf("[DVBS]: ISRC Calculate Done ===========: OK. \n");
5251
5252 if ((u16Data&0x1000)==0x0000)
5253 printf("[DVBS]: Syncd Check Error =============: Fail. \n");
5254 else
5255 printf("[DVBS]: Syncd Check Error =============: OK. \n");
5256
5257 //if ((u16Data&0x2000)==0x0000)
5258 // printf("[DVBS]: Syncd Check Error======: Fail. \n");
5259 //else
5260 // printf("[DVBS]: Syncd Check Error======: OK. \n");
5261
5262 if ((u16Data&0x4000)==0x0000)
5263 printf("[DVBS]: Demap Init ====================: Fail. \n");
5264 else
5265 printf("[DVBS]: Demap Init ====================: OK. \n");
5266 */
5267 //Spectrum Information
5268 printf("------------------------------------------------------------------------\n");
5269
5270 u16Address = 0x2836;
5271 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5272 psd_smooth_factor=(u16Data>>8)&0x7F;
5273
5274 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
5275 u16Data = u8Data;
5276 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
5277 u16Data = (u16Data<<8)|u8Data;
5278 u32temp5=u16Data;
5279 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13H, &u8Data);
5280 u16Data = u8Data;
5281 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
5282 u16Data = (u16Data<<8)|u8Data;
5283 u32temp5|=(u16Data<<16);
5284 if (psd_smooth_factor!=0)
5285 srd_left_top_value=(float)u32temp5/256.0/psd_smooth_factor;
5286 else
5287 srd_left_top_value=0;
5288
5289 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
5290 u16Data = u8Data;
5291 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
5292 u16Data = (u16Data<<8)|u8Data;
5293 u32temp5=u16Data;
5294 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
5295 u16Data = u8Data;
5296 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
5297 u16Data = (u16Data<<8)|u8Data;
5298 u32temp5|=(u16Data<<16);
5299 if (psd_smooth_factor!=0)
5300 srd_left_bottom_value=(float)u32temp5/256.0/psd_smooth_factor;
5301 else
5302 srd_left_bottom_value=0;
5303
5304 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
5305 u16Data = u8Data;
5306 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
5307 u16Data = (u16Data<<8)|u8Data;
5308 u32temp5=u16Data;
5309 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE17H, &u8Data);
5310 u16Data = u8Data;
5311 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE17L, &u8Data);
5312 u16Data = (u16Data<<8)|u8Data;
5313 u32temp5|=(u16Data<<16);
5314 if (psd_smooth_factor!=0)
5315 srd_right_top_value=(float)u32temp5/256.0/psd_smooth_factor;
5316 else
5317 srd_right_top_value=0;
5318
5319 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18H, &u8Data);
5320 u16Data = u8Data;
5321 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18L, &u8Data);
5322 u16Data = (u16Data<<8)|u8Data;
5323 u32temp5=u16Data;
5324 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19H, &u8Data);
5325 u16Data = u8Data;
5326 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19L, &u8Data);
5327 u16Data = (u16Data<<8)|u8Data;
5328 u32temp5|=(u16Data<<16);
5329 if (psd_smooth_factor!=0)
5330 srd_right_bottom_value=(float)u32temp5/256.0/psd_smooth_factor;
5331 else
5332 srd_right_bottom_value=0;
5333
5334 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1AH, &u8Data);
5335 u16Data = u8Data;
5336 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1AL, &u8Data);
5337 u16Data = (u16Data<<8)|u8Data;
5338 srd_left=u16Data;
5339 printf("[DVBS]: FFT Left ======================: %d, %f\n", srd_left, srd_left_top_value - srd_left_bottom_value);
5340 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1BH, &u8Data);
5341 u16Data = u8Data;
5342 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1BL, &u8Data);
5343 u16Data = (u16Data<<8)|u8Data;
5344 srd_right=u16Data;
5345 printf("[DVBS]: FFT Right =====================: %d, %f\n", srd_right, srd_right_top_value - srd_right_bottom_value);
5346 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1CH, &u8Data);
5347 u16Data = u8Data;
5348 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1CL, &u8Data);
5349 u16Data = (u16Data<<8)|u8Data;
5350 srd_left_top=u16Data;
5351 printf("[DVBS]: FFT Left Top ==================: %d, %f\n", srd_left_top, srd_left_top_value);
5352 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1DH, &u8Data);
5353 u16Data = u8Data;
5354 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1DL, &u8Data);
5355 u16Data = (u16Data<<8)|u8Data;
5356 srd_left_bottom=u16Data;
5357 printf("[DVBS]: FFT Left Bottom ===============: %d, %f\n", srd_left_bottom, srd_left_bottom_value);
5358 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1EH, &u8Data);
5359 u16Data = u8Data;
5360 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1EL, &u8Data);
5361 u16Data = (u16Data<<8)|u8Data;
5362 srd_right_top=u16Data;
5363 printf("[DVBS]: FFT Right Top =================: %d, %f\n", srd_right_top, srd_right_top_value);
5364 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1FH, &u8Data);
5365 u16Data = u8Data;
5366 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1FL, &u8Data);
5367 u16Data = (u16Data<<8)|u8Data;
5368 srd_right_bottom=u16Data;
5369 printf("[DVBS]: FFT Right Bottom ==============: %d, %f\n", srd_right_bottom, srd_right_bottom_value);
5370
5371 printf("-----------------------------------------\n");
5372 printf("[DVBS]: Left-Bottom ===================: %d\n", srd_left-srd_left_bottom);
5373 printf("[DVBS]: Left-Top ======================: %d\n", srd_left_top - srd_left);
5374 printf("[DVBS]: Right-Top =====================: %d\n", srd_right - srd_right_top);
5375 printf("[DVBS]: Right-Bottom ==================: %d\n", srd_right_bottom - srd_right);
5376
5377 if (psd_smooth_factor!=0)
5378 {
5379 if ((srd_left_top-srd_left_bottom)!=0)
5380 printf("[DVBS]: Left Slope ====================: %f\n", (srd_left_top_value - srd_left_bottom_value)/(srd_left_top-srd_left_bottom));
5381 else
5382 printf("[DVBS]: Left Slope ====================: %f\n", 0.000000);
5383
5384 if((srd_right_bottom - srd_right_top)!=0)
5385 printf("[DVBS]: Right Slope ===================: %f\n", (srd_right_top_value - srd_right_bottom_value)/(srd_right_bottom - srd_right_top));
5386 else
5387 printf("[DVBS]: Right Slope ===================: %f\n", 0.000000);
5388
5389 if (((srd_right_top_value - srd_right_bottom_value)!=0)&&((srd_right_bottom - srd_right_top))!=0)
5390 printf("[DVBS]: Slope Ratio ===================: %f\n", ((srd_left_top_value - srd_left_bottom_value)/(srd_left_top-srd_left_bottom))/((srd_right_top_value - srd_right_bottom_value)/(srd_right_bottom - srd_right_top)));
5391 else
5392 printf("[DVBS]: Slope Ratio ===================: %f\n", 0.000000);
5393 }
5394 else
5395 {
5396 printf("[DVBS]: Left Slope ======================: %d\n", 0);
5397 printf("[DVBS]: Right Slope =====================: %d\n", 0);
5398 printf("[DVBS]: Slope Ratio =====================: %d\n", 0);
5399 }
5400 #endif
5401 return status;
5402 }
5403
INTERN_DVBS_Demod_Get_Debug_Info_polling(void)5404 MS_BOOL INTERN_DVBS_Demod_Get_Debug_Info_polling(void)
5405 {
5406 MS_BOOL bRet = FALSE;
5407 #if 0
5408 MS_U8 u8Data = 0;
5409 MS_U16 u16Data = 0;
5410 MS_U16 u16Address = 0;
5411 MS_U32 u32DebugInfo_Fb = 0; //Fb, SymbolRate
5412 MS_U32 u32DebugInfo_Fs = 96000; //Fs, 96000k
5413 float AGC_IF_Gain;
5414 float DAGC0_Gain, DAGC1_Gain, DAGC2_Gain, DAGC3_Gain, DAGC0_Peak_Mean, DAGC1_Peak_Mean, DAGC2_Peak_Mean, DAGC3_Peak_Mean;
5415 short AGC_Err, DAGC0_Err, DAGC1_Err, DAGC2_Err, DAGC3_Err;
5416 float DCR_Offset_I, DCR_Offset_Q;
5417 float FineCFO_loop_input_value, FineCFO_loop_out_value;
5418 double FineCFO_loop_ki_value, TR_loop_ki;
5419 float PR_in_value, PR_out_value, PR_loop_ki, PR_loopback_ki;
5420 float IQB_Phase, IQB_Gain;
5421 MS_U16 IIS_cnt, ConvegenceLen;
5422 float Linear_SNR_dd, SNR_dd_dB, Linear_SNR_da, SNR_da_dB, SNR_nda_dB, Linear_SNR;
5423 float Packet_Err, BER;
5424 float TR_Indicator_ff, TR_SFO_Converge, Fs_value, Fb_value;
5425 float TR_Loop_Output, TR_Loop_Ki, TR_loop_input, TR_tmp0, TR_tmp1, TR_tmp2;
5426 float Eq_variance_da, Eq_variance_dd;
5427 float ndasnr_ratio, ndasnr_a, ndasnr_ab;
5428 MS_U16 BitErr, BitErrPeriod;
5429 MS_BOOL BEROver;
5430
5431 //Fb
5432 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5433 //bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
5434 if((u8Data&0x02)==0x00) //Manual Tune
5435 {
5436 u32DebugInfo_Fb = 0x0;//_u32CurrentSR;
5437 }
5438 else //Blind Scan
5439 {
5440 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
5441 u16Data = u8Data;
5442 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
5443 u16Data = (u16Data<<8)|u8Data;
5444 u32DebugInfo_Fb = u16Data;
5445 }
5446 printf("++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
5447 printf("Fs ====================================: %lu [kHz]\n",u32DebugInfo_Fs);
5448 printf("Fb ====================================: %lu [kHz]\n",u32DebugInfo_Fb);
5449 //---------------------------------------------------------
5450 //Page1-GAIN & DCR
5451 //---------------------------------------------------------
5452 //GAIN
5453 printf("\n");
5454 printf("========================================================================\n");
5455 printf("Debug Message [GAIN & DCR]==============================================\n");
5456
5457 //Debug select
5458 u16Address = (DEBUG_SEL_IF_AGC_GAIN>>16)&0xffff;
5459 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5460 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_IF_AGC_GAIN)&0xffff);
5461 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5462
5463 //Freeze and dump
5464 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5465 //AGC_IF_GAIN
5466 u16Address = (DEBUG_OUT_AGC)&0xffff;
5467 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5468 AGC_IF_Gain=u16Data;
5469 //Unfreeze
5470 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5471
5472 AGC_IF_Gain=AGC_IF_Gain/0x8000; //(16, 15)
5473 printf("[DVBS]: AGC_IF_Gain ===================: %f\n", AGC_IF_Gain);
5474 //---------------------------------------------------------
5475 //Debug select
5476 u16Address = (DEBUG_SEL_DAGC0_GAIN>>16)&0xffff;
5477 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5478 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_GAIN)&0xffff);
5479 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5480
5481 //Freeze and dump
5482 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5483 //DAGC0_GAIN
5484 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
5485 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5486 u16Data = (u16Data>>4);
5487 DAGC0_Gain=(u16Data&0x0fff);
5488 //Unfreeze
5489 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5490 //---------------------------------------------------------
5491 //Debug select
5492 u16Address = (DEBUG_SEL_DAGC1_GAIN>>16)&0xffff;
5493 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5494 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_GAIN)&0xffff);
5495 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5496
5497 //Freeze and dump
5498 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5499 //DAGC1_GAIN
5500 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
5501 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5502 DAGC1_Gain=(u16Data&0x07ff);
5503 //Unfreeze
5504 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5505 //---------------------------------------------------------
5506 //Debug select
5507 u16Address = (DEBUG_SEL_DAGC2_GAIN>>16)&0xffff;
5508 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5509 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_GAIN)&0xffff);
5510 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5511
5512 //Freeze and dump
5513 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5514 //DAGC2_GAIN
5515 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
5516 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5517 DAGC2_Gain=(u16Data&0x0fff);
5518 //Unfreeze
5519 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5520 //---------------------------------------------------------
5521 //Debug select
5522 u16Address = (DEBUG_SEL_DAGC3_GAIN>>16)&0xffff;
5523 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5524 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_GAIN)&0xffff);
5525 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5526
5527 //Freeze and dump
5528 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5529 //DAGC3_GAIN
5530 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
5531 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5532 u16Data = (u16Data>>4);
5533 DAGC3_Gain=(u16Data&0x0fff);
5534 //Unfreeze
5535 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5536 //---------------------------------------------------------
5537
5538 DAGC0_Gain=DAGC0_Gain/0x200; //<12,9>
5539 DAGC1_Gain=DAGC1_Gain/0x200; //<11,9>
5540 DAGC2_Gain=DAGC2_Gain/0x200; //<12,9>
5541 DAGC3_Gain=DAGC3_Gain/0x200; //<12,9>
5542 printf("[DVBS]: DAGC0_Gain ====================: %f\n", DAGC0_Gain);
5543 printf("[DVBS]: DAGC1_Gain ====================: %f\n", DAGC1_Gain);
5544 printf("[DVBS]: DAGC2_Gain ====================: %f\n", DAGC2_Gain);
5545 printf("[DVBS]: DAGC3_Gain ====================: %f\n", DAGC3_Gain);
5546
5547 //---------------------------------------------------------
5548 //ERROR
5549 //Debug select
5550 u16Address = (DEBUG_SEL_AGC_ERR>>16)&0xffff;
5551 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5552 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_AGC_ERR)&0xffff);
5553 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5554
5555 //Freeze and dump
5556 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5557 //AGC_ERR
5558 u16Address = (DEBUG_OUT_AGC)&0xffff;
5559 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5560 AGC_Err=(u16Data&0x03ff);
5561 //Unfreeze
5562 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5563
5564 //Debug select
5565 u16Address = (DEBUG_SEL_DAGC0_ERR>>16)&0xffff;
5566 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5567 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_ERR)&0xffff);
5568 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5569
5570 //Freeze and dump
5571 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5572 //DAGC0_ERR
5573 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
5574 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5575 u16Data = (u16Data>>4);
5576 DAGC0_Err=(u16Data&0x7fff);
5577 //Unfreeze
5578 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5579
5580 //Debug select
5581 u16Address = (DEBUG_SEL_DAGC1_ERR>>16)&0xffff;
5582 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5583 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_ERR)&0xffff);
5584 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5585
5586 //Freeze and dump
5587 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5588 //DAGC1_ERR
5589 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
5590 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5591 DAGC1_Err=(u16Data&0x7fff);
5592 //Unfreeze
5593 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5594
5595 //Debug select
5596 u16Address = (DEBUG_SEL_DAGC2_ERR>>16)&0xffff;
5597 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5598 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_ERR)&0xffff);
5599 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5600
5601 //Freeze and dump
5602 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5603 //DAGC2_ERR
5604 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
5605 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5606 DAGC2_Err=(u16Data&0x7fff);
5607 //Unfreeze
5608 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5609
5610 //Debug select
5611 u16Address = (DEBUG_SEL_DAGC3_ERR>>16)&0xffff;
5612 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5613 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_ERR)&0xffff);
5614 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5615
5616 //Freeze and dump
5617 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5618 //DAGC3_ERR
5619 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
5620 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5621 u16Data = (u16Data>>4);
5622 DAGC3_Err=(u16Data&0x7fff);
5623 //Unfreeze
5624 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5625
5626 if (AGC_Err>=0x200)
5627 AGC_Err=AGC_Err-0x400;
5628 if (DAGC0_Err>=0x4000)
5629 DAGC0_Err=DAGC0_Err-0x8000;
5630 if (DAGC1_Err>=0x4000)
5631 DAGC1_Err=DAGC1_Err-0x8000;
5632 if (DAGC2_Err>=0x4000)
5633 DAGC2_Err=DAGC2_Err-0x8000;
5634 if (DAGC3_Err>=0x4000)
5635 DAGC3_Err=DAGC3_Err-0x8000;
5636
5637 printf("[DVBS]: AGC_Err =========================: %.3f\n", (float)AGC_Err);
5638 printf("[DVBS]: DAGC0_Err =======================: %.3f\n", (float)DAGC0_Err);
5639 printf("[DVBS]: DAGC1_Err =======================: %.3f\n", (float)DAGC1_Err);
5640 printf("[DVBS]: DAGC2_Err =======================: %.3f\n", (float)DAGC2_Err);
5641 printf("[DVBS]: DAGC3_Err =======================: %.3f\n", (float)DAGC3_Err);
5642 //---------------------------------------------------------
5643 //PEAK_MEAN
5644 //Debug select
5645 u16Address = (DEBUG_SEL_DAGC0_PEAK_MEAN>>16)&0xffff;
5646 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5647 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_PEAK_MEAN)&0xffff);
5648 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5649
5650 //Freeze and dump
5651 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5652 //DAGC0_PEAK_MEAN
5653 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
5654 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5655 u16Data = (u16Data>>4);
5656 DAGC0_Peak_Mean=(u16Data&0x0fff);
5657 //Unfreeze
5658 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5659
5660 //Debug select
5661 u16Address = (DEBUG_SEL_DAGC1_PEAK_MEAN>>16)&0xffff;
5662 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5663 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_PEAK_MEAN)&0xffff);
5664 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5665
5666 //Freeze and dump
5667 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5668 //DAGC1_PEAK_MEAN
5669 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
5670 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5671 DAGC1_Peak_Mean=(u16Data&0x0fff);
5672 //Unfreeze
5673 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5674
5675 //Debug select
5676 u16Address = (DEBUG_SEL_DAGC2_PEAK_MEAN>>16)&0xffff;
5677 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5678 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_PEAK_MEAN)&0xffff);
5679 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5680
5681 //Freeze and dump
5682 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5683 //DAGC2_PEAK_MEAN
5684 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
5685 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5686 DAGC2_Peak_Mean=(u16Data&0x0fff);
5687 //Unfreeze
5688 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5689
5690 //Debug select
5691 u16Address = (DEBUG_SEL_DAGC3_PEAK_MEAN>>16)&0xffff;
5692 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5693 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_PEAK_MEAN)&0xffff);
5694 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5695
5696 //Freeze and dump
5697 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5698 //DAGC3_PEAK_MEAN
5699 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
5700 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5701 u16Data = (u16Data>>4);
5702 DAGC3_Peak_Mean=(u16Data&0x0fff);
5703 //Unfreeze
5704 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5705
5706
5707 DAGC0_Peak_Mean = DAGC0_Peak_Mean / 0x800; //<12,11>
5708 DAGC1_Peak_Mean = DAGC1_Peak_Mean / 0x800; //<12,11>
5709 DAGC2_Peak_Mean = DAGC2_Peak_Mean / 0x800; //<12,11>
5710 DAGC3_Peak_Mean = DAGC3_Peak_Mean / 0x800; //<12,11>
5711
5712 printf("[DVBS]: DAGC0_Peak_Mean ===============: %f\n", DAGC0_Peak_Mean);
5713 printf("[DVBS]: DAGC1_Peak_Mean ===============: %f\n", DAGC1_Peak_Mean);
5714 printf("[DVBS]: DAGC2_Peak_Mean ===============: %f\n", DAGC2_Peak_Mean);
5715 printf("[DVBS]: DAGC3_Peak_Mean ===============: %f\n", DAGC3_Peak_Mean);
5716 //---------------------------------------------------------
5717 //Freeze and dump
5718 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5719
5720 u16Address = (DCR_OFFSET)&0xffff;
5721 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5722
5723 DCR_Offset_I=(u16Data&0xff);
5724 if (DCR_Offset_I >= 0x80)
5725 DCR_Offset_I = DCR_Offset_I-0x100;
5726 DCR_Offset_I = DCR_Offset_I/0x80;
5727
5728 DCR_Offset_Q=(u16Data>>8)&0xff;
5729 if (DCR_Offset_Q >= 0x80)
5730 DCR_Offset_Q = DCR_Offset_Q-0x100;
5731 DCR_Offset_Q = DCR_Offset_Q/0x80;
5732
5733 //Unfreeze
5734 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5735
5736 printf("[DVBS]: DCR_Offset_I ==================: %f\n", DCR_Offset_I);
5737 printf("[DVBS]: DCR_Offset_Q ==================: %f\n", DCR_Offset_Q);
5738 //---------------------------------------------------------
5739 ////Page1-FineCFO & PR & IIS & IQB
5740 //---------------------------------------------------------
5741 //FineCFO
5742 printf("------------------------------------------------------------------------\n");
5743 printf("Debug Message [FineCFO & PR & IIS & IQB & SNR Status]===================\n");
5744 //Debug Select
5745 u16Address = INNER_DEBUG_SEL;
5746 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5747 u16Data=((u16Data&0xC0FF)|0x0400);
5748 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5749
5750 //Freeze and dump
5751 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5752
5753 u16Address = INNEREXT_FINEFE_DBG_OUT0;
5754 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5755 FineCFO_loop_out_value=u16Data;
5756 u16Address = INNEREXT_FINEFE_DBG_OUT2;
5757 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5758 FineCFO_loop_out_value=(FineCFO_loop_out_value+(float)u16Data*pow(2.0, 16));
5759
5760 //Too large.Use 10Bit
5761 u16Address = INNEREXT_FINEFE_KI_FF0;
5762 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5763 FineCFO_loop_ki_value=u16Data;
5764 u16Address = INNEREXT_FINEFE_KI_FF2;
5765 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5766 FineCFO_loop_ki_value=(FineCFO_loop_ki_value+(float)u16Data*pow(2.0, 16));
5767 u16Address = INNEREXT_FINEFE_KI_FF4;
5768 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5769 FineCFO_loop_ki_value=(FineCFO_loop_ki_value+(double)(u16Data&0x00FF)*pow(2.0, 32));
5770 //Unfreeze
5771 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5772
5773 //---------------------------------------------------------
5774 //Debug Select
5775 u16Address = INNER_DEBUG_SEL;
5776 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5777 u16Data=((u16Data&0xC0FF)|0x0100);
5778 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5779
5780 //Freeze and dump
5781 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5782
5783 u16Address = INNEREXT_FINEFE_DBG_OUT0;
5784 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5785 FineCFO_loop_input_value=u16Data;
5786 u16Address = INNEREXT_FINEFE_DBG_OUT2;
5787 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5788 FineCFO_loop_input_value=(FineCFO_loop_input_value+(float)u16Data*pow(2.0, 16));
5789
5790 //Unfreeze
5791 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5792
5793 FineCFO_loop_ki_value = FineCFO_loop_ki_value/1024;
5794
5795 if (FineCFO_loop_out_value > 8388608)
5796 FineCFO_loop_out_value=FineCFO_loop_out_value - 16777216;
5797 if (FineCFO_loop_ki_value > 536870912)//549755813888/1024)
5798 FineCFO_loop_ki_value=FineCFO_loop_ki_value - 1073741824;//1099511627776/1024;
5799 if (FineCFO_loop_input_value> 1048576)
5800 FineCFO_loop_input_value=FineCFO_loop_input_value - 2097152;
5801
5802 FineCFO_loop_out_value = ((float)FineCFO_loop_out_value/16777216);
5803 FineCFO_loop_ki_value = ((double)FineCFO_loop_ki_value/67108864*u32DebugInfo_Fb);//68719476736/1024*Fb
5804 FineCFO_loop_input_value = ((float)FineCFO_loop_input_value/2097152);
5805
5806 printf("[DVBS]: FineCFO_loop_out_value ========: %f \n", FineCFO_loop_out_value);
5807 printf("[DVBS]: FineCFO_loop_ki_value =========: %f \n", FineCFO_loop_ki_value);
5808 printf("[DVBS]: FineCFO_loop_input_value ======: %f \n", FineCFO_loop_input_value);
5809
5810 //---------------------------------------------------------
5811 //Phase Recovery
5812 //Debug select
5813 u16Address = INNER_DEBUG_SEL;
5814 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5815 u16Data=(((u16Data&0x00FF)|0x0600)&0xffff);
5816 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5817
5818 //Freeze and dump
5819 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5820
5821 u16Address = INNER_PR_DEBUG_OUT0;
5822 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5823 PR_out_value=u16Data;
5824 if (PR_out_value>=0x1000)
5825 PR_out_value=PR_out_value-0x2000;
5826
5827 //Unfreeze
5828 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5829 //---------------------------------------------------------
5830 //Debug select
5831 u16Address = INNER_DEBUG_SEL;
5832 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5833 u16Data=(((u16Data&0x00FF)|0x0100)&0xffff);
5834 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5835
5836 //Freeze and dump
5837 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5838
5839 u16Address = INNER_PR_DEBUG_OUT0;
5840 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5841 PR_in_value=u16Data;
5842 u16Address = INNER_PR_DEBUG_OUT2;
5843 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5844 PR_in_value=(((u16Data&0x000F)<<16)|(MS_U16)PR_in_value);
5845 if (PR_in_value>=0x80000)
5846 PR_in_value=PR_in_value-0x100000;
5847
5848 //Unfreeze
5849 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5850 //---------------------------------------------------------
5851 //Debug select
5852 u16Address = INNER_DEBUG_SEL;
5853 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5854 u16Data=(((u16Data&0xC0FF)|0x0400)&0xffff);
5855 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5856
5857 //Freeze and dump
5858 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5859
5860 u16Address = INNER_PR_DEBUG_OUT0;
5861 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5862 PR_loop_ki=u16Data;
5863 u16Address = INNER_PR_DEBUG_OUT2;
5864 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5865 PR_loop_ki=(((u16Data&0x00FF)<<16)+PR_loop_ki);
5866 if (PR_loop_ki>=0x800000)
5867 PR_loop_ki=PR_loop_ki-0x1000000;
5868
5869 //Unfreeze
5870 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5871 //---------------------------------------------------------
5872 //Debug select
5873 u16Address = INNER_DEBUG_SEL;
5874 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5875 u16Data=(((u16Data&0x00FF)|0x0500)&0xffff);
5876 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5877
5878 //Freeze and dump
5879 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5880
5881 u16Address = INNER_PR_DEBUG_OUT0;
5882 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5883 PR_loopback_ki=u16Data;
5884 u16Address = INNER_PR_DEBUG_OUT2;
5885 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5886 PR_loopback_ki=(((u16Data&0x00FF)<<16)+PR_loopback_ki);
5887 if (PR_loopback_ki>=0x800000)
5888 PR_loopback_ki=PR_loopback_ki-0x1000000;
5889
5890 //Unfreeze
5891 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5892
5893 PR_out_value = ((float)PR_out_value/4096);
5894 PR_in_value = ((float)PR_in_value/131072);
5895 PR_loop_ki = ((float)PR_loop_ki/67108864*u32DebugInfo_Fb);
5896 PR_loopback_ki = ((float)PR_loopback_ki/67108864*u32DebugInfo_Fb);
5897
5898 printf("[DVBS]: PR_out_value ==================: %f\n", PR_out_value);
5899 printf("[DVBS]: PR_in_value ===================: %f\n", PR_in_value);
5900 printf("[DVBS]: PR_loop_ki ====================: %f\n", PR_loop_ki);
5901 printf("[DVBS]: PR_loopback_ki ================: %f\n", PR_loopback_ki);
5902 //---------------------------------------------------------
5903 //IIS
5904 //Freeze and dump
5905 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5906
5907 u16Address = (IIS_COUNT0)&0xffff;
5908 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5909 IIS_cnt=u16Data;
5910 u16Address = (IIS_COUNT2)&0xffff;
5911 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5912 IIS_cnt=(u16Data&0x1f)<<16|IIS_cnt;
5913
5914 printf("[DVBS]: IIS_cnt =======================: %d\n", IIS_cnt);
5915
5916 //Unfreeze
5917 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5918 //IQB
5919 //Freeze and dump
5920 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5921
5922 u16Address = (IQB_PHASE)&0xffff;
5923 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5924 IQB_Phase=u16Data&0x3FF;
5925 if (IQB_Phase>=0x200)
5926 IQB_Phase=IQB_Phase-0x400;
5927 IQB_Phase=IQB_Phase/0x400*180;
5928
5929 u16Address = (IQB_GAIN)&0xffff;
5930 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5931 IQB_Gain=u16Data&0x7FF;
5932 IQB_Gain=IQB_Gain/0x400;
5933
5934 printf("[DVBS]: IQB_Phase =====================: %f\n", IQB_Phase);
5935 printf("[DVBS]: IQB_Gain ======================: %f\n", IQB_Gain);
5936
5937 //Unfreeze
5938 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5939 //---------------------------------------------------------
5940 //SNR
5941 //Freeze and dump
5942 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5943
5944 Eq_variance_da=0;
5945 u16Address = 0x249E;
5946 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5947 Eq_variance_da=u16Data;
5948 u16Address = 0x24A0;
5949 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5950 Eq_variance_da=((float)(u16Data&0x03fff)*pow(2.0, 16)+Eq_variance_da)/pow(2.0, 29);
5951
5952 if (Eq_variance_da==0)
5953 Eq_variance_da=1;
5954 Linear_SNR_da=1.0/Eq_variance_da;
5955 SNR_da_dB=10*log10(Linear_SNR_da);
5956
5957 Eq_variance_dd=0;
5958 u16Address = 0x24A2;
5959 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5960 Eq_variance_dd=u16Data;
5961 u16Address = 0x24A4;
5962 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5963 Eq_variance_dd=(((float)(u16Data&0x3fff)*65536)+Eq_variance_dd)/pow(2.0, 29);
5964
5965 if (Eq_variance_dd==0)
5966 Eq_variance_dd=1;
5967 Linear_SNR_dd=1.0/Eq_variance_dd;
5968 SNR_dd_dB=10*log10(Linear_SNR_dd);
5969
5970 ndasnr_a=0;
5971 u16Address = 0x248C;
5972 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5973 ndasnr_a=u16Data;
5974 u16Address = 0x248E;
5975 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5976 ndasnr_a=(((float)(u16Data&0x0003)*pow(2.0, 16))+ndasnr_a)/65536;
5977
5978 ndasnr_ab=0;
5979 u16Address = 0x2490;
5980 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5981 ndasnr_ab=u16Data;
5982 u16Address = 0x2492;
5983 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5984 ndasnr_ab=(((float)(u16Data&0x03ff)*pow(2.0, 16))+ndasnr_ab)/4194304;
5985
5986 ndasnr_ab=sqrt(ndasnr_ab);
5987 if (ndasnr_ab==0)
5988 ndasnr_ab=1;
5989 ndasnr_ratio=(float)ndasnr_a/ndasnr_ab;
5990 if (ndasnr_ratio> 1)
5991 SNR_nda_dB=10*log10(1/(ndasnr_ratio - 1));
5992 else
5993 SNR_nda_dB=0;
5994
5995 u16Address = 0x24BA;
5996 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5997 Linear_SNR=u16Data;
5998 u16Address = 0x24BC;
5999 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6000 Linear_SNR=(((float)(u16Data&0x0007)*pow(2.0, 16))+Linear_SNR)/64;
6001 if (Linear_SNR==0)
6002 Linear_SNR=1;
6003 Linear_SNR=10*log10(Linear_SNR);
6004
6005 //Unfreeze
6006 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
6007 printf("[DVBS]: SNR ===========================: %.2f\n", Linear_SNR);
6008 printf("[DVBS]: SNR_DA_dB =====================: %.2f\n", SNR_da_dB);
6009 printf("[DVBS]: SNR_DD_dB =====================: %.2f\n", SNR_dd_dB);
6010 printf("[DVBS]: SNR_NDA_dB ====================: %.2f\n", SNR_nda_dB);
6011 //---------------------------------------------------------
6012 printf("------------------------------------------------------------------------\n");
6013 printf("Debug Message [DVBS - PacketErr & BER]==================================\n");
6014 //BER
6015 //freeze
6016 u16Address = 0x2103;
6017 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6018 u16Data=u16Data|0x0001;
6019 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6020
6021 // bank 17 0x18 [7:0] reg_bit_err_sblprd_7_0 [15:8] reg_bit_err_sblprd_15_8
6022 u16Address = 0x2166;
6023 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6024 Packet_Err=u16Data;
6025
6026 printf("[DVBS]: Packet Err ====================: %.3E\n", Packet_Err);
6027
6028 /////////// Post-Viterbi BER /////////////
6029 // bank 7 0x18 [7:0] reg_bit_err_sblprd_7_0
6030 // [15:8] reg_bit_err_sblprd_15_8
6031 u16Address = 0x2146;
6032 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6033 BitErrPeriod=u16Data;
6034
6035 // bank 17 0x1D [7:0] reg_bit_err_num_7_0 [15:8] reg_bit_err_num_15_8
6036 // bank 17 0x1E [7:0] reg_bit_err_num_23_16 [15:8] reg_bit_err_num_31_24
6037 u16Address = 0x216A;
6038 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6039 BitErr=u16Data;
6040 u16Address = 0x216C;
6041 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6042 BitErr=(u16Data<<16)|BitErr;
6043
6044 if (BitErrPeriod ==0 )//protect 0
6045 BitErrPeriod=1;
6046 if (BitErr <=0 )
6047 BER=0.5 / (float)(BitErrPeriod*128*188*8);
6048 else
6049 BER=(float)(BitErr) / (float)(BitErrPeriod*128*188*8);
6050
6051 printf("[DVBS]: Post-Viterbi BER ==============: %.3E\n", BER);
6052
6053 // bank 7 0x19 [7] reg_bit_err_num_freeze
6054 u16Address = 0x2103;
6055 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6056 u16Data=u16Data&(~0x0001);
6057 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6058
6059 /////////// Pre-Viterbi BER /////////////
6060 // bank 17 0x08 [3] reg_rd_freezeber
6061 u16Address = 0x2110;
6062 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6063 u16Data=u16Data|0x0008;
6064 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6065
6066 // bank 17 0x0b [7:0] reg_ber_timerl [15:8] reg_ber_timerm
6067 // bank 17 0x0c [5:0] reg_ber_timerh
6068 u16Address = 0x2116;
6069 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6070 BitErrPeriod=u16Data;
6071 u16Address = 0x2118;
6072 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6073 BitErrPeriod=((u16Data&0x3f)<<16)|BitErrPeriod;
6074
6075 // bank 17 0x0f [7:0] reg_ber_7_0 [15:8] reg_ber_15_8
6076 u16Address = 0x211E;
6077 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6078 BitErr=u16Data;
6079
6080 // bank 17 0x0D [13:8] reg_cor_intstat_reg
6081 u16Address = 0x211A;
6082 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6083 if (u16Data & 0x1000)
6084 {
6085 BEROver = true;
6086 }
6087 else
6088 {
6089 BEROver = false;
6090 }
6091
6092 if (BitErrPeriod ==0 )//protect 0
6093 BitErrPeriod=1;
6094 if (BitErr <=0 )
6095 BER=0.5 / (float)(BitErrPeriod) / 256;
6096 else
6097 BER=(float)(BitErr) / (float)(BitErrPeriod) / 256;
6098 printf("[DVBS]: Pre-Viterbi BER ===============: %.3E\n", BER);
6099
6100 // bank 17 0x08 [3] reg_rd_freezeber
6101 u16Address = 0x2110;
6102 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6103 u16Data=u16Data&(~0x0008);
6104 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6105
6106 u16Address = 0x2188;
6107 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6108 ConvegenceLen = ((u16Data>>8)&0xFF);
6109 printf("[DVBS]: ConvegenceLen =================: %d\n", ConvegenceLen);
6110
6111 //---------------------------------------------------------
6112 //Timing Recovery
6113 //Debug select
6114 u16Address = (INNER_DEBUG_SEL_TR>>16)&0xffff;
6115 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6116 u16Data=(((u16Data&0x00ff)|INNER_DEBUG_SEL_TR)&0xffff);
6117 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6118
6119 //Freeze and dump
6120 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
6121
6122 u16Address = (TR_INDICATOR_FF0)&0xffff;
6123 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6124 TR_Indicator_ff=u16Data;
6125 u16Address = (TR_INDICATOR_FF0)&0xffff;
6126 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6127 TR_Indicator_ff=((u16Data<<16) | (MS_U16)TR_Indicator_ff)&0x7fffff;
6128 if (TR_Indicator_ff >= 0x400000)
6129 TR_Indicator_ff=TR_Indicator_ff - 0x800000;
6130
6131 //Unfreeze
6132 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
6133
6134 //Debug select
6135 u16Address = (DEBUG_SEL_TR_SFO_CONVERGE>>16)&0xffff;
6136 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6137 u16Data=(((u16Data&0x00ff)|DEBUG_SEL_TR_SFO_CONVERGE)&0xffff);
6138 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6139
6140 //Freeze and dump
6141 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
6142
6143 u16Address = (TR_INDICATOR_FF0)&0xffff;
6144 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6145 TR_SFO_Converge=u16Data;
6146 u16Address = (TR_INDICATOR_FF0)&0xffff;
6147 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6148 TR_SFO_Converge=((u16Data<<16) | (MS_U16)TR_SFO_Converge)&0x7fffff;
6149 if (TR_SFO_Converge >= 0x400000)
6150 TR_SFO_Converge=TR_SFO_Converge - 0x800000;
6151
6152 u16Address = INNER_TR_LOPF_VALUE_DEBUG0;
6153 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6154 TR_loop_ki=u16Data;
6155 u16Address = INNER_TR_LOPF_VALUE_DEBUG2;
6156 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6157 TR_loop_ki=((float)u16Data*pow(2.0, 16))+TR_loop_ki;
6158 u16Address = INNER_TR_LOPF_VALUE_DEBUG4;
6159 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6160 TR_loop_ki=(((double)(u16Data&0x01ff)*pow(2.0, 32))+ TR_loop_ki);
6161 if (TR_loop_ki>=pow(2.0, 40))
6162 TR_loop_ki=TR_loop_ki-pow(2.0, 41);
6163
6164 //Unfreeze
6165 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
6166
6167 //Debug select
6168 u16Address = (DEBUG_SEL_TR_INPUT>>16)&0xffff;
6169 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6170 u16Data=(((u16Data&0x00ff)|DEBUG_SEL_TR_INPUT)&0xffff);
6171 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6172
6173 //Freeze and dump
6174 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
6175
6176 u16Address = (TR_INDICATOR_FF0)&0xffff;
6177 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6178 TR_loop_input=u16Data;
6179 //banknum=(TR_INDICATOR_FF1>>8)&0xff;
6180 //addr=(TR_INDICATOR_FF1)&0xff;
6181 //if(InformRead(banknum, addr, &data)==FALSE) return;
6182 //TR_loop_input=((float)((data&0x00ff)<<16) + TR_loop_input);
6183 if (TR_loop_input >= 0x8000)
6184 TR_loop_input=TR_loop_input - 0x10000;
6185
6186 //Unfreeze
6187 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
6188
6189 Fs_value=u32DebugInfo_Fs;
6190 Fb_value=u32DebugInfo_Fb;
6191 TR_tmp0=(float)TR_SFO_Converge/0x200000;
6192 TR_tmp2=TR_loop_ki/pow(2.0, 39);
6193 TR_tmp1=(float)Fs_value/2/Fb_value;
6194
6195 TR_Indicator_ff = (TR_Indicator_ff/0x400);
6196 TR_Loop_Output = (TR_tmp0/TR_tmp1*1000000);
6197 TR_Loop_Ki = (TR_tmp2/TR_tmp1*1000000);
6198 TR_loop_input = (TR_loop_input/0x8000);
6199
6200 printf("[DVBS]: TR_Indicator_ff================: %f \n", TR_Indicator_ff);
6201 printf("[DVBS]: TR_Loop_Output=================: %f [ppm]\n", TR_Loop_Output);
6202 printf("[DVBS]: TR_Loop_Ki=====================: %f [ppm]\n", TR_Loop_Ki);
6203 printf("[DVBS]: TR_loop_input==================: %f \n", TR_loop_input);
6204 #endif
6205 bRet=true;
6206 return bRet;
6207 }
6208
6209 //------------------------------------------------------------------
6210 // END Get And Show Info Function
6211 //------------------------------------------------------------------
6212
6213 //------------------------------------------------------------------
6214 // BlindScan Function
6215 //------------------------------------------------------------------
6216
INTERN_DVBS_BlindScan_Start(MS_U16 u16StartFreq,MS_U16 u16EndFreq)6217 MS_BOOL INTERN_DVBS_BlindScan_Start(MS_U16 u16StartFreq,MS_U16 u16EndFreq)
6218 {
6219 MS_BOOL status=TRUE;
6220 MS_U8 u8Data=0;
6221
6222 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_Start+\n"));
6223
6224 _u16BlindScanStartFreq=u16StartFreq;
6225 _u16BlindScanEndFreq=u16EndFreq;
6226 _u16TunerCenterFreq=0;
6227 _u16ChannelInfoIndex=0;
6228
6229 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_WR_DBG_90, &u8Data);
6230 u8Data &= 0xd0;
6231 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_WR_DBG_90, u8Data);
6232
6233 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)_u16BlindScanStartFreq&0x00ff);
6234 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(_u16BlindScanStartFreq>>8)&0x00ff);
6235
6236 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_Start- _u16BlindScanStartFreq%d u16StartFreq %d u16EndFreq %d\n", _u16BlindScanStartFreq, u16StartFreq, u16EndFreq));
6237
6238 return status;
6239 }
6240
INTERN_DVBS_BlindScan_NextFreq(MS_BOOL * bBlindScanEnd)6241 MS_BOOL INTERN_DVBS_BlindScan_NextFreq(MS_BOOL* bBlindScanEnd)
6242 {
6243 MS_BOOL status=TRUE;
6244 MS_U8 u8Data=0;
6245
6246 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_NextFreq+\n"));
6247
6248 * bBlindScanEnd=FALSE;
6249
6250 if (_u16TunerCenterFreq >=_u16BlindScanEndFreq)
6251 {
6252 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_NextFreq . _u16TunerCenterFreq %d _u16BlindScanEndFreq%d\n", _u16TunerCenterFreq, _u16BlindScanEndFreq));
6253 * bBlindScanEnd=TRUE;
6254
6255 return status;
6256 }
6257 //Set Tuner Frequency
6258 MsOS_DelayTask(10);
6259
6260 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_WR_DBG_90, &u8Data);
6261 if ((u8Data&0x02)==0x00)//Manual Tune
6262 {
6263 u8Data&=~(0x28);
6264 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_WR_DBG_90, u8Data);
6265 u8Data|=0x02;
6266 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_WR_DBG_90, u8Data);
6267 u8Data|=0x01;
6268 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_WR_DBG_90, u8Data);
6269 }
6270 else
6271 {
6272 u8Data&=~(0x28);
6273 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_WR_DBG_90, u8Data);
6274 }
6275
6276 return status;
6277 }
6278
INTERN_DVBS_BlindScan_GetTunerFreq(MS_U16 * u16TunerCenterFreq,MS_U16 * u16TunerCutOffFreq)6279 MS_BOOL INTERN_DVBS_BlindScan_GetTunerFreq(MS_U16 *u16TunerCenterFreq, MS_U16 *u16TunerCutOffFreq)
6280 {
6281 MS_BOOL status=TRUE;
6282 MS_U8 u8Data=0;
6283 MS_U16 u16WaitCount;
6284 MS_U16 u16TunerCutOff;
6285
6286 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_SetTunerFreq+\n"));
6287
6288 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_WR_DBG_90, &u8Data);
6289 if ((u8Data&0x02)==0x02)
6290 {
6291 u8Data|=0x08;
6292 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_WR_DBG_90, u8Data);
6293 u16WaitCount=0;
6294 do
6295 {
6296 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
6297 u16WaitCount++;
6298 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
6299 MsOS_DelayTask(1);
6300 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
6301 }
6302 else if((u8Data&0x01)==0x01)
6303 {
6304 u8Data|=0x20;
6305 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_WR_DBG_90, u8Data);
6306 u16WaitCount=0;
6307 do
6308 {
6309 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
6310 u16WaitCount++;
6311 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
6312 MsOS_DelayTask(1);
6313 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
6314 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_WR_DBG_90, &u8Data);
6315 u8Data|=0x02;
6316 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_WR_DBG_90, u8Data);
6317 }
6318 u16WaitCount=0;
6319
6320 _u16TunerCenterFreq=0;
6321
6322 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, &u8Data);
6323 //printf("INTERN_DVBS_BlindScan_GetTunerFreq E_DMD_S2_BS_Tuner_Center_Freq_H=%d\n", u8Data);//RRRRR
6324 _u16TunerCenterFreq=u8Data;
6325 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, &u8Data);
6326 //printf("INTERN_DVBS_BlindScan_GetTunerFreq E_DMD_S2_BS_Tuner_Center_Freq_L=%d\n", u8Data);//RRRRR
6327 _u16TunerCenterFreq=(_u16TunerCenterFreq<<8)|u8Data;
6328
6329 *u16TunerCenterFreq = _u16TunerCenterFreq;
6330 //claire test
6331 u16TunerCutOff=44000;
6332 if(_u16TunerCenterFreq<=990)//980
6333 {
6334
6335 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_BALANCE_TRACK, &u8Data);
6336 if(u8Data==0x01)
6337 {
6338 if(_u16TunerCenterFreq<970)//970
6339 {
6340 u16TunerCutOff=10000;
6341 }
6342 else
6343 {
6344 u16TunerCutOff=20000;
6345 }
6346 u8Data=0x02;
6347 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_BALANCE_TRACK, u8Data);
6348 }
6349 else if(u8Data==0x02)
6350 {
6351 u8Data=0x00;
6352 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_BALANCE_TRACK, u8Data);
6353 }
6354 }
6355
6356 if(u16TunerCutOffFreq != NULL)
6357 *u16TunerCutOffFreq = u16TunerCutOff;
6358
6359
6360 //end claire test
6361
6362 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_SetTunerFreq- _u16TunerCenterFreq:%d\n", _u16TunerCenterFreq));
6363
6364
6365 return status;
6366 }
6367
INTERN_DVBS_BlindScan_WaitCurFreqFinished(MS_U8 * u8Progress,MS_U8 * u8FindNum,MS_U8 * substate_reg,MS_U32 * u32Data,MS_U16 * symbolrate_reg,MS_U16 * CFO_reg)6368 MS_BOOL INTERN_DVBS_BlindScan_WaitCurFreqFinished(MS_U8* u8Progress,MS_U8 *u8FindNum, MS_U8 *substate_reg, MS_U32 *u32Data, MS_U16 *symbolrate_reg, MS_U16 *CFO_reg)
6369 {
6370 MS_BOOL status=TRUE;
6371 //MS_U32 u32Data=0;
6372 MS_U16 u16Data=0;
6373 MS_U8 u8Data=0, u8Data2=0;
6374 MS_U16 u16WaitCount;
6375
6376 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_WaitCurFreqFinished+\n"));
6377
6378 u16WaitCount=0;
6379 *u8FindNum=0;
6380 *u8Progress=0;
6381
6382 do
6383 {
6384 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data); //State=BlindScan
6385 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_BLINDSCAN_CHECK, &u8Data2); //SubState=BlindScan
6386 u16WaitCount++;
6387 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_BlindScan_WaitCurFreqFinished State: 0x%x Status: 0x%x u16WaitCount:%d\n", u8Data, u8Data2, u16WaitCount));
6388 //printf("INTERN_DVBS_BlindScan_WaitCurFreqFinished State: 0x%x Status: 0x%x u16WaitCount:%d\n", u8Data, u8Data2, u16WaitCount);
6389
6390 MsOS_DelayTask(1);
6391 }while(((u8Data!=17)||(u8Data2!=0xff))&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));//E_DMD_S2_STATE_FLAG
6392
6393
6394
6395 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DUMMY_REG_2, &u8Data);
6396 u16Data=u8Data;
6397
6398
6399 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_WaitCurFreqFinished OuterCheckStatus:0x%x\n", u16Data));
6400
6401 if (u16WaitCount>=INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
6402 {
6403 status=false;
6404 ULOGD("DEMOD","Debug blind scan wait finished time out!!!!\n");
6405 }
6406 else
6407 {
6408
6409 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SUBSTATE_FLAG, &u8Data);//SubState
6410 *substate_reg=u8Data;
6411 if (u8Data==0)
6412 {
6413
6414 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
6415 *u32Data=u8Data;
6416 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
6417 *u32Data=(*u32Data<<8)|u8Data;
6418 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
6419 *u32Data=(*u32Data<<8)|u8Data;
6420 //_u16ChannelInfoArray[0][_u16ChannelInfoIndex]=((*u32Data+500)/1000);
6421 //_u16LockedCenterFreq=((*u32Data+500)/1000); //Center Freq
6422
6423
6424 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
6425 u16Data=u8Data;
6426 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
6427 u16Data=(u16Data<<8)|u8Data;
6428 *symbolrate_reg=u16Data;
6429 //_u16ChannelInfoArray[1][_u16ChannelInfoIndex]=(u16Data);//Symbol Rate
6430 //_u16LockedSymbolRate=u16Data;
6431 //_u16ChannelInfoIndex++;
6432 //*u8FindNum=_u16ChannelInfoIndex;
6433 //printf("claire debug blind scan: find TP frequency %d SR %d index %d\n",_u16LockedCenterFreq,_u16LockedSymbolRate,_u16ChannelInfoIndex);
6434
6435
6436 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
6437 u16Data=u8Data;
6438 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
6439 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset_Locked
6440 *CFO_reg=u16Data;
6441 /*
6442 if (u16Data*1000 >= 0x8000)
6443 {
6444 u16Data=0x10000- u16Data*1000;
6445 _s16CurrentCFO=-1*u16Data/1000;
6446 }
6447 else
6448 {
6449 _s16CurrentCFO=u16Data;
6450 }
6451 */
6452 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
6453 u16Data=u8Data;
6454 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
6455 u16Data=(u16Data<<8)|u8Data;
6456 _u16CurrentStepSize=u16Data; //Tuner_Frequency_Step
6457
6458
6459 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18H, &u8Data);
6460 u16Data=u8Data;
6461 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18L, &u8Data);
6462 u16Data=(u16Data<<8)|u8Data;
6463 _u16PreLockedHB=u16Data; //Pre_Scanned_HB
6464
6465
6466 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19H, &u8Data);
6467 u16Data=u8Data;
6468 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19L, &u8Data);
6469 u16Data=(u16Data<<8)|u8Data;
6470 _u16PreLockedLB=u16Data; //Pre_Scanned_LB
6471
6472 DBG_INTERN_DVBS(ULOGD("DEMOD","Current Locked BWH:%d BWL:%d Step:%d\n ",_u16PreLockedHB, _u16PreLockedLB, _u16CurrentStepSize));
6473 }
6474 else if (u8Data==1)
6475 {
6476 DBG_INTERN_DVBS(ULOGD("DEMOD", "Debug blind scan: TP not found\n"));
6477
6478 //ULOGD("DEMOD", "Debug blind scan: TP not found\n");
6479
6480 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, &u8Data);
6481 u16Data=u8Data;
6482 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, &u8Data);
6483 u16Data=(u16Data<<8)|u8Data;
6484 _u16NextCenterFreq=u16Data;
6485
6486
6487 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
6488 u16Data=u8Data;
6489 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
6490 u16Data=(u16Data<<8)|u8Data;
6491 _u16PreLockedHB=u16Data; //Pre_Scanned_HB
6492
6493
6494
6495 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13H, &u8Data);
6496 u16Data=u8Data;
6497 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
6498 u16Data=(u16Data<<8)|u8Data;
6499 _u16PreLockedLB=u16Data; //Pre_Scanned_LB
6500
6501
6502 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
6503 u16Data=u8Data;
6504 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
6505 u16Data=(u16Data<<8)|u8Data;
6506 _u16CurrentSymbolRate=u16Data; //Fine_Symbol_Rate
6507
6508
6509 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
6510 u16Data=u8Data;
6511 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
6512 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset
6513 *CFO_reg=u16Data;
6514 /*
6515 if (u16Data*1000 >= 0x8000)
6516 {
6517 u16Data=0x1000- u16Data*1000;
6518 _s16CurrentCFO=-1*u16Data/1000;
6519 }
6520 else
6521 {
6522 _s16CurrentCFO=u16Data;
6523 }
6524 */
6525 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
6526 u16Data=u8Data;
6527 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
6528 u16Data=(u16Data<<8)|u8Data;
6529 _u16CurrentStepSize=u16Data; //Tuner_Frequency_Step
6530
6531 DBG_INTERN_DVBS(ULOGD("DEMOD","Pre Locked BWH:%d BWL:%d Step:%d\n ",_u16PreLockedHB, _u16PreLockedLB, _u16CurrentStepSize));
6532 }
6533 }
6534 *u8Progress=100;
6535
6536 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_WaitCurFreqFinished- u8Progress: %d u8FindNum %d\n", *u8Progress, *u8FindNum));
6537
6538 return status;
6539 }
6540
INTERN_DVBS_BlindScan_Cancel(void)6541 MS_BOOL INTERN_DVBS_BlindScan_Cancel(void)
6542 {
6543 MS_BOOL status=TRUE;
6544 MS_U8 u8Data=0;
6545 MS_U16 u16Data;
6546
6547 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_Cancel+\n"));
6548
6549 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_WR_DBG_90, &u8Data);
6550 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6551 u8Data&=0xF0;
6552 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_WR_DBG_90, u8Data);
6553 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6554
6555 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E1, 0x00);
6556 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E0, 0x00);
6557 u16Data = 0x0000;
6558 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)u16Data&0x00ff);
6559 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(u16Data>>8)&0x00ff);
6560
6561 _u16TunerCenterFreq=0;
6562 _u16ChannelInfoIndex=0;
6563
6564 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_Cancel-\n"));
6565
6566 return status;
6567 }
6568
INTERN_DVBS_BlindScan_End(void)6569 MS_BOOL INTERN_DVBS_BlindScan_End(void)
6570 {
6571 MS_BOOL status=TRUE;
6572 MS_U8 u8Data=0;
6573 MS_U16 u16Data;
6574
6575 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_End+\n"));
6576
6577 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_WR_DBG_90, &u8Data);
6578 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6579 u8Data&=0xF0;
6580 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_WR_DBG_90, u8Data);
6581 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6582
6583 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E1, 0x00);
6584 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E0, 0x00);
6585 u16Data = 0x0000;
6586 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)u16Data&0x00ff);
6587 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(u16Data>>8)&0x00ff);
6588
6589 _u16TunerCenterFreq=0;
6590 _u16ChannelInfoIndex=0;
6591
6592 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_End-\n"));
6593
6594 return status;
6595 }
6596
INTERN_DVBS_BlindScan_GetChannel(MS_U16 u16ReadStart,MS_U16 * u16TPNum,HAL_DEMOD_MS_FE_CARRIER_PARAM * pTable)6597 MS_BOOL INTERN_DVBS_BlindScan_GetChannel(MS_U16 u16ReadStart,MS_U16* u16TPNum,HAL_DEMOD_MS_FE_CARRIER_PARAM *pTable)
6598 {
6599 MS_BOOL status=TRUE;
6600 MS_U16 u16TableIndex;
6601
6602 *u16TPNum=_u16ChannelInfoIndex-u16ReadStart;
6603 for(u16TableIndex = 0; u16TableIndex < (*u16TPNum); u16TableIndex++)
6604 {
6605 pTable[u16TableIndex].u32Frequency = _u16ChannelInfoArray[0][_u16ChannelInfoIndex-1];
6606 pTable[u16TableIndex].SatParam.u32SymbolRate = _u16ChannelInfoArray[1][_u16ChannelInfoIndex-1];
6607 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_GetChannel Freq: %d SymbolRate: %d\n", pTable[u16TableIndex].u32Frequency, pTable[u16TableIndex].SatParam.u32SymbolRate));
6608 }
6609 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_u16TPNum:%d\n", *u16TPNum));
6610
6611 return status;
6612 }
6613
INTERN_DVBS_BlindScan_GetCurrentFreq(MS_U32 * u32CurrentFeq)6614 MS_BOOL INTERN_DVBS_BlindScan_GetCurrentFreq(MS_U32 *u32CurrentFeq)
6615 {
6616 MS_BOOL status=TRUE;
6617 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_BlindScan_GetCurrentFreq+\n"));
6618
6619 *u32CurrentFeq=_u16TunerCenterFreq;
6620 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_BlindScan_GetCurrentFreq-: %d\n", _u16TunerCenterFreq));
6621 return status;
6622 }
6623
6624 //------------------------------------------------------------------
6625 // END BlindScan Function
6626 //------------------------------------------------------------------
6627
6628 //------------------------------------------------------------------
6629 // DiSEqc Function
6630 //------------------------------------------------------------------
INTERN_DVBS_DiSEqC_Init(void)6631 MS_BOOL INTERN_DVBS_DiSEqC_Init(void)
6632 {
6633 MS_BOOL status = true;
6634 MS_U8 u8Data = 0;
6635
6636 //Clear status
6637 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6638 u8Data=(u8Data|0x3E)&(~0x3E);
6639 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6640
6641 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, 0x00);
6642 //Tone En
6643 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC0, &u8Data);
6644 u8Data=(u8Data&(~0x06))|(0x06);
6645 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, u8Data);
6646
6647 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_DiSEqC_Init\n"));
6648
6649 return status;
6650 }
6651
INTERN_DVBS_DiSEqC_SetTone(MS_BOOL bTone1)6652 MS_BOOL INTERN_DVBS_DiSEqC_SetTone(MS_BOOL bTone1)
6653 {
6654 MS_BOOL status=TRUE;
6655 MS_U8 u8Data=0;
6656 MS_U8 u8ReSet22k=0;
6657
6658 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC4, 0x01);//0x62;DVBS2_DISEQC_TX1
6659 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, 0x4E);//0x60
6660 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCC, 0x88);//0x66
6661
6662 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);//0x61
6663 u8ReSet22k=u8Data;
6664
6665 if (bTone1==TRUE)
6666 {
6667 //Tone burst 1
6668 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, 0x19);
6669 _u8ToneBurstFlag=1;
6670 }
6671 else
6672 {
6673 //Tone burst 0
6674 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, 0x11);
6675 _u8ToneBurstFlag=2;
6676 }
6677 //DIG_DISEQC_TX_EN
6678 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6679 //u8Data=u8Data&~(0x01);//Tx Disable
6680 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6681
6682 MsOS_DelayTask(1);
6683 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);//0x66 high byte DVBS2_DISEQC_TX_EN
6684 u8Data=u8Data|0x3E; //Status clear
6685 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6686 MsOS_DelayTask(10);
6687 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6688 u8Data=u8Data&~(0x3E);
6689 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6690 MsOS_DelayTask(1);
6691
6692 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6693 u8Data=u8Data|0x01; //Tx Enable
6694 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6695
6696 MsOS_DelayTask(30);//(100)
6697 //For ToneBurst 22k issue.
6698 u8Data=u8ReSet22k;
6699 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);//0x61
6700
6701 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_DiSEqC_SetTone:%d\n", bTone1));
6702 //MsOS_DelayTask(100);
6703 return status;
6704 }
6705
INTERN_DVBS_DiSEqC_SetLNBOut(MS_BOOL bLow)6706 MS_BOOL INTERN_DVBS_DiSEqC_SetLNBOut(MS_BOOL bLow)
6707 {
6708 MS_BOOL status=TRUE;
6709 MS_U8 u8Data=0;
6710
6711 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6712 if (bLow==TRUE)
6713 {
6714 u8Data=(u8Data|0x40); //13V
6715 }
6716 else
6717 {
6718 u8Data=(u8Data&(~0x40));//18V
6719 }
6720 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);
6721
6722 return status;
6723 }
6724
INTERN_DVBS_DiSEqC_GetLNBOut(MS_BOOL * bLNBOutLow)6725 MS_BOOL INTERN_DVBS_DiSEqC_GetLNBOut(MS_BOOL* bLNBOutLow)
6726 {
6727 MS_BOOL status=TRUE;
6728 MS_U8 u8Data=0;
6729
6730 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6731 if( (u8Data&0x40)==0x40)
6732 {
6733 * bLNBOutLow=TRUE;
6734 }
6735 else
6736 {
6737 * bLNBOutLow=FALSE;
6738 }
6739
6740 return status;
6741 }
6742
INTERN_DVBS_DiSEqC_Set22kOnOff(MS_BOOL b22kOn)6743 MS_BOOL INTERN_DVBS_DiSEqC_Set22kOnOff(MS_BOOL b22kOn)
6744 {
6745 MS_BOOL status=TRUE;
6746 MS_U8 u8Data=0;
6747
6748 //Set DiSeqC 22K
6749 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCC, 0x44); //Set 11K-->22K
6750
6751 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6752
6753 if (b22kOn==TRUE)
6754 {
6755 u8Data=(u8Data&0xc7);
6756 u8Data=(u8Data|0x08);
6757 }
6758 else
6759 {
6760 u8Data=(u8Data&0xc7);
6761 }
6762 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);
6763
6764 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_DiSEqC_Set22kOnOff:%d\n", b22kOn));
6765 return status;
6766 }
6767
INTERN_DVBS_DiSEqC_Get22kOnOff(MS_BOOL * b22kOn)6768 MS_BOOL INTERN_DVBS_DiSEqC_Get22kOnOff(MS_BOOL* b22kOn)
6769 {
6770 MS_BOOL status=TRUE;
6771 MS_U8 u8Data=0;
6772
6773 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6774 if ((u8Data&0x38)==0x08)
6775 {
6776 *b22kOn=TRUE;
6777 }
6778 else
6779 {
6780 *b22kOn=FALSE;
6781 }
6782
6783 return status;
6784 }
6785
INTERN_DVBS_DiSEqC_SendCmd(MS_U8 * pCmd,MS_U8 u8CmdSize)6786 MS_BOOL INTERN_DVBS_DiSEqC_SendCmd(MS_U8* pCmd,MS_U8 u8CmdSize)
6787 {
6788 MS_BOOL status=TRUE;
6789 MS_U8 u8Data;
6790 MS_U8 u8Index;
6791 MS_U16 u16WaitCount;
6792 /*
6793 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6794 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6795 u8Data=(u8Data&~(0x10));
6796 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6797 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6798 */
6799 #if 0 //For Unicable command timing
6800 u16WaitCount=0;
6801 do
6802 {
6803 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data);
6804 //printf(">>> INTERN_DVBS_DiSEqC_SendCmd DiSEqC Status = 0x%x <<<\n", u8Data);
6805 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6806 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6807 MsOS_DelayTask(1);
6808 u16WaitCount++;
6809 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
6810
6811 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
6812 {
6813 DBG_INTERN_DVBS(printf("INTERN_DVBS DiSEqC Send Command Busy!!!\n"));
6814 return FALSE;
6815 }
6816 #endif
6817
6818 //u16Address=0x0BC4;
6819 for (u8Index=0; u8Index < u8CmdSize; u8Index++)
6820 {
6821 u8Data=*(pCmd+u8Index);
6822 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC4 + u8Index, u8Data);//#define DVBS2_DISEQC_TX1 (_REG_DVBS2(0x62)+0)//[7:0]
6823 DBG_INTERN_DVBS(ULOGD("DEMOD","=============INTERN_DVBS_DiSEqC_SendCmd(Demod1) = 0x%X\n",u8Data));
6824 }
6825
6826 //set DiSEqC Tx Length, Odd Enable, Tone Burst Mode
6827 u8Data=((u8CmdSize-1)&0x07)|0x40;
6828 if (_u8ToneBurstFlag==1)
6829 {
6830 u8Data|=0x80;//0x20;
6831 }
6832 else if (_u8ToneBurstFlag==2)
6833 {
6834 u8Data|=0x20;//0x80;
6835 }
6836 _u8ToneBurstFlag=0;
6837 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_8, u8Data);
6838
6839 //add this only for check mailbox R/W
6840 #if 1
6841 DBG_INTERN_DVBS(ULOGD("DEMOD"," Write into E_DMD_S2_MB_DMDTOP_DBG_8 = 0x%X!!!\n",u8Data));
6842 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_8, &u8Data);
6843 DBG_INTERN_DVBS(ULOGD("DEMOD"," Read from E_DMD_S2_MB_DMDTOP_DBG_8 = 0x%X!!!\n",u8Data));
6844 #endif
6845
6846 MsOS_DelayTask(25);//MsOS_DelayTask(10);
6847 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_WR_DBG_90, &u8Data);//#define TOP_WR_DBG_90 (_REG_DMDTOP(0x3A)+0)
6848 //u8Data=u8Data|0x10;
6849 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_WR_DBG_90, u8Data|0x10);//enable DiSEqC_Data_Tx
6850 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); DBG_INTERN_DVBS(printf(">>>+++ INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X +++<<<\n",u8Data));
6851 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); DBG_INTERN_DVBS(printf(">>>+++ INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d +++<<<\n",u8Data));
6852
6853 #if 1 //For Unicable command timing???
6854 u16WaitCount=0;
6855 do
6856 {
6857 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); DBG_INTERN_DVBS(printf(">>>*** INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X ***<<<\n",u8Data));
6858 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); DBG_INTERN_DVBS(printf(">>>*** INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d ***<<<\n",u8Data));
6859 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_WR_DBG_90, &u8Data);
6860 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6861 MsOS_DelayTask(1);
6862 u16WaitCount++;
6863 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)) ;
6864
6865 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
6866 {
6867 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS DiSEqC Send Command Busy!!!\n"));
6868 return FALSE;
6869 }
6870 else
6871 {
6872 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS DiSEqC Send Command Success!!!\n"));
6873 return TRUE;
6874 }
6875
6876
6877 #endif
6878 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); printf(">>>--- INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X ---<<<\n",u8Data);
6879 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); printf(">>>--- INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d ---<<<\n",u8Data+1);
6880
6881 return status;
6882 }
6883
INTERN_DVBS_DiSEqC_SetTxToneMode(MS_BOOL bTxTone22kOff)6884 MS_BOOL INTERN_DVBS_DiSEqC_SetTxToneMode(MS_BOOL bTxTone22kOff)
6885 {
6886 MS_BOOL status=TRUE;
6887 MS_U8 u8Data=0;
6888
6889 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xD7, &u8Data);//h006b h006b 15 15 reg_diseqc_tx_tone_mode
6890 if (bTxTone22kOff==TRUE)
6891 {
6892 u8Data=(u8Data|0x80); //1: without 22K.
6893 }
6894 else
6895 {
6896 u8Data=(u8Data&(~0x80)); //0: with 22K.
6897 }
6898 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xD7, u8Data);
6899
6900 return status;
6901 }
6902
INTERN_DVBS_UnicableAGCCheckPower(MS_BOOL pbAGCCheckPower)6903 MS_BOOL INTERN_DVBS_UnicableAGCCheckPower(MS_BOOL pbAGCCheckPower)
6904 {
6905 //MS_BOOL status = TRUE;
6906 MS_U8 u8Data=0;
6907
6908 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, 0x00);
6909
6910 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_WR_DBG_90, &u8Data);
6911 u8Data &= 0xFE;//clean bit0
6912 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_WR_DBG_90, u8Data);
6913
6914 if (pbAGCCheckPower == FALSE)//0
6915 {
6916 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6917 u8Data &= 0xFE;//clean bit0
6918 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6919 //printf("CMD=MS_FALSE==============================\n");
6920 }
6921 else
6922 {
6923 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6924 u8Data |= 0x01; //bit1=1
6925 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6926 //printf("CMD=MS_TRUE==============================\n");
6927 }
6928
6929 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_WR_DBG_90, &u8Data);
6930 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6931 u8Data &= 0xF0;
6932 u8Data |= 0x01;
6933 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_WR_DBG_90, u8Data);
6934 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6935 MsOS_DelayTask(500);
6936
6937 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6938 u8Data &= 0x80; //Read bit7
6939 if (u8Data == 0x80)
6940 {
6941 u8Data = 0x00;
6942 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6943 u8Data = 0x00;
6944 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6945 return TRUE;
6946 }
6947 else
6948 {
6949 u8Data = 0x00;
6950 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6951 u8Data = 0x00;
6952 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6953 return FALSE;
6954 }
6955 }
6956
6957 //------------------------------------------------------------------
6958 // END DiSEqc Function
6959 //------------------------------------------------------------------
6960 //------------------------------------------------------------------
6961 // R/W Function
6962 //------------------------------------------------------------------
INTERN_DVBS_WriteReg2bytes(MS_U16 u16Addr,MS_U16 u16Data)6963 MS_BOOL INTERN_DVBS_WriteReg2bytes(MS_U16 u16Addr, MS_U16 u16Data)
6964 {
6965 MS_BOOL bRet= TRUE;
6966 bRet &= MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr, (MS_U8)u16Data&0x00ff);
6967 bRet &= MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr + 0x0001, (MS_U8)(u16Data>>8)&0x00ff);
6968 return bRet;
6969 }
6970
INTERN_DVBS_ReadReg2bytes(MS_U16 u16Addr,MS_U16 * pu16Data)6971 MS_BOOL INTERN_DVBS_ReadReg2bytes(MS_U16 u16Addr, MS_U16 *pu16Data)
6972 {
6973 MS_BOOL bRet= TRUE;
6974 MS_U8 u8Data =0;
6975 MS_U16 u16Data =0;
6976
6977 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr + 0x0001, &u8Data);
6978 u16Data = u8Data;
6979 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr, &u8Data);
6980 *pu16Data = (u16Data<<8)|u8Data;
6981
6982 return bRet;
6983 }
6984
6985 //Frontend Freeze
INTERN_DVBS_DTV_FrontendSetFreeze(void)6986 MS_BOOL INTERN_DVBS_DTV_FrontendSetFreeze(void)
6987 {
6988 MS_BOOL bRet = TRUE;
6989 MS_U16 u16Address;
6990 MS_U16 u16Data = 0;
6991
6992 u16Address = (FRONTEND_FREEZE_DUMP>>16)&0xffff;
6993 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6994 u16Data|=(FRONTEND_FREEZE_DUMP&0xffff);
6995 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6996
6997 return bRet;
6998 }
6999
INTERN_DVBS_DTV_FrontendUnFreeze(void)7000 MS_BOOL INTERN_DVBS_DTV_FrontendUnFreeze(void)
7001 {
7002 MS_BOOL bRet= TRUE;
7003 MS_U16 u16Address;
7004 MS_U16 u16Data = 0;
7005
7006 u16Address = (FRONTEND_FREEZE_DUMP>>16)&0xffff;
7007 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
7008 u16Data&=~(FRONTEND_FREEZE_DUMP&0xffff);
7009 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
7010
7011 return bRet;
7012 }
7013
7014 //Inner Freeze
INTERN_DVBS_DTV_InnerSetFreeze(void)7015 MS_BOOL INTERN_DVBS_DTV_InnerSetFreeze(void)
7016 {
7017 MS_BOOL bRet= TRUE;
7018 MS_U16 u16Address;
7019 MS_U16 u16Data = 0;
7020
7021 u16Address = (INNER_FREEZE_DUMP>>16)&0xffff;
7022 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
7023 u16Data|=(INNER_FREEZE_DUMP&0xffff);
7024 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
7025
7026 return bRet;
7027 }
7028
INTERN_DVBS_DTV_InnerUnFreeze(void)7029 MS_BOOL INTERN_DVBS_DTV_InnerUnFreeze(void)
7030 {
7031 MS_BOOL bRet= TRUE;
7032 MS_U16 u16Address;
7033 MS_U16 u16Data = 0;
7034
7035 u16Address = (INNER_FREEZE_DUMP>>16)&0xffff;
7036 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
7037 u16Data&=~(INNER_FREEZE_DUMP&0xffff);
7038 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
7039
7040 return bRet;
7041 }
7042 //------------------------------------------------------------------
7043 // END R/W Function
7044 //------------------------------------------------------------------
7045
7046
7047 /***********************************************************************************
7048 Subject: read register
7049 Function: MDrv_1210_IIC_Bypass_Mode
7050 Parmeter:
7051 Return:
7052 Remark:
7053 ************************************************************************************/
7054 //void MDrv_1210_IIC_Bypass_Mode(MS_BOOL enable)
7055 //{
7056 // UNUSED(enable);
7057 // if (enable)
7058 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x10); // IIC by-pass mode on
7059 // else
7060 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x00); // IIC by-pass mode off
7061 //}
7062
7063