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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102 //0312
103
104 #define _INTERN_DVBS_C_
105 #include <math.h>
106 #include "MsCommon.h"
107 #include "MsIRQ.h"
108 #include "MsOS.h"
109 //#include "apiPWS.h"
110
111 #include "MsTypes.h"
112 #include "drvBDMA.h"
113 //#include "drvIIC.h"
114 //#include "msAPI_Tuner.h"
115 //#include "msAPI_MIU.h"
116 //#include "BinInfo.h"
117 //#include "halVif.h"
118 #include "drvDMD_INTERN_DVBS.h"
119 #include "halDMD_INTERN_DVBS.h"
120 #include "halDMD_INTERN_common.h"
121
122 #include "drvMMIO.h"
123 //#include "TDAG4D01A_SSI_DVBT.c"
124 #include "drvDMD_VD_MBX.h"
125 //-----------------------------------------------------------------------
126 #define BIN_ID_INTERN_DVBS_DEMOD BIN_ID_INTERN_DVBS
127
128 //For DVBS
129 //#define DVBT2FEC_REG_BASE 0x3300
130 #define DVBS2OPPRO_REG_BASE 0x3E00
131 #define TOP_REG_BASE 0x2000 //DMDTOP
132 #define REG_BACKEND 0x1F00//_REG_BACKEND
133 #define DVBSFEC_REG_BASE 0x3F00
134 #define DVBS2FEC_REG_BASE 0x3300
135 #define DVBS2_REG_BASE 0x3A00
136 #define DVBS2_INNER_REG_BASE 0x3B00
137 #define DVBS2_INNER_EXT_REG_BASE 0x3C00
138 #define DVBS2_INNER_EXT2_REG_BASE 0x3D00
139 //#define DVBSTFEC_REG_BASE 0x2300 //DVBTFEC
140 #define FRONTEND_REG_BASE 0x2800
141 #define FRONTENDEXT_REG_BASE 0x2900
142 #define FRONTENDEXT2_REG_BASE 0x2A00
143 #define DMDANA_REG_BASE 0x2E00 //DMDDTOP//reg_dmdana.xls
144 #define DVBTM_REG_BASE 0x3400
145
146 #define SAMPLING_RATE_FS (144000)//(108000)//(96000)
147 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000)
148 #define INTERN_DVBS_TUNER_WAIT_TIMEOUT (50)
149
150 //#define DVBS2_Function (1)
151 //#define MSB131X_ADCPLL_IQ_SWAP 0
152 //#define INTERN_DVBS_TS_DATA_SWAP 0
153
154 //#define MS_DEBUG //enable debug dump
155
156 #ifdef MS_DEBUG
157 #define DBG_INTERN_DVBS(x) x
158 #define DBG_GET_SIGNAL_DVBS(x) x
159 #define DBG_INTERN_DVBS_TIME(x) x
160 #define DBG_INTERN_DVBS_LOCK(x) x
161 #define INTERN_DVBS_INTERNAL_DEBUG 1
162 #else
163 #define DBG_INTERN_DVBS(x) //x
164 #define DBG_GET_SIGNAL_DVBS(x) //x
165 #define DBG_INTERN_DVBS_TIME(x) //x
166 #define DBG_INTERN_DVBS_LOCK(x) //x
167 #define INTERN_DVBS_INTERNAL_DEBUG 0
168 #endif
169 //----------------------------------------------------------
170 #define DBG_DUMP_LOAD_DSP_TIME 0
171
172
173 #define SIGNAL_LEVEL_OFFSET 0.00f
174 #define TAKEOVERPOINT -60.0f
175 #define TAKEOVERRANGE 0.5f
176 #define LOG10_OFFSET -0.21f
177 #define INTERN_DVBS_USE_SAR_3_ENABLE 0
178 //extern MS_U32 msAPI_Timer_GetTime0(void);
179 //#define INTERN_DVBS_GET_TIME msAPI_Timer_GetTime0()
180
181
182 //Debug Info
183 //Lock/Done Flag
184 #define AGC_LOCK 0x28170100
185 #define DAGC0_LOCK 0x283B0001
186 #define DAGC1_LOCK 0x285B0001
187 #define DAGC2_LOCK 0x28620001 //ACIDAGC 1 2
188 #define DAGC3_LOCK 0x286E0001
189 #define DCR_LOCK 0x28220100
190 #define COARSE_SYMBOL_RATE_DONE 0x2A200001 //CSRD 1 2
191 #define FINE_SYMBOL_RATE_DONE 0x2A200008 //FSRD 1 2
192 #define POWER4CFO_DONE 0x29280100 //POWER4CFO 1 2
193 //#define CLOSE_COARSE_CFO_LOCK 0x244E0001
194 #define TR_LOCK 0x3B0E0100 //TR 1 2
195 #define PR_LOCK 0x3B401000
196 #define FRAME_SYNC_ACQUIRE 0x3B300001
197 #define EQ_LOCK 0x3B5A1000
198 #define P_SYNC_LOCK 0x22160002
199 #define IN_SYNC_LOCK 0x3F0D8000
200
201 //AGC / DAGC
202 #define DEBUG_SEL_IF_AGC_GAIN 0x28260003
203 #define DEBUG_SEL_AGC_ERR 0x28260004
204 #define DEBUG_OUT_AGC 0x2828
205
206 #define DEBUG_SEL_DAGC0_GAIN 0x28E80003
207 #define DEBUG_SEL_DAGC0_ERR 0x28E80001
208 #define DEBUG_SEL_DAGC0_PEAK_MEAN 0x28E80005
209 #define DEBUG_OUT_DAGC0 0x2878
210
211 #define DEBUG_SEL_DAGC1_GAIN 0x28E80003//???
212 #define DEBUG_SEL_DAGC1_ERR 0x28E80001
213 #define DEBUG_SEL_DAGC1_PEAK_MEAN 0x28E80005
214 #define DEBUG_OUT_DAGC1 0x28B8
215
216 #define DEBUG_SEL_DAGC2_GAIN 0x28E80003
217 #define DEBUG_SEL_DAGC2_ERR 0x28E80001
218 #define DEBUG_SEL_DAGC2_PEAK_MEAN 0x28E80005
219 #define DEBUG_OUT_DAGC2 0x28C4
220
221 #define DEBUG_SEL_DAGC3_GAIN 0x29DA0003
222 #define DEBUG_SEL_DAGC3_ERR 0x29DA0001
223 #define DEBUG_SEL_DAGC3_PEAK_MEAN 0x29DA0005
224 #define DEBUG_OUT_DAGC3 0x29DC
225
226 #define INNER_DEBUG_SEL_TR 0x24080D00 //TR
227 #define DEBUG_SEL_TR_SFO_CONVERGE 0x24080B00
228 #define DEBUG_SEL_TR_INPUT 0x24080F00
229
230 #define FRONTEND_FREEZE_DUMP 0x27028000
231 #define INNER_FREEZE_DUMP 0x24080010
232
233 #define DCR_OFFSET 0x2740
234 #define INNER_DEBUG_SEL 0x2408
235 #define INNEREXT_FINEFE_DBG_OUT0 0x2550
236 #define INNEREXT_FINEFE_DBG_OUT2 0x2552
237 #define INNEREXT_FINEFE_KI_FF0 0x2556
238 #define INNEREXT_FINEFE_KI_FF2 0x2558
239 #define INNEREXT_FINEFE_KI_FF4 0x255A
240 #define INNER_PR_DEBUG_OUT0 0x2486
241 #define INNER_PR_DEBUG_OUT2 0x2488
242
243 #define IIS_COUNT0 0x2746
244 #define IIS_COUNT2 0x2748
245 #define IQB_PHASE 0x2766
246 #define IQB_GAIN 0x2768
247 #define TR_INDICATOR_FF0 0x2454
248 #define TR_INDICATOR_FF2 0x2456
249 #define INNER_TR_LOPF_VALUE_DEBUG0 0x2444
250 #define INNER_TR_LOPF_VALUE_DEBUG2 0x2446
251 #define INNER_TR_LOPF_VALUE_DEBUG4 0x2448
252 //------------------------------------------------------------
253 //Init Mailbox parameter.
254 #define INTERN_DVBS_TS_SERIAL_INVERSION 0
255 //For Parameter Init Setting
256 #define A_S2_ZIF_EN 0x01 //[0]
257 #define A_S2_RF_AGC_EN 0x00 //[0]
258 #define A_S2_DCR_EN 0x00 //[0] 0=Auto :1=Force
259 #define A_S2_IQB_EN 0x01 //[2]
260 #define A_S2_IIS_EN 0x00 //[0]
261 #define A_S2_CCI_EN 0x00 //[0] 0:1=Enable
262 #define A_S2_FORCE_ACI_SELECT 0xFF //[3:0] 0xFF=OFF(internal default)
263 #define A_S2_IQ_SWAP 0x01 //[0]
264 #define A_S2_AGC_REF_EXT_0 0x00 //[7:0] //0x00 0x90
265 #define A_S2_AGC_REF_EXT_1 0x02 //[11:8] //0x02 0x07
266 #define A_S2_AGC_K 0x07 //[15:12]
267 #define A_S2_ADCI_GAIN 0x0F //[4:0]
268 #define A_S2_ADCQ_GAIN 0x0F //[12:8]
269 #define A_S2_SRD_SIG_SRCH_RNG 0x6A //[7:0]
270 #define A_S2_SRD_DC_EXC_RNG 0x16 //[7:0]
271 //FRONTENDEXT_SRD_FRC_CFO
272 #define A_S2_FORCE_CFO_0 0x00 //[7:0]
273 #define A_S2_FORCE_CFO_1 0x00 //[11:8]
274 #define A_S2_DECIMATION_NUM 0x00 //[3:0] 00=(Internal Default)
275 #define A_S2_PSD_SMTH_TAP 0x29 //[6:0] Bit7 no define.
276 //CCI Parameter
277 //Set_Tuner_BW=(((U16)REG_BASE[DIG_SWUSE1FH]<<8)|REG_BASE[DIG_SWUSE1FL]);
278 #define A_S2_CCI_FREQN_0_L 0x00 //[7:0]
279 #define A_S2_CCI_FREQN_0_H 0x00 //[11:8]
280 #define A_S2_CCI_FREQN_1_L 0x00 //[7:0]
281 #define A_S2_CCI_FREQN_1_H 0x00 //[11:8]
282 #define A_S2_CCI_FREQN_2_L 0x00 //[7:0]
283 #define A_S2_CCI_FREQN_2_H 0x00 //[11:8]
284 //Inner TR Parameter
285 #define A_S2_TR_LOPF_KP 0x00 //[4:0] 00=(Internal Default)
286 #define A_S2_TR_LOPF_KI 0x00 //[4:0] 00=(Internal Default)
287 //Inner FineFE Parameter
288 #define A_S2_FINEFE_KI_SWITCH_0 0x00 //[15:12] 00=(Internal Default)
289 #define A_S2_FINEFE_KI_SWITCH_1 0x00 //[3:0] 00=(Internal Default)
290 #define A_S2_FINEFE_KI_SWITCH_2 0x00 //[7:4] 00=(Internal Default)
291 #define A_S2_FINEFE_KI_SWITCH_3 0x00 //[11:8] 00=(Internal Default)
292 #define A_S2_FINEFE_KI_SWITCH_4 0x00 //[15:12] 00=(Internal Default)
293 //Inner PR KP Parameter
294 #define A_S2_PR_KP_SWITCH_0 0x00 //[11:8] 00=(Internal Default)
295 #define A_S2_PR_KP_SWITCH_1 0x00 //[15:12] 00=(Internal Default)
296 #define A_S2_PR_KP_SWITCH_2 0x00 //[3:0] 00=(Internal Default)
297 #define A_S2_PR_KP_SWITCH_3 0x00 //[7:4] 00=(Internal Default)
298 #define A_S2_PR_KP_SWITCH_4 0x00 //[11:8] 00=(Internal Default)
299 //Inner FS Parameter
300 #define A_S2_FS_GAMMA 0x10 //[7:0]
301 #define A_S2_FS_ALPHA0 0x10 //[7:0]
302 #define A_S2_FS_ALPHA1 0x10 //[7:0]
303 #define A_S2_FS_ALPHA2 0x10 //[7:0]
304 #define A_S2_FS_ALPHA3 0x10 //[7:0]
305
306 #define A_S2_FS_H_MODE_SEL 0x01 //[0]
307 #define A_S2_FS_OBSWIN 0x08 //[12:8]
308 #define A_S2_FS_PEAK_DET_TH_L 0x00 //[7:0]
309 #define A_S2_FS_PEAK_DET_TH_H 0x01 //[15:8]
310 #define A_S2_FS_CONFIRM_NUM 0x01 //[3:0]
311 //Inner EQ Parameter
312 #define A_S2_EQ_MU_FFE_DA 0x00 //[3:0] 00=(Internal Default)
313 #define A_S2_EQ_MU_FFE_DD 0x00 //[7:4] 00=(Internal Default)
314 #define A_S2_EQ_ALPHA_SNR_DA 0x00 //[7:4] 00=(Internal Default)
315 #define A_S2_EQ_ALPHA_SNR_DD 0x00 //[11:8] 00=(Internal Default)
316 //Outer FEC Parameter
317 #define A_S2_FEC_ALFA 0x00 //[12:8]
318 #define A_S2_FEC_BETA 0x01 //[7:4]
319 #define A_S2_FEC_SCALING_LLR 0x00 //[7:0] 00=(Internal Default)
320 //TS Parameter
321 #if INTERN_DVBS_TS_SERIAL_INVERSION
322 #define A_S2_TS_SERIAL 0x01 //[0]
323 #else
324 #define A_S2_TS_SERIAL 0x00 //[0]
325 #endif
326 #define A_S2_TS_CLK_RATE 0x00
327 #define A_S2_TS_OUT_INV 0x00 //[5]
328 #define A_S2_TS_DATA_SWAP 0x00 //[5]
329 //Rev Parameter
330
331 #define A_S2_FW_VERSION_L 0x00 //From FW
332 #define A_S2_FW_VERSION_H 0x00 //From FW
333 #define A_S2_CHIP_VERSION 0x01
334 #define A_S2_FS_L 0x00
335 #define A_S2_FS_H 0x00
336 #define A_S2_MANUAL_TUNE_SYMBOLRATE_L 0x20
337 #define A_S2_MANUAL_TUNE_SYMBOLRATE_H 0x4E
338
339 MS_U8 INTERN_DVBS_DSPREG[] =
340 {
341 A_S2_ZIF_EN, A_S2_RF_AGC_EN, A_S2_DCR_EN, A_S2_IQB_EN, A_S2_IIS_EN, A_S2_CCI_EN, A_S2_FORCE_ACI_SELECT, A_S2_IQ_SWAP, // 00H ~ 07H
342 A_S2_AGC_REF_EXT_0, A_S2_AGC_REF_EXT_1, A_S2_AGC_K, A_S2_ADCI_GAIN, A_S2_ADCQ_GAIN, A_S2_SRD_SIG_SRCH_RNG, A_S2_SRD_DC_EXC_RNG, A_S2_FORCE_CFO_0, // 08H ~ 0FH
343 A_S2_FORCE_CFO_1, A_S2_DECIMATION_NUM, A_S2_PSD_SMTH_TAP, A_S2_CCI_FREQN_0_L, A_S2_CCI_FREQN_0_H, A_S2_CCI_FREQN_1_L, A_S2_CCI_FREQN_1_H, A_S2_CCI_FREQN_2_L, // 10H ~ 17H
344 A_S2_CCI_FREQN_2_H, A_S2_TR_LOPF_KP, A_S2_TR_LOPF_KI, A_S2_FINEFE_KI_SWITCH_0, A_S2_FINEFE_KI_SWITCH_1, A_S2_FINEFE_KI_SWITCH_2, A_S2_FINEFE_KI_SWITCH_3, A_S2_FINEFE_KI_SWITCH_4, // 18H ~ 1FH
345 A_S2_PR_KP_SWITCH_0, A_S2_PR_KP_SWITCH_1, A_S2_PR_KP_SWITCH_2, A_S2_PR_KP_SWITCH_3, A_S2_PR_KP_SWITCH_4, A_S2_FS_GAMMA, A_S2_FS_ALPHA0, A_S2_FS_ALPHA1, // 20H ~ 27H
346 A_S2_FS_ALPHA2, A_S2_FS_ALPHA3, A_S2_FS_H_MODE_SEL, A_S2_FS_OBSWIN, A_S2_FS_PEAK_DET_TH_L, A_S2_FS_PEAK_DET_TH_H, A_S2_FS_CONFIRM_NUM, A_S2_EQ_MU_FFE_DA, // 28h ~ 2FH
347 A_S2_EQ_MU_FFE_DD, A_S2_EQ_ALPHA_SNR_DA, A_S2_EQ_ALPHA_SNR_DD, A_S2_FEC_ALFA, A_S2_FEC_BETA, A_S2_FEC_SCALING_LLR, A_S2_TS_SERIAL, A_S2_TS_CLK_RATE, // 30H ~ 37H
348 A_S2_TS_OUT_INV, A_S2_TS_DATA_SWAP, A_S2_FW_VERSION_L, A_S2_FW_VERSION_H, A_S2_CHIP_VERSION, A_S2_FS_L, A_S2_FS_H, A_S2_MANUAL_TUNE_SYMBOLRATE_L, // 38H ~ 3CH
349 A_S2_MANUAL_TUNE_SYMBOLRATE_H,
350 };
351
352 /****************************************************************
353 *Local Variables *
354 ****************************************************************/
355
356
357 static MS_U16 _u16SignalLevel[185][2]=
358 {//AV2028 SR=22M, 2/3 CN=5.9
359 {255, 920},{255, 915},{255, 910},{255, 905},{255, 900},{255, 895},{255, 890},{255, 885},{255, 880},{255, 875},
360 {255, 870},{255, 865},{255, 860},{255, 855},{255, 850},{2121, 845},{3988, 840},{11629, 835},{19270, 830},{19744, 825},
361 {20218, 820},{20692, 815},{21166, 810},{21640, 805},{22114, 800},{22350, 795},{22587, 790},{22823, 785},{23059, 780},{23296, 775},
362 {23532, 770},{23790, 765},{24049, 760},{24307, 755},{24566, 750},{24777, 745},{24988, 740},{25198, 735},{25409, 730},{25548, 725},
363 {25687, 720},{25826, 715},{25965, 710},{26104, 705},{26242, 700},{26311, 695},{26380, 690},{26449, 685},{26517, 680},{26586, 675},
364 {26655, 670},{26723, 665},{26792, 660},{26861, 655},{26929, 650},{27079, 645},{27229, 640},{27379, 635},{27529, 630},{27733, 625},
365 {27937, 620},{28140, 615},{28344, 610},{28547, 605},{28751, 600},{28763, 595},{28775, 590},{28787, 585},{28800, 580},{28812, 575},
366 {28824, 570},{29001, 565},{29178, 560},{29354, 555},{29531, 550},{29603, 545},{29674, 540},{29746, 535},{29818, 530},{29890, 525},
367 {29961, 520},{30033, 515},{30105, 510},{30177, 505},{30248, 500},{30382, 495},{30497, 490},{30593, 485},{30718, 480},{30803, 475},
368 {30899, 470},{30981, 465},{31074, 460},{31150, 455},{31238, 450},{31320, 445},{31373, 440},{31459, 435},{31529, 430},{31610, 425},
369 {31696, 420},{31735, 415},{31794, 410},{31839, 405},{31901, 400},{31974, 395},{32040, 390},{32078, 385},{32156, 380},{32205, 375},
370 {32255, 370},{32305, 365},{32347, 360},{32389, 355},{32435, 350},{32452, 345},{32470, 340},{32540, 335},{32590, 330},{32650, 325},
371 {32710, 320},{32740, 315},{32790, 310},{32830, 305},{32870, 300},{32920, 295},{32950, 290},{32990, 285},{33040, 280},{33090, 275},
372 {33130, 270},{33160, 265},{33180, 260},{33230, 255},{33270, 250},{33300, 245},{33330, 240},{33390, 235},{33440, 230},{33470, 225},
373 {33480, 220},{33550, 215},{33610, 210},{33650, 205},{33710, 200},{33730, 195},{33790, 190},{33830, 185},{33900, 180},{33940, 175},
374 {34010, 170},{34050, 165},{34100, 160},{34140, 155},{34190, 150},{34250, 145},{34300, 140},{34390, 135},{34450, 130},{34510, 125},
375 {34550, 120},{34610, 115},{34670, 110},{34730, 105},{34770, 100},{34850, 95},{34920, 90},{34990, 85},{35040, 80},{35120, 75},
376 {35140, 70},{35210, 65},{35290, 60},{35320, 55},{35350, 50},{35420, 45},{35500, 40},{35530, 35},{35560, 30},{35600, 25},
377 {35670, 20},{35700, 15},{35720, 10},{35770, 5},{35780, 0}
378 };
379
380 /*
381 {//AV2028 SR=22M, 2/3 CN=5.9
382 {32100, 920},{32200, 915},{32350, 910},{32390, 905},{32480, 900},{32550, 895},{32620, 890},{32680, 885},{32750, 880},{32830, 875},
383 {32930, 870},{33010, 865},{33100, 860},{33200, 855},{33310, 850},{33410, 845},{33520, 840},{33640, 835},{33770, 830},{33900, 825},
384 {34030, 820},{34150, 815},{34290, 810},{34390, 805},{34490, 800},{34580, 795},{34700, 790},{34800, 785},{34880, 780},{34940, 775},
385 {35030, 770},{35130, 765},{35180, 760},{35260, 755},{35310, 750},{35340, 745},{35380, 740},{35400, 735},{35450, 730},{35550, 725},
386 {35620, 720},{35700, 715},{35800, 710},{35890, 705},{36000, 700},{36120, 695},{36180, 690},{36280, 685},{36400, 680},{36570, 675},
387 {36730, 670},{36910, 665},{37060, 660},{37100, 655},{37260, 650},{37340, 645},{37410, 640},{37580, 635},{37670, 630},{37700, 625},
388 {37750, 620},{37800, 615},{37860, 610},{37980, 605},{38050, 600},{38170, 595},{38370, 590},{38540, 585},{38710, 580},{38870, 575},
389 {39020, 570},{39070, 565},{39100, 560},{39180, 555},{39280, 550},{39460, 545},{39510, 540},{39600, 535},{39620, 530},{39680, 525},
390 {39720, 520},{39830, 515},{39880, 510},{39930, 505},{39960, 500},{40000, 495},{40200, 490},{40360, 485},{40540, 480},{40730, 475},
391 {40880, 470},{41020, 465},{41150, 460},{41280, 455},{41410, 450},{41520, 445},{41620, 440},{41730, 435},{41840, 430},{41930, 425},
392 {42010, 420},{42100, 415},{42180, 410},{42260, 405},{42350, 400},{42440, 395},{42520, 390},{42580, 385},{42660, 380},{42730, 375},
393 {42800, 370},{42870, 365},{42940, 360},{43000, 355},{43060, 350},{43130, 345},{43180, 340},{43250, 335},{43310, 330},{43370, 325},
394 {43420, 320},{43460, 315},{43520, 310},{43570, 305},{43620, 300},{43660, 295},{43710, 290},{43750, 285},{43810, 280},{43860, 275},
395 {43910, 270},{43940, 265},{43990, 260},{44020, 255},{44060, 250},{44110, 245},{44140, 240},{44190, 235},{44230, 230},{44270, 225},
396 {44320, 220},{44370, 215},{44400, 210},{44450, 205},{44490, 200},{44530, 195},{44590, 190},{44630, 185},{44660, 180},{44720, 175},
397 {44750, 170},{44790, 165},{44830, 160},{44880, 155},{44910, 150},{44960, 145},{45000, 140},{45030, 135},{45070, 130},{45100, 125},
398 {45130, 120},{45160, 115},{45200, 110},{45240, 105},{45270, 100},{45300, 95},{45330, 90},{45360, 85},{45400, 80},{45430, 75},
399 {45460, 70},{45490, 65},{45530, 60},{45560, 55},{45590, 50},{45630, 45},{45670, 40},{45690, 35},{45740, 30},{45760, 25},
400 {45800, 20},{45830, 15},{45860, 10},{45880, 5},{45920, 0}
401 };
402 */
403
404 MS_U8 u8DemodLockFlag;
405 MS_U8 modulation_order;
406 static MS_BOOL _bDemodType=FALSE;//DVBS:FALSE ; S2:TRUE
407 //static MS_BOOL TPSLock = 0;
408 static MS_U32 u32ChkScanTimeStartDVBS = 0;
409 static MS_U8 g_dvbs_lock = 0;
410 //static float intern_dvb_s_qam_ref[] = {3.0, 0.0, 0.0, 0.0, 0.0, 80.0}; //16q,32q,64q,128q,256q, and others
411 static MS_U8 _u8_DVBS2_CurrentCodeRate;
412 static float _fPostBer=0;
413 static float _f_DVBS_CurrentSNR=0;
414 static MS_U8 _u8ToneBurstFlag=0;
415 static MS_U16 _u16BlindScanStartFreq=0;
416 static MS_U16 _u16BlindScanEndFreq=0;
417 static MS_U16 _u16TunerCenterFreq=0;
418 static MS_U16 _u16ChannelInfoIndex=0;
419 //Debug Only+
420 static MS_U16 _u16NextCenterFreq=0;
421 static MS_U16 _u16LockedSymbolRate=0;
422 static MS_U16 _u16LockedCenterFreq=0;
423 static MS_U16 _u16PreLockedHB=0;
424 static MS_U16 _u16PreLockedLB=0;
425 static MS_U16 _u16CurrentSymbolRate=0;
426 static MS_S16 _s16CurrentCFO=0;
427 static MS_U16 _u16CurrentStepSize=0;
428 //Debug Only-
429 static MS_U16 _u16ChannelInfoArray[2][1000];
430 //static MS_U32 _u32CurrentSR=0;
431 static MS_BOOL _bSerialTS=FALSE;
432 static MS_BOOL _bTSDataSwap=FALSE;
433
434 //Global Variables
435 S_CMDPKTREG gsCmdPacketDVBS;
436 //MS_U8 gCalIdacCh0, gCalIdacCh1;
437 static MS_BOOL bDMD_DVBS_NoChannelDetectedWithRFPower = FALSE;
438 static MS_U32 u32DMD_DVBS_NoChannelTimeAccWithRFPower = 0;
439 extern MS_U32 u32DMD_DVBS2_DJB_START_ADDR;
440 #ifdef INTERN_DVBS_LOAD_FW_FROM_CODE_MEMORY
441 MS_U8 INTERN_DVBS_table[] =
442 {
443 #include "fwDMD_INTERN_DVBS.dat"
444 };
445
446 #endif
447
448 MS_BOOL INTERN_DVBS_Show_Demod_Version(void);
449 MS_BOOL INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE *pQAMMode);
450 MS_BOOL INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE *pDemodType);
451 MS_BOOL INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE *pCodeRate);
452 MS_BOOL INTERN_DVBS_GetCurrentSymbolRate(MS_U32 *u32SymbolRate);
453 MS_BOOL INTERN_DVBS_GetCurrentSymbolRateOffset(MS_U16 *pData);
454
455 #if (INTERN_DVBS_INTERNAL_DEBUG)
456 void INTERN_DVBS_info(void);
457 MS_BOOL INTERN_DVBS_Show_AGC_Info(void);
458 #endif
459
460 //------------------------------------------------------------------
461 // System Info Function
462 //------------------------------------------------------------------
463 //=====================================================================================
INTERN_DVBS_DSPReg_Init(const MS_U8 * u8DVBS_DSPReg,MS_U8 u8Size)464 MS_U16 INTERN_DVBS_DSPReg_Init(const MS_U8 *u8DVBS_DSPReg, MS_U8 u8Size)
465 {
466 #if 0
467 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
468 #endif
469 MS_U8 status = true;
470 #if 0
471 MS_U16 u16DspAddr = 0;
472 #endif
473 DBG_INTERN_DVBS(printf("INTERN_DVBS_DSPReg_Init\n"));
474
475 #if 0//def MS_DEBUG
476 {
477 MS_U8 u8buffer[256];
478 printf("INTERN_DVBS_DSPReg_Init Reset\n");
479 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
480 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, 0);
481
482 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
483 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
484 printf("INTERN_DVBS_DSPReg_Init ReadBack, should be all 0\n");
485 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
486 printf("%x ", u8buffer[idx]);
487 printf("\n");
488
489 printf("INTERN_DVBS_DSPReg_Init Value\n");
490 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
491 printf("%x ", INTERN_DVBS_DSPREG[idx]);
492 printf("\n");
493 }
494 #endif
495
496 //for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
497 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBS_DSPREG[idx]);
498
499 // readback to confirm.
500 // ~read this to check mailbox initial values
501 #if 0
502 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
503 {
504 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &u8RegRead);
505 if (u8RegRead != INTERN_DVBS_DSPREG[idx])
506 {
507 DBG_INTERN_DVBS(printf("[Error]INTERN_DVBS_DSPReg_Init, idx=%d, drv_val=0x%x, firmware_val=0x%x\n",idx,INTERN_DVBS_DSPREG[idx],u8RegRead));
508 }
509 }
510 #endif
511 #if 0
512 if (u8DVBS_DSPReg != NULL)
513 {
514 if (1 == u8DVBS_DSPReg[0])
515 {
516 u8DVBS_DSPReg+=2;
517 for (idx = 0; idx<u8Size; idx++)
518 {
519 u16DspAddr = *u8DVBS_DSPReg;
520 u8DVBS_DSPReg++;
521 u16DspAddr = (u16DspAddr) + ((*u8DVBS_DSPReg)<<8);
522 u8DVBS_DSPReg++;
523 u8Mask = *u8DVBS_DSPReg;
524 u8DVBS_DSPReg++;
525 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
526 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBS_DSPReg) & (u8Mask));
527 u8DVBS_DSPReg++;
528 DBG_INTERN_DVBS(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
529 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
530 }
531 }
532 else
533 {
534 DBG_INTERN_DVBS(printf("FATAL: parameter version incorrect\n"));
535 }
536 }
537 #endif
538 #if 0//def MS_DEBUG
539 {
540 MS_U8 u8buffer[256];
541 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
542 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
543 printf("INTERN_DVBC_DSPReg_Init ReadBack\n");
544 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
545 printf("%x ", u8buffer[idx]);
546 printf("\n");
547 }
548 #endif
549
550 #if 0//def MS_DEBUG
551 {
552 MS_U8 u8buffer[256];
553 for (idx = 0; idx<128; idx++)
554 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2380+idx, &(u8buffer[idx]));
555 printf("INTERN_DVBS_DSPReg_Init ReadReg 0x2000~0x207F\n");
556 for (idx = 0; idx<128; idx++)
557 {
558 printf("%x ", u8buffer[idx]);
559 if ((idx & 0xF) == 0xF) printf("\n");
560 }
561 printf("\n");
562 }
563 #endif
564 return status;
565 }
566
567 /***********************************************************************************
568 Subject: Command Packet Interface
569 Function: INTERN_DVBS_Cmd_Packet_Send
570 Parmeter:
571 Return: MS_BOOL
572 Remark:
573 ************************************************************************************/
INTERN_DVBS_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)574 MS_BOOL INTERN_DVBS_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
575 {
576 MS_U8 status = true, indx;
577 MS_U8 reg_val, timeout = 0;
578 return true;
579
580 // ==== Command Phase ===================
581 DBG_INTERN_DVBS(printf("--->INTERN_DVBS (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
582 pCmdPacket->param[0],pCmdPacket->param[1],
583 pCmdPacket->param[2],pCmdPacket->param[3],
584 pCmdPacket->param[4],pCmdPacket->param[5] ));
585
586 // wait _BIT_END clear
587 do
588 {
589 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
590 if((reg_val & _BIT_END) != _BIT_END)
591 {
592 break;
593 }
594 MsOS_DelayTask(5);
595 if (timeout > 200)
596 {
597 DBG_INTERN_DVBS(printf("---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n"));
598 return false;
599 }
600 timeout++;
601 } while (1);
602
603 // set cmd_3:0 and _BIT_START
604 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
605 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
606 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
607
608
609 //DBG_INTERN_DVBS(printf("demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
610 // wait _BIT_START clear
611 do
612 {
613 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
614 if((reg_val & _BIT_START) != _BIT_START)
615 {
616 break;
617 }
618 MsOS_DelayTask(10);
619 if (timeout > 200)
620 {
621 DBG_INTERN_DVBS(printf("---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n"));
622 return false;
623 }
624 timeout++;
625 } while (1);
626
627 // ==== Data Phase ======================
628
629 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
630
631 for (indx = 0; indx < param_cnt; indx++)
632 {
633 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
634 //DBG_INTERN_DVBS(printf("demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
635
636 // set param[indx] and _BIT_DRQ
637 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
638 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
639 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
640
641 // wait _BIT_DRQ clear
642 do
643 {
644 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
645 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
646 {
647 break;
648 }
649 MsOS_DelayTask(5);
650 if (timeout > 200)
651 {
652 DBG_INTERN_DVBS(printf("---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n"));
653 return false;
654 }
655 timeout++;
656 } while (1);
657 }
658
659 // ==== End Phase =======================
660
661 // set _BIT_END to finish command
662 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
663 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
664
665 return status;
666 }
667
668 /***********************************************************************************
669 Subject: Command Packet Interface
670 Function: INTERN_DVBS_Cmd_Packet_Exe_Check
671 Parmeter:
672 Return: MS_BOOL
673 Remark:
674 ************************************************************************************/
INTERN_DVBS_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)675 MS_BOOL INTERN_DVBS_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
676 {
677 return TRUE;
678 }
679
680 /***********************************************************************************
681 Subject: SoftStop
682 Function: INTERN_DVBS_SoftStop
683 Parmeter:
684 Return: MS_BOOL
685 Remark:
686 ************************************************************************************/
INTERN_DVBS_SoftStop(void)687 MS_BOOL INTERN_DVBS_SoftStop ( void )
688 {
689 #if 1
690 MS_U16 u16WaitCnt=0;
691
692 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
693 {
694 DBG_INTERN_DVBS(printf(">> MB Busy!\n"));
695 return FALSE;
696 }
697
698 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
699
700 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
701 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
702
703 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
704 {
705 if (u16WaitCnt++ >= 0xFFF)// 0xFF)
706 {
707 DBG_INTERN_DVBS(printf(">> DVBT SoftStop Fail!\n"));
708 return FALSE;
709 }
710 }
711
712 //HAL_DMD_RIU_WriteByte(0x103460, 0x01); // reset VD_MCU
713 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
714 #endif
715 return TRUE;
716 }
717
718 /***********************************************************************************
719 Subject: Reset
720 Function: INTERN_DVBC_Reset
721 Parmeter:
722 Return: MS_BOOL
723 Remark:
724 ************************************************************************************/
725 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
726
INTERN_DVBS_Reset(void)727 MS_BOOL INTERN_DVBS_Reset ( void )// no midify
728 {
729 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_reset\n"));
730
731 DBG_INTERN_DVBS_TIME(printf("INTERN_DVBS_Reset, t = %d\n",MsOS_GetSystemTime()));
732
733 //INTERN_DVBS_SoftStop();
734
735 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x02); // reset RIU remapping reset
736 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x03); // reset DMD_MCU
737
738 MsOS_DelayTask(1);
739 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
740
741 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
742 MsOS_DelayTask(5);
743
744 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
745 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
746
747 u32ChkScanTimeStartDVBS = MsOS_GetSystemTime();
748 g_dvbs_lock = 0;
749
750 return TRUE;
751 }
INTERN_DVBS_PowerSaving(void)752 MS_BOOL INTERN_DVBS_PowerSaving ( void )
753 {
754 MS_U8 i;
755
756 //---P2=0---/;
757 for( i = 0; i < 231; i++){
758 MDrv_SYS_DMD_VD_MBX_WriteReg(0x350A + i, 0x11);}
759 // `M3_RIU_W((`RIUBASE_DMD_CLKGEN>>1)+7'h40, 2'b01, 16'h0000);
760 MDrv_SYS_DMD_VD_MBX_WriteReg(0x3580, 0x00);
761
762 //---P2=1---/;
763 for( i = 0; i < 146; i++){
764 MDrv_SYS_DMD_VD_MBX_WriteReg(0xA202 + i, 0x11);}
765 // `M3_RIU_W((`RIUBASE_DMD_CLKGEN_EXT>>1)+7'h14, 2'b01, 16'h0003);
766 MDrv_SYS_DMD_VD_MBX_WriteReg(0xA228, 0x03);
767
768 // ================================================================
769 // DEMOD_1 CLOCK GATED
770 // ================================================================
771 //---P2=0---/;
772 for( i = 0; i <= 177; i++){
773 MDrv_SYS_DMD_VD_MBX_WriteReg(0x3635+ i, 0x11);}
774 // `M3_RIU_W((`RIUBASE_DMD_CLKGEN_1>>1)+7'h1b, 2'b01, 16'h000f);
775 MDrv_SYS_DMD_VD_MBX_WriteReg(0x3636, 0x0f);
776
777
778 // ================================================================
779 // SRAM Power Down
780 // ================================================================
781 // [ 0]reg_force_allsram_on = 1'b0
782 // [ 1]reg_force_allsram_on_demod_1 = 1'b0
783 // [ 2] = 1'b0
784 // [ 3]reg_demod_1_sram_sd_en = 1'b0
785 // [ 4]reg_manhattan_sram_share_sram_sd_en = 1'b0
786 // [ 5]reg_mulan_sram_share_sram_sd_en = 1'b0
787 // [ 6]reg_dvb_frontend_sram_sd_en = 1'b0
788 // [ 7]reg_dtmb_sram_sd_en = 1'b0
789 // [ 8]reg_dvbt_sram_sd_en = 1'b0
790 // [ 9]reg_atsc_sram_sd_en = 1'b0
791 // [10]reg_vif_sram_sd_en = 1'b0
792 // [11]reg_backend_sram_sd_en = 1'b0
793 // [12]reg_adcdma_sram_sd_en = 1'b0
794 // [13]reg_isdbt_sram_sd_en = 1'b0
795 // [14]reg_dvbt2_sram_sd_en = 1'b0
796 // [15]reg_dvbs2_sram_sd_en = 1'b0
797 // `M3_RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h48, 2'b11, 16'hfffc);
798 // `M3_RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h48, 2'b11, 16'hfffc);
799 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2091, 0xff);
800 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2090, 0xfc);
801
802 // all controlled by reg_mulan_sram_share_sram_sd_en
803 // reg_sram_pwr_ctrl_sel[15:0]
804 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h70, 2'b11, 16'h0000);
805 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h70, 2'b11, 16'h0000);
806 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e1, 0x00);
807 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e0, 0x00);
808 // reg_sram_pwr_ctrl_sel[31:16]
809 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h71, 2'b11, 16'h0000);
810 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h71, 2'b11, 16'h0000);
811 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e3, 0x00);
812 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e2, 0x00);
813 // reg_sram_pwr_ctrl_sel[47:32]
814 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h72, 2'b11, 16'h0000);
815 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h72, 2'b11, 16'h0000);
816 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e5, 0x00);
817 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e4, 0x00);
818 // reg_sram_pwr_ctrl_sel[63:48]
819 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h73, 2'b11, 16'h0000);
820 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h73, 2'b11, 16'h0000);
821 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e7, 0x00);
822 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e6, 0x00);
823 // reg_sram_pwr_ctrl_sel[79:64]
824 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h74, 2'b11, 16'h0000);
825 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h74, 2'b11, 16'h0000);
826 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e9, 0x00);
827 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e8, 0x00);
828
829 // $display("================================================================");
830 // $display("Reset");
831 // $display("================================================================");
832 // Release DVBT2 & dmd_ana_misc Reset
833 // [0] reg_atsc_on[0]
834 // [1] reg_dvbt_on[1]
835 // [2] reg_vif_on[2]
836 // [3] reg_isdbt_on[3]
837 // [4] reg_atsc_rst[4]
838 // [5] reg_dvbt_rst[5]
839 // [6] reg_vif_rst[6]
840 // [7] reg_get_adc[7]
841 // [8] reg_ce8x_gate[8]
842 // [9] reg_ce_gate[9]
843 // [10] reg_dac_clk_inv[10]
844 // [11] reg_vdmcu_clock_faster[11]
845 // [12] reg_vif_if_agc_sel[12]
846 // [13] reg_dmd_ana_misc_rst[13]
847 // [14] reg_adcd_wmask[14]
848 // [15] reg_sif_only[15]
849 // `M3_RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h01, 2'b11, 16'h2070);
850
851 // Release DTMB Reset & Enable Manhattan frontend Enable
852 // [0] reg_dtmb_on
853 // [1] reg_dtmb_rst
854 // [4] reg_manhattan_frontend_on //No used @ Maserati
855 // [5] reg_manhattan_dvb_srd_sw_rst (1'b1 for DTMB)
856 // `M3_RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h02, 2'b01, 16'h0022);
857
858 // ================================================================
859 // MPLL Power Down
860 // ================================================================
861 // Set MPLL_ADC_DIV_SE
862 // [0] : reg_mpll_adc_clk_cc_en
863 // [1] : reg_adc_clk_pd
864 // [2] : reg_mpll_div2_pd
865 // [3] : reg_mpll_div3_pd
866 // [4] : reg_mpll_div4_pd
867 // [5] : reg_mpll_div8_pd
868 // [6] : reg_mpll_div10_pd
869 // [7] : reg_mpll_div17_pd
870 // [13:8]: reg_mpll_adc_div_sel
871 // `M3_RIU_W((`RIUBASE_DMD_ANA_MISC_M3>>1)+7'h30, 2'b01, 16'h12fe);//Different
872 // `M3_RIU_W((`RIUBASE_DMD_ANA_MISC_M3>>1)+7'h30, 2'b01, 16'h12fe);//Different
873 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2e60, 0xfe);
874
875 // [2:0] : reg_mpll_ictrl set 3'h3
876 // [3] : reg_mpll_in_sel set 1'h0
877 // [4] : reg_mpll_xtal2adc_sel if 1'h1 ADC_CLK=XTAL.
878 // [5] : reg_mpll_xtal2next_pll_sel
879 // [6] : reg_mpll_vco_offset(T8), reg_mpll_adc_clk_cc_mode(T9)
880 // [7] : reg_mpll_pd set 1'b1
881 // [8] : reg_xtal_en set 1'b0
882 // [10:9]: reg_xtal_sel set 2'h3 XTAL strength
883 // [11] : reg_mpll_porst set 1'b1
884 // [12] : reg_mpll_reset set 1'b1
885 // [13] : reg_pd_dmpll_clk XTAL to MPLL clock reference power down
886 // [14] : reg_mpll_pdiv_clk_pd set 1'b0
887 // Set MPLL_RESET=MPLL_PORST=1
888 // `M3_RIU_W((`RIUBASE_DMD_ANA_MISC_M3>>1)+7'h35, 2'b11, 16'h1e83);//Different
889 // `M3_RIU_W((`RIUBASE_DMD_ANA_MISC_M3>>1)+7'h35, 2'b11, 16'h1e83);//Different
890 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2e6b, 0x1e);
891 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2e6a, 0x83);
892
893 return TRUE;
894 }
895 /***********************************************************************************
896 Subject: Exit
897 Function: INTERN_DVBC_Exit
898 Parmeter:
899 Return: MS_BOOL
900 Remark:
901 ************************************************************************************/
INTERN_DVBS_Exit(void)902 MS_BOOL INTERN_DVBS_Exit ( void )
903 {
904 MS_U8 u8Data=0;
905 MS_U8 u8Data_temp=0;
906
907 u8Data_temp=HAL_DMD_RIU_ReadByte(0x101E39);
908 HAL_DMD_RIU_WriteByte(0x101E39, 0);
909
910 u8Data=HAL_DMD_RIU_ReadByte(0x1128C0);
911 u8Data&=~(0x02);
912 HAL_DMD_RIU_WriteByte(0x1128C0, u8Data);//revert IQ Swap status
913
914 HAL_DMD_RIU_WriteByte(0x101E39, u8Data_temp);
915 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_Exit\n"));
916 INTERN_DVBS_SoftStop();
917 INTERN_DVBS_PowerSaving();
918
919 return TRUE;
920 }
921
922 /***********************************************************************************
923 Subject: Load DSP code to chip
924 Function: INTERN_DVBS_LoadDSPCode
925 Parmeter:
926 Return: MS_BOOL
927 Remark:
928 ************************************************************************************/
INTERN_DVBS_LoadDSPCode(void)929 static MS_BOOL INTERN_DVBS_LoadDSPCode(void)
930 {
931 MS_U8 udata = 0x00;
932 MS_U16 i;
933 MS_U16 fail_cnt=0;
934
935 #if (DBG_DUMP_LOAD_DSP_TIME==1)
936 MS_U32 u32Time;
937 #endif
938
939 //MDrv_Sys_DisableWatchDog();
940 /*
941 HAL_DMD_RIU_WriteByte(0x103480, 0x01);//reference GUI//reset
942 HAL_DMD_RIU_WriteByte(0x103481, 0x00);
943 HAL_DMD_RIU_WriteByte(0x103480, 0x00);
944 HAL_DMD_RIU_WriteByte(0x103483, 0x50);
945 HAL_DMD_RIU_WriteByte(0x103483, 0x51);
946 HAL_DMD_RIU_WriteByte(0x103484, 0x00);
947 HAL_DMD_RIU_WriteByte(0x103485, 0x00);
948 */
949 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
950 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
951 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
952 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
953 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
954 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
955
956 //// Load code thru VDMCU_IF ////
957 DBG_INTERN_DVBS(printf(">Load Code.....\n"));
958 for ( i = 0; i < sizeof(INTERN_DVBS_table); i++)
959 {
960 HAL_DMD_RIU_WriteByte(0x10348C, INTERN_DVBS_table[i]);
961 //HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBS_table[i]); // write data to VD MCU 51 code sram
962 }
963
964 //// Content verification ////
965 DBG_INTERN_DVBS(printf(">Verify Code...\n"));
966
967 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
968 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
969
970 for ( i = 0; i < sizeof(INTERN_DVBS_table); i++)
971 {
972 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
973 if (udata != INTERN_DVBS_table[i])
974 {
975 printf(">fail add = 0x%x\n", i);
976 printf(">code = 0x%x\n", INTERN_DVBS_table[i]);
977 printf(">data = 0x%x\n", udata);
978
979 if (fail_cnt > 10)
980 {
981 printf(">DVB-S DSP Loadcode fail!");
982 return false;
983 }
984 fail_cnt++;
985 }
986 }
987
988 #if 0 //use for Kris DJB with VCM
989 //====================================================================
990 // add S2 DRAM bufer start address into fixed location
991 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x30); // sram address low byte; 0x30 is defined in FW
992 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
993
994 //0x30~0x33
995 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBS2_DJB_START_ADDR);
996 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBS2_DJB_START_ADDR >> 8));
997 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBS2_DJB_START_ADDR >> 16));
998 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBS2_DJB_START_ADDR >> 24));
999
1000 printf("@@@@@ share dram address = 0x %x \n ",u32DMD_DVBS2_DJB_START_ADDR);
1001 //=====================================================================
1002 #endif
1003
1004 /*
1005 HAL_DMD_RIU_WriteByte(0x103483, 0x50);
1006 HAL_DMD_RIU_WriteByte(0x103483, 0x00);
1007 HAL_DMD_RIU_WriteByte(0x103480, 0x01);
1008 HAL_DMD_RIU_WriteByte(0x103481, 0x01);
1009 HAL_DMD_RIU_WriteByte(0x103480, 0x00);
1010 */
1011
1012 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
1013 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
1014 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
1015 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
1016
1017
1018 DBG_INTERN_DVBS(printf(">DSP Loadcode done."));
1019 #if 0
1020 INTERN_DVBS_Config(6875, 128, 36125, 0,1);
1021 INTERN_DVBS_Active(ENABLE);
1022 while(1);
1023 #endif
1024 //HAL_DMD_RIU_WriteByte(0x101E3E, 0x04); // DVBT = BIT1 -> 0x02
1025
1026 return TRUE;
1027 }
1028
1029 /***********************************************************************************
1030 Subject: DVB-S CLKGEN initialized function
1031 Function: INTERN_DVBS_Power_On_Initialization
1032 Parmeter:
1033 Return: MS_BOOL
1034 Remark:
1035 ************************************************************************************/
INTERN_DVBS_InitClkgen(MS_BOOL bRFAGCTristateEnable)1036 void INTERN_DVBS_InitClkgen(MS_BOOL bRFAGCTristateEnable)
1037 {
1038 //MS_U8 u8Temp=0;
1039 // This file is translated by Steven Hung's riu2script.pl
1040
1041 // ==============================================================
1042 // Start demod top initial setting by HK MCU ......
1043 // ==============================================================
1044 // [8] : reg_chiptop_dummy_0 (reg_dmdtop_dmd_sel)
1045 // 1'b0->reg_DMDTOP control by HK_MCU.
1046 // 1'b1->reg_DMDTOP control by DMD_MCU.
1047 // [9] : reg_chiptop_dummy_0 (reg_dmd_ana_regsel)
1048 // 1'b0->reg_DMDANA control by HK_MCU.
1049 // 1'b1->reg_DMDANA control by DMD_MCU.
1050 // select HK MCU ......
1051 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0000);
1052 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0000);
1053 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
1054
1055 // ============================================================== ADC SYNC FLOW START
1056 // DMD_ANA_ADC_SYNC CLK_W
1057 // [4:0] : reg_ckg_adcd
1058 // [0] : disable clock = 1'b1
1059 // [1] : invert clock
1060 // `RIU_W((`RIUBASE_DMD_ANA_MISC>>1)+7'h68, 2'b01, 16'h0001);
1061 // `RIU_W((`RIUBASE_DMD_ANA_MISC>>1)+7'h68, 2'b01, 16'h0001);
1062 //wriu 0x1128d0 0x01
1063 HAL_DMD_RIU_WriteByte(0x1128d0,0x01);
1064 // ============================================================== ADC SYNC FLOW END
1065
1066 // ==============================================================
1067 // Start TOP CLKGEN initial setting ......
1068 // ==============================================================
1069 // CLK_DMDMCU clock setting
1070 // reg_ckg_dmdmcu@0x0f[4:0]
1071 // [0] : disable clock
1072 // [1] : invert clock
1073 // [4:2]:
1074 // 000:170 MHz(MPLL_DIV_BUF)
1075 // 001:160MHz
1076 // 010:144MHz
1077 // 011:123MHz
1078 // 100:108MHz (Kriti:DVBT2)
1079 // 101:mem_clcok
1080 // 110:mem_clock div 2
1081 // 111:select XTAL
1082 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
1083 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
1084 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1085 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1086
1087
1088 // set parallel ts clock
1089 // [11] : reg_ckg_demod_test_in_en = 0
1090 // 0: select internal ADC CLK
1091 // 1: select external test-in clock
1092 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
1093 // 0: select gated clock
1094 // 1: select free-run clock
1095 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
1096 // 0: normal phase to pad
1097 // 1: invert phase to pad
1098 // [8] : reg_ckg_atsc_dvb_div_sel = 1
1099 // 0: select clk_dmplldiv5
1100 // 1: select clk_dmplldiv3
1101 // [4:0]: reg_ckg_dvbtm_ts_divnum = 11
1102 // Demod TS output clock phase tuning number
1103 // If (reg_ckg_tsout_ph_tun_num == reg_ckg_dvbtm_ts_divnum),
1104 // Demod TS output clock is equal Demod TS internal working clock.
1105 // => TS clock = (864/3)/(2*(5+1)) = 24MHz
1106 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1107 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1108 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1109 HAL_DMD_RIU_WriteByte(0x103300, 0x05);
1110
1111
1112 // enable DVBTC ts clock
1113 // [11:8]: reg_ckg_dvbtc_ts
1114 // [8] : disable clock
1115 // [9] : invert clock
1116 // [11:10]: Select clock source
1117 // 00:clk_atsc_dvb_div
1118 // 01:62 MHz
1119 // 10:54 MHz
1120 // 11:reserved
1121 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
1122 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
1123 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1124 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1125
1126
1127 // enable dvbc adc clock
1128 // [3:0]: reg_ckg_dvbtc_adc
1129 // [0] : disable clock
1130 // [1] : invert clock
1131 // [3:2]: Select clock source => for demod clkgen clk_dvbtc_adc
1132 // 00: clk_dmdadc
1133 // 01: clk_dmdadc_div2
1134 // 10: clk_dmdadc_div4
1135 // 11: DFT_CLK
1136 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
1137 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
1138 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1139 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1140
1141
1142 // ==============================================================
1143 // Start demod_0 CLKGEN setting ......
1144 // ==============================================================
1145 // enable atsc_adcd_sync clock
1146 // [3:0] : reg_ckg_atsc_adcd_sync
1147 // [0] : disable clock
1148 // [1] : invert clock
1149 // [3:2]: Select clock source
1150 // 00: clk_dmdadc_sync
1151 // 01: 1'b0
1152 // 10: 1'b0
1153 // 11: DFT_CLK
1154 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
1155 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
1156 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1157 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1158
1159 // DMD_ANA_ADC_SYNC CLK_W
1160 // [4:0] : reg_ckg_adcd
1161 // [0] : disable clock = 1'b0
1162 // [1] : invert clock
1163 // [12:8] : reg_ckg_adcd_q
1164 // [0] : disable clock = 1'b0
1165 // [1] : invert clock
1166 // `RIU_W((`RIUBASE_DMD_ANA_MISC>>1)+7'h68, 2'b11, 16'h0000);
1167 // `RIU_W((`RIUBASE_DMD_ANA_MISC>>1)+7'h68, 2'b11, 16'h0000);
1168 //wriu 0x1128d1 0x00
1169 //wriu 0x1128d0 0x00
1170 HAL_DMD_RIU_WriteByte(0x1128d1, 0x00);
1171 HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
1172
1173 // DVBS2
1174 // @0x350c
1175 // [3:0] : reg_ckg_dvbs_outer1x
1176 // [0] : disable clock
1177 // [1] : invert clock
1178 // [3:2]: Select clock source
1179 // 00: adc_clk_buf
1180 // 01: dvb_clk86_buf
1181 // 10: dvb_clk43_buf
1182 // 11: 1'b0
1183 // [6:4] : reg_ckg_dvbs_outer2x
1184 // [4] : disable clock
1185 // [5] : invert clock
1186 // [6] : Select clock source
1187 // 00: adc_clk_buf
1188 // 01: 1'b0
1189 // 10: 1'b0
1190 // 11: DFT_CLK
1191 // [10:8]: reg_ckg_dvbs2_inner
1192 // [8] : disable clock
1193 // [9] : invert clock
1194 // [10]: Select clock source
1195 // 00: adc_clk_buf
1196 // 01: 1'b0
1197 // 10: 1'b0
1198 // 11: DFT_CLK
1199 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1200 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1201 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1202 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1203
1204
1205 // DVBS2
1206 // @0x350d
1207 // [11:8]: reg_ckg_dvbs2_oppro
1208 // [8] : disable clock
1209 // [9] : invert clock
1210 // [11:10]: Select clock source
1211 // 00: mpll_clk144_buf
1212 // 01: mpll_clk96_buf
1213 // 10: mpll_clk72_buf
1214 // 11: mpll_clk48_buf
1215 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0d, 2'b11, 16'h0000);
1216 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0d, 2'b11, 16'h0000);
1217 HAL_DMD_RIU_WriteByte(0x111f1b, 0x00);
1218 HAL_DMD_RIU_WriteByte(0x111f1a, 0x00);
1219
1220
1221 // @0x3510
1222 // [3:0] : reg_ckg_dvbtm_adc
1223 // N/A
1224 // [6:4] : reg_ckg_dvbt_inner1x
1225 // [4] : disable clock
1226 // [5] : invert clock
1227 // [6] : Select clock source
1228 // 00: dvb_clk24_buf
1229 // 01: dvb_clk21p5_buf
1230 // 10: 1'b0
1231 // 11: DFT_CLK
1232 // [10:8] reg_ckg_dvbt_inner2x
1233 // [8] : disable clock
1234 // [9] : invert clock
1235 // [10]: Select clock source
1236 // 00: dvb_clk48_buf
1237 // 01: dvb_clk43_buf
1238 // 10: 1'b0
1239 // 11: DFT_CLK
1240 // [14:12] reg_ckg_dvbt_inner4x
1241 // [12]: disable clock
1242 // [13]: invert clock
1243 // [14]: Select clock source
1244 // 00: dvb_clk96_buf
1245 // 01: dvb_clk86_buf
1246 // 10: 1'b0
1247 // 11: DFT_CLK
1248 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h1110);
1249 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h1110);
1250 HAL_DMD_RIU_WriteByte(0x111f21, 0x11);
1251 HAL_DMD_RIU_WriteByte(0x111f20, 0x10);
1252
1253 // @0x3511
1254 // [2:0] : reg_ckg_dvbt_outer1x
1255 // [0] : disable clock
1256 // [1] : invert clock
1257 // [2] : Select clock source
1258 // 00: dvb_clk48_buf
1259 // 01: dvb_clk43_buf
1260 // 10: 1'b0
1261 // 11: DFT_CLK
1262 // [6:4] : reg_ckg_dvbt_outer2x
1263 // [4] : disable clock
1264 // [5] : invert clock
1265 // [6] : Select clock source
1266 // 00: dvb_clk96_buf
1267 // 01: dvb_clk86_buf
1268 // 10: 1'b0
1269 // 11: DFT_CLK
1270 // [11:8]: reg_ckg_dvbtc_outer2x
1271 // [8] : disable clock
1272 // [9] : invert clock
1273 // [11:10]: Select clock source
1274 // 00: mpll_clk57p6_buf
1275 // 01: dvb_clk43_buf
1276 // 10: dvb_clk86_buf
1277 // 11: dvb_clk96_buf
1278 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0c11);
1279 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0c11);
1280 HAL_DMD_RIU_WriteByte(0x111f23, 0x0c);
1281 HAL_DMD_RIU_WriteByte(0x111f22, 0x11);
1282
1283
1284 // @0x3512
1285 // [11:8]: reg_ckg_acifir
1286 // [8] : disable clock
1287 // [9] : invert clock
1288 // [11:10]: Select clock source
1289 // 000: 1'b0
1290 // 001: clk_dmdadc
1291 // 010: clk_vif_ssc_mux
1292 // 011: 1'b0
1293 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b10, 16'h0400);
1294 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b10, 16'h0400);
1295 HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1296
1297
1298 // @0x3514
1299 // [12:8]: reg_ckg_dvbtm_sram_t1o2x_t22x
1300 // [8] : disable clock
1301 // [9] : invert clock
1302 // [12:10]: Select clock source
1303 // 000: dvb_clk48_buf
1304 // 001: dvb_clk43_buf
1305 // 010: 1'b0
1306 // 011: 1'b0
1307 // 100: 1'b0
1308 // 101: 1'b0
1309 // 110: 1'b0
1310 // 111: 1'b0
1311 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b11, 16'h0000);
1312 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b11, 16'h0000);
1313 HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
1314 HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1315
1316
1317 // @0x3516
1318 // [8:4] : reg_ckg_dvbtm_sram_adc_t22x
1319 // [4] : disable clock
1320 // [5] : invert clock
1321 // [8:6]: Select clock source
1322 // 000: dvb_clk48_buf
1323 // 001: dvb_clk43_buf
1324 // 010: 1'b0
1325 // 011: 1'b0
1326 // 100: adc_clk_buf
1327 // 101: 1'b0
1328 // 110: 1'b0
1329 // 111: 1'b0
1330 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h16, 2'b11, 16'h0001);
1331 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h16, 2'b11, 16'h0001);
1332 HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
1333 HAL_DMD_RIU_WriteByte(0x111f2c, 0x01);
1334
1335
1336 // @0x3517
1337 // [4:0] : reg_ckg_dvbtm_sram_t12x_t22x
1338 // [0] : disable clock
1339 // [1] : invert clock
1340 // [4:2]: Select clock source
1341 // 000: dvb_clk48_buf
1342 // 001: dvb_clk43_buf
1343 // 010: 1'b0
1344 // 011: 1'b0
1345 // 100: 1'b0
1346 // 101: 1'b0
1347 // 110: 1'b0
1348 // 111: 1'b0
1349 // [12:8] reg_ckg_dvbtm_sram_t12x_t24x
1350 // [8] : disable clock
1351 // [9] : invert clock
1352 // [12:10]: Select clock source
1353 // 000: dvb_clk96_buf
1354 // 001: dvb_clk86_buf
1355 // 010: dvb_clk48_buf
1356 // 011: dvb_clk43_buf
1357 // 100: 1'b0
1358 // 101: 1'b0
1359 // 110: 1'b0
1360 // 111: 1'b0
1361 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h17, 2'b11, 16'h0000);
1362 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h17, 2'b11, 16'h0000);
1363 HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
1364 HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
1365
1366
1367 // @0x3518
1368 // [4:0] : reg_ckg_dvbtm_sram_t14x_t24x
1369 // [0] : disable clock
1370 // [1] : invert clock
1371 // [4:2]: Select clock source
1372 // 000: dvb_clk96_buf
1373 // 001: dvb_clk96_buf
1374 // 010: 1'b0
1375 // 011: 1'b0
1376 // 100: 1'b0
1377 // 101: 1'b0
1378 // 110: 1'b0
1379 // 111: 1'b0
1380 // [12:8]: reg_ckg_dvbtm_ts_in
1381 // [8] : disable clock
1382 // [9] : invert clock
1383 // [12:10]: Select clock source
1384 // 000: clk_dvbtc_rs_p
1385 // 001: dvb_clk48_buf
1386 // 010: dvb_clk43_buf
1387 // 011: clk_dvbs_outer1x_pre_mux4
1388 // 100: clk_dvbs2_oppro_pre_mux4
1389 // 101: 1'b0
1390 // 110: 1'b0
1391 // 111: 1'b0
1392 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b11, 16'h0001);
1393 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b11, 16'h0001);
1394 HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1395 HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1396
1397
1398 // @0x3519
1399 // [2:0] : reg_ckg_tdp_jl_inner1x
1400 // [0] : disable clock
1401 // [1] : invert clock
1402 // [2] : Select clock source
1403 // 00: dvb_clk24_buf
1404 // 01: dvb_clk21p5_buf
1405 // 10: 1'b0
1406 // 11: DFT_CLK
1407 // [6:4] : reg_ckg_tdp_jl_inner4x
1408 // [4] : disable clock
1409 // [5] : invert clock
1410 // [6] : Select clock source
1411 // 00: dvb_clk96_buf
1412 // 01: dvb_clk86_buf
1413 // 10: 1'b0
1414 // 11: DFT_CLK
1415 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h19, 2'b11, 16'h3c00);
1416 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h19, 2'b11, 16'h3c00);
1417 HAL_DMD_RIU_WriteByte(0x111f33, 0x3c);
1418 HAL_DMD_RIU_WriteByte(0x111f32, 0x00);
1419
1420
1421 // @0x351a
1422 // [6:4] : reg_ckg_dvbt2_inner1x
1423 // [4] : disable clock
1424 // [5] : invert clock
1425 // [6] : Select clock source
1426 // 00: dvb_clk96_buf
1427 // 01: dvb_clk86_buf
1428 // 10: 1'b0
1429 // 11: DFT_CLK
1430 // [10:8]: reg_ckg_dvbt2_inner2x
1431 // [8] : disable clock
1432 // [9] : invert clock
1433 // [10]: Select clock source
1434 // 00: dvb_clk48_buf
1435 // 01: dvb_clk43_buf
1436 // 10: 1'b0
1437 // 11: DFT_CLK
1438 // [14:12]:reg_ckg_dvbt2_inner4x
1439 // [12] : disable clock
1440 // [13] : invert clock
1441 // [14] : Select clock source
1442 // 00: dvb_clk96_buf
1443 // 01: dvb_clk86_buf
1444 // 10: 1'b0
1445 // 11: DFT_CLK
1446 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1a, 2'b11, 16'h0000);
1447 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1a, 2'b11, 16'h0000);
1448 HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
1449 HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
1450
1451
1452 // @0x351b
1453 // [1:0] : reg_ckg_dvbt2_ldpc
1454 // DVBT2 LDPC gated clock control register
1455 // [0] = 1:clock enable.
1456 // [1] = 1:manual mode.
1457 // [3:2] : reg_ckg_dvbt2_bch
1458 // DVBT2 BCH gated clock control register;
1459 // [0] = 1:clock enable
1460 // [1] = 1:manual mode.
1461 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1b, 2'b11, 16'h0011);
1462 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1b, 2'b11, 16'h0011);
1463 HAL_DMD_RIU_WriteByte(0x111f37, 0x00);
1464 HAL_DMD_RIU_WriteByte(0x111f36, 0x11);
1465
1466
1467 // @0x351d
1468 // [4:0] : reg_ckg_dvbtm_adc_eq_1x
1469 // [0] : disable clock
1470 // [1] : invert clock
1471 // [2] : Select clock source
1472 // 00: adc_clk_buf
1473 // 01: 1'b0
1474 // 10: 1'b0
1475 // 11: DFT_CLK
1476 // [12:8]: reg_ckg_dvbtm_adc_eq_0p5x
1477 // [4] : disable clock
1478 // [5] : invert clock
1479 // [6]: Select clock source
1480 // 00: clk_adc_div2_buf
1481 // 01: 1'b0
1482 // 10: 1'b0
1483 // 11: DFT_CLK
1484 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1d, 2'b11, 16'h0000);
1485 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1d, 2'b11, 16'h0000);
1486 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1487 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1488
1489
1490 // @0x351e
1491 // [4:0] : reg_ckg_dvbtm_sram_t11x_t22x
1492 // [0] : disable clock
1493 // [1] : invert clock
1494 // [4:2]: Select clock source
1495 // 000: dvb_clk48_buf
1496 // 001: dvb_clk43_buf
1497 // 010: dvb_clk24_buf
1498 // 011: dvb_clk21p5_buf
1499 // 100: 1'b0
1500 // 101: 1'b0
1501 // 110: 1'b0
1502 // 111: 1'b0
1503 // [12:8]: reg_ckg_dvbtm_sram_t11x_t24x
1504 // [8] : disable clock
1505 // [9] : invert clock
1506 // [:2]: Select clock source
1507 // 000: dvb_clk48_buf
1508 // 001: dvb_clk43_buf
1509 // 010: dvb_clk24_buf
1510 // 011: dvb_clk21p5_buf
1511 // 100: 1'b0
1512 // 101: 1'b0
1513 // 110: 1'b0
1514 // 111: 1'b0
1515 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1e, 2'b11, 16'h0c04);
1516 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1e, 2'b11, 16'h0000);
1517 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1e, 2'b11, 16'h0000);
1518 HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
1519 HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
1520
1521
1522 // @0x3522
1523 // [3:0] : reg_ckg_dvbt_t2_inner0p5x_dvbc_eq1x
1524 // [0] : disable clock
1525 // [1] : invert clock
1526 // [2] : Select clock source
1527 // 00: dvb_clk12_buf
1528 // 01: dvb_clk10p75_buf
1529 // 10: 1'b0
1530 // 11: DFT_CLK
1531 // [7:4] : reg_ckg_dvbt_t2_inner2x_dvbc_eq4x
1532 // [4] : disable clock
1533 // [5] : invert clock
1534 // [6] : Select clock source
1535 // 00: dvb_clk48_buf
1536 // 01: dvb_clk43_buf
1537 // 10: 1'b0
1538 // 11: DFT_CLK
1539 // [11:8]: reg_ckg_dvbt_t2_inner1x
1540 // [8] : disable clock
1541 // [9] : invert clock
1542 // [11:10]: Select clock source
1543 // 00: dvb_clk24_buf
1544 // 01: dvb_clk21p5_buf
1545 // 10: 1'b0
1546 // 11: DFT_CLK
1547 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0111);
1548 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0111);
1549 HAL_DMD_RIU_WriteByte(0x111f45, 0x01);
1550 HAL_DMD_RIU_WriteByte(0x111f44, 0x11);
1551
1552 // @0x353a
1553 // [2:0] : reg_ckg_dvbtm_sram_t12x_t24x_srd1x_isdbt_inner2x
1554 // [0] : disable clock
1555 // [1] : invert clock
1556 // [2] : Select clock source
1557 // 00: clk_dvbtm_sram_t12x_t24x_srd1x_p
1558 // 01: clk_isdbt_inner2x_p
1559 // 10: 1'b0
1560 // 11: DFT_CLK
1561 // [6:4] : reg_ckg_dvbtm_sram_t12x_t24x_isdbt_inner2x
1562 // [4] : disable clock
1563 // [5] : invert clock
1564 // [6] : Select clock source
1565 // 00: clk_dvbtm_sram_t12x_t24x_p
1566 // 01: clk_isdbt_inner2x_p
1567 // 10: 1'b0
1568 // 11: DFT_CLK
1569 // [10:8]: reg_ckg_dvbtm_sram_t24x_isdbt_inner2x
1570 // [8] : disable clock
1571 // [9] : invert clock
1572 // [10]: Select clock source
1573 // 00: clk_dvbtm_sram_t14x_t24x_p
1574 // 01: clk_isdbt_inner2x_p
1575 // 10: 1'b0
1576 // 11: DFT_CLK
1577 // [14:12]: reg_ckg_dvbtm_sram_t12x_t24x_s2inner_isdbt_inner4x
1578 // [12] : disable clock
1579 // [13] : invert clock
1580 // [14] : Select clock source
1581 // 00: clk_dvbtm_sram_t12x_t24x_s2inner_p
1582 // 01: clk_isdbt_inner4x_p
1583 // 10: 1'b0
1584 // 11: DFT_CLK
1585 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3a, 2'b11, 16'h0110);
1586 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3a, 2'b11, 16'h0110);
1587 HAL_DMD_RIU_WriteByte(0x111f75, 0x01);
1588 HAL_DMD_RIU_WriteByte(0x111f74, 0x10);
1589
1590 // @0x353b
1591 // [2:0] : reg_ckg_dvbtm_sram_t12x_t24x_s2inner_isdbt_inner2x
1592 // [0] : disable clock
1593 // [1] : invert clock
1594 // [2] : Select clock source
1595 // 00: clk_dvbtm_sram_t12x_t24x_s2inner_p
1596 // 01: clk_isdbt_inner2x_p
1597 // 10: 1'b0
1598 // 11: DFT_CLK
1599 // [6:4] : reg_ckg_dvbtm_sram_t22x_isdbt_inner2x
1600 // [4] : disable clock
1601 // [5] : invert clock
1602 // [6] : Select clock source
1603 // 00: clk_dvbtm_sram_t12x_t22x_p
1604 // 01: clk_isdbt_inner2x_p
1605 // 10: 1'b0
1606 // 11: DFT_CLK
1607 // [10:8]: reg_ckg_dvbtm_sram_t14x_t24x_s2inner_isdbt_inner2x
1608 // [8] : disable clock
1609 // [9] : invert clock
1610 // [10]: Select clock source
1611 // 00: clk_dvbtm_sram_t14x_t24x_s2inner_p
1612 // 01: clk_isdbt_inner2x_p
1613 // 10: 1'b0
1614 // 11: DFT_CLK
1615 // [14:12]: reg_ckg_dvbtm_sram_t12x_t24x_srd1x_isdbt_inner4x
1616 // [12] : disable clock
1617 // [13] : invert clock
1618 // [14]: Select clock source
1619 // 00: clk_dvbtm_sram_t12x_t24x_srd1x_p
1620 // 01: clk_isdbt_inner4x_p
1621 // 10: 1'b0
1622 // 11: DFT_CLK
1623 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0010);
1624 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0010);
1625 HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
1626 HAL_DMD_RIU_WriteByte(0x111f76, 0x10);
1627
1628 // @0x353c
1629 // [2:0] : reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifssc_isdbt_inner4x
1630 // [0] : disable clock
1631 // [1] : invert clock
1632 // [2] : Select clock source
1633 // 00: clk_dvbtm_sram_t14x_t24x_srd1x_vifssc_p
1634 // 01: clk_isdbt_inner4x_p
1635 // 10: 1'b0
1636 // 11: DFT_CLK
1637 // [6:4] : reg_ckg_dvbtm_sram_t12x_t22x_isdbt_inner2x
1638 // [4] : disable clock
1639 // [5] : invert clock
1640 // [6] : Select clock source
1641 // 00: clk_dvbtm_sram_t12x_t22x_p
1642 // 01: clk_isdbt_inner2x_p
1643 // 10: 1'b0
1644 // 11: DFT_CLK
1645 // [10:8]: reg_ckg_dvbtm_sram_t11x_t22x_isdbt_inner2x
1646 // [8] : disable clock
1647 // [9] : invert clock
1648 // [10]: Select clock source
1649 // 00: clk_dvbtm_sram_t11x_t22x_p
1650 // 01: clk_isdbt_inner2x_p
1651 // 10: 1'b0
1652 // 11: DFT_CLK
1653 // [14:12]: reg_ckg_dvbtm_sram_t12x_t24x_isdbt_outer6x
1654 // [12] : disable clock
1655 // [13] : invert clock
1656 // [14]: Select clock source
1657 // 00: clk_dvbtm_sram_t12x_t24x_p
1658 // 01: clk_isdbt_outer6x_dvbt_outer2x_c_mux
1659 // 10: 1'b0
1660 // 11: DFT_CLK
1661 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3c, 2'b11, 16'h0110);
1662 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3c, 2'b11, 16'h0110);
1663 HAL_DMD_RIU_WriteByte(0x111f79, 0x01);
1664 HAL_DMD_RIU_WriteByte(0x111f78, 0x10);
1665
1666 // @0x353e
1667 // [2:0] : reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_isdbt_outer6x
1668 // [0] : disable clock
1669 // [1] : invert clock
1670 // [2] : Select clock source
1671 // 00: clk_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_mux8
1672 // 01: clk_isdbt_outer6x_p
1673 // 10: 1'b0
1674 // 11: DFT_CLK
1675 // [6:4] : reg_ckg_dvbtm_sram_t22x_miu
1676 // [4] : disable clock
1677 // [5] : invert clock
1678 // [6] : Select clock source
1679 // 00: clk_dvbt2_inner2x_p
1680 // 01: clk_miu_p
1681 // 10: 1'b0
1682 // 11: DFT_CLK
1683 // [10:8]: reg_ckg_dvbtm_sram_adc_t22x_isdbt_inner2x
1684 // [8] : disable clock
1685 // [9] : invert clock
1686 // [10]: Select clock source
1687 // 00: clk_dvbtm_sram_adc_t22x_p
1688 // 01: clk_isdbt_inner2x_p
1689 // 10: 1'b0
1690 // 11: DFT_CLK
1691 // [14:12]: reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_miu
1692 // [12] : disable clock
1693 // [13] : invert clock
1694 // [14]: Select clock source
1695 // 00: clk_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_mux8
1696 // 01: clk_miu_p
1697 // 10: 1'b0
1698 // 11: DFT_CLK
1699 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3e, 2'b11, 16'h1111);
1700 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3e, 2'b11, 16'h1111);
1701 HAL_DMD_RIU_WriteByte(0x111f7d, 0x11);
1702 HAL_DMD_RIU_WriteByte(0x111f7c, 0x11);
1703
1704 // @0x353f
1705 // [2:0] : reg_ckg_dvbs_outer2x_dvbt_outer2x_miu_isdbt_outer6x
1706 // [0] : disable clock
1707 // [1] : invert clock
1708 // [2] : Select clock source
1709 // 00: clk_dvbs_outer2x_dvbt_outer2x_miu_mux8
1710 // 01: clk_isdbt_outer6x_p
1711 // 10: 1'b0
1712 // 11: DFT_CLK
1713 // [6:4] : reg_ckg_dvbtm_sram_t22x_dvbtc_rs
1714 // [4] : disable clock
1715 // [5] : invert clock
1716 // [6] : Select clock source
1717 // 00: clk_dvbt2_inner2x_p
1718 // 01: clk_dvbtc_rs_p
1719 // 10: 1'b0
1720 // 11: DFT_CLK
1721 // [10:8]: reg_ckg_dvbtc_outer2x_isdbt_outer_rs
1722 // [8] : disable clock
1723 // [9] : invert clock
1724 // [10]: Select clock source
1725 // 00: clk_dvbtc_outer2x_p
1726 // 01: clk_isdbt_outer_rs_p
1727 // 10: 1'b0
1728 // 11: DFT_CLK
1729 // [14:12]: reg_ckg_dvbtm_sram_t22x_isdbt_outer6x_dvbt_outer2x
1730 // [12] : disable clock
1731 // [13] : invert clock
1732 // [14]: Select clock source
1733 // 00: clk_dvbtm_sram_t12x_t22x_p
1734 // 01: clk_isdbt_outer6x_dvbt_outer2x_mux
1735 // 10: 1'b0
1736 // 11: DFT_CLK
1737 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3f, 2'b11, 16'h1041);
1738 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3f, 2'b11, 16'h1041);
1739 HAL_DMD_RIU_WriteByte(0x111f7f, 0x10);
1740 HAL_DMD_RIU_WriteByte(0x111f7e, 0x41);
1741
1742
1743 // @0x3570
1744 // [4:0] : reg_ckg_dvbt_inner2x_srd0p5x
1745 // [0] : disable clock
1746 // [1] : invert clock
1747 // [3:2]: Select clock source
1748 // 00: dvb_clk48_buf
1749 // 01: dvb_clk43_buf
1750 // 10: clk_adc_div2_buf
1751 // 11: 1'b0
1752 // 11: 1'b0
1753 // [13:8]: reg_ckg_dvbtm_sram_t1outer1x_t24x
1754 // [8] : disable clock
1755 // [9] : invert clock
1756 // [12:10]: Select clock source
1757 // 000: dvb_clk96_buf
1758 // 001: dvb_clk86_buf
1759 // 010: dvb_clk48_buf
1760 // 011: dvb_clk43_buf
1761 // 100: 1'b0
1762 // 101: 1'b0
1763 // 110: 1'b0
1764 // 111: 1'b0
1765 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h70, 2'b11, 16'h0008);
1766 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h70, 2'b11, 16'h0008);
1767 HAL_DMD_RIU_WriteByte(0x111fe1, 0x00);
1768 HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1769
1770
1771 // @0x3571
1772 // [4:0] : reg_ckg_dvbtm_sram_t12x_t24x_srd1x
1773 // [0] : disable clock
1774 // [1] : invert clock
1775 // [3:2]: Select clock source
1776 // 000: dvb_clk96_buf
1777 // 001: dvb_clk86_buf
1778 // 010: dvb_clk48_buf
1779 // 011: dvb_clk43_buf
1780 // 100: adc_clk_buf
1781 // 101: 1'b0
1782 // 110: 1'b0
1783 // 111: 1'b0
1784 // [12:8]: reg_ckg_dvbtm_sram_t14x_t24x_srd1x
1785 // [8] : disable clock
1786 // [9] : invert clock
1787 // [12:10]: Select clock source
1788 // 000: dvb_clk96_buf
1789 // 001: dvb_clk86_buf
1790 // 010: adc_clk_buf
1791 // 011: 1'b0
1792 // 100: 1'b0
1793 // 101: 1'b0
1794 // 110: 1'b0
1795 // 111: 1'b0
1796 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h71, 2'b11, 16'h0810);
1797 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h71, 2'b11, 16'h0810);
1798 HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1799 HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1800
1801
1802 // @0x3572
1803 // [6:0] : reg_ckg_dvbt2_s2_bch_out
1804 // [0] : disable clock
1805 // [1] : invert clock
1806 // [2] : Select clock source
1807 // 00: dvb_clk48_buf
1808 // 01: dvb_clk43_buf
1809 // 10: 1'b0
1810 // 11: DFT_CLK
1811 // [12:8]: reg_ckg_dvbt2_outer2x
1812 // [8] : disable clock
1813 // [9] : invert clock
1814 // [12:10]: Select clock source
1815 // 000: mpll_clk144_buf
1816 // 001: mpll_clk108_buf
1817 // 010: mpll_clk96_buf
1818 // 011: mpll_clk72_buf
1819 // 100: mpll_clk54_buf
1820 // 101: mpll_clk48_buf
1821 // 110: mpll_clk36_buf
1822 // 111: mpll_clk24_buf
1823 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h72, 2'b11, 16'h0008);
1824 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h72, 2'b11, 16'h0008);
1825 HAL_DMD_RIU_WriteByte(0x111fe5, 0x00);
1826 HAL_DMD_RIU_WriteByte(0x111fe4, 0x08);
1827
1828
1829 // @0x3573
1830 // [3:0] : reg_ckg_dvbt2_inner4x_s2_inner
1831 // [0] : disable clock
1832 // [1] : invert clock
1833 // [2] : Select clock source
1834 // 00: dvb_clk96_buf
1835 // 01: dvb_clk86_buf
1836 // 10: 1'b0
1837 // 11: DFT_CLK
1838 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h73, 2'b11, 16'h0008);
1839 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h73, 2'b11, 16'h0008);
1840 HAL_DMD_RIU_WriteByte(0x111fe7, 0x00);
1841 HAL_DMD_RIU_WriteByte(0x111fe6, 0x08);
1842
1843
1844 // @0x3574
1845 // [4:0] reg_ckg_dvbtm_sram_t12x_t24x_s2inner
1846 // [0] : disable clock
1847 // [1] : invert clock
1848 // [4:2]:Select clock source
1849 // 000: dvb_clk96_buf
1850 // 001: dvb_clk86_buf
1851 // 010: dvb_clk48_buf
1852 // 011: dvb_clk43_buf
1853 // 100: adc_clk_buf
1854 // 101: 1'b0
1855 // 110: 1'b0
1856 // 111: 1'b0
1857 // [12:8] reg_ckg_dvbtm_sram_t14x_t24x_s2inner
1858 // [8] : disable clock
1859 // [9] : invert clock
1860 // [12:10]: Select clock source
1861 // 000: dvb_clk96_buf
1862 // 001: dvb_clk86_buf
1863 // 010: adc_clk_buf
1864 // 011: dvb_clk24_buf //JL SRAM Share (Windermere U02 ECO)
1865 // 100: dvb_clk21p5_buf //JL SRAM Share (Windermere U02 ECO)
1866 // 101: 1'b0
1867 // 110: 1'b0
1868 // 111: 1'b0
1869 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h74, 2'b11, 16'h0810);
1870 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h74, 2'b11, 16'h0810);
1871 HAL_DMD_RIU_WriteByte(0x111fe9, 0x08);
1872 HAL_DMD_RIU_WriteByte(0x111fe8, 0x10);
1873
1874
1875 // @0x3575
1876 // [4:0] : reg_ckg_dvbtc_rs
1877 // [0] : disable clock
1878 // [1] : invert clock
1879 // [4:2]:Select clock source
1880 // 000: mpll_clk216_buf
1881 // 001: mpll_clk172p8_buf
1882 // 010: mpll_clk144_buf
1883 // 011: mpll_clk288_buf
1884 // 100: dvb_clk96_buf
1885 // 101: dvb_clk86_buf
1886 // 110: mpll_clk57p6_buf
1887 // 111: dvb_clk43_buf
1888 // [11:8] : reg_ckg_dvbs_outer2x_dvbt_outer2x (N/A)
1889 // [15:12]: reg_ckg_dvbs_outer2x_dvbt_outer2x_miu
1890 // [12] : disable clock
1891 // [13] : invert clock
1892 // [15:14]:Select clock source
1893 // 000: 1'b0
1894 // 001: dvb_clk96_buf
1895 // 010: dvb_clk86_buf
1896 // 011: clk_miu
1897 // 100: 1'b0
1898 // 101: 1'b0
1899 // 110: 1'b0
1900 // 111: 1'b0
1901 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h75, 2'b11, 16'h0000);
1902 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h75, 2'b11, 16'h0000);
1903 HAL_DMD_RIU_WriteByte(0x111feb, 0x00);
1904 HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1905
1906
1907 // @0x3576
1908 // [4:0] : reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x
1909 // [0] : disable clock
1910 // [1] : invert clock
1911 // [4:2]:Select clock source
1912 // 000: 1'b0
1913 // 001: dvb_clk96_buf
1914 // 010: dvb_clk86_buf
1915 // 011: dvb_clk48_buf
1916 // 100: dvb_clk43_buf
1917 // 101: 1'b0
1918 // 110: 1'b0
1919 // 111: 1'b0
1920 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h76, 2'b11, 16'h0000);
1921 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h76, 2'b11, 16'h0000);
1922 HAL_DMD_RIU_WriteByte(0x111fed, 0x00);
1923 HAL_DMD_RIU_WriteByte(0x111fec, 0x00);
1924
1925
1926 // @0x3577
1927 // [3:0] : reg_ckg_dvbt2_inner4x_dvbtc_rs
1928 // [0] : disable clock
1929 // [1] : invert clock
1930 // [3:2]: Select clock source
1931 // 00: dvb_clk96_buf
1932 // 01: dvb_clk86_buf
1933 // 10: clk_dvbtc_rs_p
1934 // 11: 1'b0
1935 // [8:4] : reg_ckg_dvbtm_sram_adc_t22x_dvbtc_rs
1936 // [4] : disable clock
1937 // [5] : invert clock
1938 // [6] : Select clock source
1939 // 000: dvb_clk48_buf
1940 // 001: dvb_clk43_buf
1941 // 010: 1'b0
1942 // 011: adc_clk_buf
1943 // 100: 1'b0
1944 // 101: 1'b0
1945 // 110: 1'b0
1946 // 111: 1'b0
1947 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h77, 2'b11, 16'h0088);
1948 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h77, 2'b11, 16'h0088);
1949 HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1950 HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1951
1952
1953 // Maserati
1954 // @0x3578
1955 // [4:0] : reg_ckg_dvbt2_inner2x_srd0p5x
1956 // [0] : disable clock
1957 // [1] : invert clock
1958 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h78, 2'b01, 16'h0008);
1959 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h78, 2'b01, 16'h0008);
1960 HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1961
1962 // [3:0] : reg_ckg_sram_t22x_isdbt_inn2x_dtmb_inn2x
1963 // [0] : disable clock
1964 // [1] : invert clock
1965 // [3:2]:Select clock source
1966 // 000: clk_dvbtm_sram_t12x_t22x_p
1967 // 001: clk_isdbt_inner2x_p
1968 // 010: clk_share_dtmb_inner2x_isdbt_sram4_mux
1969 // 011:
1970 // [7:4] : reg_ckg_sram_t14x_t24x_s2inn_isdbt_inn2x_dtmb_inn6x
1971 // [4] : disable clock
1972 // [5] : invert clock
1973 // [7:6]:Select clock source
1974 // 000: clk_dvbtm_sram_t14x_t24x_s2inner_p
1975 // 001: clk_isdbt_inner2x_p
1976 // 010: clk_share_dtmb_inner6x_isdbt_sram3_mux
1977 // 011:
1978 // [11:8] : reg_ckg_sram_t14x_t24x_s2inn_isdbt_inn2x_dtmb_eq2x
1979 // [4] : disable clock
1980 // [5] : invert clock
1981 // [7:6]:Select clock source
1982 // 000: clk_dvbtm_sram_t14x_t24x_s2inner_p
1983 // 001: clk_isdbt_inner2x_p
1984 // 010: clk_share_dtmb_eq2x_isdbt_sram3_mux
1985 // 011:
1986 // [15:12]: reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifssc_isdbt_inner4x_dtmb_inner12x
1987 // [12] : disable clock
1988 // [13] : invert clock
1989 // [15:14]:Select clock source
1990 // 000: clk_dvbtm_sram_t14x_t24x_srd1x_vifssc_p
1991 // 001: clk_isdbt_inner4x_p
1992 // 010: clk_dvbtc_sram2_p
1993 // 011: clk_dtmb_eq2x_inner2x_12x_mux
1994 // `RIU_W((`RIUBASE_DEMOD_8>>1)+7'h48, 2'b11, 16'h0001);
1995 // `RIU_W((`RIUBASE_DEMOD_8>>1)+7'h48, 2'b11, 16'h0001);
1996 HAL_DMD_RIU_WriteByte(0x152991, 0x00);
1997 HAL_DMD_RIU_WriteByte(0x152990, 0x01);
1998 // ==============================================================
1999 // End demod top initial setting by HK MCU ......
2000 // ==============================================================
2001 //wriu 0x101e39 0x03
2002 HAL_DMD_RIU_WriteByte(0x101e39, 0x03);
2003
2004 //==========================================================
2005 //diseqc_out : PAD_GPIO13_I
2006 //swich to Diseqc out pin from GPIO
2007 //==========================================================
2008 //Bank: Reg_CHIP_TOP(0x101e)
2009 //reg_test_out_mode : addr h��12, [6:4] = 3��h0
2010 //reg_ts4config : addr h��40, [11:10] = 2��h0
2011 //reg_ts5config : addr h��40, [13:12] = 2��h0
2012 //reg_i2smutemode : addr h��2, [15:14] = 2��h0
2013 //reg_fifthuartmode : h��4, [3:2] = 2��h0
2014 //reg_od5thuart : h��55, [5:4] = 2��h0
2015 //reg_diseqc_out_config : ��h45, [1] = 1��b1
2016 //u8Temp = HAL_DMD_RIU_ReadByte(0x101E38);
2017 //u8Temp|=0x20;
2018 //HAL_DMD_RIU_WriteByte(0x101E38, u8Temp);
2019
2020 // SRAM allocation 64K avoid change souce from T2 failed.
2021 HAL_DMD_RIU_WriteByte(0x111701,0x00);
2022 HAL_DMD_RIU_WriteByte(0x111700,0x00);
2023
2024 HAL_DMD_RIU_WriteByte(0x111705,0x00);
2025 HAL_DMD_RIU_WriteByte(0x111704,0x00);
2026
2027 HAL_DMD_RIU_WriteByte(0x111703,0xff);
2028 HAL_DMD_RIU_WriteByte(0x111702,0xff);
2029
2030 HAL_DMD_RIU_WriteByte(0x111707,0xff);
2031 HAL_DMD_RIU_WriteByte(0x111706,0xff);
2032
2033 //Diff from TV tool
2034 HAL_DMD_RIU_WriteByte(0x111708,0x01);
2035 HAL_DMD_RIU_WriteByte(0x111709,0x00);
2036
2037 HAL_DMD_RIU_WriteByte(0x11170a,0x0f);
2038 HAL_DMD_RIU_WriteByte(0x11170b,0x00);
2039
2040 HAL_DMD_RIU_WriteByte(0x111718,0x02);
2041 HAL_DMD_RIU_WriteByte(0x111719,0x00);
2042
2043 HAL_DMD_RIU_WriteByte(0x11171a,0x00);
2044 HAL_DMD_RIU_WriteByte(0x11171b,0x00);
2045
2046 HAL_DMD_RIU_WriteByte(0x1117e0,0x14);
2047 HAL_DMD_RIU_WriteByte(0x1117e1,0x14);
2048
2049 HAL_DMD_RIU_WriteByte(0x1117e4,0x00);
2050 HAL_DMD_RIU_WriteByte(0x1117e5,0x00);
2051
2052 HAL_DMD_RIU_WriteByte(0x1117e6,0x00);
2053 HAL_DMD_RIU_WriteByte(0x1117e7,0x00);
2054
2055 // SRAM End Address
2056 HAL_DMD_RIU_WriteByte(0x111707,0xff);
2057 HAL_DMD_RIU_WriteByte(0x111706,0xff);
2058
2059 // DRAM Disable
2060 HAL_DMD_RIU_WriteByte(0x111718,HAL_DMD_RIU_ReadByte(0x111718)&(~0x04));
2061
2062 DBG_INTERN_DVBS(printf("INTERN_DVBS_InitClkgen\n"));
2063 }
2064
2065 /***********************************************************************************
2066 Subject: Power on initialized function
2067 Function: INTERN_DVBS_Power_On_Initialization
2068 Parmeter:
2069 Return: MS_BOOL
2070 Remark:
2071 ************************************************************************************/
INTERN_DVBS_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBS_DSPRegInitExt,MS_U8 u8DMD_DVBS_DSPRegInitSize)2072 MS_BOOL INTERN_DVBS_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBS_DSPRegInitExt, MS_U8 u8DMD_DVBS_DSPRegInitSize)
2073 {
2074 MS_U8 status = true;
2075 //MS_U8 u8ChipVersion;
2076
2077 DBG_INTERN_DVBS(printf("INTERN_DVBS_Power_On_Initialization\n"));
2078
2079 #if defined(PWS_ENABLE)
2080 Mapi_PWS_Stop_VDMCU();
2081 #endif
2082 INTERN_DVBS_InitClkgen(bRFAGCTristateEnable);//~~ no modify
2083 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);//~~ no modify
2084
2085 DBG_INTERN_DVBS(printf("@@@@@INTERN_DVBS_Power_On_Initialization1:bRFAGCTristateEnable=%d ;u8ADCIQMode=%d \n",bRFAGCTristateEnable,u8ADCIQMode));
2086 DBG_INTERN_DVBS(printf("@@@@@INTERN_DVBS_Power_On_Initialization2:u8PadSel=%d ;bPGAEnable=%d \n",u8PadSel,bPGAEnable));
2087 DBG_INTERN_DVBS(printf("@@@@@INTERN_DVBS_Power_On_Initialization2:u8PGAGain=%d \n",u8PGAGain));
2088
2089 //// Firmware download //////////
2090 DBG_INTERN_DVBS(printf("INTERN_DVBS Load DSP...\n"));
2091 //MsOS_DelayTask(100);
2092
2093 {
2094 if (INTERN_DVBS_LoadDSPCode() == FALSE)
2095 {
2096 DBG_INTERN_DVBS(printf("DVB-S Load DSP Code Fail\n"));
2097 return FALSE;
2098 }
2099 else
2100 {
2101 DBG_INTERN_DVBS(printf("DVB-S Load DSP Code OK\n"));
2102 }
2103 }
2104
2105 //// MCU Reset //////////
2106 if (INTERN_DVBS_Reset() == FALSE)
2107 {
2108 DBG_INTERN_DVBS(printf("INTERN_DVBS Reset...Fail\n"));
2109 return FALSE;
2110 }
2111 else
2112 {
2113 DBG_INTERN_DVBS(printf("INTERN_DVBS Reset...OK\n"));
2114 }
2115
2116
2117 status &= INTERN_DVBS_DSPReg_Init(u8DMD_DVBS_DSPRegInitExt, u8DMD_DVBS_DSPRegInitSize);
2118 //status &= INTERN_DVBS_Active(ENABLE);//enable this
2119
2120 //Read Demod FW Version.
2121 INTERN_DVBS_Show_Demod_Version();
2122
2123 return status;
2124 }
2125 /************************************************************************************************
2126 Subject: Driving control
2127 Function: INTERN_DVBC_Driving_Control
2128 Parmeter: bInversionEnable : TRUE For High
2129 Return: void
2130 Remark:
2131 *************************************************************************************************/
INTERN_DVBS_Driving_Control(MS_BOOL bEnable)2132 void INTERN_DVBS_Driving_Control(MS_BOOL bEnable)
2133 {
2134 MS_U8 u8Temp;
2135
2136 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
2137
2138 if (bEnable)
2139 {
2140 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
2141 }
2142 else
2143 {
2144 u8Temp = u8Temp & (~0x01);
2145 }
2146
2147 DBG_INTERN_DVBS(printf("---> INTERN_DVBS_Driving_Control(Bit0) = 0x%x \n",u8Temp));
2148 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
2149 }
2150
2151 /************************************************************************************************
2152 Subject: Clk Inversion control
2153 Function: INTERN_DVBS_Clk_Inversion_Control
2154 Parmeter: bInversionEnable : TRUE For Inversion Action
2155 Return: void
2156 Remark:
2157 *************************************************************************************************/
INTERN_DVBS_Clk_Inversion_Control(MS_BOOL bInversionEnable)2158 void INTERN_DVBS_Clk_Inversion_Control(MS_BOOL bInversionEnable)
2159 {
2160 MS_U8 u8Temp;
2161
2162 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
2163
2164 if (bInversionEnable)
2165 {
2166 u8Temp = u8Temp | 0x02; //bit 9: clk inv
2167 }
2168 else
2169 {
2170 u8Temp = u8Temp & (~0x02);
2171 }
2172
2173 DBG_INTERN_DVBS(printf("---> Inversion(Bit9) = 0x%x \n",u8Temp));
2174 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
2175 }
2176
2177 /************************************************************************************************
2178 Subject: Transport stream serial/parallel control
2179 Function: INTERN_DVBS_Serial_Control
2180 Parmeter: bEnable : TRUE For serial
2181 Return: MS_BOOL :
2182 Remark:
2183 *************************************************************************************************/
INTERN_DVBS_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)2184 MS_BOOL INTERN_DVBS_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
2185 {
2186 MS_U8 status = true;
2187 MS_U8 temp_val;
2188 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_ts... u8TSClk=%d\n", u8TSClk));
2189
2190 if (u8TSClk == 0xFF) u8TSClk=0x13;
2191 if (bEnable) //Serial mode for TS pad
2192 {
2193 // serial
2194 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
2195 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2196
2197 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
2198 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2199 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
2200 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2201 temp_val|=0x04;
2202 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2203 #else
2204 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
2205 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2206 temp_val|=0x07;
2207 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2208 #endif
2209 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
2210 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
2211
2212 //// INTERN_DVBS TS Control: Serial //////////
2213
2214 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, TS_SERIAL);
2215
2216 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2217 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 0);
2218 #else
2219 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 1);
2220 #endif
2221 gsCmdPacketDVBS.cmd_code = CMD_TS_CTRL;
2222
2223 gsCmdPacketDVBS.param[0] = TS_SERIAL;
2224 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2225 gsCmdPacketDVBS.param[1] = 0;//TS_CLK_NO_INV;
2226 #else
2227 gsCmdPacketDVBS.param[1] = 1;//TS_CLK_INVERSE;
2228 #endif
2229 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 2);
2230 }
2231 else
2232 {
2233 //parallel
2234 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
2235 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2236
2237 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2238 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2239 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2240 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
2241 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2242 temp_val|=0x05;
2243 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2244 #else
2245 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
2246 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2247 temp_val|=0x07;
2248 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2249 #endif
2250
2251 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
2252 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
2253
2254 //// INTERN_DVBS TS Control: Parallel //////////
2255
2256 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, TS_PARALLEL);
2257
2258 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2259 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 0);
2260 #else
2261 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 1);
2262 #endif
2263 //// INTERN_DVBC TS Control: Parallel //////////
2264 gsCmdPacketDVBS.cmd_code = CMD_TS_CTRL;
2265
2266 gsCmdPacketDVBS.param[0] = TS_PARALLEL;
2267 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2268 gsCmdPacketDVBS.param[1] = 0;//TS_CLK_NO_INV;
2269 #else
2270 gsCmdPacketDVBS.param[1] = 1;//TS_CLK_INVERSE;
2271 #endif
2272 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 2);
2273 }
2274
2275 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2276 DBG_INTERN_DVBS(printf("---> Inversion(Bit5) = %d \n",0 ));
2277 #else
2278 DBG_INTERN_DVBS(printf("---> Inversion(Bit5) = %d \n",1 ));
2279 #endif
2280
2281 INTERN_DVBS_Driving_Control(INTERN_DVBS_DTV_DRIVING_LEVEL);
2282 return status;
2283 }
2284
2285 /************************************************************************************************
2286 Subject: TS1 output control
2287 Function: INTERN_DVBS_PAD_TS1_Enable
2288 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
2289 Return: void
2290 Remark:
2291 *************************************************************************************************/
INTERN_DVBS_PAD_TS1_Enable(MS_BOOL flag)2292 void INTERN_DVBS_PAD_TS1_Enable(MS_BOOL flag)
2293 {
2294 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_TS1_Enable... \n"));
2295
2296 if(flag) // PAD_TS1 Enable TS CLK PAD
2297 {
2298 //printf("=== TS1_Enable ===\n");
2299 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
2300 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
2301 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
2302 }
2303 else // PAD_TS1 Disable TS CLK PAD
2304 {
2305 //printf("=== TS1_Disable ===\n");
2306 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
2307 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
2308 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
2309 }
2310 }
2311
2312 /************************************************************************************************
2313 Subject: channel change config
2314 Function: INTERN_DVBC_Config
2315 Parmeter: BW: bandwidth
2316 Return: MS_BOOL :
2317 Remark:
2318 *************************************************************************************************/
INTERN_DVBS_Config(MS_U32 u32SymbolRate,DMD_DVBS_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)2319 MS_BOOL INTERN_DVBS_Config(MS_U32 u32SymbolRate, DMD_DVBS_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
2320 {
2321
2322 MS_BOOL status= true;
2323 MS_U16 u16CenterFreq;
2324 // MS_U16 u16Fc = 0;
2325 MS_U8 temp_val;
2326 MS_U8 u8Data =0;
2327 MS_U8 u8counter = 0;
2328 MS_U32 u32CurrentSR;
2329
2330 u32CurrentSR = u32SymbolRate/1000; //KHz
2331 //u32SymbolRate= u32SymbolRate/1000;//to match fw format
2332 u16CenterFreq =u32IFFreq;
2333 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_config+, SR=%d, QAM=%d, u32IFFreq=%d, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n", u32CurrentSR, eQamMode, u32IFFreq, bSpecInv, bSerialTS, u8TSClk));
2334 DBG_INTERN_DVBS(printf("INTERN_DVBS_Config, t = %d\n",MsOS_GetSystemTime()));
2335
2336 u8TSClk=0x05;//if (u8TSClk == 0xFF) u8TSClk=0x13;//set a fater speed for initial condition
2337 status &= INTERN_DVBS_Reset();
2338
2339 u8DemodLockFlag=0;
2340
2341 // Symbol Rate
2342 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, u32CurrentSR&0xff);
2343 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, (u32CurrentSR>>8)&0xff);
2344 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, (u32CurrentSR>>16)&0xff);
2345 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config u32SymbolRate %d<<<\n", u32CurrentSR));
2346
2347 #if 0
2348 //======== check SR is right or not ===========
2349 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &u8Data);
2350 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L,u8Data));
2351 u32SR =u8Data;
2352 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &u8Data);
2353 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H,u8Data));
2354 u32SR =((U32)u8Data<<8)|u32SR ;
2355 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &u8Data);
2356 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MB_DMDTOP_DBG_5 addr=%d mailbox value=%d<<<\n", E_DMD_S2_MB_DMDTOP_DBG_5,u8Data));
2357 u32SR =((U32)u8Data<<16)|u32SR;
2358 //=================================================
2359 #endif
2360
2361 // IQ Swap ,ADCPLL IQ swap / DMDANA_IQ_SWAP
2362 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_IQ_SWAP, bSpecInv? 0x01:0x00);
2363 if(bSpecInv)
2364 {
2365 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DMDANA_REG_BASE+0xC0, &u8Data);//Demod\reg_dmdana.xls
2366 u8Data|=(0x02);
2367 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DMDANA_REG_BASE+0xC0, u8Data);
2368 }
2369
2370 // TS mode
2371 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, bSerialTS? 0x01:0x00);
2372 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config TS Serial %d<<<\n", bSerialTS));
2373 _bSerialTS = bSerialTS;
2374
2375 if (bSerialTS)
2376 {
2377 // serial
2378 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2379 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2380
2381 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
2382 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2383 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2384 temp_val|=0x04;
2385 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2386 #else
2387 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2388 temp_val|=0x07;
2389 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2390 #endif
2391 }
2392 else
2393 {
2394 //parallel
2395 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2396 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2397
2398 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2399 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2400 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2401 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2402 temp_val|=0x05;
2403 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2404 #else
2405 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2406 temp_val|=0x07;
2407 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2408 #endif
2409 }
2410 #if (INTERN_DVBS_INTERNAL_DEBUG == 1)
2411 INTERN_DVBS_Show_Demod_Version();
2412 #endif
2413
2414 //-----------------------------------------------------------
2415 //From INTERN_DVBS_Demod_Restart function.
2416
2417 //FW sw reset
2418 //[0]: 0: SW Reset, 1: Start state machine
2419 //[1]: 1: Blind scan enable, 0: manual scan
2420 //[2]: 1: Code flow track enable
2421 //[3]: 1: go to AGC state
2422 //[4]: 1: set DiSEqC
2423 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2424 u8Data = (u8Data&0xF0)|0x01;
2425 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2426 //DBG_INTERN_DVBS(printf(">>>REG write check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2427 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2428 //DBG_INTERN_DVBS(printf(">>>REG read check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2429
2430 u8counter = 20;
2431 while( ((u8Data&0x01) == 0x00) && (u8counter != 0) )
2432 {
2433 MsOS_DelayTask(1);
2434 printf("TOP_WR_DBG_90=0x%x, status=%d, u8counter=%d\n", u8Data, status, u8counter);
2435 u8Data|=0x01;
2436 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
2437 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
2438 DBG_INTERN_DVBS(printf(">>>(while)REG read check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2439 u8counter--;
2440 }
2441
2442 if((u8Data & 0x01)==0x00)
2443 {
2444 status = FALSE;
2445 }
2446
2447 DBG_INTERN_DVBS(printf("INTERN_DVBS_config done\n"));
2448 return status;
2449 }
2450 /************************************************************************************************
2451 Subject: channel change config
2452 Function: INTERN_DVBS_Blind_Scan_Config
2453 Parmeter: BW: bandwidth
2454 Return: MS_BOOL :
2455 Remark:
2456 *************************************************************************************************/
INTERN_DVBS_BlindScan_Config(MS_U32 u32SymbolRate,DMD_DVBS_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)2457 MS_BOOL INTERN_DVBS_BlindScan_Config(MS_U32 u32SymbolRate, DMD_DVBS_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
2458 {
2459
2460 MS_BOOL status= true;
2461 MS_U16 u16CenterFreq;
2462 // MS_U16 u16Fc = 0;
2463 MS_U8 temp_val;
2464 MS_U8 u8Data=0;
2465 MS_U16 u16WaitCount = 0;
2466 MS_U32 u32CurrentSR;
2467
2468 u32CurrentSR = u32SymbolRate/1000; //KHz
2469 //u32SymbolRate= u32SymbolRate/1000;//to match fw format
2470 u16CenterFreq =u32IFFreq;
2471 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_blindScan_Config+, SR=%d, QAM=%d, u32IFFreq=%d, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n", u32CurrentSR, eQamMode, u32IFFreq, bSpecInv, bSerialTS, u8TSClk));
2472 DBG_INTERN_DVBS(printf("INTERN_DVBS_blindScan_Config, t = %d\n",MsOS_GetSystemTime()));
2473
2474 //status &= INTERN_DVBS_Reset();
2475 g_dvbs_lock = 0;
2476 u8DemodLockFlag=0;
2477
2478 // Symbol Rate
2479 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, u32CurrentSR&0xff);
2480 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, (u32CurrentSR>>8)&0xff);
2481 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, (u32CurrentSR>>16)&0xff);
2482 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config u32SymbolRate %d<<<\n", u32CurrentSR));
2483
2484 #if 0
2485 //======== check SR is right or not ===========
2486 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &u8Data);
2487 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L,u8Data));
2488 u32SR =u8Data;
2489 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &u8Data);
2490 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H,u8Data));
2491 u32SR =((U32)u8Data<<8)|u32SR ;
2492 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &u8Data);
2493 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MB_DMDTOP_DBG_5 addr=%d mailbox value=%d<<<\n", E_DMD_S2_MB_DMDTOP_DBG_5,u8Data));
2494 u32SR =((U32)u8Data<<16)|u32SR;
2495 //=================================================
2496 #endif
2497
2498 // IQ Swap ,ADCPLL IQ swap / DMDANA_IQ_SWAP
2499 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_IQ_SWAP, bSpecInv? 0x01:0x00);
2500 if(bSpecInv)
2501 {
2502 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DMDANA_REG_BASE+0xC0, &u8Data);//Demod\reg_dmdana.xls
2503 u8Data|=(0x02);
2504 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DMDANA_REG_BASE+0xC0, u8Data);
2505 }
2506
2507 // TS mode
2508 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, bSerialTS? 0x01:0x00);
2509 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config TS Serial %d<<<\n", bSerialTS));
2510 _bSerialTS = bSerialTS;
2511 u8TSClk=0x05;//if (u8TSClk == 0xFF) u8TSClk=0x13;//set a fater speed for initial condition
2512
2513 if (bSerialTS)
2514 {
2515 // serial
2516 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2517 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2518
2519 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
2520 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2521 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2522 temp_val|=0x04;
2523 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2524 #else
2525 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2526 temp_val|=0x07;
2527 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2528 #endif
2529 }
2530 else
2531 {
2532 //parallel
2533 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2534 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2535
2536 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2537 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2538 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2539 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2540 temp_val|=0x05;
2541 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2542 #else
2543 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2544 temp_val|=0x07;
2545 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2546 #endif
2547 }
2548 #if (INTERN_DVBS_INTERNAL_DEBUG == 1)
2549 INTERN_DVBS_Show_Demod_Version();
2550 #endif
2551
2552 //-----------------------------------------------------------
2553 //From INTERN_DVBS_Demod_Restart function.
2554
2555 //enable send DiSEqC
2556 //[0]: 0: SW Reset, 1: Start state machine
2557 //[1]: 1: Blind scan enable, 0: manual scan
2558 //[2]: 1: Code flow track enable
2559 //[3]: 1: go to AGC state
2560 //[4]: 1: set DiSEqC
2561 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2562 u8Data |= 0x08;
2563 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2564
2565 u16WaitCount=0;
2566 do
2567 {
2568 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
2569 u16WaitCount++;
2570 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
2571 MsOS_DelayTask(1);
2572 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
2573
2574 // disable blind scan
2575 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2576 u8Data&=~(0x02);
2577 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2578
2579 //disble send DiSEqC
2580 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2581 u8Data&=~(0x08);
2582 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2583
2584
2585 DBG_INTERN_DVBS(printf("INTERN_DVBS_blindScan_Config done\n"));
2586 return status;
2587 }
2588
INTERN_DVBS_Power_ON_OFF(MS_U8 bPowerOn)2589 void INTERN_DVBS_Power_ON_OFF(MS_U8 bPowerOn)
2590 {
2591 bPowerOn = bPowerOn;
2592 }
2593
INTERN_DVBS_Power_Save(void)2594 MS_BOOL INTERN_DVBS_Power_Save(void)
2595 {
2596 return TRUE;
2597 }
2598 //------------------------------------------------------------------
2599 // END System Info Function
2600 //------------------------------------------------------------------
2601
2602 //------------------------------------------------------------------
2603 // Get And Show Info Function
2604 //------------------------------------------------------------------
2605 /************************************************************************************************
2606 Subject: enable hw to lock channel
2607 Function: INTERN_DVBS_Active
2608 Parmeter: bEnable
2609 Return: MS_BOOL
2610 Remark:
2611 *************************************************************************************************/
INTERN_DVBS_Active(MS_BOOL bEnable)2612 MS_BOOL INTERN_DVBS_Active(MS_BOOL bEnable)
2613 {
2614 MS_U8 status = TRUE;
2615 //MS_U8 u8Data;
2616
2617 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_Active\n"));
2618
2619 //// INTERN_DVBS Finite State Machine on/off //////////
2620 #if 0
2621 gsCmdPacketDVBC.cmd_code = CMD_FSM_CTRL;
2622
2623 gsCmdPacketDVBS.param[0] = (MS_U8)bEnable;
2624 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 1);
2625 #else
2626
2627 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
2628 #endif
2629
2630 bDMD_DVBS_NoChannelDetectedWithRFPower = FALSE;
2631 u32DMD_DVBS_NoChannelTimeAccWithRFPower = 0;
2632 return status;
2633 }
2634
INTERN_DVBS_GetTsDivNum(MS_FLOAT * fTSDivNum)2635 MS_BOOL INTERN_DVBS_GetTsDivNum(MS_FLOAT* fTSDivNum)
2636 {
2637 MS_U8 u8Data = 0;
2638 MS_BOOL status = true;
2639 MS_U32 u32SymbolRate=0;
2640 //float fSymbolRate;
2641 //MS_U8 ISSY_EN = 0;
2642 MS_U8 code_rate_idx = 0;
2643 MS_U8 pilot_flag = 0;
2644 MS_U8 fec_type_idx = 0;
2645 MS_U8 mod_type_idx = 0;
2646 MS_U16 k_bch_array[2][11] ={
2647 {16008, 21408, 25728, 32208, 38688, 43040, 48408, 51648, 53840, 57472, 58192},
2648 { 3072, 5232, 6312, 7032, 9552, 10632, 11712, 12432, 13152, 14232, 0}};
2649 MS_U16 n_ldpc_array[2] = {64800, 16200};
2650 MS_FLOAT pilot_term = 0;
2651 MS_FLOAT k_bch;
2652 MS_FLOAT n_ldpc;
2653 MS_FLOAT ts_div_num_offset = 2.0;
2654 //MS_U32 u32Time_start,u32Time_end;
2655 //MS_U32 u32temp;
2656 //MS_FLOAT pkt_interval;
2657 //MS_U8 time_counter=0;
2658
2659 INTERN_DVBS_GetCurrentSymbolRate(&u32SymbolRate);
2660 //fSymbolRate=u32SymbolRate+0.0;///1000.0;//Symbol Rate(KHz)
2661 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum u32SymbolRate=%d\n", u32SymbolRate));
2662 // DMD_DVBS_MODULATION_TYPE pQAMMode;
2663
2664 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//V
2665 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum GetCurrentDemodType E_DMD_S2_SYSTEM_TYPE=%d\n", u8Data));//u8Data:0 is S2; 1 is DVBS
2666
2667 if(!u8Data)//DVBS2
2668 {
2669 #if 0
2670 //Get DVBS2 Code Rate
2671 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);//V
2672 printf("[S2]INTERN_DVBS_GetTsDivNum DVBS2 E_DMD_S2_CODERATE=0x%x\n", u8Data);
2673 switch (u8Data)
2674 {
2675 case 0x03: //CR 1/2
2676 k_bch=32208.0;
2677 _u8_DVBS2_CurrentCodeRate = 5;
2678 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_2\n"));
2679 break;
2680 case 0x01: //CR 1/3
2681 k_bch=21408.0; //8PSK???
2682 _u8_DVBS2_CurrentCodeRate = 6;
2683 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_3\n"));
2684 break;
2685 case 0x05: //CR 2/3
2686 k_bch=43040.0;
2687 _u8_DVBS2_CurrentCodeRate = 7;
2688 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=2_3\n"));
2689 break;
2690 case 0x00: //CR 1/4
2691 k_bch=16008.0; //8PSK???
2692 _u8_DVBS2_CurrentCodeRate = 8;
2693 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_4\n"));
2694 break;
2695 case 0x06: //CR 3/4
2696 k_bch=48408.0;
2697 _u8_DVBS2_CurrentCodeRate = 9;
2698 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=3_4\n"));
2699 break;
2700 case 0x02: //CR 2/5
2701 k_bch=25728.0; //8PSK???
2702 _u8_DVBS2_CurrentCodeRate = 10;
2703 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=2_5\n"));
2704 break;
2705 case 0x04: //CR 3/5
2706 k_bch=38688.0;
2707 _u8_DVBS2_CurrentCodeRate = 11;
2708 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=3_5\n"));
2709 break;
2710 case 0x07: //CR 4/5
2711 k_bch=51648.0;
2712 _u8_DVBS2_CurrentCodeRate = 12;
2713 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=4_5\n"));
2714 break;
2715 case 0x08: //CR 5/6
2716 k_bch=53840.0;
2717 _u8_DVBS2_CurrentCodeRate = 13;
2718 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=5_6\n"));
2719 break;
2720 case 0x09: //CR 8/9
2721 k_bch=57472.0;
2722 _u8_DVBS2_CurrentCodeRate = 14;
2723 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=8_9\n"));
2724 break;
2725 case 0x0A: //CR 9/10
2726 k_bch=58192.0;
2727 _u8_DVBS2_CurrentCodeRate = 15;
2728 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=9_10\n"));
2729 break;
2730 default:
2731 k_bch=58192.0;
2732 _u8_DVBS2_CurrentCodeRate = 15;
2733 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate= default 9_10\n"));
2734 break;
2735 } //printf("INTERN_DVBS_GetTsDivNum k_bch=%ld\n", (MS_U32)k_bch);
2736 #endif
2737 //INTERN_DVBS_GetCurrentModulationType(&pQAMMode); //V
2738 //printf("INTERN_DVBS_GetTsDivNum Mod_order=%d\n", modulation_order);
2739
2740 // pilot_flag => 0 : off 1 : on
2741 // fec_type_idx => 0 : normal 1 : short
2742 // mod_type_idx => 0 : QPSK 1 : 8PSK 2 : 16APSK 3 : 32APSK
2743 // code_rate_idx => d0: 1/4, d1: 1/3, d2: 2/5, d3: 1/2, d4: 3/5, d5: 2/3, d6: 3/4, d7: 4/5, d8: 5/6, d9: 8/9, d10: 9/10
2744 //set TS clock rate
2745 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &code_rate_idx);
2746 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FEC_TYPE, &fec_type_idx);
2747 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MOD_TYPE, &mod_type_idx);
2748 modulation_order = mod_type_idx;
2749 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_PILOT_FLAG, &pilot_flag);
2750 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_PILOT_FLAG, &u8Data);
2751
2752 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_ISSY_ACTIVE, &ISSY_EN);
2753 //if(ISSY_EN==0)
2754 //{
2755 k_bch = k_bch_array[fec_type_idx][code_rate_idx];
2756 n_ldpc = n_ldpc_array[fec_type_idx];
2757 pilot_term = ((float) n_ldpc / modulation_order / 1440 * 36) * pilot_flag;
2758 if(_bSerialTS)//serial mode
2759 {
2760 *fTSDivNum =288000.0/(k_bch/((n_ldpc/modulation_order+90+pilot_term)/u32SymbolRate));
2761 *fTSDivNum = *fTSDivNum/2 -1;
2762 }
2763 else//parallel mode
2764 {
2765 *fTSDivNum = 288000.0/(k_bch/((n_ldpc/modulation_order+90+pilot_term)/u32SymbolRate)/8);
2766 *fTSDivNum = *fTSDivNum/2 -1;
2767 }
2768 *fTSDivNum-=ts_div_num_offset;
2769 //}
2770 #if 0
2771 else if(ISSY_EN==1)//ISSY = 1
2772 {
2773 //u32Time_start = msAPI_Timer_GetTime0();
2774 time_counter=0;
2775 do
2776 {
2777 MDrv_SYS_DMD_VD_MBX_ReadReg((0x3E00 + 0x4D*2), &u8Data);//DVBS2OPPRO_ISCR_CAL_DONE (_REG_DVBS2OPPRO(0x4D)+0)
2778 u8Data &= 0x01;
2779 // u32Time_end =msAPI_Timer_GetTime0();
2780 MsOS_DelayTask(1);
2781 time_counter = time_counter +1;
2782 }while( (u8Data!=0x01) && ( (time_counter )< 50) );
2783
2784 //read pkt interval
2785 MDrv_SYS_DMD_VD_MBX_ReadReg((0x3E00 + 0x70*2), &u8Data);
2786 u32temp = u8Data;
2787 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x70*2+1), &u8Data);
2788 u32temp |= (MS_U32)u8Data<<8;
2789 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x71*2), &u8Data);
2790 u32temp |= (MS_U32)u8Data<<16;
2791 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x71*2+1), &u8Data);
2792 u32temp |= (MS_U32)u8Data<<24;
2793 pkt_interval = (MS_FLOAT) u32temp / 1024.0;
2794 if(_bSerialTS)//serial mode
2795 {
2796 *fTSDivNum=288000.0 / (188*8*u32SymbolRate/pkt_interval) - ts_div_num_offset;
2797 *fTSDivNum = (*fTSDivNum-1)/2;
2798 }
2799 else
2800 {
2801 *fTSDivNum=288000.0 / (188*u32SymbolRate/pkt_interval) - ts_div_num_offset;
2802 *fTSDivNum = (*fTSDivNum-1)/2;
2803 }
2804
2805 }
2806
2807 else
2808 {
2809 *fTSDivNum =0x0A;
2810 }
2811
2812 if(*fTSDivNum>255)
2813 *fTSDivNum=255;
2814 if(*fTSDivNum<1)
2815 *fTSDivNum=1;
2816
2817 //printf("INTERN_DVBS_GetTsDivNum Pilot E_DMD_S2_MB_DMDTOP_DBG_9=%d\n", u8Data);
2818 /*if(u8Data) // Pilot ON
2819 printf(">>>INTERN_DVBS_GetTsDivNum Pilot ON<<<\n");
2820 else //Pilot off
2821 printf(">>>INTERN_DVBS_GetTsDivNum Pilot off<<<\n");
2822 */
2823 if(_bSerialTS)
2824 {
2825 if(u8Data)//if pilot ON
2826 {
2827 if(modulation_order==2)
2828 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90+36*22)/u32SymbolRate)) - 3);
2829 else if(modulation_order==3)
2830 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90+36*15)/u32SymbolRate)) - 3);
2831 }
2832 else
2833 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90)/u32SymbolRate)) - 3);
2834 }
2835 else//Parallel mode
2836 {
2837 if(u8Data)
2838 {
2839 if(modulation_order==2)
2840 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0+36*22)/u32SymbolRate)/8.0) - 3);
2841 else if(modulation_order==3)
2842 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0+36*15)/u32SymbolRate)/8.0) - 3);
2843 }
2844 else
2845 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0)/u32SymbolRate)/8.0) - 3);
2846 }
2847 #endif
2848 }
2849 else //S
2850 {
2851 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE + 0x3A*2, &u8Data);
2852 //u8_gCodeRate = (u8Data & 0x70)>>4;
2853 //DVBS Code Rate
2854 //switch (u8_gCodeRate)
2855 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
2856 switch (u8Data)
2857 {
2858 case 0x00: //CR 1/2
2859 _u8_DVBS2_CurrentCodeRate = 0;
2860 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=1_2\n"));
2861 if(_bSerialTS)
2862 *fTSDivNum = (288000.0/((1.0/2.0)*(188.0/204.0)*u32SymbolRate*2));
2863 else
2864 *fTSDivNum = (288000.0/((1.0/2.0)*(188.0/204.0)*u32SymbolRate*2/8.0));
2865
2866 *fTSDivNum = *fTSDivNum/2-1-5;
2867 break;
2868 case 0x01: //CR 2/3
2869 _u8_DVBS2_CurrentCodeRate = 1;
2870 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=2_3\n"));
2871 if(_bSerialTS)
2872 *fTSDivNum = (MS_U8)(288000.0/((2.0/3.0)*(188.0/204.0)*u32SymbolRate*2));
2873 else
2874 *fTSDivNum = (MS_U8)(288000.0/((2.0/3.0)*(188.0/204.0)*u32SymbolRate*2/8.0));
2875
2876 *fTSDivNum = *fTSDivNum/2-1-5;
2877 break;
2878 case 0x02: //CR 3/4
2879 _u8_DVBS2_CurrentCodeRate = 2;
2880 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=3_4\n"));
2881 if(_bSerialTS)
2882 *fTSDivNum = (288000.0/((3.0/4.0)*(188.0/204.0)*u32SymbolRate*2));
2883 else
2884 *fTSDivNum = (288000.0/((3.0/4.0)*(188.0/204.0)*u32SymbolRate*2/8.0));
2885
2886 *fTSDivNum = *fTSDivNum/2-1-5;
2887 break;
2888 case 0x03: //CR 5/6
2889 _u8_DVBS2_CurrentCodeRate = 3;
2890 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=5_6\n"));
2891 if(_bSerialTS)
2892 *fTSDivNum = (288000.0/((5.0/6.0)*(188.0/204.0)*u32SymbolRate*2));
2893 else
2894 *fTSDivNum = (288000.0/((5.0/6.0)*(188.0/204.0)*u32SymbolRate*2/8.0));
2895
2896 *fTSDivNum = *fTSDivNum/2-1-5;
2897 break;
2898 case 0x04: //CR 7/8
2899 _u8_DVBS2_CurrentCodeRate = 4;
2900 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=7_8\n"));
2901 if(_bSerialTS)
2902 *fTSDivNum =(288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2));
2903 else
2904 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2/8.0));
2905
2906 *fTSDivNum = *fTSDivNum/2-1-5;
2907 break;
2908 default:
2909 _u8_DVBS2_CurrentCodeRate = 4;
2910 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate= default 7_8\n"));
2911 if(_bSerialTS)
2912 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2));
2913 else
2914 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2/8.0));
2915
2916 *fTSDivNum = *fTSDivNum/2-1-5;
2917 break;
2918 }
2919 } //printf("INTERN_DVBS_GetTsDivNum u8TSClk = 0x%x\n", *u8TSDivNum);
2920 return status;
2921 }
2922
INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK_TYPE eType,float fCurrRFPowerDbm,float fNoChannelRFPowerDbm,MS_U32 u32TimeInterval)2923 MS_BOOL INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK_TYPE eType, float fCurrRFPowerDbm, float fNoChannelRFPowerDbm, MS_U32 u32TimeInterval)
2924 {
2925 MS_U8 u8Data =0; //MS_U8 u8Data2 =0;
2926 MS_U8 bRet = TRUE;
2927 MS_FLOAT fTSDivNum=0;
2928
2929 switch( eType )
2930 {
2931 case DMD_DVBS_GETLOCK:
2932 #if (INTERN_DVBS_INTERNAL_DEBUG)
2933 INTERN_DVBS_info();
2934 #endif
2935 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2936 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_GetLock manual tune=%d<<<\n", u8Data));
2937 if ((u8Data&0x02)==0x00)//manual mode
2938 {
2939 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);
2940 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_GetLock MailBox state=%d<<<\n", u8Data));
2941
2942 if((u8Data == 15) || (u8Data == 16))
2943 {
2944 if (u8Data==15)
2945 {
2946 _bDemodType=FALSE; //S
2947 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Demod DVBS Lock<<<\n"));
2948 }
2949 else if(u8Data==16)
2950 {
2951 _bDemodType=TRUE; //S2
2952 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Demod DVBS2 Lock<<<\n"));
2953 }
2954 if(g_dvbs_lock == 0)
2955 {
2956 g_dvbs_lock = 1;
2957 }
2958
2959 if(u8DemodLockFlag==0)
2960 {
2961 u8DemodLockFlag=1;
2962
2963 // caculate TS clock divider number
2964 INTERN_DVBS_GetTsDivNum(&fTSDivNum); //ts_div_num
2965
2966 if (fTSDivNum > 0x1F)
2967 fTSDivNum = 0x1F;
2968 else if (fTSDivNum < 0x00)
2969 fTSDivNum=0x00;
2970
2971 u8Data = (MS_U8)fTSDivNum;
2972 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_GetLock TsClkDivNum = 0x%x<<<\n", u8Data));
2973 HAL_DMD_RIU_WriteByte(0x103300, u8Data);
2974
2975 //Ts Output Enable
2976 //HAL_DMD_RIU_WriteByte(0x101eaa,0x10);
2977 }
2978 DBG_INTERN_DVBS(printf("@INTERN_DVBS_Demod Lock+++\n"));
2979 bRet = TRUE;
2980 }
2981 else
2982 {
2983 if(g_dvbs_lock == 1)
2984 {
2985 g_dvbs_lock = 0;
2986 u8DemodLockFlag=0;
2987 }
2988 DBG_INTERN_DVBS(printf("@INTERN_DVBS_Demod UnLock---\n"));
2989 bRet = FALSE;
2990 }
2991
2992 if(_bSerialTS==1)
2993 {
2994 if (bRet==FALSE)
2995 {
2996 _bTSDataSwap=FALSE;
2997 }
2998 else
2999 {
3000 if (_bTSDataSwap==FALSE)
3001 {
3002 _bTSDataSwap=TRUE;
3003 MDrv_SYS_DMD_VD_MBX_ReadReg( (DVBTM_REG_BASE + 0x20*2), &u8Data);//DVBTM_REG_BASE
3004 u8Data^=0x20;//h0020 h0020 5 5 reg_ts_data_reverse
3005 MDrv_SYS_DMD_VD_MBX_WriteReg( (DVBTM_REG_BASE + 0x20*2), u8Data);
3006 }
3007 }
3008 }
3009 }
3010 else
3011 {
3012 bRet = TRUE;
3013 }
3014 break;
3015
3016 default:
3017 bRet = FALSE;
3018 }
3019 return bRet;
3020 }
3021
INTERN_DVBS_GetTunrSignalLevel_PWR(void)3022 float INTERN_DVBS_GetTunrSignalLevel_PWR(void)// Need check debug out table
3023 {
3024 MS_BOOL status=TRUE;
3025 MS_U16 u16Data =0;
3026 MS_U8 u8Data =0;
3027 MS_U8 u8Index =0;
3028 float fCableLess = 0.0;
3029
3030 if (FALSE == INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0) )//Demod unlock
3031 {
3032 fCableLess = 0;
3033 }
3034
3035 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x11*2, &u8Data);//FRONTEND_AGC_DEBUG_SEL
3036 u8Data=(u8Data&0xF0)|0x03;
3037 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x11*2, u8Data);
3038
3039 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x02, &u8Data);//FRONTEND_LATCH
3040 u8Data|=0x80;
3041 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x02, u8Data);
3042
3043 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x12*2+1, &u8Data);//FRONTEND_AGC_DEBUG_OUT_R1
3044 u16Data=u8Data;
3045 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x12*2, &u8Data);//FRONTEND_AGC_DEBUG_OUT_R0
3046 u16Data=(u16Data<<8)|u8Data;
3047 //printf("===========================Tuner 65535-u16Data = %d\n", (65535-u16Data));
3048 //MsOS_DelayTask(400);
3049
3050 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x02, &u8Data);//FRONTEND_LOAD0
3051 u8Data&=~(0x80);
3052 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x02, u8Data);
3053
3054 if (status==FALSE)
3055 {
3056 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS GetSignalStrength fail!!! \n "));
3057 fCableLess = 0;
3058 }
3059
3060 DBG_INTERN_DVBS(printf("#### INTERN_DVBS_GetTunrSignalLevel_PWR u16Data = %d\n", (int)u16Data));
3061 for (u8Index=0; u8Index < (sizeof(_u16SignalLevel)/sizeof(_u16SignalLevel[0])); u8Index++)
3062 {
3063 if ((65535 - u16Data) <= _u16SignalLevel[u8Index][0])
3064 {
3065 if (u8Index >=1)
3066 {
3067 fCableLess = (float)(_u16SignalLevel[u8Index][1])+((float)(_u16SignalLevel[u8Index][0] - (65535 - u16Data)) / (float)(_u16SignalLevel[u8Index][0] - _u16SignalLevel[u8Index-1][0]))*(float)(_u16SignalLevel[u8Index-1][1] - _u16SignalLevel[u8Index][1]);
3068 break;
3069 }
3070 else
3071 {
3072 fCableLess = _u16SignalLevel[u8Index][1];
3073 break;
3074 }
3075 }
3076 }
3077 //---------------------------------------------------
3078 /*
3079 if (fCableLess >= 350)
3080 fCableLess = fCableLess - 35;
3081 else if ((fCableLess < 350) && (fCableLess >= 250))
3082 fCableLess = fCableLess - 25;
3083 else
3084 fCableLess = fCableLess - 5;
3085 */
3086
3087 if (fCableLess < 0)
3088 fCableLess = 0;
3089 if (fCableLess > 920)
3090 fCableLess = 920;
3091
3092 fCableLess = (-1.0)*(fCableLess/10.0);
3093
3094 DBG_INTERN_DVBS(printf("INTERN_DVBS GetSignalStrength %f\n", fCableLess));
3095
3096 return fCableLess;
3097 }
3098
3099 /****************************************************************************
3100 Subject: To get the Post viterbi BER
3101 Function: INTERN_DVBS_GetPostViterbiBer
3102 Parmeter: Quility
3103 Return: E_RESULT_SUCCESS
3104 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBC_VIT_STATUS_NG
3105 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
3106 We will not read the Period, and have the "/256/8"
3107 *****************************************************************************/
INTERN_DVBS_GetPostViterbiBer(float * postber)3108 MS_BOOL INTERN_DVBS_GetPostViterbiBer(float *postber)//POST BER //V
3109 {
3110 MS_BOOL status = true;
3111 MS_U8 reg = 0, reg_frz = 0;
3112 MS_U16 BitErrPeriod;
3113 MS_U32 BitErr;
3114
3115 /////////// Post-Viterbi BER /////////////After Viterbi
3116
3117 // freeze ,DVBSRS_BACKEND_BIT_ERR_NUM_FREEZE
3118 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1*2+1, ®_frz);//h0001 h0001 8 8 reg_ber_en
3119 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x1*2+1, reg_frz|0x01);
3120
3121 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0 ,DVBSFEC_BIT_ERR_SBLPRD_7_0
3122 // 0x47 [15:8] reg_bit_err_sblprd_15_8
3123 //KRIS register table
3124 //h0018 h0018 7 0 reg_bit_err_sblprd_7_0
3125 //h0018 h0018 15 8 reg_bit_err_sblprd_15_8
3126 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x18*2+1, ®);
3127 BitErrPeriod = reg;
3128
3129 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x18*2, ®);
3130 BitErrPeriod = (BitErrPeriod << 8)|reg;
3131
3132
3133 //h001d h001d 7 0 reg_bit_err_num_7_0
3134 //h001d h001d 15 8 reg_bit_err_num_15_8
3135 //h001e h001e 7 0 reg_bit_err_num_23_16
3136 //h001e h001e 15 8 reg_bit_err_num_31_24
3137
3138 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1E*2+1, ®);
3139 BitErr = reg;
3140 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1E*2, ®);
3141 BitErr = (BitErr << 8)|reg;
3142 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1D*2+1, ®);
3143 BitErr = (BitErr << 8)|reg;
3144 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1D*2, ®);
3145 BitErr = (BitErr << 8)|reg;
3146
3147 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
3148 reg_frz=reg_frz&(~0x01);
3149 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x1*2+1, reg_frz);
3150
3151 if (BitErrPeriod == 0 ) //PRD
3152 BitErrPeriod = 1;
3153
3154 if (BitErr <= 0 )
3155 *postber = 0.5f / ((float)BitErrPeriod*128*188*8);
3156 else
3157 *postber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
3158
3159 if (*postber <= 0.0f)
3160 *postber = 1.0e-10f;
3161
3162 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS PostVitBER = %8.3e \n", *postber));
3163
3164 return status;
3165 }
3166
3167
INTERN_DVBS_GetPreViterbiBer(float * preber)3168 MS_BOOL INTERN_DVBS_GetPreViterbiBer(float *preber)//PER BER // not yet
3169 {
3170 MS_BOOL status = true;
3171 //MS_U8 reg = 0, reg_frz = 0;
3172 //MS_U16 BitErrPeriod;
3173 //MS_U32 BitErr;
3174
3175 #if 0
3176 /////////// Pre-Viterbi BER /////////////Before Viterbi
3177
3178 // freeze ,DVBSRS_BACKEND_BIT_ERR_NUM_FREEZE
3179 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x10, ®_frz);
3180 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSTFEC_REG_BASE+0x10, reg_frz|0x08);
3181
3182 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0 ,DVBSFEC_BIT_ERR_SBLPRD_7_0
3183 // 0x47 [15:8] reg_bit_err_sblprd_15_8
3184 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x19, ®);
3185 BitErrPeriod = reg;
3186
3187 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x18, ®);
3188 BitErrPeriod = (BitErrPeriod << 8)|reg;
3189
3190 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x17, ®);
3191 BitErrPeriod = (BitErrPeriod << 8)|reg;
3192
3193 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x16, ®);
3194 BitErrPeriod = (BitErrPeriod << 8)|reg;
3195 BitErrPeriod = (BitErrPeriod & 0x3FFF);
3196
3197 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
3198 // 0x6b [15:8] reg_bit_err_num_15_8
3199 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
3200 // 0x6d [15:8] reg_bit_err_num_31_24
3201 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x1F, ®);
3202 BitErr = reg;
3203
3204 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x1E, ®);
3205 BitErr = (BitErr << 8)|reg;
3206
3207 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
3208 reg_frz=reg_frz&(~0x08);
3209 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x10, reg_frz);
3210
3211 if (BitErrPeriod ==0 )//protect 0
3212 BitErrPeriod=1;
3213 if (BitErr <=0 )
3214 *perber=0.5f / (float)BitErrPeriod / 256;
3215 else
3216 *perber=(float)BitErr / (float)BitErrPeriod / 256;
3217
3218 if (*perber <= 0.0f)
3219 *perber = 1.0e-10f;
3220
3221 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS PerVitBER = %8.3e \n", *perber));
3222 #endif
3223
3224 return status;
3225 }
3226
3227 /****************************************************************************
3228 Subject: To get the Packet error
3229 Function: INTERN_DVBS_GetPacketErr
3230 Parmeter: pktErr
3231 Return: E_RESULT_SUCCESS
3232 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
3233 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
3234 We will not read the Period, and have the "/256/8"
3235 *****************************************************************************/
INTERN_DVBS_GetPacketErr(MS_U16 * pktErr)3236 MS_BOOL INTERN_DVBS_GetPacketErr(MS_U16 *pktErr)//V
3237 {
3238 MS_BOOL status = true;
3239 MS_U8 u8Data = 0;
3240 MS_U16 u16PktErr = 0;
3241
3242 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);
3243 if(!u8Data) //DVB-S2
3244 {
3245 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x02*2, &u8Data);//DVBS2FEC_OUTER_FREEZE (_REG_DVBS2FEC(0x02)+0) //[0]
3246 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE+0x02*2, u8Data|0x01);
3247
3248 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x26*2+1, &u8Data);//DVBS2FEC_BCH_EFLAG2_SUM1 (_REG_DVBS2FEC(0x2B)+1)
3249 u16PktErr = u8Data;
3250 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x26*2, &u8Data);
3251 u16PktErr = (u16PktErr << 8)|u8Data;
3252
3253 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x02*2, &u8Data);
3254 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE+0x02*2, u8Data&(~0x01));
3255 }
3256 else
3257 { //DVB-S
3258 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x19*2, &u8Data); //0x19 [7] reg_bit_err_num_freeze
3259 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x19*2, u8Data|0x80);
3260
3261 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(REG_BACKEND+0x33*2+1, &u8Data);// DVBSFEC_UNCRT_PKT_NUM_15_8 (_REG_DVBSFEC(0x1F)+1)
3262 u16PktErr = u8Data;
3263 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(REG_BACKEND+0x33*2, &u8Data);
3264 u16PktErr = (u16PktErr << 8)|u8Data;
3265
3266 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x19*2, &u8Data); //0x19 [7] reg_bit_err_num_freeze
3267 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x19*2, u8Data&(~0x80));
3268 }
3269 *pktErr = u16PktErr;
3270
3271 DBG_INTERN_DVBS(printf("INTERN_DVBS PktErr = %d \n", (int)u16PktErr));
3272
3273 return status;
3274 }
3275
3276 /****************************************************************************
3277 Subject: Read the signal to noise ratio (SNR)
3278 Function: INTERN_DVBS_GetSNR
3279 Parmeter: None
3280 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
3281 Remark:
3282 *****************************************************************************/
INTERN_DVBS_GetSNR(float * f_snr)3283 MS_BOOL INTERN_DVBS_GetSNR(float *f_snr)//V
3284 {
3285 MS_BOOL status= TRUE;
3286 MS_U8 u8Data =0, reg_frz =0;
3287 //NDA SNR
3288 MS_U32 u32NDA_SNR_A =0;
3289 MS_U32 u32NDA_SNR_AB =0;
3290 //NDA SNR
3291 float NDA_SNR_A =0.0;
3292 float NDA_SNR_AB =0.0;
3293 float NDA_SNR =0.0;
3294 double NDA_SNR_LINEAR=0.0;
3295 //float snr_poly =0.0;
3296 //float Fixed_SNR =0.0;
3297
3298 if (INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0)== FALSE)
3299 {
3300 return 0;
3301 }
3302
3303 // freeze
3304 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE+0x04*2, ®_frz);
3305 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_INNER_REG_BASE+0x04*2, reg_frz|0x10);//INNE_LATCH bit[4]
3306
3307 //NDA SNR_A
3308 // read Linear_SNR
3309 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x47*2, &u8Data);
3310 u32NDA_SNR_A=(u8Data&0x03);
3311 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x46*2 + 1, &u8Data);
3312 u32NDA_SNR_A=(u32NDA_SNR_A<<8)|u8Data;
3313 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x46*2, &u8Data);
3314 u32NDA_SNR_A=(u32NDA_SNR_A<<8)|u8Data;
3315 //NDA SNR_AB
3316 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x49*2+1, &u8Data);
3317 u32NDA_SNR_AB=(u8Data&0x3F);
3318 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x49*2, &u8Data);
3319 u32NDA_SNR_AB = (u32NDA_SNR_AB<<8)|u8Data;
3320 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x48*2 + 1, &u8Data);
3321 u32NDA_SNR_AB=(u32NDA_SNR_AB<<8)|u8Data;
3322 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x48*2, &u8Data);
3323 u32NDA_SNR_AB=(u32NDA_SNR_AB<<8)|u8Data;
3324
3325 //UN_freeze
3326 reg_frz=reg_frz&(~0x10);
3327 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_INNER_REG_BASE+0x08, reg_frz);
3328
3329 if (status== FALSE)
3330 {
3331 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetSNR Fail! \n"));
3332 return 0;
3333 }
3334 //NDA SNR
3335 NDA_SNR_A=(float)u32NDA_SNR_A/65536;
3336 NDA_SNR_AB=(float)u32NDA_SNR_AB/4194304;
3337 //
3338 //since support 16,32APSK we need to add judgement
3339 if(modulation_order==4)
3340 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB/(2-1.252295758529242));//for 16APSK CR2/3
3341 else if(modulation_order==5)//(2-1.41333232789)
3342 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB/(2-1.41333232789));//for 32APSK CR3/4
3343 else
3344 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB);
3345
3346 NDA_SNR_LINEAR =(1/((NDA_SNR_A/NDA_SNR_AB)-1)) ;
3347
3348 if(NDA_SNR_LINEAR<=0)
3349 NDA_SNR=1.0;
3350 else
3351 NDA_SNR=10*log10(NDA_SNR_LINEAR);
3352
3353 //printf("[DVBS]: NDA_SNR ================================: %.1f\n", NDA_SNR);
3354 _f_DVBS_CurrentSNR = NDA_SNR;
3355 /*
3356 //[DVBS/S2, QPSK/8PSK, 1/2~9/10 the same CN]
3357 snr_poly = 0.0; //use Polynomial curve fitting to fix SNR
3358 snr_poly = 0.005261367463671*pow(NDA_SNR, 3)-0.116517828301214*pow(NDA_SNR, 2)+0.744836970505452*pow(NDA_SNR, 1)-0.86727609780167;
3359 Fixed_SNR = NDA_SNR + snr_poly;
3360 //printf("[DVBS]: NDA_SNR + snr_poly =====================: %.1f\n", Fixed_SNR);
3361
3362 if (Fixed_SNR < 17.0)
3363 Fixed_SNR = Fixed_SNR;
3364 else if ((Fixed_SNR < 20.0) && (Fixed_SNR >= 17.0))
3365 Fixed_SNR = Fixed_SNR - 0.8;
3366 else if ((Fixed_SNR < 22.5) && (Fixed_SNR >= 20.0))
3367 Fixed_SNR = Fixed_SNR - 2.0;
3368 else if ((Fixed_SNR < 27.0) && (Fixed_SNR >= 22.5))
3369 Fixed_SNR = Fixed_SNR - 3.0;
3370 else if ((Fixed_SNR < 29.0) && (Fixed_SNR >= 27.0))
3371 Fixed_SNR = Fixed_SNR - 3.5;
3372 else if (Fixed_SNR >= 29.0)
3373 Fixed_SNR = Fixed_SNR - 3.0;
3374
3375 if (Fixed_SNR < 1.0)
3376 Fixed_SNR = 1.0;
3377 if (Fixed_SNR > 30.0)
3378 Fixed_SNR = 30.0;
3379 */
3380 *f_snr = NDA_SNR;
3381 //printf("[DVBS]: NDA_SNR=============================: %.1f\n", NDA_SNR);
3382
3383 return status;
3384 }
3385
3386 //SSI
INTERN_DVBS_GetSignalStrength(MS_U16 * pu16SignalBar,const DMD_DVBS_InitData * sDMD_DVBS_InitData,MS_U8 u8SarValue,float fRFPowerDbm)3387 MS_BOOL INTERN_DVBS_GetSignalStrength(MS_U16 *pu16SignalBar, const DMD_DVBS_InitData *sDMD_DVBS_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
3388 {
3389 //-1.2~-92.2 dBm
3390 MS_BOOL status = true;
3391 MS_U8 u8Data =0;
3392 MS_U8 _u8_DVBS2_CurrentCodeRateLocal = 0;
3393 float ch_power_db=0.0f, ch_power_db_rel=0.0f;
3394
3395 DBG_INTERN_DVBS_TIME(printf("INTERN_DVBS_GetSignalStrength, t=%d, RF level=%f, Table=%x\n",MsOS_GetSystemTime(), fRFPowerDbm, (MS_U32)(sDMD_DVBS_InitData->pTuner_RfagcSsi)));
3396
3397 // if (INTERN_DVBC_Lock(COFDM_TPS_LOCK))
3398 // if (INTERN_DVBC_Lock(COFDM_AGC_LOCK))
3399 // Actually, it's more reasonable, that signal level depended on cable input power level
3400 // thougth the signal isn't dvb-t signal.
3401 //
3402 // use pointer of IFAGC table to identify
3403 // case 1: RFAGC from SAR, IFAGC controlled by demod
3404 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
3405 //status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
3406 // sDMD_DVBS_InitData->pTuner_RfagcSsi, sDMD_DVBS_InitData->u16Tuner_RfagcSsi_Size,
3407 // sDMD_DVBS_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBS_InitData->u16Tuner_IfagcSsi_HiRef_Size,
3408 // sDMD_DVBS_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBS_InitData->u16Tuner_IfagcSsi_LoRef_Size,
3409 // sDMD_DVBS_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBS_InitData->u16Tuner_IfagcErr_HiRef_Size,
3410 // sDMD_DVBS_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBS_InitData->u16Tuner_IfagcErr_LoRef_Size);
3411 ch_power_db = INTERN_DVBS_GetTunrSignalLevel_PWR();
3412 //printf("@@@@@@@@@ ch_power_db = %f \n", ch_power_db);
3413
3414 MS_U8 u8Data2 = 0;
3415 MS_U8 _u8_DVBS2_CurrentConstellationLocal = 0;
3416 DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3417
3418
3419 status &= INTERN_DVBS_GetCurrentDemodType(&pDemodType);
3420
3421 if((MS_U8)pDemodType == (MS_U8)DMD_SAT_DVBS)//S
3422 {
3423 float fDVBS_SSI_Pref[]=
3424 {
3425 //0, 1, 2, 3, 4
3426 -78.9, -77.15, -76.14, -75.19, -74.57,//QPSK
3427 };
3428 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE + 0x84, &u8Data);
3429 _u8_DVBS2_CurrentCodeRateLocal = (u8Data & 0x07);
3430 ch_power_db_rel = ch_power_db - fDVBS_SSI_Pref[_u8_DVBS2_CurrentCodeRateLocal];
3431 }
3432 else
3433 {
3434 float fDVBS2_SSI_Pref[][11]=
3435 {
3436 // 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
3437 //1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10
3438 {-85.17, -84.08, -83.15, -81.86, -80.63, -79.77, -78.84, -78.19, -77.69, -76.68, -76.46}, //QPSK
3439 { 0.0, 0.0, 0.0, 0.0, -77.36, -76.24, -74.95, 0.0, -73.52, -72.18, -71.84} //8PSK
3440 };
3441
3442 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
3443 _u8_DVBS2_CurrentCodeRateLocal = (u8Data & 0x3C)>>2;
3444
3445 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
3446 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD6, &u8Data2);
3447
3448 if(((u8Data & 0x03)==0x01) && ((u8Data2 & 0x80)==0x00))
3449 {
3450 _u8_DVBS2_CurrentConstellationLocal = DMD_DVBS_QPSK;
3451 }
3452 else if (((u8Data & 0x03)==0x01) && ((u8Data2 & 0x80)==0x80))
3453 {
3454 _u8_DVBS2_CurrentConstellationLocal = DMD_DVBS_8PSK;//8PSK
3455 }
3456 ch_power_db_rel = ch_power_db - fDVBS2_SSI_Pref[_u8_DVBS2_CurrentConstellationLocal][_u8_DVBS2_CurrentCodeRateLocal];
3457 }
3458
3459 if(ch_power_db_rel <= -15.0f)
3460 {
3461 *pu16SignalBar = 0;
3462 }
3463 else if (ch_power_db_rel <= 0.0f)
3464 {
3465 *pu16SignalBar = (MS_U16)(2.0f/3 * (ch_power_db_rel+15.0f));
3466 }
3467 else if (ch_power_db_rel <= 20.0f)
3468 {
3469 *pu16SignalBar = (MS_U16)(4.0f * ch_power_db_rel + 10.0f);
3470 }
3471 else if (ch_power_db_rel <= 35.0f)
3472 {
3473 *pu16SignalBar = (MS_U16)(2.0f/3 * (ch_power_db_rel-20.0f) + 90.0);
3474 }
3475 else
3476 {
3477 *pu16SignalBar = 100;
3478 }
3479
3480 DBG_INTERN_DVBS(printf(">>>>>Signal Strength(SSI) = %d\n", (int)*pu16SignalBar));
3481
3482 return status;
3483 }
3484
3485 //SQI
3486 /****************************************************************************
3487 Subject: To get the DVT Signal quility
3488 Function: INTERN_DVBS_GetSignalQuality
3489 Parmeter: Quility
3490 Return: E_RESULT_SUCCESS
3491 E_RESULT_FAILURE
3492 Remark: Here we have 4 level range
3493 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
3494 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
3495 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
3496 <4>.4th Range => Quality <10
3497 *****************************************************************************/
INTERN_DVBS_GetSignalQuality(MS_U16 * quality,const DMD_DVBS_InitData * sDMD_DVBS_InitData,MS_U8 u8SarValue,float fRFPowerDbm)3498 MS_BOOL INTERN_DVBS_GetSignalQuality(MS_U16 *quality, const DMD_DVBS_InitData *sDMD_DVBS_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
3499 {
3500
3501 float fber = 0.0;
3502 //float log_ber;
3503 MS_BOOL status = TRUE;
3504 float f_snr = 0.0, ber_sqi = 0.0, cn_rel = 0.0;
3505 MS_U8 u8Data =0;
3506 MS_U16 u16Data =0;
3507 DMD_DVBS_CODE_RATE_TYPE _u8_DVBS2_CurrentCodeRateLocal ;
3508 MS_U16 bchpkt_error,BCH_Eflag2_Window;
3509 //fRFPowerDbm = fRFPowerDbm;
3510 float snr_poly =0.0;
3511 float Fixed_SNR =0.0;
3512 double eFlag_PER=0.0;
3513
3514 if (TRUE == INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0))
3515 {
3516 if(_bDemodType) //S2
3517 {
3518
3519 //INTERN_DVBS_GetSNR(&f_snr);
3520 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_7, &u8Data);
3521 u16Data=u8Data;
3522 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_6, &u8Data);
3523 u16Data = (u16Data<<8)|u8Data;
3524 f_snr=(float)u16Data/256.0;
3525 snr_poly = 0.005261367463671*pow(f_snr, 3)-0.116517828301214*pow(f_snr, 2)+0.744836970505452*pow(f_snr, 1)-0.86727609780167;
3526 Fixed_SNR = f_snr + snr_poly;
3527
3528 if (Fixed_SNR < 17.0)
3529 Fixed_SNR = Fixed_SNR;
3530 else if ((Fixed_SNR < 20.0) && (Fixed_SNR >= 17.0))
3531 Fixed_SNR = Fixed_SNR - 0.8;
3532 else if ((Fixed_SNR < 22.5) && (Fixed_SNR >= 20.0))
3533 Fixed_SNR = Fixed_SNR - 2.0;
3534 else if ((Fixed_SNR < 27.0) && (Fixed_SNR >= 22.5))
3535 Fixed_SNR = Fixed_SNR - 3.0;
3536 else if ((Fixed_SNR < 29.0) && (Fixed_SNR >= 27.0))
3537 Fixed_SNR = Fixed_SNR - 3.5;
3538 else if (Fixed_SNR >= 29.0)
3539 Fixed_SNR = Fixed_SNR - 3.0;
3540
3541
3542 if (Fixed_SNR < 1.0)
3543 Fixed_SNR = 1.0;
3544 if (Fixed_SNR > 30.0)
3545 Fixed_SNR = 30.0;
3546
3547 //BCH EFLAG2_Window, window size 0x2000
3548 BCH_Eflag2_Window=0x2000;
3549 MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE + 0x25*2 + 1, (BCH_Eflag2_Window>>8));
3550 MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE + 0x25*2 , (BCH_Eflag2_Window&0xff));
3551 INTERN_DVBS_GetPacketErr(&bchpkt_error);
3552 eFlag_PER = (float)(bchpkt_error)/(float)(BCH_Eflag2_Window);
3553 if(eFlag_PER>0)
3554 fber = 0.089267531133002*pow(eFlag_PER, 2) + 0.019640560289510*eFlag_PER + 0.0000001;
3555 else
3556 fber = 0;
3557
3558 #ifdef MSOS_TYPE_LINUX
3559 //log_ber = ( - 1) *log10f(1 / fber);
3560 if (fber > 1.0E-1)
3561 ber_sqi = (log10f(1.0f/fber))*20.0f + 8.0f;
3562 else if(fber > 8.5E-7)
3563 ber_sqi = (log10f(1.0f/fber))*20.0f - 30.0f;
3564 else
3565 ber_sqi = 100.0;
3566 #else
3567 //log_ber = ( - 1) *Log10Approx(1 / fber);
3568 if (fber > 1.0E-1)
3569 ber_sqi = (Log10Approx(1.0f/fber))*20.0f + 8.0f;
3570 else if(fber > 8.5E-7)
3571 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 30.0f;
3572 else
3573 ber_sqi = 100.0;
3574
3575 #endif
3576
3577 *quality = Fixed_SNR/30*ber_sqi;
3578 DBG_INTERN_DVBS(printf(" Fixed_SNR %f\n",Fixed_SNR));
3579 DBG_INTERN_DVBS(printf(" BCH_Eflag2_Window %d\n",BCH_Eflag2_Window));
3580 DBG_INTERN_DVBS(printf(" eFlag_PER [%f]\n fber [%8.3e]\n ber_sqi [%f]\n",eFlag_PER,fber,ber_sqi));
3581 }
3582 else //S
3583 {
3584 if (INTERN_DVBS_GetPostViterbiBer(&fber) == FALSE)//ViterbiBer
3585 {
3586 DBG_INTERN_DVBS(printf("\nGetPostViterbiBer Fail!"));
3587 return FALSE;
3588 }
3589 _fPostBer=fber;
3590
3591
3592 if (status==FALSE)
3593 {
3594 DBG_INTERN_DVBS(printf("MSB131X_DTV_GetSignalQuality GetPostViterbiBer Fail!\n"));
3595 return 0;
3596 }
3597 float fDVBS_SQI_CNref[]=
3598 { //0, 1, 2, 3, 4
3599 4.2, 5.9, 6, 6.9, 7.5,//QPSK
3600 };
3601
3602 INTERN_DVBS_GetCurrentDemodCodeRate(&_u8_DVBS2_CurrentCodeRateLocal);
3603 #if 0
3604 #ifdef MSOS_TYPE_LINUX
3605 log_ber = ( - 1.0f) *log10f(1.0f / fber); //BY modify
3606 #else
3607 log_ber = ( - 1.0f) *Log10Approx(1.0f / fber); //BY modify
3608 #endif
3609 DBG_INTERN_DVBS(printf("\nLog(BER) = %f\n",log_ber));
3610 #endif
3611 if (fber > 2.5E-2)
3612 ber_sqi = 0.0;
3613 else if(fber > 8.5E-7)
3614 #ifdef MSOS_TYPE_LINUX
3615 ber_sqi = (log10f(1.0f/fber))*20.0f - 32.0f; //40.0f;
3616 #else
3617 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 32.0f;//40.0f;
3618 #endif
3619 else
3620 ber_sqi = 100.0;
3621
3622 //status &= INTERN_DVBS_GetSNR(&f_snr);
3623 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_7, &u8Data);
3624 u16Data=u8Data;
3625 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_6, &u8Data);
3626 u16Data = (u16Data<<8)|u8Data;
3627 f_snr=(float)u16Data/256.0;
3628 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS GetSNR = %d \n", (int)f_snr));
3629
3630 cn_rel = f_snr - fDVBS_SQI_CNref[_u8_DVBS2_CurrentCodeRateLocal];
3631
3632 DBG_INTERN_DVBS(printf(" fber = %f\n",fber));
3633 DBG_INTERN_DVBS(printf(" f_snr = %f\n",f_snr));
3634 DBG_INTERN_DVBS(printf(" cn_nordig_s1 = %f\n",fDVBS_SQI_CNref[_u8_DVBS2_CurrentCodeRateLocal]));
3635 DBG_INTERN_DVBS(printf(" cn_rel = %f\n",cn_rel));
3636 DBG_INTERN_DVBS(printf(" ber_sqi = %f\n",ber_sqi));
3637
3638 if (cn_rel < -7.0f)
3639 {
3640 *quality = 0;
3641 }
3642 else if (cn_rel < 3.0)
3643 {
3644 *quality = (MS_U16)(ber_sqi*((cn_rel - 3.0)/10.0 + 1.0));
3645 }
3646 else
3647 {
3648 *quality = (MS_U16)ber_sqi;
3649 }
3650
3651
3652 }
3653 //INTERN_DVBS_GetTunrSignalLevel_PWR();//For Debug.
3654 DBG_INTERN_DVBS(printf(">>>>>Signal Quility(SQI) = %d\n", *quality));
3655 return TRUE;
3656 }
3657 else
3658 {
3659 *quality = 0;
3660 }
3661
3662 return TRUE;
3663 }
3664
3665 /****************************************************************************
3666 Subject: To get the Cell ID
3667 Function: INTERN_DVBS_Get_CELL_ID
3668 Parmeter: point to return parameter cell_id
3669
3670 Return: TRUE
3671 FALSE
3672 Remark:
3673 *****************************************************************************/
INTERN_DVBS_Get_CELL_ID(MS_U16 * cell_id)3674 MS_BOOL INTERN_DVBS_Get_CELL_ID(MS_U16 *cell_id)
3675 {
3676 MS_BOOL status = true;
3677 MS_U8 value1 = 0;
3678 MS_U8 value2 = 0;
3679
3680 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [15:8]
3681 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [7:0]
3682
3683 *cell_id = ((MS_U16)value1<<8)|value2;
3684 return status;
3685 }
3686
3687 /****************************************************************************
3688 Subject: To get the DVBC Carrier Freq Offset
3689 Function: INTERN_DVBS_Get_FreqOffset
3690 Parmeter: Frequency offset (in KHz), bandwidth
3691 Return: E_RESULT_SUCCESS
3692 E_RESULT_FAILURE
3693 Remark:
3694 *****************************************************************************/
INTERN_DVBS_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)3695 MS_BOOL INTERN_DVBS_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
3696 {
3697 //MS_U8 u8Data;
3698 //MS_U16 u16Data;
3699 //MS_S16 s16CFO;
3700 //float FreqOffset;
3701 //MS_U32 u32FreqOffset = 0;
3702 //MS_U8 reg = 0;
3703 MS_BOOL status = TRUE;
3704 #if 0
3705 DBG_INTERN_DVBS(printf(">>> INTERN_DVBS_Get_FreqOffset DVBS_Estimated_CFO <<<\n"));
3706 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_97, &u8Data);
3707 u16Data=u8Data;
3708 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_96, &u8Data);
3709 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset
3710 if (u16Data >= 0x8000)
3711 {
3712 u16Data=0x10000- u16Data;
3713 s16CFO=-1*u16Data;
3714 }
3715 else
3716 {
3717 s16CFO=u16Data;
3718 }
3719 DBG_INTERN_DVBS(printf(">>> INTERN_DVBS_Get_FreqOffset CFO = %d[KHz] <<<\n", s16CFO));
3720 if(abs(s16CFO)%1000 >= 500)
3721 {
3722 if(s16CFO < 0)
3723 *pFreqOff=(s16CFO/1000)-1.0;
3724 else
3725 *pFreqOff=(s16CFO/1000)+1.0;
3726 }
3727 else
3728 *pFreqOff = s16CFO/1000;
3729 DBG_INTERN_DVBS(printf(">>> INTERN_DVBS_Get_FreqOffset *pFreqOff = %d[MHz] <<<\n", (MS_S16)*pFreqOff));
3730 // no use.
3731 u8BW = u8BW;
3732 /*
3733 printf("INTERN_DVBS_Get_FreqOffset\n");//DBG_INTERN_DVBS(printf("INTERN_DVBS_Get_FreqOffset\n"));
3734
3735 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x1C*2 + 1, 0x08);
3736
3737 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x05, ®);
3738 reg|=0x80;
3739 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x05, reg);
3740
3741 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x23*2, ®);
3742 u32FreqOffset=reg;
3743 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x22*2 + 1, ®);
3744 u32FreqOffset=(u32FreqOffset<<8)|reg;
3745 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x22*2, ®);
3746 u32FreqOffset=(u32FreqOffset<<8)|reg;
3747
3748 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x05, ®);
3749 reg&=~(0x80);
3750 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x05, reg);
3751
3752 FreqOffset=(float)u32FreqOffset;
3753 if (FreqOffset>=2048)
3754 {
3755 FreqOffset=FreqOffset-4096;
3756 }
3757 FreqOffset=(FreqOffset/4096)*SAMPLING_RATE_FS;
3758
3759 *pFreqOff = FreqOffset/1000; //KHz
3760 printf("INTERN_DVBS_Get_FreqOffset:%d[MHz]\n", (MS_S16)FreqOffset/1000);//DBG_INTERN_DVBS(printf("INTERN_DVBS_Get_FreqOffset:%f[MHz]\n", FreqOffset/1000));
3761 */
3762 #endif
3763 return status;
3764 }
3765
3766 /****************************************************************************
3767 Subject: To get the current modulation type at the DVB-S Demod
3768 Function: INTERN_DVBS_GetCurrentModulationType
3769 Parmeter: pointer for return QAM type
3770
3771 Return: TRUE
3772 FALSE
3773 Remark:
3774 *****************************************************************************/
INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE * pQAMMode)3775 MS_BOOL INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE *pQAMMode)
3776 {
3777 MS_U8 u8Data=0;
3778 MS_U16 u16tmp=0;
3779 MS_U8 MOD_type;
3780 MS_BOOL status = true;
3781 //DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3782
3783 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentModulationType\n"));
3784
3785 //status &= INTERN_DVBS_GetCurrentDemodType(&pDemodType);
3786
3787 // read code rate, pilot on/off, long/short FEC type, and modulation type for calculating TOP_DVBTM_TS_CLK_DIVNUM
3788 // pilot_flag => 0 : off 1 : on
3789 // fec_type_idx => 0 : normal 1 : short
3790 // mod_type_idx => 0 : QPSK 1 : 8PSK 2 : 16APSK
3791 // code_rate_idx => 0 : 1/4 1 : 1/3 2 : 2/5 3 : 1/2 4 : 3/5 5 : 2/3
3792 // 6 : 3/4 7 : 4/5 8 : 5/6 9 : 8/9 10 : 9/10
3793 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//V
3794 if(u8Data)
3795 {
3796 *pQAMMode = DMD_DVBS_QPSK;
3797 modulation_order=2;
3798 printf("INTERN_DVBS_GetCurrentModulationType [dvbs]ModulationType=DVBS_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS_QPSK\n"));
3799 //return TRUE;
3800 }
3801 else //S2
3802 {
3803 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x96, &u8Data);
3804 //printf(">>> INTERN_DVBS_GetCurrentModulationType INNER 0x4B = 0x%x <<<\n", u8Data);
3805 //if((u8Data & 0x0F)==0x02) //QPSK
3806 /*MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MOD_TYPE, &u8Data1);
3807 printf("@@@@@E_DMD_S2_MOD_TYPE = %d \n ",u8Data1);
3808 printf("@@@@@ E_DMD_S2_MOD_TYPE=%d \n",E_DMD_S2_MOD_TYPE);
3809
3810 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_IS_ID, &u8Data1);
3811 printf("@@@@@E_DMD_S2_IS_ID = %d \n ",u8Data1);
3812 printf("@@@@@ E_DMD_S2_IS_ID=%d \n",E_DMD_S2_IS_ID);*/
3813
3814 // INNER_DEBUG_SEL
3815 MDrv_SYS_DMD_VD_MBX_ReadReg(0x3b00+0x04*2+1, &u8Data);
3816 u8Data = u8Data & 0xc0;
3817 MDrv_SYS_DMD_VD_MBX_WriteReg(0x3b00+0x04*2+1, u8Data);
3818
3819 // reg_plscdec_debug_out
3820 // PLSCDEC info
3821 //[0:4] PLSC MODCOD
3822 //[5] dummy frame
3823 //[6] reserve frame
3824 //[7:9] modulation type
3825 //[10:13] code rate type
3826 //[14] FEC type
3827 //[15] pilot type
3828 MDrv_SYS_DMD_VD_MBX_ReadReg(0x3b00+0x6b*2 , &u8Data);
3829 u16tmp = (MS_U16)u8Data;
3830 MDrv_SYS_DMD_VD_MBX_ReadReg(0x3b00+0x6b*2+1 , &u8Data);
3831 u16tmp |= (MS_U16)u8Data << 8;
3832 MOD_type = ((MS_U8)(u16tmp>>7)&0x07); // 2:QPSK, 3:8PSK, 4:16APSK, 5:32APSK
3833
3834 if(MOD_type==2)
3835 {
3836 *pQAMMode = DMD_DVBS_QPSK;
3837 modulation_order=2;
3838 printf("INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS2_QPSK\n"));
3839 //return TRUE;
3840 }
3841 else if(MOD_type==3)
3842 {
3843 *pQAMMode = DMD_DVBS_8PSK;
3844 modulation_order=3;
3845 printf("INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_8PSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS2_8PSK\n"));
3846 //return TRUE;
3847 }
3848 else if(MOD_type==4)
3849 {
3850 *pQAMMode = DMD_DVBS_16APSK;
3851 modulation_order=4;
3852 printf("INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_16APSK\n");
3853 }
3854 else
3855 {
3856 *pQAMMode = DMD_DVBS_QPSK;
3857 modulation_order=2;
3858 printf("INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=NOT SUPPORT\n");
3859 return FALSE;
3860 }
3861
3862 }
3863
3864 return status;
3865 /*#else
3866 *pQAMMode = DMD_DVBS_QPSK;
3867 printf("[dvbs]ModulationType=DVBS_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS_QPSK\n"));
3868 //return true;
3869 #endif*/
3870 }
3871
3872 /****************************************************************************
3873 Subject: To get the current DemodType at the DVB-S Demod
3874 Function: INTERN_DVBS_GetCurrentDemodType
3875 Parmeter: pointer for return DVBS/DVBS2 type
3876
3877 Return: TRUE
3878 FALSE
3879 Remark:
3880 *****************************************************************************/
INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE * pDemodType)3881 MS_BOOL INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE *pDemodType)//V
3882 {
3883 MS_U8 u8Data=0;
3884 MS_BOOL status = true;
3885
3886 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentDemodType\n"));
3887
3888 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x80, &u8Data);//status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x80, &u8Data);
3889 //printf(">>> INTERN_DVBS_GetCurrentDemodType INNER 0x40 = 0x%x <<<\n", u8Data);
3890 //if ((u8Data & 0x01) == 0)
3891 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//E_DMD_S2_SYSTEM_TYPE 0: S2 ; 1 :S
3892 if(!u8Data) //S2
3893 {
3894 *pDemodType = DMD_SAT_DVBS2;
3895 DBG_INTERN_DVBS(printf("[dvbs]DemodType=DVBS2\n"));
3896 }
3897 else //S
3898 {
3899 *pDemodType = DMD_SAT_DVBS;
3900 DBG_INTERN_DVBS(printf("[dvbs]DemodType=DVBS\n"));
3901 }
3902 return status;
3903 }
3904 /****************************************************************************
3905 Subject: To get the current CodeRate at the DVB-S Demod
3906 Function: INTERN_DVBS_GetCurrentCodeRate
3907 Parmeter: pointer for return Code Rate type
3908
3909 Return: TRUE
3910 FALSE
3911 Remark:
3912 *****************************************************************************/
INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE * pCodeRate)3913 MS_BOOL INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE *pCodeRate)
3914 {
3915 MS_U8 u8Data = 0;//, u8_gCodeRate = 0;
3916 MS_BOOL status = true;
3917
3918 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate\n"));
3919 //DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3920 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);
3921 //status &= INTERN_DVBS_GetCurrentDemodType(&pDemodType);
3922 if(!u8Data)
3923 //if((MS_U8)pDemodType == (MS_U8)DMD_SAT_DVBS2 ) //S2
3924 {
3925 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
3926 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
3927 //u8_gCodeRate = (u8Data & 0x3C);
3928 //_u8_DVBS2_CurrentCodeRate = 0;
3929 switch (u8Data)
3930 //switch (u8_gCodeRate)
3931 {
3932 case 0x03:
3933 *pCodeRate = DMD_CONV_CODE_RATE_1_2;
3934 _u8_DVBS2_CurrentCodeRate = 5;//0;
3935 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=1_2\n"));
3936 break;
3937 case 0x01:
3938 *pCodeRate = DMD_CONV_CODE_RATE_1_3;
3939 _u8_DVBS2_CurrentCodeRate = 6;//1;
3940 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=1_3\n"));
3941 break;
3942 case 0x05:
3943 *pCodeRate = DMD_CONV_CODE_RATE_2_3;
3944 _u8_DVBS2_CurrentCodeRate = 7;//2;
3945 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=2_3\n"));
3946 break;
3947 case 0x00:
3948 *pCodeRate = DMD_CONV_CODE_RATE_1_4;
3949 _u8_DVBS2_CurrentCodeRate = 8;//3;
3950 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=1_4\n"));
3951 break;
3952 case 0x06:
3953 *pCodeRate = DMD_CONV_CODE_RATE_3_4;
3954 _u8_DVBS2_CurrentCodeRate = 9;//4;
3955 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=3_4\n"));
3956 break;
3957 case 0x02:
3958 *pCodeRate = DMD_CONV_CODE_RATE_2_5;
3959 _u8_DVBS2_CurrentCodeRate = 10;//5;
3960 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=2_5\n"));
3961 break;
3962 case 0x04:
3963 *pCodeRate = DMD_CONV_CODE_RATE_3_5;
3964 _u8_DVBS2_CurrentCodeRate = 11;//6;
3965 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=3_5\n"));
3966 break;
3967 case 0x07:
3968 *pCodeRate = DMD_CONV_CODE_RATE_4_5;
3969 _u8_DVBS2_CurrentCodeRate = 12;//7;
3970 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=4_5\n"));
3971 break;
3972 case 0x08:
3973 *pCodeRate = DMD_CONV_CODE_RATE_5_6;
3974 _u8_DVBS2_CurrentCodeRate = 13;//8;
3975 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=5_6\n"));
3976 break;
3977 case 0x09:
3978 *pCodeRate = DMD_CONV_CODE_RATE_8_9;
3979 _u8_DVBS2_CurrentCodeRate = 14;//9;
3980 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=8_9\n"));
3981 break;
3982 case 0x0a:
3983 *pCodeRate = DMD_CONV_CODE_RATE_9_10;
3984 _u8_DVBS2_CurrentCodeRate = 15;//10;
3985 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=9_10\n"));
3986 break;
3987 default:
3988 *pCodeRate = DMD_CONV_CODE_RATE_9_10;
3989 _u8_DVBS2_CurrentCodeRate = 15;//10;
3990 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=DVBS2_Default\n"));
3991 }
3992 }
3993 else //S
3994 {
3995 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
3996 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE + 0x3A*2, &u8Data);
3997 //u8_gCodeRate = (u8Data & 0x70)>>4;
3998 switch (u8Data)
3999 //switch (u8_gCodeRate)
4000 {
4001 case 0x00:
4002 *pCodeRate = DMD_CONV_CODE_RATE_1_2;
4003 _u8_DVBS2_CurrentCodeRate = 0;
4004 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate=1_2\n"));
4005 break;
4006 case 0x01:
4007 *pCodeRate = DMD_CONV_CODE_RATE_2_3;
4008 _u8_DVBS2_CurrentCodeRate = 1;
4009 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate=2_3\n"));
4010 break;
4011 case 0x02:
4012 *pCodeRate = DMD_CONV_CODE_RATE_3_4;
4013 _u8_DVBS2_CurrentCodeRate = 2;
4014 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate=3_4\n"));
4015 break;
4016 case 0x03:
4017 *pCodeRate = DMD_CONV_CODE_RATE_5_6;
4018 _u8_DVBS2_CurrentCodeRate = 3;
4019 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate=5_6\n"));
4020 break;
4021 case 0x04:
4022 *pCodeRate = DMD_CONV_CODE_RATE_7_8;
4023 _u8_DVBS2_CurrentCodeRate = 4;
4024 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate=7_8\n"));
4025 break;
4026 default:
4027 *pCodeRate = DMD_CONV_CODE_RATE_7_8;
4028 _u8_DVBS2_CurrentCodeRate = 4;
4029 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate=DVBS_Default\n"));
4030 }
4031 }
4032 return status;
4033 }
4034
4035 /****************************************************************************
4036 Subject: To get the current symbol rate at the DVB-S Demod
4037 Function: INTERN_DVBS_GetCurrentSymbolRate
4038 Parmeter: pointer pData for return Symbolrate
4039
4040 Return: TRUE
4041 FALSE
4042 Remark:
4043 *****************************************************************************/
INTERN_DVBS_GetCurrentSymbolRate(MS_U32 * u32SymbolRate)4044 MS_BOOL INTERN_DVBS_GetCurrentSymbolRate(MS_U32 *u32SymbolRate)
4045 {
4046 MS_U8 tmp = 0;
4047 MS_U16 u16SymbolRateTmp = 0;
4048
4049 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &tmp);
4050 u16SymbolRateTmp = tmp;
4051 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &tmp);
4052 u16SymbolRateTmp = (u16SymbolRateTmp<<8)|tmp;
4053
4054 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &tmp);
4055 *u32SymbolRate = (tmp<<16)|u16SymbolRateTmp;
4056
4057 DBG_INTERN_DVBS_LOCK(printf("[dvbs]Symbol Rate=%d\n",*u32SymbolRate));
4058
4059 return TRUE;
4060 }
4061
INTERN_DVBS_Version(MS_U16 * ver)4062 MS_BOOL INTERN_DVBS_Version(MS_U16 *ver)
4063 {
4064 MS_U8 status = true;
4065 MS_U8 tmp = 0;
4066 MS_U16 u16_INTERN_DVBS_Version;
4067
4068 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FW_VERSION_L, &tmp);
4069 u16_INTERN_DVBS_Version = tmp;
4070 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FW_VERSION_H, &tmp);
4071 u16_INTERN_DVBS_Version = u16_INTERN_DVBS_Version<<8|tmp;
4072 *ver = u16_INTERN_DVBS_Version;
4073
4074 return status;
4075 }
4076
INTERN_DVBS_Show_Demod_Version(void)4077 MS_BOOL INTERN_DVBS_Show_Demod_Version(void)
4078 {
4079 MS_BOOL status = true;
4080 MS_U16 u16_INTERN_DVBS_Version;
4081
4082 status &= INTERN_DVBS_Version(&u16_INTERN_DVBS_Version);
4083
4084 printf(">>> [Macan]Demod FW Version: R%d.%d <<<\n", ((u16_INTERN_DVBS_Version>>8)&0x00FF),(u16_INTERN_DVBS_Version&0x00FF));
4085
4086
4087 return status;
4088 }
4089
INTERN_DVBS_GetRollOff(MS_U8 * pRollOff)4090 MS_BOOL INTERN_DVBS_GetRollOff(MS_U8 *pRollOff)
4091 {
4092 MS_BOOL status=TRUE;
4093 MS_U8 u8Data=0;
4094
4095 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x1E, &u8Data);//#define INNER_TR_ROLLOFF (_REG_INNER(0x0F)+0)
4096 if ((u8Data&0x03)==0x00)
4097 *pRollOff = 0; //Rolloff 0.35
4098 else if (((u8Data&0x03)==0x01) || ((u8Data&0x03)==0x03))
4099 *pRollOff = 1; //Rolloff 0.25
4100 else
4101 *pRollOff = 2; //Rolloff 0.20
4102 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetRollOff:%d\n", *pRollOff));
4103
4104 return status;
4105 }
4106
INTERN_DVBS_Get_DTV_SQuality_BAR(MS_U8 * u8_gSQValue)4107 MS_BOOL INTERN_DVBS_Get_DTV_SQuality_BAR(MS_U8 *u8_gSQValue)
4108 {
4109 MS_BOOL status=TRUE;
4110 MS_U16 u16_gSignalQualityValue;
4111 MS_U16 _u16_packetError;
4112
4113 status = INTERN_DVBS_GetSignalQuality(&u16_gSignalQualityValue,0,0,0);
4114 status = INTERN_DVBS_GetPacketErr(&_u16_packetError);
4115
4116 if ((_u16_packetError >= 1) && (u16_gSignalQualityValue > 30)) //Average
4117 {
4118 *u8_gSQValue = 30;
4119 }
4120 else if ((_u16_packetError >= 1) && (u16_gSignalQualityValue > 10)) //Poor
4121 {
4122 *u8_gSQValue = 10;
4123 }
4124
4125 return status;
4126 }
4127
4128 /****************************************************************************
4129 ** Function: Read demod related information
4130 ** Polling after demod lock
4131 ** GAIN & DCR /Fine CFO & PR & IIS & IQB & SNR /PacketErr & BER
4132 ****************************************************************************/
INTERN_DVBS_Show_AGC_Info(void)4133 MS_BOOL INTERN_DVBS_Show_AGC_Info(void)
4134 {
4135 MS_BOOL status = TRUE;
4136
4137 //MS_U8 tmp = 0;
4138 //MS_U8 agc_k = 0,d0_k = 0,d0_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0,d3_k = 0,d3_ref = 0;
4139 //MS_U16 if_agc_gain = 0,d0_gain = 0,d1_gain = 0,d2_gain = 0,d3_gain = 0, agc_ref = 0;
4140 //MS_U16 if_agc_err = 0;
4141 #if 0
4142 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x08*2 + 1,&agc_k);
4143 agc_k = ((agc_k & 0xF0)>>4);
4144 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x09*2 + 1,&tmp);
4145 agc_ref = tmp;
4146 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0xE8,&tmp);
4147 //agc_ref = (agc_ref<<8)|tmp;
4148 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x38*2,&d0_k);
4149 d0_k = ((d0_k & 0xF0)>>4);
4150 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x38*2 + 1,&d0_ref);
4151 d0_ref = (d0_ref & 0xFF);
4152 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x58*2,&d1_k);
4153 d1_k = (d1_k & 0xF0)>>4;
4154 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x58*2 + 1,&d1_ref);
4155 d1_ref = (d1_ref & 0xFF);
4156 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5E*2,&d2_k);
4157 d2_k = ((d2_k & 0xF0)>>4);
4158 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x5E*2 + 1,&d2_ref);
4159 d2_ref = (d2_ref & 0xFF);
4160 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6A*2,&d3_k);
4161 d3_k = ((d3_k & 0xF0)>>4);
4162 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref);
4163 d3_ref = (d3_ref & 0xFF);
4164
4165
4166 // select IF gain to read
4167 //Debug Select
4168 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x13*2, &tmp);
4169 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x13*2, (tmp&0xF0)|0x03);
4170 //IF_AGC_GAIN
4171 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2 + 1, &tmp);
4172 if_agc_gain = tmp;
4173 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2, &tmp);
4174 if_agc_gain = (if_agc_gain<<8)|tmp;
4175
4176
4177 // select d0 gain to read.
4178 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x74*2 + 1, &tmp);
4179 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x74*2 + 1, (tmp&0xF0)|0x03);
4180 //DAGC0_GAIN
4181 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3D*2, &tmp);
4182 d0_gain = tmp;
4183 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3C*2 + 1, &tmp);
4184 d0_gain = (d0_gain<<8)|tmp;
4185 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3C*2, &tmp);
4186 d0_gain = (d0_gain<<4)|(tmp>>4);
4187
4188
4189 // select d1 gain to read.
4190 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x8C, &tmp);
4191 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x8C, (tmp&0xF0)|0x00);
4192 //DAGC1_GAIN
4193 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5C*2 + 1, &tmp);
4194 d1_gain = tmp;
4195 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5C*2, &tmp);
4196 d1_gain = (d1_gain<<8)|tmp;
4197
4198
4199 // select d2 gain to read.
4200 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x06, &tmp);
4201 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT_REG_BASE + 0x06, (tmp&0xF0)|0x03);
4202 //DAGC2_GAIN
4203 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x62*2 + 1, &tmp);
4204 d2_gain = tmp;
4205 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x62*2, &tmp);
4206 d2_gain = (d2_gain<<8)|tmp;
4207
4208
4209 // select d3 gain to read.
4210 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp);
4211 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03);
4212 //DAGC3_GAIN
4213 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6F*2, &tmp);
4214 d3_gain = tmp;
4215 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6E*2 + 1, &tmp);
4216 d3_gain = (d3_gain<<8)|tmp;
4217 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6E*2, &tmp);
4218 d3_gain = (d3_gain<<4)|(tmp>>4);
4219
4220
4221 // select IF gain err to read
4222 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x13*2, &tmp);
4223 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x13*2, (tmp&0xF0)|0x00);
4224
4225 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2 + 1, &tmp);
4226 if_agc_err = tmp;
4227 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2, &tmp);
4228 if_agc_err = (if_agc_err<<8)|tmp;
4229
4230
4231 DBG_INTERN_DVBS(printf("[dvbs]agc_k=0x%x, agc_ref=0x%x, d0_k=0x%x, d0_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x, d3_k=0x%x, d3_ref=0x%x\n",
4232 agc_k, agc_ref, d0_k, d0_ref, d1_k, d1_ref, d2_k, d2_ref, d3_k, d3_ref));
4233
4234 DBG_INTERN_DVBS(printf("[dvbs]agc_g=0x%x, d0_g=0x%x, d1_g=0x%x, d2_g=0x%x, d3_g=0x%x, agc_err=0x%x\n", if_agc_gain, d0_gain, d1_gain, d2_gain, d3_gain, if_agc_err));
4235
4236 DBG_INTERN_DVBS(printf("[dvbs]agc_k=0x%x, agc_ref=0x%x, d0_k=0x%x, d0_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x, d3_k=0x%x, d3_ref=0x%x\n",
4237 agc_k, agc_ref, d0_k, d0_ref, d1_k, d1_ref, d2_k, d2_ref, d3_k, d3_ref));
4238
4239 DBG_INTERN_DVBS(printf("[dvbs]agc_g=0x%x, d0_g=0x%x, d1_g=0x%x, d2_g=0x%x, d3_g=0x%x, agc_err=0x%x\n", if_agc_gain, d0_gain, d1_gain, d2_gain, d3_gain, if_agc_err));
4240 #endif
4241 return status;
4242 }
4243
INTERN_DVBS_info(void)4244 void INTERN_DVBS_info(void)
4245 {
4246 //status &= INTERN_DVBS_Show_Demod_Version();
4247 //status &= INTERN_DVBS_Demod_Get_Debug_Info_get_once();
4248 //status &= INTERN_DVBS_Demod_Get_Debug_Info_polling();
4249 }
4250
INTERN_DVBS_Demod_Get_Debug_Info_get_once(void)4251 MS_BOOL INTERN_DVBS_Demod_Get_Debug_Info_get_once(void)
4252 {
4253 MS_BOOL status = TRUE;
4254 //MS_U8 u8Data = 0;
4255 //MS_U16 u16Data = 0, u16Address = 0;
4256 //float psd_smooth_factor;
4257 //float srd_right_bottom_value, srd_right_top_value, srd_left_bottom_value, srd_left_top_value;
4258 //MS_U16 u32temp5;
4259 //MS_U16 srd_left, srd_right, srd_left_top, srd_left_bottom, srd_right_top, srd_right_bottom;
4260
4261 #if 0
4262 //Lock Flag
4263 printf("========================================================================\n");
4264 printf("Debug Message Flag [Lock Flag]==========================================\n");
4265
4266 u16Address = (AGC_LOCK>>16)&0xffff;
4267 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4268 if ((u16Data&(AGC_LOCK&0xffff))!=(AGC_LOCK&0xffff))
4269 printf("[DVBS]: AGC LOCK ======================: Fail. \n");
4270 else
4271 printf("[DVBS]: AGC LOCK ======================: OK. \n");
4272
4273 u16Address = (DAGC0_LOCK>>16)&0xffff;
4274 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4275 if ((u16Data&(DAGC0_LOCK&0xffff))!=(DAGC0_LOCK&0xffff))
4276 printf("[DVBS]: DAGC0 LOCK ====================: Fail. \n");
4277 else
4278 printf("[DVBS]: DAGC0 LOCK ====================: OK. \n");
4279
4280 u16Address = (DAGC1_LOCK>>16)&0xffff;
4281 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4282 if ((u16Data&(DAGC1_LOCK&0xffff))!=(DAGC1_LOCK&0xffff))
4283 printf("[DVBS]: DAGC1 LOCK ====================: Fail. \n");
4284 else
4285 printf("[DVBS]: DAGC1 LOCK ====================: OK. \n");
4286
4287 u16Address = (DAGC2_LOCK>>16)&0xffff;
4288 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4289 if ((u16Data&(DAGC2_LOCK&0xffff))!=(DAGC2_LOCK&0xffff))
4290 printf("[DVBS]: DAGC2 LOCK ====================: Fail. \n");
4291 else
4292 printf("[DVBS]: DAGC2 LOCK ====================: OK. \n");
4293
4294 u16Address = (DAGC3_LOCK>>16)&0xffff;
4295 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4296 if ((u16Data&(DAGC3_LOCK&0xffff))!=(DAGC3_LOCK&0xffff))
4297 printf("[DVBS]: DAGC3 LOCK ====================: Fail. \n");
4298 else
4299 printf("[DVBS]: DAGC3 LOCK ====================: OK. \n");
4300
4301 u16Address = (DCR_LOCK>>16)&0xffff;
4302 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4303 if ((u16Data&(DCR_LOCK&0xffff))!=(DCR_LOCK&0xffff))
4304 printf("[DVBS]: DCR LOCK ======================: Fail. \n");
4305 else
4306 printf("[DVBS]: DCR LOCK ======================: OK. \n");
4307 //Mark Coarse SRD
4308 //Mark Fine SRD
4309 /*
4310 u16Address = (CLOSE_COARSE_CFO_LOCK>>16)&0xffff;
4311 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4312 if ((u16Data&(CLOSE_COARSE_CFO_LOCK&0xffff))!=(CLOSE_COARSE_CFO_LOCK&0xffff))
4313 printf("[DVBS]: Close CFO =====================: Fail. \n");
4314 else
4315 printf("[DVBS]: Close CFO =====================: OK. \n");
4316 */
4317 u16Address = (TR_LOCK>>16)&0xffff;
4318 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4319 if ((u16Data&(TR_LOCK&0xffff))!=(TR_LOCK&0xffff))
4320 printf("[DVBS]: TR LOCK =======================: Fail. \n");
4321 else
4322 printf("[DVBS]: TR LOCK =======================: OK. \n");
4323
4324 u16Address = (FRAME_SYNC_ACQUIRE>>16)&0xffff;
4325 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4326 if ((u16Data&(FRAME_SYNC_ACQUIRE&0xffff))!=(FRAME_SYNC_ACQUIRE&0xffff))
4327 printf("[DVBS]: FS Acquire ====================: Fail. \n");
4328 else
4329 printf("[DVBS]: FS Acquire ====================: OK. \n");
4330
4331 u16Address = (PR_LOCK>>16)&0xffff;
4332 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4333 if ((u16Data&(PR_LOCK&0xffff))!=(PR_LOCK&0xffff))
4334 printf("[DVBS]: PR LOCK =======================: Fail. \n");
4335 else
4336 printf("[DVBS]: PR LOCK =======================: OK. \n");
4337
4338 u16Address = (EQ_LOCK>>16)&0xffff;
4339 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4340 if ((u16Data&(EQ_LOCK&0xffff))!=(EQ_LOCK&0xffff))
4341 printf("[DVBS]: EQ LOCK =======================: Fail. \n");
4342 else
4343 printf("[DVBS]: EQ LOCK =======================: OK. \n");
4344
4345 u16Address = (P_SYNC_LOCK>>16)&0xffff;
4346 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4347 if ((u16Data&0x0002)!=0x0002)
4348 printf("[DVBS]: P_sync ========================: Fail. \n");
4349 else
4350 printf("[DVBS]: P_sync ========================: OK. \n");
4351
4352 u16Address = (IN_SYNC_LOCK>>16)&0xffff;
4353 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4354 if ((u16Data&0x8000)!=0x8000)
4355 printf("[DVBS]: In_sync =======================: Fail. \n");
4356 else
4357 printf("[DVBS]: In_sync =======================: OK. \n");
4358 //---------------------------------------------------------
4359 //Lock Time
4360 printf("------------------------------------------------------------------------\n");
4361 printf("Debug Message [Lock Time]===============================================\n");
4362
4363 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_05, &u8Data);
4364 printf("[DVBS]: AGC Lock Time =================: %d\n",u8Data&0x00FF);
4365 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_06, &u8Data);
4366 printf("[DVBS]: DCR Lock Time =================: %d\n",u8Data&0x00FF);
4367 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_2, &u8Data);
4368 printf("[DVBS]: TR Lock Time ==================: %d\n",u8Data&0x00FF);
4369 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_3, &u8Data);
4370 printf("[DVBS]: FS Lock Time ==================: %d\n",u8Data&0x00FF);
4371 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_4, &u8Data);
4372 printf("[DVBS]: PR Lock Time ==================: %d\n",u8Data&0x00FF);
4373 //printf("[DVBS]: PLSC Lock Time ================: %d\n",(u16Data>>8)&0x00FF);//No used
4374 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_6, &u8Data);
4375 printf("[DVBS]: EQ Lock Time ==================: %d\n",u8Data&0x00FF);
4376 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_7, &u8Data);
4377 printf("[DVBS]: FEC Lock Time =================: %d\n",u8Data&0x00FF);
4378
4379 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_0, &u8Data);
4380 printf("[DVBS]: CSRD ==========================: %d\n",u8Data&0x00FF);
4381 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_1, &u8Data);
4382 printf("[DVBS]: FSRD ==========================: %d\n",u8Data&0x00FF);
4383 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_01, &u8Data);
4384 printf("[DVBS]: CCFO ==========================: %d\n",u8Data&0x00FF);
4385 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_02, &u8Data);
4386 printf("[DVBS]: FCFO ==========================: %d\n",u8Data&0x00FF);
4387 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);
4388 printf("[DVBS]: State =========================: %d\n",u8Data&0x00FF);
4389 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SUBSTATE_FLAG, &u8Data);
4390 printf("[DVBS]: SubState ======================: %d\n",u8Data&0x00FF);
4391
4392 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00H, &u8Data);
4393 u16Data = u8Data;
4394 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00L, &u8Data);
4395 u16Data = (u16Data<<8)|u8Data;
4396 printf("[DVBS]: DBG1: =========================: 0x%x\n",u16Data);
4397 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01H, &u8Data);
4398 u16Data = u8Data;
4399 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01L, &u8Data);
4400 u16Data = (u16Data<<8)|u8Data;
4401 printf("[DVBS]: DBG2: =========================: 0x%x\n",u16Data);
4402 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE02H, &u8Data);
4403 u16Data = u8Data;
4404 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE02L, &u8Data);
4405 u16Data = (u16Data<<8)|u8Data;
4406 printf("[DVBS]: DBG3: =========================: 0x%x\n",u16Data);
4407 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE03H, &u8Data);
4408 u16Data = u8Data;
4409 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE03L, &u8Data);
4410 u16Data = (u16Data<<8)|u8Data;
4411 printf("[DVBS]: DBG4: =========================: 0x%x\n",u16Data);
4412 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE04H, &u8Data);
4413 u16Data = u8Data;
4414 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE04L, &u8Data);
4415 u16Data = (u16Data<<8)|u8Data;
4416 printf("[DVBS]: DBG5: =========================: 0x%x\n",u16Data);
4417 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE05H, &u8Data);
4418 u16Data = u8Data;
4419 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE05L, &u8Data);
4420 u16Data = (u16Data<<8)|u8Data;
4421 printf("[DVBS]: DBG6: =========================: 0x%x\n",u16Data);
4422 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE06H, &u8Data);
4423 u16Data = u8Data;
4424 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE06L, &u8Data);
4425 u16Data = (u16Data<<8)|u8Data;
4426 printf("[DVBS]: EQ Sum: =======================: 0x%x\n",u16Data);
4427 //---------------------------------------------------------
4428 //FIQ Status
4429 printf("------------------------------------------------------------------------\n");
4430 printf("Debug Message [FIQ Status]==============================================\n");
4431 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00H, &u8Data);
4432 u16Data = u8Data;
4433 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00L, &u8Data);
4434 u16Data = (u16Data<<8)|u8Data;
4435
4436 if ((u16Data&0x0001)==0x0000)
4437 printf("[DVBS]: AGC Lock ======================: Fail. \n");
4438 else
4439 printf("[DVBS]: AGC Lock ======================: OK. \n");
4440
4441 if ((u16Data&0x0002)==0x0000)
4442 printf("[DVBS]: Hum Detect ====================: Fail. \n");
4443 else
4444 printf("[DVBS]: Hum Detect ====================: OK. \n");
4445
4446 if ((u16Data&0x0004)==0x0000)
4447 printf("[DVBS]: DCR Lock ======================: Fail. \n");
4448 else
4449 printf("[DVBS]: DCR Lock ======================: OK. \n");
4450
4451 if ((u16Data&0x0008)==0x0000)
4452 printf("[DVBS]: IIS Detect ====================: Fail. \n");
4453 else
4454 printf("[DVBS]: IIS Detect ====================: OK. \n");
4455
4456 if ((u16Data&0x0010)==0x0000)
4457 printf("[DVBS]: DAGC0 Lock ====================: Fail. \n");
4458 else
4459 printf("[DVBS]: DAGC0 Lock ====================: OK. \n");
4460
4461 if ((u16Data&0x0020)==0x0000)
4462 printf("[DVBS]: DAGC1 Lock ====================: Fail. \n");
4463 else
4464 printf("[DVBS]: DAGC1 Lock ====================: OK. \n");
4465
4466 if ((u16Data&0x0040)==0x0000)
4467 printf("[DVBS]: DAGC2 Lock ====================: Fail. \n");
4468 else
4469 printf("[DVBS]: DAGC2 Lock ====================: OK. \n");
4470
4471 if ((u16Data&0x0080)==0x0000)
4472 printf("[DVBS]: CCI Detect ====================: Fail. \n");
4473 else
4474 printf("[DVBS]: CCI Detect ====================: OK. \n");
4475
4476 if ((u16Data&0x0100)==0x0000)
4477 printf("[DVBS]: SRD Coarse Done ===============: Fail. \n");
4478 else
4479 printf("[DVBS]: SRD Coarse Done ===============: OK. \n");
4480
4481 if ((u16Data&0x0200)==0x0000)
4482 printf("[DVBS]: SRD Fine Done =================: Fail. \n");
4483 else
4484 printf("[DVBS]: SRD Fine Done =================: OK. \n");
4485
4486 if ((u16Data&0x0400)==0x0000)
4487 printf("[DVBS]: EQ Lock =======================: Fail. \n");
4488 else
4489 printf("[DVBS]: EQ Lock =======================: OK. \n");
4490
4491 if ((u16Data&0x0800)==0x0000)
4492 printf("[DVBS]: FineFE Done ===================: Fail. \n");
4493 else
4494 printf("[DVBS]: FineFE Done ===================: OK. \n");
4495
4496 if ((u16Data&0x1000)==0x0000)
4497 printf("[DVBS]: PR Lock =======================: Fail. \n");
4498 else
4499 printf("[DVBS]: PR Lock =======================: OK. \n");
4500
4501 if ((u16Data&0x2000)==0x0000)
4502 printf("[DVBS]: Reserved Frame ================: Fail. \n");
4503 else
4504 printf("[DVBS]: Reserved Frame ================: OK. \n");
4505
4506 if ((u16Data&0x4000)==0x0000)
4507 printf("[DVBS]: Dummy Frame ===================: Fail. \n");
4508 else
4509 printf("[DVBS]: Dummy Frame ===================: OK. \n");
4510
4511 if ((u16Data&0x8000)==0x0000)
4512 printf("[DVBS]: PLSC Done =====================: Fail. \n");
4513 else
4514 printf("[DVBS]: PLSC Done =====================: OK. \n");
4515
4516 printf("------------------------------------------------------------------------\n");
4517 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01H, &u8Data);
4518 u16Data = u8Data;
4519 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01L, &u8Data);
4520 u16Data = (u16Data<<8)|u8Data;
4521 if ((u16Data&0x0001)==0x0000)
4522 printf("[DVBS]: FS Get Info From Len ==========: Fail. \n");
4523 else
4524 printf("[DVBS]: FS Get Info From Len ==========: OK. \n");
4525
4526 if ((u16Data&0x0002)==0x0000)
4527 printf("[DVBS]: IQ Swap Detect ================: Fail. \n");
4528 else
4529 printf("[DVBS]: IQ Swap Detect ================: OK. \n");
4530
4531 if ((u16Data&0x0004)==0x0000)
4532 printf("[DVBS]: FS Acquisition ================: Fail. \n");
4533 else
4534 printf("[DVBS]: FS Acquisition ================: OK. \n");
4535
4536 if ((u16Data&0x0008)==0x0000)
4537 printf("[DVBS]: TR Lock =======================: Fail. \n");
4538 else
4539 printf("[DVBS]: TR Lock =======================: OK. \n");
4540
4541 if ((u16Data&0x0010)==0x0000)
4542 printf("[DVBS]: CLCFE Lock ====================: Fail. \n");
4543 else
4544 printf("[DVBS]: CLCFE Lock ====================: OK. \n");
4545
4546 if ((u16Data&0x0020)==0x0000)
4547 printf("[DVBS]: OLCFE Lock ====================: Fail. \n");
4548 else
4549 printf("[DVBS]: OLCFE Lock ====================: OK. \n");
4550
4551 if ((u16Data&0x0040)==0x0000)
4552 printf("[DVBS]: Fsync Found ===================: Fail. \n");
4553 else
4554 printf("[DVBS]: Fsync Found ===================: OK. \n");
4555
4556 if ((u16Data&0x0080)==0x0000)
4557 printf("[DVBS]: Fsync Lock ====================: Fail. \n");
4558 else
4559 printf("[DVBS]: Fsync Lock ====================: OK. \n");
4560
4561 if ((u16Data&0x0100)==0x0000)
4562 printf("[DVBS]: Fsync Fail Search =============: Fail. \n");
4563 else
4564 printf("[DVBS]: Fsync Fail Search =============: OK. \n");
4565
4566 if ((u16Data&0x0200)==0x0000)
4567 printf("[DVBS]: Fsync Fail Lock ===============: Fail. \n");
4568 else
4569 printf("[DVBS]: Fsync Fail Lock ===============: OK. \n");
4570
4571 if ((u16Data&0x0400)==0x0000)
4572 printf("[DVBS]: False Alarm ===================: Fail. \n");
4573 else
4574 printf("[DVBS]: False Alarm ===================: OK. \n");
4575
4576 if ((u16Data&0x0800)==0x0000)
4577 printf("[DVBS]: Viterbi In Sync ===============: Fail. \n");
4578 else
4579 printf("[DVBS]: Viterbi In Sync ===============: OK. \n");
4580
4581 if ((u16Data&0x1000)==0x0000)
4582 printf("[DVBS]: Uncrt Over ====================: Fail. \n");
4583 else
4584 printf("[DVBS]: Uncrt Over ====================: OK. \n");
4585
4586 if ((u16Data&0x2000)==0x0000)
4587 printf("[DVBS]: CLK Cnt Over ==================: Fail. \n");
4588 else
4589 printf("[DVBS]: CLK Cnt Over ==================: OK. \n");
4590
4591 //if ((u16Data&0x4000)==0x0000)
4592 // printf("[DVBS]: Data In Ready FIFO ============: Fail. \n");
4593 //else
4594 // printf("[DVBS]: Data In Ready FIFO ============: OK. \n");
4595
4596 //if ((u16Data&0x8000)==0x0000)
4597 // printf("[DVBS]: IIR Buff Busy =================: Fail. \n");
4598 //else
4599 // printf("[DVBS]: IIR Buff Busy =================: OK. \n");
4600
4601 /*
4602 printf("------------------------------------------------------------------------\n");
4603 u16Address = 0x0B64;
4604 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address+1, &u8Data);
4605 u16Data = u8Data;
4606 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address , &u8Data);
4607 u16Data = (u16Data<<8)|u8Data;
4608 if ((u16Data&0x0001)==0x0000)
4609 printf("[DVBS]: IIR Busy LDPC =================: Fail. \n");
4610 else
4611 printf("[DVBS]: IIR Busy LDPC =================: OK. \n");
4612
4613 if ((u16Data&0x0002)==0x0000)
4614 printf("[DVBS]: BCH Busy ======================: Fail. \n");
4615 else
4616 printf("[DVBS]: BCH Busy ======================: OK. \n");
4617
4618 if ((u16Data&0x0004)==0x0000)
4619 printf("[DVBS]: Oppro Ready Out ===============: Fail. \n");
4620 else
4621 printf("[DVBS]: Oppro Ready Out ===============: OK. \n");
4622
4623 if ((u16Data&0x0008)==0x0000)
4624 printf("[DVBS]: LDPC Win ======================: Fail. \n");
4625 else
4626 printf("[DVBS]: LDPC Win ======================: OK. \n");
4627
4628 if ((u16Data&0x0010)==0x0000)
4629 printf("[DVBS]: LDPC Error ====================: Fail. \n");
4630 else
4631 printf("[DVBS]: LDPC Error ====================: OK. \n");
4632
4633 if ((u16Data&0x0020)==0x0000)
4634 printf("[DVBS]: Out BCH Error =================: Fail. \n");
4635 else
4636 printf("[DVBS]: Out BCH Error =================: OK. \n");
4637
4638 if ((u16Data&0x0040)==0x0000)
4639 printf("[DVBS]: Descr BCH FEC Num Error =======: Fail. \n");
4640 else
4641 printf("[DVBS]: Descr BCH FEC Num Error =======: OK. \n");
4642
4643 if ((u16Data&0x0080)==0x0000)
4644 printf("[DVBS]: Descr BCH Data Num Error ======: Fail. \n");
4645 else
4646 printf("[DVBS]: Descr BCH Data Num Error ======: OK. \n");
4647
4648 if ((u16Data&0x0100)==0x0000)
4649 printf("[DVBS]: Packet Error Out ==============: Fail. \n");
4650 else
4651 printf("[DVBS]: Packet Error Out ==============: OK. \n");
4652
4653 if ((u16Data&0x0200)==0x0000)
4654 printf("[DVBS]: BBH CRC Error =================: Fail. \n");
4655 else
4656 printf("[DVBS]: BBH CRC Error =================: OK. \n");
4657
4658 if ((u16Data&0x0400)==0x0000)
4659 printf("[DVBS]: BBH Decode Done ===============: Fail. \n");
4660 else
4661 printf("[DVBS]: BBH Decode Done ===============: OK. \n");
4662
4663 if ((u16Data&0x0800)==0x0000)
4664 printf("[DVBS]: ISRC Calculate Done ===========: Fail. \n");
4665 else
4666 printf("[DVBS]: ISRC Calculate Done ===========: OK. \n");
4667
4668 if ((u16Data&0x1000)==0x0000)
4669 printf("[DVBS]: Syncd Check Error =============: Fail. \n");
4670 else
4671 printf("[DVBS]: Syncd Check Error =============: OK. \n");
4672
4673 //if ((u16Data&0x2000)==0x0000)
4674 // printf("[DVBS]: Syncd Check Error======: Fail. \n");
4675 //else
4676 // printf("[DVBS]: Syncd Check Error======: OK. \n");
4677
4678 if ((u16Data&0x4000)==0x0000)
4679 printf("[DVBS]: Demap Init ====================: Fail. \n");
4680 else
4681 printf("[DVBS]: Demap Init ====================: OK. \n");
4682 */
4683 //Spectrum Information
4684 printf("------------------------------------------------------------------------\n");
4685
4686 u16Address = 0x2836;
4687 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4688 psd_smooth_factor=(u16Data>>8)&0x7F;
4689
4690 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
4691 u16Data = u8Data;
4692 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
4693 u16Data = (u16Data<<8)|u8Data;
4694 u32temp5=u16Data;
4695 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13H, &u8Data);
4696 u16Data = u8Data;
4697 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
4698 u16Data = (u16Data<<8)|u8Data;
4699 u32temp5|=(u16Data<<16);
4700 if (psd_smooth_factor!=0)
4701 srd_left_top_value=(float)u32temp5/256.0/psd_smooth_factor;
4702 else
4703 srd_left_top_value=0;
4704
4705 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
4706 u16Data = u8Data;
4707 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
4708 u16Data = (u16Data<<8)|u8Data;
4709 u32temp5=u16Data;
4710 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
4711 u16Data = u8Data;
4712 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
4713 u16Data = (u16Data<<8)|u8Data;
4714 u32temp5|=(u16Data<<16);
4715 if (psd_smooth_factor!=0)
4716 srd_left_bottom_value=(float)u32temp5/256.0/psd_smooth_factor;
4717 else
4718 srd_left_bottom_value=0;
4719
4720 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
4721 u16Data = u8Data;
4722 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
4723 u16Data = (u16Data<<8)|u8Data;
4724 u32temp5=u16Data;
4725 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE17H, &u8Data);
4726 u16Data = u8Data;
4727 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE17L, &u8Data);
4728 u16Data = (u16Data<<8)|u8Data;
4729 u32temp5|=(u16Data<<16);
4730 if (psd_smooth_factor!=0)
4731 srd_right_top_value=(float)u32temp5/256.0/psd_smooth_factor;
4732 else
4733 srd_right_top_value=0;
4734
4735 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18H, &u8Data);
4736 u16Data = u8Data;
4737 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18L, &u8Data);
4738 u16Data = (u16Data<<8)|u8Data;
4739 u32temp5=u16Data;
4740 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19H, &u8Data);
4741 u16Data = u8Data;
4742 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19L, &u8Data);
4743 u16Data = (u16Data<<8)|u8Data;
4744 u32temp5|=(u16Data<<16);
4745 if (psd_smooth_factor!=0)
4746 srd_right_bottom_value=(float)u32temp5/256.0/psd_smooth_factor;
4747 else
4748 srd_right_bottom_value=0;
4749
4750 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1AH, &u8Data);
4751 u16Data = u8Data;
4752 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1AL, &u8Data);
4753 u16Data = (u16Data<<8)|u8Data;
4754 srd_left=u16Data;
4755 printf("[DVBS]: FFT Left ======================: %d, %f\n", srd_left, srd_left_top_value - srd_left_bottom_value);
4756 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1BH, &u8Data);
4757 u16Data = u8Data;
4758 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1BL, &u8Data);
4759 u16Data = (u16Data<<8)|u8Data;
4760 srd_right=u16Data;
4761 printf("[DVBS]: FFT Right =====================: %d, %f\n", srd_right, srd_right_top_value - srd_right_bottom_value);
4762 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1CH, &u8Data);
4763 u16Data = u8Data;
4764 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1CL, &u8Data);
4765 u16Data = (u16Data<<8)|u8Data;
4766 srd_left_top=u16Data;
4767 printf("[DVBS]: FFT Left Top ==================: %d, %f\n", srd_left_top, srd_left_top_value);
4768 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1DH, &u8Data);
4769 u16Data = u8Data;
4770 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1DL, &u8Data);
4771 u16Data = (u16Data<<8)|u8Data;
4772 srd_left_bottom=u16Data;
4773 printf("[DVBS]: FFT Left Bottom ===============: %d, %f\n", srd_left_bottom, srd_left_bottom_value);
4774 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1EH, &u8Data);
4775 u16Data = u8Data;
4776 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1EL, &u8Data);
4777 u16Data = (u16Data<<8)|u8Data;
4778 srd_right_top=u16Data;
4779 printf("[DVBS]: FFT Right Top =================: %d, %f\n", srd_right_top, srd_right_top_value);
4780 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1FH, &u8Data);
4781 u16Data = u8Data;
4782 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1FL, &u8Data);
4783 u16Data = (u16Data<<8)|u8Data;
4784 srd_right_bottom=u16Data;
4785 printf("[DVBS]: FFT Right Bottom ==============: %d, %f\n", srd_right_bottom, srd_right_bottom_value);
4786
4787 printf("-----------------------------------------\n");
4788 printf("[DVBS]: Left-Bottom ===================: %d\n", srd_left-srd_left_bottom);
4789 printf("[DVBS]: Left-Top ======================: %d\n", srd_left_top - srd_left);
4790 printf("[DVBS]: Right-Top =====================: %d\n", srd_right - srd_right_top);
4791 printf("[DVBS]: Right-Bottom ==================: %d\n", srd_right_bottom - srd_right);
4792
4793 if (psd_smooth_factor!=0)
4794 {
4795 if ((srd_left_top-srd_left_bottom)!=0)
4796 printf("[DVBS]: Left Slope ====================: %f\n", (srd_left_top_value - srd_left_bottom_value)/(srd_left_top-srd_left_bottom));
4797 else
4798 printf("[DVBS]: Left Slope ====================: %f\n", 0.000000);
4799
4800 if((srd_right_bottom - srd_right_top)!=0)
4801 printf("[DVBS]: Right Slope ===================: %f\n", (srd_right_top_value - srd_right_bottom_value)/(srd_right_bottom - srd_right_top));
4802 else
4803 printf("[DVBS]: Right Slope ===================: %f\n", 0.000000);
4804
4805 if (((srd_right_top_value - srd_right_bottom_value)!=0)&&((srd_right_bottom - srd_right_top))!=0)
4806 printf("[DVBS]: Slope Ratio ===================: %f\n", ((srd_left_top_value - srd_left_bottom_value)/(srd_left_top-srd_left_bottom))/((srd_right_top_value - srd_right_bottom_value)/(srd_right_bottom - srd_right_top)));
4807 else
4808 printf("[DVBS]: Slope Ratio ===================: %f\n", 0.000000);
4809 }
4810 else
4811 {
4812 printf("[DVBS]: Left Slope ======================: %d\n", 0);
4813 printf("[DVBS]: Right Slope =====================: %d\n", 0);
4814 printf("[DVBS]: Slope Ratio =====================: %d\n", 0);
4815 }
4816 #endif
4817 return status;
4818 }
4819
INTERN_DVBS_Demod_Get_Debug_Info_polling(void)4820 MS_BOOL INTERN_DVBS_Demod_Get_Debug_Info_polling(void)
4821 {
4822 MS_BOOL bRet = FALSE;
4823 #if 0
4824 MS_U8 u8Data = 0;
4825 MS_U16 u16Data = 0;
4826 MS_U16 u16Address = 0;
4827 MS_U32 u32DebugInfo_Fb = 0; //Fb, SymbolRate
4828 MS_U32 u32DebugInfo_Fs = 96000; //Fs, 96000k
4829 float AGC_IF_Gain;
4830 float DAGC0_Gain, DAGC1_Gain, DAGC2_Gain, DAGC3_Gain, DAGC0_Peak_Mean, DAGC1_Peak_Mean, DAGC2_Peak_Mean, DAGC3_Peak_Mean;
4831 short AGC_Err, DAGC0_Err, DAGC1_Err, DAGC2_Err, DAGC3_Err;
4832 float DCR_Offset_I, DCR_Offset_Q;
4833 float FineCFO_loop_input_value, FineCFO_loop_out_value;
4834 double FineCFO_loop_ki_value, TR_loop_ki;
4835 float PR_in_value, PR_out_value, PR_loop_ki, PR_loopback_ki;
4836 float IQB_Phase, IQB_Gain;
4837 MS_U16 IIS_cnt, ConvegenceLen;
4838 float Linear_SNR_dd, SNR_dd_dB, Linear_SNR_da, SNR_da_dB, SNR_nda_dB, Linear_SNR;
4839 float Packet_Err, BER;
4840 float TR_Indicator_ff, TR_SFO_Converge, Fs_value, Fb_value;
4841 float TR_Loop_Output, TR_Loop_Ki, TR_loop_input, TR_tmp0, TR_tmp1, TR_tmp2;
4842 float Eq_variance_da, Eq_variance_dd;
4843 float ndasnr_ratio, ndasnr_a, ndasnr_ab;
4844 MS_U16 BitErr, BitErrPeriod;
4845 MS_BOOL BEROver;
4846
4847 //Fb
4848 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
4849 //bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
4850 if((u8Data&0x02)==0x00) //Manual Tune
4851 {
4852 u32DebugInfo_Fb = 0x0;//_u32CurrentSR;
4853 }
4854 else //Blind Scan
4855 {
4856 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
4857 u16Data = u8Data;
4858 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
4859 u16Data = (u16Data<<8)|u8Data;
4860 u32DebugInfo_Fb = u16Data;
4861 }
4862 printf("++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
4863 printf("Fs ====================================: %lu [kHz]\n",u32DebugInfo_Fs);
4864 printf("Fb ====================================: %lu [kHz]\n",u32DebugInfo_Fb);
4865 //---------------------------------------------------------
4866 //Page1-GAIN & DCR
4867 //---------------------------------------------------------
4868 //GAIN
4869 printf("\n");
4870 printf("========================================================================\n");
4871 printf("Debug Message [GAIN & DCR]==============================================\n");
4872
4873 //Debug select
4874 u16Address = (DEBUG_SEL_IF_AGC_GAIN>>16)&0xffff;
4875 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4876 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_IF_AGC_GAIN)&0xffff);
4877 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4878
4879 //Freeze and dump
4880 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4881 //AGC_IF_GAIN
4882 u16Address = (DEBUG_OUT_AGC)&0xffff;
4883 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4884 AGC_IF_Gain=u16Data;
4885 //Unfreeze
4886 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4887
4888 AGC_IF_Gain=AGC_IF_Gain/0x8000; //(16, 15)
4889 printf("[DVBS]: AGC_IF_Gain ===================: %f\n", AGC_IF_Gain);
4890 //---------------------------------------------------------
4891 //Debug select
4892 u16Address = (DEBUG_SEL_DAGC0_GAIN>>16)&0xffff;
4893 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4894 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_GAIN)&0xffff);
4895 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4896
4897 //Freeze and dump
4898 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4899 //DAGC0_GAIN
4900 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
4901 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4902 u16Data = (u16Data>>4);
4903 DAGC0_Gain=(u16Data&0x0fff);
4904 //Unfreeze
4905 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4906 //---------------------------------------------------------
4907 //Debug select
4908 u16Address = (DEBUG_SEL_DAGC1_GAIN>>16)&0xffff;
4909 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4910 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_GAIN)&0xffff);
4911 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4912
4913 //Freeze and dump
4914 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4915 //DAGC1_GAIN
4916 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
4917 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4918 DAGC1_Gain=(u16Data&0x07ff);
4919 //Unfreeze
4920 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4921 //---------------------------------------------------------
4922 //Debug select
4923 u16Address = (DEBUG_SEL_DAGC2_GAIN>>16)&0xffff;
4924 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4925 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_GAIN)&0xffff);
4926 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4927
4928 //Freeze and dump
4929 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4930 //DAGC2_GAIN
4931 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
4932 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4933 DAGC2_Gain=(u16Data&0x0fff);
4934 //Unfreeze
4935 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4936 //---------------------------------------------------------
4937 //Debug select
4938 u16Address = (DEBUG_SEL_DAGC3_GAIN>>16)&0xffff;
4939 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4940 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_GAIN)&0xffff);
4941 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4942
4943 //Freeze and dump
4944 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4945 //DAGC3_GAIN
4946 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
4947 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4948 u16Data = (u16Data>>4);
4949 DAGC3_Gain=(u16Data&0x0fff);
4950 //Unfreeze
4951 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4952 //---------------------------------------------------------
4953
4954 DAGC0_Gain=DAGC0_Gain/0x200; //<12,9>
4955 DAGC1_Gain=DAGC1_Gain/0x200; //<11,9>
4956 DAGC2_Gain=DAGC2_Gain/0x200; //<12,9>
4957 DAGC3_Gain=DAGC3_Gain/0x200; //<12,9>
4958 printf("[DVBS]: DAGC0_Gain ====================: %f\n", DAGC0_Gain);
4959 printf("[DVBS]: DAGC1_Gain ====================: %f\n", DAGC1_Gain);
4960 printf("[DVBS]: DAGC2_Gain ====================: %f\n", DAGC2_Gain);
4961 printf("[DVBS]: DAGC3_Gain ====================: %f\n", DAGC3_Gain);
4962
4963 //---------------------------------------------------------
4964 //ERROR
4965 //Debug select
4966 u16Address = (DEBUG_SEL_AGC_ERR>>16)&0xffff;
4967 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4968 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_AGC_ERR)&0xffff);
4969 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4970
4971 //Freeze and dump
4972 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4973 //AGC_ERR
4974 u16Address = (DEBUG_OUT_AGC)&0xffff;
4975 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4976 AGC_Err=(u16Data&0x03ff);
4977 //Unfreeze
4978 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4979
4980 //Debug select
4981 u16Address = (DEBUG_SEL_DAGC0_ERR>>16)&0xffff;
4982 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4983 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_ERR)&0xffff);
4984 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4985
4986 //Freeze and dump
4987 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4988 //DAGC0_ERR
4989 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
4990 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4991 u16Data = (u16Data>>4);
4992 DAGC0_Err=(u16Data&0x7fff);
4993 //Unfreeze
4994 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4995
4996 //Debug select
4997 u16Address = (DEBUG_SEL_DAGC1_ERR>>16)&0xffff;
4998 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4999 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_ERR)&0xffff);
5000 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5001
5002 //Freeze and dump
5003 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5004 //DAGC1_ERR
5005 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
5006 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5007 DAGC1_Err=(u16Data&0x7fff);
5008 //Unfreeze
5009 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5010
5011 //Debug select
5012 u16Address = (DEBUG_SEL_DAGC2_ERR>>16)&0xffff;
5013 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5014 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_ERR)&0xffff);
5015 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5016
5017 //Freeze and dump
5018 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5019 //DAGC2_ERR
5020 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
5021 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5022 DAGC2_Err=(u16Data&0x7fff);
5023 //Unfreeze
5024 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5025
5026 //Debug select
5027 u16Address = (DEBUG_SEL_DAGC3_ERR>>16)&0xffff;
5028 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5029 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_ERR)&0xffff);
5030 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5031
5032 //Freeze and dump
5033 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5034 //DAGC3_ERR
5035 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
5036 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5037 u16Data = (u16Data>>4);
5038 DAGC3_Err=(u16Data&0x7fff);
5039 //Unfreeze
5040 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5041
5042 if (AGC_Err>=0x200)
5043 AGC_Err=AGC_Err-0x400;
5044 if (DAGC0_Err>=0x4000)
5045 DAGC0_Err=DAGC0_Err-0x8000;
5046 if (DAGC1_Err>=0x4000)
5047 DAGC1_Err=DAGC1_Err-0x8000;
5048 if (DAGC2_Err>=0x4000)
5049 DAGC2_Err=DAGC2_Err-0x8000;
5050 if (DAGC3_Err>=0x4000)
5051 DAGC3_Err=DAGC3_Err-0x8000;
5052
5053 printf("[DVBS]: AGC_Err =========================: %.3f\n", (float)AGC_Err);
5054 printf("[DVBS]: DAGC0_Err =======================: %.3f\n", (float)DAGC0_Err);
5055 printf("[DVBS]: DAGC1_Err =======================: %.3f\n", (float)DAGC1_Err);
5056 printf("[DVBS]: DAGC2_Err =======================: %.3f\n", (float)DAGC2_Err);
5057 printf("[DVBS]: DAGC3_Err =======================: %.3f\n", (float)DAGC3_Err);
5058 //---------------------------------------------------------
5059 //PEAK_MEAN
5060 //Debug select
5061 u16Address = (DEBUG_SEL_DAGC0_PEAK_MEAN>>16)&0xffff;
5062 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5063 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_PEAK_MEAN)&0xffff);
5064 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5065
5066 //Freeze and dump
5067 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5068 //DAGC0_PEAK_MEAN
5069 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
5070 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5071 u16Data = (u16Data>>4);
5072 DAGC0_Peak_Mean=(u16Data&0x0fff);
5073 //Unfreeze
5074 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5075
5076 //Debug select
5077 u16Address = (DEBUG_SEL_DAGC1_PEAK_MEAN>>16)&0xffff;
5078 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5079 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_PEAK_MEAN)&0xffff);
5080 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5081
5082 //Freeze and dump
5083 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5084 //DAGC1_PEAK_MEAN
5085 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
5086 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5087 DAGC1_Peak_Mean=(u16Data&0x0fff);
5088 //Unfreeze
5089 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5090
5091 //Debug select
5092 u16Address = (DEBUG_SEL_DAGC2_PEAK_MEAN>>16)&0xffff;
5093 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5094 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_PEAK_MEAN)&0xffff);
5095 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5096
5097 //Freeze and dump
5098 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5099 //DAGC2_PEAK_MEAN
5100 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
5101 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5102 DAGC2_Peak_Mean=(u16Data&0x0fff);
5103 //Unfreeze
5104 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5105
5106 //Debug select
5107 u16Address = (DEBUG_SEL_DAGC3_PEAK_MEAN>>16)&0xffff;
5108 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5109 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_PEAK_MEAN)&0xffff);
5110 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5111
5112 //Freeze and dump
5113 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5114 //DAGC3_PEAK_MEAN
5115 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
5116 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5117 u16Data = (u16Data>>4);
5118 DAGC3_Peak_Mean=(u16Data&0x0fff);
5119 //Unfreeze
5120 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5121
5122
5123 DAGC0_Peak_Mean = DAGC0_Peak_Mean / 0x800; //<12,11>
5124 DAGC1_Peak_Mean = DAGC1_Peak_Mean / 0x800; //<12,11>
5125 DAGC2_Peak_Mean = DAGC2_Peak_Mean / 0x800; //<12,11>
5126 DAGC3_Peak_Mean = DAGC3_Peak_Mean / 0x800; //<12,11>
5127
5128 printf("[DVBS]: DAGC0_Peak_Mean ===============: %f\n", DAGC0_Peak_Mean);
5129 printf("[DVBS]: DAGC1_Peak_Mean ===============: %f\n", DAGC1_Peak_Mean);
5130 printf("[DVBS]: DAGC2_Peak_Mean ===============: %f\n", DAGC2_Peak_Mean);
5131 printf("[DVBS]: DAGC3_Peak_Mean ===============: %f\n", DAGC3_Peak_Mean);
5132 //---------------------------------------------------------
5133 //Freeze and dump
5134 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5135
5136 u16Address = (DCR_OFFSET)&0xffff;
5137 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5138
5139 DCR_Offset_I=(u16Data&0xff);
5140 if (DCR_Offset_I >= 0x80)
5141 DCR_Offset_I = DCR_Offset_I-0x100;
5142 DCR_Offset_I = DCR_Offset_I/0x80;
5143
5144 DCR_Offset_Q=(u16Data>>8)&0xff;
5145 if (DCR_Offset_Q >= 0x80)
5146 DCR_Offset_Q = DCR_Offset_Q-0x100;
5147 DCR_Offset_Q = DCR_Offset_Q/0x80;
5148
5149 //Unfreeze
5150 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5151
5152 printf("[DVBS]: DCR_Offset_I ==================: %f\n", DCR_Offset_I);
5153 printf("[DVBS]: DCR_Offset_Q ==================: %f\n", DCR_Offset_Q);
5154 //---------------------------------------------------------
5155 ////Page1-FineCFO & PR & IIS & IQB
5156 //---------------------------------------------------------
5157 //FineCFO
5158 printf("------------------------------------------------------------------------\n");
5159 printf("Debug Message [FineCFO & PR & IIS & IQB & SNR Status]===================\n");
5160 //Debug Select
5161 u16Address = INNER_DEBUG_SEL;
5162 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5163 u16Data=((u16Data&0xC0FF)|0x0400);
5164 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5165
5166 //Freeze and dump
5167 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5168
5169 u16Address = INNEREXT_FINEFE_DBG_OUT0;
5170 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5171 FineCFO_loop_out_value=u16Data;
5172 u16Address = INNEREXT_FINEFE_DBG_OUT2;
5173 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5174 FineCFO_loop_out_value=(FineCFO_loop_out_value+(float)u16Data*pow(2.0, 16));
5175
5176 //Too large.Use 10Bit
5177 u16Address = INNEREXT_FINEFE_KI_FF0;
5178 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5179 FineCFO_loop_ki_value=u16Data;
5180 u16Address = INNEREXT_FINEFE_KI_FF2;
5181 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5182 FineCFO_loop_ki_value=(FineCFO_loop_ki_value+(float)u16Data*pow(2.0, 16));
5183 u16Address = INNEREXT_FINEFE_KI_FF4;
5184 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5185 FineCFO_loop_ki_value=(FineCFO_loop_ki_value+(double)(u16Data&0x00FF)*pow(2.0, 32));
5186 //Unfreeze
5187 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5188
5189 //---------------------------------------------------------
5190 //Debug Select
5191 u16Address = INNER_DEBUG_SEL;
5192 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5193 u16Data=((u16Data&0xC0FF)|0x0100);
5194 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5195
5196 //Freeze and dump
5197 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5198
5199 u16Address = INNEREXT_FINEFE_DBG_OUT0;
5200 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5201 FineCFO_loop_input_value=u16Data;
5202 u16Address = INNEREXT_FINEFE_DBG_OUT2;
5203 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5204 FineCFO_loop_input_value=(FineCFO_loop_input_value+(float)u16Data*pow(2.0, 16));
5205
5206 //Unfreeze
5207 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5208
5209 FineCFO_loop_ki_value = FineCFO_loop_ki_value/1024;
5210
5211 if (FineCFO_loop_out_value > 8388608)
5212 FineCFO_loop_out_value=FineCFO_loop_out_value - 16777216;
5213 if (FineCFO_loop_ki_value > 536870912)//549755813888/1024)
5214 FineCFO_loop_ki_value=FineCFO_loop_ki_value - 1073741824;//1099511627776/1024;
5215 if (FineCFO_loop_input_value> 1048576)
5216 FineCFO_loop_input_value=FineCFO_loop_input_value - 2097152;
5217
5218 FineCFO_loop_out_value = ((float)FineCFO_loop_out_value/16777216);
5219 FineCFO_loop_ki_value = ((double)FineCFO_loop_ki_value/67108864*u32DebugInfo_Fb);//68719476736/1024*Fb
5220 FineCFO_loop_input_value = ((float)FineCFO_loop_input_value/2097152);
5221
5222 printf("[DVBS]: FineCFO_loop_out_value ========: %f \n", FineCFO_loop_out_value);
5223 printf("[DVBS]: FineCFO_loop_ki_value =========: %f \n", FineCFO_loop_ki_value);
5224 printf("[DVBS]: FineCFO_loop_input_value ======: %f \n", FineCFO_loop_input_value);
5225
5226 //---------------------------------------------------------
5227 //Phase Recovery
5228 //Debug select
5229 u16Address = INNER_DEBUG_SEL;
5230 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5231 u16Data=(((u16Data&0x00FF)|0x0600)&0xffff);
5232 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5233
5234 //Freeze and dump
5235 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5236
5237 u16Address = INNER_PR_DEBUG_OUT0;
5238 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5239 PR_out_value=u16Data;
5240 if (PR_out_value>=0x1000)
5241 PR_out_value=PR_out_value-0x2000;
5242
5243 //Unfreeze
5244 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5245 //---------------------------------------------------------
5246 //Debug select
5247 u16Address = INNER_DEBUG_SEL;
5248 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5249 u16Data=(((u16Data&0x00FF)|0x0100)&0xffff);
5250 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5251
5252 //Freeze and dump
5253 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5254
5255 u16Address = INNER_PR_DEBUG_OUT0;
5256 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5257 PR_in_value=u16Data;
5258 u16Address = INNER_PR_DEBUG_OUT2;
5259 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5260 PR_in_value=(((u16Data&0x000F)<<16)|(MS_U16)PR_in_value);
5261 if (PR_in_value>=0x80000)
5262 PR_in_value=PR_in_value-0x100000;
5263
5264 //Unfreeze
5265 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5266 //---------------------------------------------------------
5267 //Debug select
5268 u16Address = INNER_DEBUG_SEL;
5269 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5270 u16Data=(((u16Data&0xC0FF)|0x0400)&0xffff);
5271 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5272
5273 //Freeze and dump
5274 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5275
5276 u16Address = INNER_PR_DEBUG_OUT0;
5277 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5278 PR_loop_ki=u16Data;
5279 u16Address = INNER_PR_DEBUG_OUT2;
5280 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5281 PR_loop_ki=(((u16Data&0x00FF)<<16)+PR_loop_ki);
5282 if (PR_loop_ki>=0x800000)
5283 PR_loop_ki=PR_loop_ki-0x1000000;
5284
5285 //Unfreeze
5286 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5287 //---------------------------------------------------------
5288 //Debug select
5289 u16Address = INNER_DEBUG_SEL;
5290 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5291 u16Data=(((u16Data&0x00FF)|0x0500)&0xffff);
5292 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5293
5294 //Freeze and dump
5295 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5296
5297 u16Address = INNER_PR_DEBUG_OUT0;
5298 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5299 PR_loopback_ki=u16Data;
5300 u16Address = INNER_PR_DEBUG_OUT2;
5301 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5302 PR_loopback_ki=(((u16Data&0x00FF)<<16)+PR_loopback_ki);
5303 if (PR_loopback_ki>=0x800000)
5304 PR_loopback_ki=PR_loopback_ki-0x1000000;
5305
5306 //Unfreeze
5307 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5308
5309 PR_out_value = ((float)PR_out_value/4096);
5310 PR_in_value = ((float)PR_in_value/131072);
5311 PR_loop_ki = ((float)PR_loop_ki/67108864*u32DebugInfo_Fb);
5312 PR_loopback_ki = ((float)PR_loopback_ki/67108864*u32DebugInfo_Fb);
5313
5314 printf("[DVBS]: PR_out_value ==================: %f\n", PR_out_value);
5315 printf("[DVBS]: PR_in_value ===================: %f\n", PR_in_value);
5316 printf("[DVBS]: PR_loop_ki ====================: %f\n", PR_loop_ki);
5317 printf("[DVBS]: PR_loopback_ki ================: %f\n", PR_loopback_ki);
5318 //---------------------------------------------------------
5319 //IIS
5320 //Freeze and dump
5321 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5322
5323 u16Address = (IIS_COUNT0)&0xffff;
5324 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5325 IIS_cnt=u16Data;
5326 u16Address = (IIS_COUNT2)&0xffff;
5327 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5328 IIS_cnt=(u16Data&0x1f)<<16|IIS_cnt;
5329
5330 printf("[DVBS]: IIS_cnt =======================: %d\n", IIS_cnt);
5331
5332 //Unfreeze
5333 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5334 //IQB
5335 //Freeze and dump
5336 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5337
5338 u16Address = (IQB_PHASE)&0xffff;
5339 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5340 IQB_Phase=u16Data&0x3FF;
5341 if (IQB_Phase>=0x200)
5342 IQB_Phase=IQB_Phase-0x400;
5343 IQB_Phase=IQB_Phase/0x400*180;
5344
5345 u16Address = (IQB_GAIN)&0xffff;
5346 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5347 IQB_Gain=u16Data&0x7FF;
5348 IQB_Gain=IQB_Gain/0x400;
5349
5350 printf("[DVBS]: IQB_Phase =====================: %f\n", IQB_Phase);
5351 printf("[DVBS]: IQB_Gain ======================: %f\n", IQB_Gain);
5352
5353 //Unfreeze
5354 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5355 //---------------------------------------------------------
5356 //SNR
5357 //Freeze and dump
5358 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5359
5360 Eq_variance_da=0;
5361 u16Address = 0x249E;
5362 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5363 Eq_variance_da=u16Data;
5364 u16Address = 0x24A0;
5365 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5366 Eq_variance_da=((float)(u16Data&0x03fff)*pow(2.0, 16)+Eq_variance_da)/pow(2.0, 29);
5367
5368 if (Eq_variance_da==0)
5369 Eq_variance_da=1;
5370 Linear_SNR_da=1.0/Eq_variance_da;
5371 SNR_da_dB=10*log10(Linear_SNR_da);
5372
5373 Eq_variance_dd=0;
5374 u16Address = 0x24A2;
5375 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5376 Eq_variance_dd=u16Data;
5377 u16Address = 0x24A4;
5378 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5379 Eq_variance_dd=(((float)(u16Data&0x3fff)*65536)+Eq_variance_dd)/pow(2.0, 29);
5380
5381 if (Eq_variance_dd==0)
5382 Eq_variance_dd=1;
5383 Linear_SNR_dd=1.0/Eq_variance_dd;
5384 SNR_dd_dB=10*log10(Linear_SNR_dd);
5385
5386 ndasnr_a=0;
5387 u16Address = 0x248C;
5388 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5389 ndasnr_a=u16Data;
5390 u16Address = 0x248E;
5391 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5392 ndasnr_a=(((float)(u16Data&0x0003)*pow(2.0, 16))+ndasnr_a)/65536;
5393
5394 ndasnr_ab=0;
5395 u16Address = 0x2490;
5396 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5397 ndasnr_ab=u16Data;
5398 u16Address = 0x2492;
5399 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5400 ndasnr_ab=(((float)(u16Data&0x03ff)*pow(2.0, 16))+ndasnr_ab)/4194304;
5401
5402 ndasnr_ab=sqrt(ndasnr_ab);
5403 if (ndasnr_ab==0)
5404 ndasnr_ab=1;
5405 ndasnr_ratio=(float)ndasnr_a/ndasnr_ab;
5406 if (ndasnr_ratio> 1)
5407 SNR_nda_dB=10*log10(1/(ndasnr_ratio - 1));
5408 else
5409 SNR_nda_dB=0;
5410
5411 u16Address = 0x24BA;
5412 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5413 Linear_SNR=u16Data;
5414 u16Address = 0x24BC;
5415 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5416 Linear_SNR=(((float)(u16Data&0x0007)*pow(2.0, 16))+Linear_SNR)/64;
5417 if (Linear_SNR==0)
5418 Linear_SNR=1;
5419 Linear_SNR=10*log10(Linear_SNR);
5420
5421 //Unfreeze
5422 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5423 printf("[DVBS]: SNR ===========================: %.2f\n", Linear_SNR);
5424 printf("[DVBS]: SNR_DA_dB =====================: %.2f\n", SNR_da_dB);
5425 printf("[DVBS]: SNR_DD_dB =====================: %.2f\n", SNR_dd_dB);
5426 printf("[DVBS]: SNR_NDA_dB ====================: %.2f\n", SNR_nda_dB);
5427 //---------------------------------------------------------
5428 printf("------------------------------------------------------------------------\n");
5429 printf("Debug Message [DVBS - PacketErr & BER]==================================\n");
5430 //BER
5431 //freeze
5432 u16Address = 0x2103;
5433 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5434 u16Data=u16Data|0x0001;
5435 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5436
5437 // bank 17 0x18 [7:0] reg_bit_err_sblprd_7_0 [15:8] reg_bit_err_sblprd_15_8
5438 u16Address = 0x2166;
5439 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5440 Packet_Err=u16Data;
5441
5442 printf("[DVBS]: Packet Err ====================: %.3E\n", Packet_Err);
5443
5444 /////////// Post-Viterbi BER /////////////
5445 // bank 7 0x18 [7:0] reg_bit_err_sblprd_7_0
5446 // [15:8] reg_bit_err_sblprd_15_8
5447 u16Address = 0x2146;
5448 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5449 BitErrPeriod=u16Data;
5450
5451 // bank 17 0x1D [7:0] reg_bit_err_num_7_0 [15:8] reg_bit_err_num_15_8
5452 // bank 17 0x1E [7:0] reg_bit_err_num_23_16 [15:8] reg_bit_err_num_31_24
5453 u16Address = 0x216A;
5454 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5455 BitErr=u16Data;
5456 u16Address = 0x216C;
5457 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5458 BitErr=(u16Data<<16)|BitErr;
5459
5460 if (BitErrPeriod ==0 )//protect 0
5461 BitErrPeriod=1;
5462 if (BitErr <=0 )
5463 BER=0.5 / (float)(BitErrPeriod*128*188*8);
5464 else
5465 BER=(float)(BitErr) / (float)(BitErrPeriod*128*188*8);
5466
5467 printf("[DVBS]: Post-Viterbi BER ==============: %.3E\n", BER);
5468
5469 // bank 7 0x19 [7] reg_bit_err_num_freeze
5470 u16Address = 0x2103;
5471 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5472 u16Data=u16Data&(~0x0001);
5473 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5474
5475 /////////// Pre-Viterbi BER /////////////
5476 // bank 17 0x08 [3] reg_rd_freezeber
5477 u16Address = 0x2110;
5478 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5479 u16Data=u16Data|0x0008;
5480 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5481
5482 // bank 17 0x0b [7:0] reg_ber_timerl [15:8] reg_ber_timerm
5483 // bank 17 0x0c [5:0] reg_ber_timerh
5484 u16Address = 0x2116;
5485 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5486 BitErrPeriod=u16Data;
5487 u16Address = 0x2118;
5488 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5489 BitErrPeriod=((u16Data&0x3f)<<16)|BitErrPeriod;
5490
5491 // bank 17 0x0f [7:0] reg_ber_7_0 [15:8] reg_ber_15_8
5492 u16Address = 0x211E;
5493 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5494 BitErr=u16Data;
5495
5496 // bank 17 0x0D [13:8] reg_cor_intstat_reg
5497 u16Address = 0x211A;
5498 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5499 if (u16Data & 0x1000)
5500 {
5501 BEROver = true;
5502 }
5503 else
5504 {
5505 BEROver = false;
5506 }
5507
5508 if (BitErrPeriod ==0 )//protect 0
5509 BitErrPeriod=1;
5510 if (BitErr <=0 )
5511 BER=0.5 / (float)(BitErrPeriod) / 256;
5512 else
5513 BER=(float)(BitErr) / (float)(BitErrPeriod) / 256;
5514 printf("[DVBS]: Pre-Viterbi BER ===============: %.3E\n", BER);
5515
5516 // bank 17 0x08 [3] reg_rd_freezeber
5517 u16Address = 0x2110;
5518 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5519 u16Data=u16Data&(~0x0008);
5520 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5521
5522 u16Address = 0x2188;
5523 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5524 ConvegenceLen = ((u16Data>>8)&0xFF);
5525 printf("[DVBS]: ConvegenceLen =================: %d\n", ConvegenceLen);
5526
5527 //---------------------------------------------------------
5528 //Timing Recovery
5529 //Debug select
5530 u16Address = (INNER_DEBUG_SEL_TR>>16)&0xffff;
5531 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5532 u16Data=(((u16Data&0x00ff)|INNER_DEBUG_SEL_TR)&0xffff);
5533 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5534
5535 //Freeze and dump
5536 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5537
5538 u16Address = (TR_INDICATOR_FF0)&0xffff;
5539 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5540 TR_Indicator_ff=u16Data;
5541 u16Address = (TR_INDICATOR_FF0)&0xffff;
5542 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5543 TR_Indicator_ff=((u16Data<<16) | (MS_U16)TR_Indicator_ff)&0x7fffff;
5544 if (TR_Indicator_ff >= 0x400000)
5545 TR_Indicator_ff=TR_Indicator_ff - 0x800000;
5546
5547 //Unfreeze
5548 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5549
5550 //Debug select
5551 u16Address = (DEBUG_SEL_TR_SFO_CONVERGE>>16)&0xffff;
5552 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5553 u16Data=(((u16Data&0x00ff)|DEBUG_SEL_TR_SFO_CONVERGE)&0xffff);
5554 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5555
5556 //Freeze and dump
5557 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5558
5559 u16Address = (TR_INDICATOR_FF0)&0xffff;
5560 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5561 TR_SFO_Converge=u16Data;
5562 u16Address = (TR_INDICATOR_FF0)&0xffff;
5563 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5564 TR_SFO_Converge=((u16Data<<16) | (MS_U16)TR_SFO_Converge)&0x7fffff;
5565 if (TR_SFO_Converge >= 0x400000)
5566 TR_SFO_Converge=TR_SFO_Converge - 0x800000;
5567
5568 u16Address = INNER_TR_LOPF_VALUE_DEBUG0;
5569 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5570 TR_loop_ki=u16Data;
5571 u16Address = INNER_TR_LOPF_VALUE_DEBUG2;
5572 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5573 TR_loop_ki=((float)u16Data*pow(2.0, 16))+TR_loop_ki;
5574 u16Address = INNER_TR_LOPF_VALUE_DEBUG4;
5575 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5576 TR_loop_ki=(((double)(u16Data&0x01ff)*pow(2.0, 32))+ TR_loop_ki);
5577 if (TR_loop_ki>=pow(2.0, 40))
5578 TR_loop_ki=TR_loop_ki-pow(2.0, 41);
5579
5580 //Unfreeze
5581 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5582
5583 //Debug select
5584 u16Address = (DEBUG_SEL_TR_INPUT>>16)&0xffff;
5585 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5586 u16Data=(((u16Data&0x00ff)|DEBUG_SEL_TR_INPUT)&0xffff);
5587 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5588
5589 //Freeze and dump
5590 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5591
5592 u16Address = (TR_INDICATOR_FF0)&0xffff;
5593 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5594 TR_loop_input=u16Data;
5595 //banknum=(TR_INDICATOR_FF1>>8)&0xff;
5596 //addr=(TR_INDICATOR_FF1)&0xff;
5597 //if(InformRead(banknum, addr, &data)==FALSE) return;
5598 //TR_loop_input=((float)((data&0x00ff)<<16) + TR_loop_input);
5599 if (TR_loop_input >= 0x8000)
5600 TR_loop_input=TR_loop_input - 0x10000;
5601
5602 //Unfreeze
5603 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5604
5605 Fs_value=u32DebugInfo_Fs;
5606 Fb_value=u32DebugInfo_Fb;
5607 TR_tmp0=(float)TR_SFO_Converge/0x200000;
5608 TR_tmp2=TR_loop_ki/pow(2.0, 39);
5609 TR_tmp1=(float)Fs_value/2/Fb_value;
5610
5611 TR_Indicator_ff = (TR_Indicator_ff/0x400);
5612 TR_Loop_Output = (TR_tmp0/TR_tmp1*1000000);
5613 TR_Loop_Ki = (TR_tmp2/TR_tmp1*1000000);
5614 TR_loop_input = (TR_loop_input/0x8000);
5615
5616 printf("[DVBS]: TR_Indicator_ff================: %f \n", TR_Indicator_ff);
5617 printf("[DVBS]: TR_Loop_Output=================: %f [ppm]\n", TR_Loop_Output);
5618 printf("[DVBS]: TR_Loop_Ki=====================: %f [ppm]\n", TR_Loop_Ki);
5619 printf("[DVBS]: TR_loop_input==================: %f \n", TR_loop_input);
5620 #endif
5621 bRet=true;
5622 return bRet;
5623 }
5624
5625 //------------------------------------------------------------------
5626 // END Get And Show Info Function
5627 //------------------------------------------------------------------
5628
5629 //------------------------------------------------------------------
5630 // BlindScan Function
5631 //------------------------------------------------------------------
INTERN_DVBS_BlindScan_Start(MS_U16 u16StartFreq,MS_U16 u16EndFreq)5632 MS_BOOL INTERN_DVBS_BlindScan_Start(MS_U16 u16StartFreq,MS_U16 u16EndFreq)
5633 {
5634 MS_BOOL status=TRUE;
5635 MS_U8 u8Data=0;
5636
5637 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_Start+\n"));
5638
5639 _u16BlindScanStartFreq=u16StartFreq;
5640 _u16BlindScanEndFreq=u16EndFreq;
5641 _u16TunerCenterFreq=0;
5642 _u16ChannelInfoIndex=0;
5643
5644 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5645 u8Data&=0xd0;
5646 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5647
5648 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)_u16BlindScanStartFreq&0x00ff);
5649 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(_u16BlindScanStartFreq>>8)&0x00ff);
5650
5651 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_Start- _u16BlindScanStartFreq%d u16StartFreq %d u16EndFreq %d\n", _u16BlindScanStartFreq, u16StartFreq, u16EndFreq));
5652
5653 return status;
5654 }
5655
INTERN_DVBS_BlindScan_NextFreq(MS_BOOL * bBlindScanEnd)5656 MS_BOOL INTERN_DVBS_BlindScan_NextFreq(MS_BOOL* bBlindScanEnd)
5657 {
5658 MS_BOOL status=TRUE;
5659 MS_U8 u8Data=0;
5660
5661 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq+\n"));
5662
5663 * bBlindScanEnd=FALSE;
5664
5665 if (_u16TunerCenterFreq >=_u16BlindScanEndFreq)
5666 {
5667 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq . _u16TunerCenterFreq %d _u16BlindScanEndFreq%d\n", _u16TunerCenterFreq, _u16BlindScanEndFreq));
5668 * bBlindScanEnd=TRUE;
5669
5670 return status;
5671 }
5672 //Set Tuner Frequency
5673 MsOS_DelayTask(10);
5674
5675 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5676 if ((u8Data&0x02)==0x00)//Manual Tune
5677 {
5678 u8Data&=~(0x28);
5679 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5680 u8Data|=0x02;
5681 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5682 u8Data|=0x01;
5683 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5684 }
5685 else
5686 {
5687 u8Data&=~(0x28);
5688 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5689 }
5690
5691 return status;
5692 }
5693
INTERN_DVBS_BlindScan_GetTunerFreq(MS_U16 * u16TunerCenterFreq,MS_U16 * u16TunerCutOffFreq)5694 MS_BOOL INTERN_DVBS_BlindScan_GetTunerFreq(MS_U16 *u16TunerCenterFreq, MS_U16 *u16TunerCutOffFreq)
5695 {
5696 MS_BOOL status=TRUE;
5697 MS_U8 u8Data=0;
5698 MS_U16 u16WaitCount;
5699 MS_U16 u16TunerCutOff;
5700
5701 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_SetTunerFreq+\n"));
5702
5703 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5704 if ((u8Data&0x02)==0x02)
5705 {
5706 u8Data|=0x08;
5707 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5708 u16WaitCount=0;
5709 do
5710 {
5711 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
5712 u16WaitCount++;
5713 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
5714 MsOS_DelayTask(1);
5715 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
5716 }
5717 else if((u8Data&0x01)==0x01)
5718 {
5719 u8Data|=0x20;
5720 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5721 u16WaitCount=0;
5722 do
5723 {
5724 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
5725 u16WaitCount++;
5726 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
5727 MsOS_DelayTask(1);
5728 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
5729 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5730 u8Data|=0x02;
5731 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5732 }
5733 u16WaitCount=0;
5734
5735 _u16TunerCenterFreq=0;
5736
5737 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, &u8Data);
5738 //printf("INTERN_DVBS_BlindScan_GetTunerFreq E_DMD_S2_BS_Tuner_Center_Freq_H=%d\n", u8Data);//RRRRR
5739 _u16TunerCenterFreq=u8Data;
5740 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, &u8Data);
5741 //printf("INTERN_DVBS_BlindScan_GetTunerFreq E_DMD_S2_BS_Tuner_Center_Freq_L=%d\n", u8Data);//RRRRR
5742 _u16TunerCenterFreq=(_u16TunerCenterFreq<<8)|u8Data;
5743
5744 *u16TunerCenterFreq = _u16TunerCenterFreq;
5745 //claire test
5746 u16TunerCutOff=44000;
5747 if(_u16TunerCenterFreq<=990)//980
5748 {
5749
5750 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_BALANCE_TRACK, &u8Data);
5751 if(u8Data==0x01)
5752 {
5753 if(_u16TunerCenterFreq<970)//970
5754 {
5755 u16TunerCutOff=10000;
5756 }
5757 else
5758 {
5759 u16TunerCutOff=20000;
5760 }
5761 u8Data=0x02;
5762 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_BALANCE_TRACK, u8Data);
5763 }
5764 else if(u8Data==0x02)
5765 {
5766 u8Data=0x00;
5767 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_BALANCE_TRACK, u8Data);
5768 }
5769 }
5770 if(u16TunerCutOffFreq != NULL)
5771 {
5772 *u16TunerCutOffFreq = u16TunerCutOff;
5773 }
5774
5775 //end claire test
5776
5777 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_SetTunerFreq- _u16TunerCenterFreq:%d\n", _u16TunerCenterFreq));
5778
5779
5780 return status;
5781 }
5782
INTERN_DVBS_BlindScan_WaitCurFreqFinished(MS_U8 * u8Progress,MS_U8 * u8FindNum)5783 MS_BOOL INTERN_DVBS_BlindScan_WaitCurFreqFinished(MS_U8* u8Progress,MS_U8 *u8FindNum)
5784 {
5785 MS_BOOL status=TRUE;
5786 MS_U32 u32Data=0;
5787 MS_U16 u16Data=0;
5788 MS_U8 u8Data=0, u8Data2=0;
5789 MS_U16 u16WaitCount;
5790
5791 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_WaitCurFreqFinished+\n"));
5792
5793 u16WaitCount=0;
5794 *u8FindNum=0;
5795 *u8Progress=0;
5796
5797 do
5798 {
5799 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data); //State=BlindScan
5800 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_BLINDSCAN_CHECK, &u8Data2); //SubState=BlindScan
5801 u16WaitCount++;
5802 DBG_INTERN_DVBS(printf("INTERN_DVBS_BlindScan_WaitCurFreqFinished State: 0x%x Status: 0x%x u16WaitCount:%d\n", u8Data, u8Data2, u16WaitCount));
5803 //printf("INTERN_DVBS_BlindScan_WaitCurFreqFinished State: 0x%x Status: 0x%x u16WaitCount:%d\n", u8Data, u8Data2, u16WaitCount);
5804
5805 MsOS_DelayTask(1);
5806 }while(((u8Data!=17)||(u8Data2!=0xff))&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));//E_DMD_S2_STATE_FLAG
5807
5808
5809
5810 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DUMMY_REG_2, &u8Data);
5811 u16Data=u8Data;
5812
5813
5814 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_WaitCurFreqFinished OuterCheckStatus:0x%x\n", u16Data));
5815
5816 if (u16WaitCount>=INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
5817 {
5818 status=false;
5819 printf("Debug blind scan wait finished time out!!!!\n");
5820 }
5821 else
5822 {
5823
5824 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SUBSTATE_FLAG, &u8Data);//SubState
5825 if (u8Data==0)
5826 {
5827
5828 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
5829 u32Data=u8Data;
5830 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
5831 u32Data=(u32Data<<8)|u8Data;
5832 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
5833 u32Data=(u32Data<<8)|u8Data;
5834 _u16ChannelInfoArray[0][_u16ChannelInfoIndex]=((u32Data+500)/1000);
5835 _u16LockedCenterFreq=((u32Data+500)/1000); //Center Freq
5836
5837
5838 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
5839 u16Data=u8Data;
5840 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
5841 u16Data=(u16Data<<8)|u8Data;
5842 _u16ChannelInfoArray[1][_u16ChannelInfoIndex]=(u16Data);//Symbol Rate
5843 _u16LockedSymbolRate=u16Data;
5844 _u16ChannelInfoIndex++;
5845 *u8FindNum=_u16ChannelInfoIndex;
5846 //printf("claire debug blind scan: find TP frequency %d SR %d index %d\n",_u16LockedCenterFreq,_u16LockedSymbolRate,_u16ChannelInfoIndex);
5847
5848
5849 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
5850 u16Data=u8Data;
5851 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
5852 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset_Locked
5853 if (u16Data*1000 >= 0x8000)
5854 {
5855 u16Data=0x10000- u16Data*1000;
5856 _s16CurrentCFO=-1*u16Data/1000;
5857 }
5858 else
5859 {
5860 _s16CurrentCFO=u16Data;
5861 }
5862
5863 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
5864 u16Data=u8Data;
5865 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
5866 u16Data=(u16Data<<8)|u8Data;
5867 _u16CurrentStepSize=u16Data; //Tuner_Frequency_Step
5868
5869
5870 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18H, &u8Data);
5871 u16Data=u8Data;
5872 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18L, &u8Data);
5873 u16Data=(u16Data<<8)|u8Data;
5874 _u16PreLockedHB=u16Data; //Pre_Scanned_HB
5875
5876
5877 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19H, &u8Data);
5878 u16Data=u8Data;
5879 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19L, &u8Data);
5880 u16Data=(u16Data<<8)|u8Data;
5881 _u16PreLockedLB=u16Data; //Pre_Scanned_LB
5882
5883
5884 DBG_INTERN_DVBS(printf("Current Locked CF:%d BW:%d BWH:%d BWL:%d CFO:%d Step:%d\n", _u16LockedCenterFreq, _u16LockedSymbolRate,_u16PreLockedHB, _u16PreLockedLB, _s16CurrentCFO, _u16CurrentStepSize));
5885 }
5886 else if (u8Data==1)
5887 {
5888 //printf("claire debug blind scan: no find TP\n");
5889
5890
5891 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, &u8Data);
5892 u16Data=u8Data;
5893 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, &u8Data);
5894 u16Data=(u16Data<<8)|u8Data;
5895 _u16NextCenterFreq=u16Data;
5896
5897
5898 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
5899 u16Data=u8Data;
5900 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
5901 u16Data=(u16Data<<8)|u8Data;
5902 _u16PreLockedHB=u16Data; //Pre_Scanned_HB
5903
5904
5905
5906 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13H, &u8Data);
5907 u16Data=u8Data;
5908 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
5909 u16Data=(u16Data<<8)|u8Data;
5910 _u16PreLockedLB=u16Data; //Pre_Scanned_LB
5911
5912
5913 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
5914 u16Data=u8Data;
5915 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
5916 u16Data=(u16Data<<8)|u8Data;
5917 _u16CurrentSymbolRate=u16Data; //Fine_Symbol_Rate
5918
5919
5920 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
5921 u16Data=u8Data;
5922 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
5923 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset
5924 if (u16Data*1000 >= 0x8000)
5925 {
5926 u16Data=0x1000- u16Data*1000;
5927 _s16CurrentCFO=-1*u16Data/1000;
5928 }
5929 else
5930 {
5931 _s16CurrentCFO=u16Data;
5932 }
5933
5934 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
5935 u16Data=u8Data;
5936 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
5937 u16Data=(u16Data<<8)|u8Data;
5938 _u16CurrentStepSize=u16Data; //Tuner_Frequency_Step
5939
5940
5941 DBG_INTERN_DVBS(printf("Pre Locked CF:%d BW:%d HBW:%d LBW:%d Current CF:%d BW:%d CFO:%d Step:%d\n", _u16LockedCenterFreq, _u16LockedSymbolRate,_u16PreLockedHB, _u16PreLockedLB, _u16NextCenterFreq-_u16CurrentStepSize, _u16CurrentSymbolRate, _s16CurrentCFO, _u16CurrentStepSize));
5942 }
5943 }
5944 *u8Progress=100;
5945
5946 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_WaitCurFreqFinished- u8Progress: %d u8FindNum %d\n", *u8Progress, *u8FindNum));
5947
5948 return status;
5949 }
5950
INTERN_DVBS_BlindScan_Cancel(void)5951 MS_BOOL INTERN_DVBS_BlindScan_Cancel(void)
5952 {
5953 MS_BOOL status=TRUE;
5954 MS_U8 u8Data=0;
5955 MS_U16 u16Data;
5956
5957 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_Cancel+\n"));
5958
5959 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5960 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
5961 u8Data&=0xF0;
5962 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5963 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
5964
5965 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E1, 0x00);
5966 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E0, 0x00);
5967 u16Data = 0x0000;
5968 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)u16Data&0x00ff);
5969 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(u16Data>>8)&0x00ff);
5970
5971 _u16TunerCenterFreq=0;
5972 _u16ChannelInfoIndex=0;
5973
5974 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_Cancel-\n"));
5975
5976 return status;
5977 }
5978
INTERN_DVBS_BlindScan_End(void)5979 MS_BOOL INTERN_DVBS_BlindScan_End(void)
5980 {
5981 MS_BOOL status=TRUE;
5982 MS_U8 u8Data=0;
5983 MS_U16 u16Data;
5984
5985 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_End+\n"));
5986
5987 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5988 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
5989 u8Data&=0xF0;
5990 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5991 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
5992
5993 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E1, 0x00);
5994 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E0, 0x00);
5995 u16Data = 0x0000;
5996 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)u16Data&0x00ff);
5997 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(u16Data>>8)&0x00ff);
5998
5999 _u16TunerCenterFreq=0;
6000 _u16ChannelInfoIndex=0;
6001
6002 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_End-\n"));
6003
6004 return status;
6005 }
6006
INTERN_DVBS_BlindScan_GetChannel(MS_U16 u16ReadStart,MS_U16 * u16TPNum,HAL_DEMOD_MS_FE_CARRIER_PARAM * pTable)6007 MS_BOOL INTERN_DVBS_BlindScan_GetChannel(MS_U16 u16ReadStart,MS_U16* u16TPNum,HAL_DEMOD_MS_FE_CARRIER_PARAM *pTable)
6008 {
6009 MS_BOOL status=TRUE;
6010 MS_U16 u16TableIndex;
6011
6012 *u16TPNum=_u16ChannelInfoIndex-u16ReadStart;
6013 for(u16TableIndex = 0; u16TableIndex < (*u16TPNum); u16TableIndex++)
6014 {
6015 pTable[u16TableIndex].u32Frequency = _u16ChannelInfoArray[0][_u16ChannelInfoIndex-1];
6016 pTable[u16TableIndex].SatParam.u32SymbolRate = _u16ChannelInfoArray[1][_u16ChannelInfoIndex-1];
6017 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_GetChannel Freq: %d SymbolRate: %d\n", pTable[u16TableIndex].u32Frequency, pTable[u16TableIndex].SatParam.u32SymbolRate));
6018 }
6019 DBG_INTERN_DVBS(printf("INTERN_DVBS_u16TPNum:%d\n", *u16TPNum));
6020
6021 return status;
6022 }
6023
INTERN_DVBS_BlindScan_GetCurrentFreq(MS_U32 * u32CurrentFeq)6024 MS_BOOL INTERN_DVBS_BlindScan_GetCurrentFreq(MS_U32 *u32CurrentFeq)
6025 {
6026 MS_BOOL status=TRUE;
6027 DBG_INTERN_DVBS(printf("INTERN_DVBS_BlindScan_GetCurrentFreq+\n"));
6028
6029 *u32CurrentFeq=_u16TunerCenterFreq;
6030 DBG_INTERN_DVBS(printf("INTERN_DVBS_BlindScan_GetCurrentFreq-: %d\n", _u16TunerCenterFreq));
6031 return status;
6032 }
6033 //------------------------------------------------------------------
6034 // END BlindScan Function
6035 //------------------------------------------------------------------
6036
6037 //------------------------------------------------------------------
6038 // DiSEqc Function
6039 //------------------------------------------------------------------
INTERN_DVBS_DiSEqC_Init(void)6040 MS_BOOL INTERN_DVBS_DiSEqC_Init(void)
6041 {
6042 MS_BOOL status = true;
6043 MS_U8 u8Data = 0;
6044
6045 //Clear status
6046 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6047 u8Data=(u8Data|0x3E)&(~0x3E);
6048 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6049
6050 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, 0x00);
6051 //Tone En
6052 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC0, &u8Data);
6053 u8Data=(u8Data&(~0x06))|(0x06);
6054 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, u8Data);
6055
6056 DBG_INTERN_DVBS(printf("INTERN_DVBS_DiSEqC_Init\n"));
6057
6058 return status;
6059 }
6060
INTERN_DVBS_DiSEqC_SetTone(MS_BOOL bTone1)6061 MS_BOOL INTERN_DVBS_DiSEqC_SetTone(MS_BOOL bTone1)
6062 {
6063 MS_BOOL status=TRUE;
6064 MS_U8 u8Data=0;
6065 MS_U8 u8ReSet22k=0;
6066
6067 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC4, 0x01);//0x62;DVBS2_DISEQC_TX1
6068 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, 0x4E);//0x60
6069 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCC, 0x88);//0x66
6070
6071 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);//0x61
6072 u8ReSet22k=u8Data;
6073
6074 if (bTone1==TRUE)
6075 {
6076 //Tone burst 1
6077 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, 0x19);
6078 _u8ToneBurstFlag=1;
6079 }
6080 else
6081 {
6082 //Tone burst 0
6083 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, 0x11);
6084 _u8ToneBurstFlag=2;
6085 }
6086 //DIG_DISEQC_TX_EN
6087 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6088 //u8Data=u8Data&~(0x01);//Tx Disable
6089 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6090
6091 MsOS_DelayTask(1);
6092 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);//0x66 high byte DVBS2_DISEQC_TX_EN
6093 u8Data=u8Data|0x3E; //Status clear
6094 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6095 MsOS_DelayTask(10);
6096 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6097 u8Data=u8Data&~(0x3E);
6098 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6099 MsOS_DelayTask(1);
6100
6101 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6102 u8Data=u8Data|0x01; //Tx Enable
6103 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6104
6105 MsOS_DelayTask(30);//(100)
6106 //For ToneBurst 22k issue.
6107 u8Data=u8ReSet22k;
6108 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);//0x61
6109
6110 DBG_INTERN_DVBS(printf("INTERN_DVBS_DiSEqC_SetTone:%d\n", bTone1));
6111 //MsOS_DelayTask(100);
6112 return status;
6113 }
6114
INTERN_DVBS_DiSEqC_SetLNBOut(MS_BOOL bLow)6115 MS_BOOL INTERN_DVBS_DiSEqC_SetLNBOut(MS_BOOL bLow)
6116 {
6117 MS_BOOL status=TRUE;
6118 MS_U8 u8Data=0;
6119
6120 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6121 if (bLow==TRUE)
6122 {
6123 u8Data=(u8Data|0x40); //13V
6124 }
6125 else
6126 {
6127 u8Data=(u8Data&(~0x40));//18V
6128 }
6129 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);
6130
6131 return status;
6132 }
6133
INTERN_DVBS_DiSEqC_GetLNBOut(MS_BOOL * bLNBOutLow)6134 MS_BOOL INTERN_DVBS_DiSEqC_GetLNBOut(MS_BOOL* bLNBOutLow)
6135 {
6136 MS_BOOL status=TRUE;
6137 MS_U8 u8Data=0;
6138
6139 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6140 if( (u8Data&0x40)==0x40)
6141 {
6142 * bLNBOutLow=TRUE;
6143 }
6144 else
6145 {
6146 * bLNBOutLow=FALSE;
6147 }
6148
6149 return status;
6150 }
6151
INTERN_DVBS_DiSEqC_Set22kOnOff(MS_BOOL b22kOn)6152 MS_BOOL INTERN_DVBS_DiSEqC_Set22kOnOff(MS_BOOL b22kOn)
6153 {
6154 MS_BOOL status=TRUE;
6155 MS_U8 u8Data=0;
6156
6157 //Set DiSeqC 22K
6158 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCC, 0x44); //Set 11K-->22K
6159
6160 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6161
6162 if (b22kOn==TRUE)
6163 {
6164 u8Data=(u8Data&0xc7);
6165 u8Data=(u8Data|0x08);
6166 }
6167 else
6168 {
6169 u8Data=(u8Data&0xc7);
6170 }
6171 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);
6172
6173 DBG_INTERN_DVBS(printf("INTERN_DVBS_DiSEqC_Set22kOnOff:%d\n", b22kOn));
6174 return status;
6175 }
6176
INTERN_DVBS_DiSEqC_Get22kOnOff(MS_BOOL * b22kOn)6177 MS_BOOL INTERN_DVBS_DiSEqC_Get22kOnOff(MS_BOOL* b22kOn)
6178 {
6179 MS_BOOL status=TRUE;
6180 MS_U8 u8Data=0;
6181
6182 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6183 if ((u8Data&0x38)==0x08)
6184 {
6185 *b22kOn=TRUE;
6186 }
6187 else
6188 {
6189 *b22kOn=FALSE;
6190 }
6191
6192 return status;
6193 }
6194
INTERN_DVBS_DiSEqC_SendCmd(MS_U8 * pCmd,MS_U8 u8CmdSize)6195 MS_BOOL INTERN_DVBS_DiSEqC_SendCmd(MS_U8* pCmd,MS_U8 u8CmdSize)
6196 {
6197 MS_BOOL status=TRUE;
6198 MS_U8 u8Data;
6199 MS_U8 u8Index;
6200 MS_U16 u16WaitCount;
6201 /*
6202 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6203 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6204 u8Data=(u8Data&~(0x10));
6205 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6206 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6207 */
6208 #if 0 //For Unicable command timing
6209 u16WaitCount=0;
6210 do
6211 {
6212 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data);
6213 //printf(">>> INTERN_DVBS_DiSEqC_SendCmd DiSEqC Status = 0x%x <<<\n", u8Data);
6214 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6215 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6216 MsOS_DelayTask(1);
6217 u16WaitCount++;
6218 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
6219
6220 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
6221 {
6222 DBG_INTERN_DVBS(printf("INTERN_DVBS DiSEqC Send Command Busy!!!\n"));
6223 return FALSE;
6224 }
6225 #endif
6226
6227 //u16Address=0x0BC4;
6228 for (u8Index=0; u8Index < u8CmdSize; u8Index++)
6229 {
6230 u8Data=*(pCmd+u8Index);
6231 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC4 + u8Index, u8Data);//#define DVBS2_DISEQC_TX1 (_REG_DVBS2(0x62)+0)//[7:0]
6232 DBG_INTERN_DVBS(printf("=============INTERN_DVBS_DiSEqC_SendCmd(Demod1) = 0x%X\n",u8Data));
6233 }
6234
6235 //set DiSEqC Tx Length, Odd Enable, Tone Burst Mode
6236 u8Data=((u8CmdSize-1)&0x07)|0x40;
6237 if (_u8ToneBurstFlag==1)
6238 {
6239 u8Data|=0x80;//0x20;
6240 }
6241 else if (_u8ToneBurstFlag==2)
6242 {
6243 u8Data|=0x20;//0x80;
6244 }
6245 _u8ToneBurstFlag=0;
6246 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_8, u8Data);
6247
6248 //add this only for check mailbox R/W
6249 #if 1
6250 DBG_INTERN_DVBS(printf(" Write into E_DMD_S2_MB_DMDTOP_DBG_8 = 0x%X!!!\n",u8Data));
6251 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_8, &u8Data);
6252 DBG_INTERN_DVBS(printf(" Read from E_DMD_S2_MB_DMDTOP_DBG_8 = 0x%X!!!\n",u8Data));
6253 #endif
6254
6255 MsOS_DelayTask(25);//MsOS_DelayTask(10);
6256 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);//#define TOP_WR_DBG_90 (_REG_DMDTOP(0x3A)+0)
6257 //u8Data=u8Data|0x10;
6258 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data|0x10);//enable DiSEqC_Data_Tx
6259 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); DBG_INTERN_DVBS(printf(">>>+++ INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X +++<<<\n",u8Data));
6260 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); DBG_INTERN_DVBS(printf(">>>+++ INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d +++<<<\n",u8Data));
6261
6262 #if 1 //For Unicable command timing???
6263 u16WaitCount=0;
6264 do
6265 {
6266 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); DBG_INTERN_DVBS(printf(">>>*** INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X ***<<<\n",u8Data));
6267 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); DBG_INTERN_DVBS(printf(">>>*** INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d ***<<<\n",u8Data));
6268 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6269 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6270 MsOS_DelayTask(1);
6271 u16WaitCount++;
6272 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)) ;
6273
6274 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
6275 {
6276 DBG_INTERN_DVBS(printf("INTERN_DVBS DiSEqC Send Command Busy!!!\n"));
6277 return FALSE;
6278 }
6279 else
6280 {
6281 DBG_INTERN_DVBS(printf("INTERN_DVBS DiSEqC Send Command Success!!!\n"));
6282 return TRUE;
6283 }
6284
6285
6286 #endif
6287 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); printf(">>>--- INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X ---<<<\n",u8Data);
6288 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); printf(">>>--- INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d ---<<<\n",u8Data+1);
6289
6290 return status;
6291 }
6292
INTERN_DVBS_DiSEqC_SetTxToneMode(MS_BOOL bTxTone22kOff)6293 MS_BOOL INTERN_DVBS_DiSEqC_SetTxToneMode(MS_BOOL bTxTone22kOff)
6294 {
6295 MS_BOOL status=TRUE;
6296 MS_U8 u8Data=0;
6297
6298 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xD7, &u8Data);//h006b h006b 15 15 reg_diseqc_tx_tone_mode
6299 if (bTxTone22kOff==TRUE)
6300 {
6301 u8Data=(u8Data|0x80); //1: without 22K.
6302 }
6303 else
6304 {
6305 u8Data=(u8Data&(~0x80)); //0: with 22K.
6306 }
6307 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xD7, u8Data);
6308
6309 return status;
6310 }
6311
INTERN_DVBS_UnicableAGCCheckPower(MS_BOOL pbAGCCheckPower)6312 MS_BOOL INTERN_DVBS_UnicableAGCCheckPower(MS_BOOL pbAGCCheckPower)
6313 {
6314 //MS_BOOL status = TRUE;
6315 MS_U8 u8Data=0;
6316
6317 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, 0x00);
6318
6319 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6320 u8Data &= 0xFE;//clean bit0
6321 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6322
6323 if (pbAGCCheckPower == FALSE)//0
6324 {
6325 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6326 u8Data &= 0xFE;//clean bit0
6327 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6328 //printf("CMD=MS_FALSE==============================\n");
6329 }
6330 else
6331 {
6332 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6333 u8Data |= 0x01; //bit1=1
6334 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6335 //printf("CMD=MS_TRUE==============================\n");
6336 }
6337
6338 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6339 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6340 u8Data &= 0xF0;
6341 u8Data |= 0x01;
6342 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6343 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6344 MsOS_DelayTask(500);
6345
6346 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6347 u8Data &= 0x80; //Read bit7
6348 if (u8Data == 0x80)
6349 {
6350 u8Data = 0x00;
6351 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6352 u8Data = 0x00;
6353 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6354 return TRUE;
6355 }
6356 else
6357 {
6358 u8Data = 0x00;
6359 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6360 u8Data = 0x00;
6361 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6362 return FALSE;
6363 }
6364 }
6365
6366 //------------------------------------------------------------------
6367 // END DiSEqc Function
6368 //------------------------------------------------------------------
6369 //------------------------------------------------------------------
6370 // R/W Function
6371 //------------------------------------------------------------------
INTERN_DVBS_WriteReg2bytes(MS_U16 u16Addr,MS_U16 u16Data)6372 MS_BOOL INTERN_DVBS_WriteReg2bytes(MS_U16 u16Addr, MS_U16 u16Data)
6373 {
6374 MS_BOOL bRet= TRUE;
6375 bRet &= MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr, (MS_U8)u16Data&0x00ff);
6376 bRet &= MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr + 0x0001, (MS_U8)(u16Data>>8)&0x00ff);
6377 return bRet;
6378 }
6379
INTERN_DVBS_ReadReg2bytes(MS_U16 u16Addr,MS_U16 * pu16Data)6380 MS_BOOL INTERN_DVBS_ReadReg2bytes(MS_U16 u16Addr, MS_U16 *pu16Data)
6381 {
6382 MS_BOOL bRet= TRUE;
6383 MS_U8 u8Data =0;
6384 MS_U16 u16Data =0;
6385
6386 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr + 0x0001, &u8Data);
6387 u16Data = u8Data;
6388 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr, &u8Data);
6389 *pu16Data = (u16Data<<8)|u8Data;
6390
6391 return bRet;
6392 }
6393
6394 //Frontend Freeze
INTERN_DVBS_DTV_FrontendSetFreeze(void)6395 MS_BOOL INTERN_DVBS_DTV_FrontendSetFreeze(void)
6396 {
6397 MS_BOOL bRet= TRUE;
6398 MS_U16 u16Address;
6399 MS_U16 u16Data=0;
6400
6401 u16Address = (FRONTEND_FREEZE_DUMP>>16)&0xffff;
6402 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6403 u16Data|=(FRONTEND_FREEZE_DUMP&0xffff);
6404 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6405
6406 return bRet;
6407 }
6408
INTERN_DVBS_DTV_FrontendUnFreeze(void)6409 MS_BOOL INTERN_DVBS_DTV_FrontendUnFreeze(void)
6410 {
6411 MS_BOOL bRet= TRUE;
6412 MS_U16 u16Address;
6413 MS_U16 u16Data=0;
6414
6415 u16Address = (FRONTEND_FREEZE_DUMP>>16)&0xffff;
6416 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6417 u16Data&=~(FRONTEND_FREEZE_DUMP&0xffff);
6418 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6419
6420 return bRet;
6421 }
6422
6423 //Inner Freeze
INTERN_DVBS_DTV_InnerSetFreeze(void)6424 MS_BOOL INTERN_DVBS_DTV_InnerSetFreeze(void)
6425 {
6426 MS_BOOL bRet= TRUE;
6427 MS_U16 u16Address;
6428 MS_U16 u16Data=0;
6429
6430 u16Address = (INNER_FREEZE_DUMP>>16)&0xffff;
6431 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6432 u16Data|=(INNER_FREEZE_DUMP&0xffff);
6433 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6434
6435 return bRet;
6436 }
6437
INTERN_DVBS_DTV_InnerUnFreeze(void)6438 MS_BOOL INTERN_DVBS_DTV_InnerUnFreeze(void)
6439 {
6440 MS_BOOL bRet= TRUE;
6441 MS_U16 u16Address;
6442 MS_U16 u16Data=0;
6443
6444 u16Address = (INNER_FREEZE_DUMP>>16)&0xffff;
6445 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6446 u16Data&=~(INNER_FREEZE_DUMP&0xffff);
6447 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6448
6449 return bRet;
6450 }
6451 //------------------------------------------------------------------
6452 // END R/W Function
6453 //------------------------------------------------------------------
6454
6455
6456 /***********************************************************************************
6457 Subject: read register
6458 Function: MDrv_1210_IIC_Bypass_Mode
6459 Parmeter:
6460 Return:
6461 Remark:
6462 ************************************************************************************/
6463 //void MDrv_1210_IIC_Bypass_Mode(MS_BOOL enable)
6464 //{
6465 // UNUSED(enable);
6466 // if (enable)
6467 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x10); // IIC by-pass mode on
6468 // else
6469 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x00); // IIC by-pass mode off
6470 //}
6471
6472