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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102 //0312
103
104 #define _INTERN_DVBS_C_
105 #include <math.h>
106 #include "MsCommon.h"
107 #include "MsIRQ.h"
108 #include "MsOS.h"
109 //#include "apiPWS.h"
110
111 #include "MsTypes.h"
112 #include "drvBDMA.h"
113 //#include "drvIIC.h"
114 //#include "msAPI_Tuner.h"
115 //#include "msAPI_MIU.h"
116 //#include "BinInfo.h"
117 //#include "halVif.h"
118 #include "drvDMD_INTERN_DVBS.h"
119 #include "halDMD_INTERN_DVBS.h"
120 #include "halDMD_INTERN_common.h"
121
122 #include "drvMMIO.h"
123 //#include "TDAG4D01A_SSI_DVBT.c"
124 #include "drvDMD_VD_MBX.h"
125 //-----------------------------------------------------------------------
126 #define BIN_ID_INTERN_DVBS_DEMOD BIN_ID_INTERN_DVBS
127
128 //For DVBS
129 //#define DVBT2FEC_REG_BASE 0x3300
130 #define DVBS2OPPRO_REG_BASE 0x3E00
131 #define TOP_REG_BASE 0x2000 //DMDTOP
132 #define REG_BACKEND 0x1F00//_REG_BACKEND
133 #define DVBSFEC_REG_BASE 0x3F00
134 #define DVBS2FEC_REG_BASE 0x3300
135 #define DVBS2_REG_BASE 0x3A00
136 #define DVBS2_INNER_REG_BASE 0x3B00
137 #define DVBS2_INNER_EXT_REG_BASE 0x3C00
138 #define DVBS2_INNER_EXT2_REG_BASE 0x3D00
139 //#define DVBSTFEC_REG_BASE 0x2300 //DVBTFEC
140 #define FRONTEND_REG_BASE 0x2800
141 #define FRONTENDEXT_REG_BASE 0x2900
142 #define FRONTENDEXT2_REG_BASE 0x2A00
143 #define DMDANA_REG_BASE 0x2E00 //DMDDTOP//reg_dmdana.xls
144 #define DVBTM_REG_BASE 0x3400
145
146 #define SAMPLING_RATE_FS (144000)//(108000)//(96000)
147 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000)
148 #define INTERN_DVBS_TUNER_WAIT_TIMEOUT (50)
149
150 //#define DVBS2_Function (1)
151 //#define MSB131X_ADCPLL_IQ_SWAP 0
152 //#define INTERN_DVBS_TS_DATA_SWAP 0
153
154 //#define MS_DEBUG //enable debug dump
155
156 #ifdef MS_DEBUG
157 #define DBG_INTERN_DVBS(x) x
158 #define DBG_GET_SIGNAL_DVBS(x) x
159 #define DBG_INTERN_DVBS_TIME(x) x
160 #define DBG_INTERN_DVBS_LOCK(x) x
161 #define INTERN_DVBS_INTERNAL_DEBUG 1
162 #else
163 #define DBG_INTERN_DVBS(x) //x
164 #define DBG_GET_SIGNAL_DVBS(x) //x
165 #define DBG_INTERN_DVBS_TIME(x) //x
166 #define DBG_INTERN_DVBS_LOCK(x) //x
167 #define INTERN_DVBS_INTERNAL_DEBUG 0
168 #endif
169 //----------------------------------------------------------
170 #define DBG_DUMP_LOAD_DSP_TIME 0
171
172
173 #define SIGNAL_LEVEL_OFFSET 0.00f
174 #define TAKEOVERPOINT -60.0f
175 #define TAKEOVERRANGE 0.5f
176 #define LOG10_OFFSET -0.21f
177 #define INTERN_DVBS_USE_SAR_3_ENABLE 0
178 //extern MS_U32 msAPI_Timer_GetTime0(void);
179 //#define INTERN_DVBS_GET_TIME msAPI_Timer_GetTime0()
180
181
182 //Debug Info
183 //Lock/Done Flag
184 #define AGC_LOCK 0x28170100
185 #define DAGC0_LOCK 0x283B0001
186 #define DAGC1_LOCK 0x285B0001
187 #define DAGC2_LOCK 0x28620001 //ACIDAGC 1 2
188 #define DAGC3_LOCK 0x286E0001
189 #define DCR_LOCK 0x28220100
190 #define COARSE_SYMBOL_RATE_DONE 0x2A200001 //CSRD 1 2
191 #define FINE_SYMBOL_RATE_DONE 0x2A200008 //FSRD 1 2
192 #define POWER4CFO_DONE 0x29280100 //POWER4CFO 1 2
193 //#define CLOSE_COARSE_CFO_LOCK 0x244E0001
194 #define TR_LOCK 0x3B0E0100 //TR 1 2
195 #define PR_LOCK 0x3B401000
196 #define FRAME_SYNC_ACQUIRE 0x3B300001
197 #define EQ_LOCK 0x3B5A1000
198 #define P_SYNC_LOCK 0x22160002
199 #define IN_SYNC_LOCK 0x3F0D8000
200
201 //AGC / DAGC
202 #define DEBUG_SEL_IF_AGC_GAIN 0x28260003
203 #define DEBUG_SEL_AGC_ERR 0x28260004
204 #define DEBUG_OUT_AGC 0x2828
205
206 #define DEBUG_SEL_DAGC0_GAIN 0x28E80003
207 #define DEBUG_SEL_DAGC0_ERR 0x28E80001
208 #define DEBUG_SEL_DAGC0_PEAK_MEAN 0x28E80005
209 #define DEBUG_OUT_DAGC0 0x2878
210
211 #define DEBUG_SEL_DAGC1_GAIN 0x28E80003//???
212 #define DEBUG_SEL_DAGC1_ERR 0x28E80001
213 #define DEBUG_SEL_DAGC1_PEAK_MEAN 0x28E80005
214 #define DEBUG_OUT_DAGC1 0x28B8
215
216 #define DEBUG_SEL_DAGC2_GAIN 0x28E80003
217 #define DEBUG_SEL_DAGC2_ERR 0x28E80001
218 #define DEBUG_SEL_DAGC2_PEAK_MEAN 0x28E80005
219 #define DEBUG_OUT_DAGC2 0x28C4
220
221 #define DEBUG_SEL_DAGC3_GAIN 0x29DA0003
222 #define DEBUG_SEL_DAGC3_ERR 0x29DA0001
223 #define DEBUG_SEL_DAGC3_PEAK_MEAN 0x29DA0005
224 #define DEBUG_OUT_DAGC3 0x29DC
225
226 #define INNER_DEBUG_SEL_TR 0x24080D00 //TR
227 #define DEBUG_SEL_TR_SFO_CONVERGE 0x24080B00
228 #define DEBUG_SEL_TR_INPUT 0x24080F00
229
230 #define FRONTEND_FREEZE_DUMP 0x27028000
231 #define INNER_FREEZE_DUMP 0x24080010
232
233 #define DCR_OFFSET 0x2740
234 #define INNER_DEBUG_SEL 0x2408
235 #define INNEREXT_FINEFE_DBG_OUT0 0x2550
236 #define INNEREXT_FINEFE_DBG_OUT2 0x2552
237 #define INNEREXT_FINEFE_KI_FF0 0x2556
238 #define INNEREXT_FINEFE_KI_FF2 0x2558
239 #define INNEREXT_FINEFE_KI_FF4 0x255A
240 #define INNER_PR_DEBUG_OUT0 0x2486
241 #define INNER_PR_DEBUG_OUT2 0x2488
242
243 #define IIS_COUNT0 0x2746
244 #define IIS_COUNT2 0x2748
245 #define IQB_PHASE 0x2766
246 #define IQB_GAIN 0x2768
247 #define TR_INDICATOR_FF0 0x2454
248 #define TR_INDICATOR_FF2 0x2456
249 #define INNER_TR_LOPF_VALUE_DEBUG0 0x2444
250 #define INNER_TR_LOPF_VALUE_DEBUG2 0x2446
251 #define INNER_TR_LOPF_VALUE_DEBUG4 0x2448
252 //------------------------------------------------------------
253 //Init Mailbox parameter.
254 #define INTERN_DVBS_TS_SERIAL_INVERSION 0
255 //For Parameter Init Setting
256 #define A_S2_ZIF_EN 0x01 //[0]
257 #define A_S2_RF_AGC_EN 0x00 //[0]
258 #define A_S2_DCR_EN 0x00 //[0] 0=Auto :1=Force
259 #define A_S2_IQB_EN 0x01 //[2]
260 #define A_S2_IIS_EN 0x00 //[0]
261 #define A_S2_CCI_EN 0x00 //[0] 0:1=Enable
262 #define A_S2_FORCE_ACI_SELECT 0xFF //[3:0] 0xFF=OFF(internal default)
263 #define A_S2_IQ_SWAP 0x01 //[0]
264 #define A_S2_AGC_REF_EXT_0 0x00 //[7:0] //0x00 0x90
265 #define A_S2_AGC_REF_EXT_1 0x02 //[11:8] //0x02 0x07
266 #define A_S2_AGC_K 0x07 //[15:12]
267 #define A_S2_ADCI_GAIN 0x0F //[4:0]
268 #define A_S2_ADCQ_GAIN 0x0F //[12:8]
269 #define A_S2_SRD_SIG_SRCH_RNG 0x6A //[7:0]
270 #define A_S2_SRD_DC_EXC_RNG 0x16 //[7:0]
271 //FRONTENDEXT_SRD_FRC_CFO
272 #define A_S2_FORCE_CFO_0 0x00 //[7:0]
273 #define A_S2_FORCE_CFO_1 0x00 //[11:8]
274 #define A_S2_DECIMATION_NUM 0x00 //[3:0] 00=(Internal Default)
275 #define A_S2_PSD_SMTH_TAP 0x29 //[6:0] Bit7 no define.
276 //CCI Parameter
277 //Set_Tuner_BW=(((U16)REG_BASE[DIG_SWUSE1FH]<<8)|REG_BASE[DIG_SWUSE1FL]);
278 #define A_S2_CCI_FREQN_0_L 0x00 //[7:0]
279 #define A_S2_CCI_FREQN_0_H 0x00 //[11:8]
280 #define A_S2_CCI_FREQN_1_L 0x00 //[7:0]
281 #define A_S2_CCI_FREQN_1_H 0x00 //[11:8]
282 #define A_S2_CCI_FREQN_2_L 0x00 //[7:0]
283 #define A_S2_CCI_FREQN_2_H 0x00 //[11:8]
284 //Inner TR Parameter
285 #define A_S2_TR_LOPF_KP 0x00 //[4:0] 00=(Internal Default)
286 #define A_S2_TR_LOPF_KI 0x00 //[4:0] 00=(Internal Default)
287 //Inner FineFE Parameter
288 #define A_S2_FINEFE_KI_SWITCH_0 0x00 //[15:12] 00=(Internal Default)
289 #define A_S2_FINEFE_KI_SWITCH_1 0x00 //[3:0] 00=(Internal Default)
290 #define A_S2_FINEFE_KI_SWITCH_2 0x00 //[7:4] 00=(Internal Default)
291 #define A_S2_FINEFE_KI_SWITCH_3 0x00 //[11:8] 00=(Internal Default)
292 #define A_S2_FINEFE_KI_SWITCH_4 0x00 //[15:12] 00=(Internal Default)
293 //Inner PR KP Parameter
294 #define A_S2_PR_KP_SWITCH_0 0x00 //[11:8] 00=(Internal Default)
295 #define A_S2_PR_KP_SWITCH_1 0x00 //[15:12] 00=(Internal Default)
296 #define A_S2_PR_KP_SWITCH_2 0x00 //[3:0] 00=(Internal Default)
297 #define A_S2_PR_KP_SWITCH_3 0x00 //[7:4] 00=(Internal Default)
298 #define A_S2_PR_KP_SWITCH_4 0x00 //[11:8] 00=(Internal Default)
299 //Inner FS Parameter
300 #define A_S2_FS_GAMMA 0x10 //[7:0]
301 #define A_S2_FS_ALPHA0 0x10 //[7:0]
302 #define A_S2_FS_ALPHA1 0x10 //[7:0]
303 #define A_S2_FS_ALPHA2 0x10 //[7:0]
304 #define A_S2_FS_ALPHA3 0x10 //[7:0]
305
306 #define A_S2_FS_H_MODE_SEL 0x01 //[0]
307 #define A_S2_FS_OBSWIN 0x08 //[12:8]
308 #define A_S2_FS_PEAK_DET_TH_L 0x00 //[7:0]
309 #define A_S2_FS_PEAK_DET_TH_H 0x01 //[15:8]
310 #define A_S2_FS_CONFIRM_NUM 0x01 //[3:0]
311 //Inner EQ Parameter
312 #define A_S2_EQ_MU_FFE_DA 0x00 //[3:0] 00=(Internal Default)
313 #define A_S2_EQ_MU_FFE_DD 0x00 //[7:4] 00=(Internal Default)
314 #define A_S2_EQ_ALPHA_SNR_DA 0x00 //[7:4] 00=(Internal Default)
315 #define A_S2_EQ_ALPHA_SNR_DD 0x00 //[11:8] 00=(Internal Default)
316 //Outer FEC Parameter
317 #define A_S2_FEC_ALFA 0x00 //[12:8]
318 #define A_S2_FEC_BETA 0x01 //[7:4]
319 #define A_S2_FEC_SCALING_LLR 0x00 //[7:0] 00=(Internal Default)
320 //TS Parameter
321 #if INTERN_DVBS_TS_SERIAL_INVERSION
322 #define A_S2_TS_SERIAL 0x01 //[0]
323 #else
324 #define A_S2_TS_SERIAL 0x00 //[0]
325 #endif
326 #define A_S2_TS_CLK_RATE 0x00
327 #define A_S2_TS_OUT_INV 0x00 //[5]
328 #define A_S2_TS_DATA_SWAP 0x00 //[5]
329 //Rev Parameter
330
331 #define A_S2_FW_VERSION_L 0x00 //From FW
332 #define A_S2_FW_VERSION_H 0x00 //From FW
333 #define A_S2_CHIP_VERSION 0x01
334 #define A_S2_FS_L 0x00
335 #define A_S2_FS_H 0x00
336 #define A_S2_MANUAL_TUNE_SYMBOLRATE_L 0x20
337 #define A_S2_MANUAL_TUNE_SYMBOLRATE_H 0x4E
338
339 MS_U8 INTERN_DVBS_DSPREG[] =
340 {
341 A_S2_ZIF_EN, A_S2_RF_AGC_EN, A_S2_DCR_EN, A_S2_IQB_EN, A_S2_IIS_EN, A_S2_CCI_EN, A_S2_FORCE_ACI_SELECT, A_S2_IQ_SWAP, // 00H ~ 07H
342 A_S2_AGC_REF_EXT_0, A_S2_AGC_REF_EXT_1, A_S2_AGC_K, A_S2_ADCI_GAIN, A_S2_ADCQ_GAIN, A_S2_SRD_SIG_SRCH_RNG, A_S2_SRD_DC_EXC_RNG, A_S2_FORCE_CFO_0, // 08H ~ 0FH
343 A_S2_FORCE_CFO_1, A_S2_DECIMATION_NUM, A_S2_PSD_SMTH_TAP, A_S2_CCI_FREQN_0_L, A_S2_CCI_FREQN_0_H, A_S2_CCI_FREQN_1_L, A_S2_CCI_FREQN_1_H, A_S2_CCI_FREQN_2_L, // 10H ~ 17H
344 A_S2_CCI_FREQN_2_H, A_S2_TR_LOPF_KP, A_S2_TR_LOPF_KI, A_S2_FINEFE_KI_SWITCH_0, A_S2_FINEFE_KI_SWITCH_1, A_S2_FINEFE_KI_SWITCH_2, A_S2_FINEFE_KI_SWITCH_3, A_S2_FINEFE_KI_SWITCH_4, // 18H ~ 1FH
345 A_S2_PR_KP_SWITCH_0, A_S2_PR_KP_SWITCH_1, A_S2_PR_KP_SWITCH_2, A_S2_PR_KP_SWITCH_3, A_S2_PR_KP_SWITCH_4, A_S2_FS_GAMMA, A_S2_FS_ALPHA0, A_S2_FS_ALPHA1, // 20H ~ 27H
346 A_S2_FS_ALPHA2, A_S2_FS_ALPHA3, A_S2_FS_H_MODE_SEL, A_S2_FS_OBSWIN, A_S2_FS_PEAK_DET_TH_L, A_S2_FS_PEAK_DET_TH_H, A_S2_FS_CONFIRM_NUM, A_S2_EQ_MU_FFE_DA, // 28h ~ 2FH
347 A_S2_EQ_MU_FFE_DD, A_S2_EQ_ALPHA_SNR_DA, A_S2_EQ_ALPHA_SNR_DD, A_S2_FEC_ALFA, A_S2_FEC_BETA, A_S2_FEC_SCALING_LLR, A_S2_TS_SERIAL, A_S2_TS_CLK_RATE, // 30H ~ 37H
348 A_S2_TS_OUT_INV, A_S2_TS_DATA_SWAP, A_S2_FW_VERSION_L, A_S2_FW_VERSION_H, A_S2_CHIP_VERSION, A_S2_FS_L, A_S2_FS_H, A_S2_MANUAL_TUNE_SYMBOLRATE_L, // 38H ~ 3CH
349 A_S2_MANUAL_TUNE_SYMBOLRATE_H,
350 };
351
352 /****************************************************************
353 *Local Variables *
354 ****************************************************************/
355
356
357 static MS_U16 _u16SignalLevel[185][2]=
358 {//AV2028 SR=22M, 2/3 CN=5.9
359 {255, 920},{255, 915},{255, 910},{255, 905},{255, 900},{255, 895},{255, 890},{255, 885},{255, 880},{255, 875},
360 {255, 870},{255, 865},{255, 860},{255, 855},{255, 850},{2121, 845},{3988, 840},{11629, 835},{19270, 830},{19744, 825},
361 {20218, 820},{20692, 815},{21166, 810},{21640, 805},{22114, 800},{22350, 795},{22587, 790},{22823, 785},{23059, 780},{23296, 775},
362 {23532, 770},{23790, 765},{24049, 760},{24307, 755},{24566, 750},{24777, 745},{24988, 740},{25198, 735},{25409, 730},{25548, 725},
363 {25687, 720},{25826, 715},{25965, 710},{26104, 705},{26242, 700},{26311, 695},{26380, 690},{26449, 685},{26517, 680},{26586, 675},
364 {26655, 670},{26723, 665},{26792, 660},{26861, 655},{26929, 650},{27079, 645},{27229, 640},{27379, 635},{27529, 630},{27733, 625},
365 {27937, 620},{28140, 615},{28344, 610},{28547, 605},{28751, 600},{28763, 595},{28775, 590},{28787, 585},{28800, 580},{28812, 575},
366 {28824, 570},{29001, 565},{29178, 560},{29354, 555},{29531, 550},{29603, 545},{29674, 540},{29746, 535},{29818, 530},{29890, 525},
367 {29961, 520},{30033, 515},{30105, 510},{30177, 505},{30248, 500},{30382, 495},{30497, 490},{30593, 485},{30718, 480},{30803, 475},
368 {30899, 470},{30981, 465},{31074, 460},{31150, 455},{31238, 450},{31320, 445},{31373, 440},{31459, 435},{31529, 430},{31610, 425},
369 {31696, 420},{31735, 415},{31794, 410},{31839, 405},{31901, 400},{31974, 395},{32040, 390},{32078, 385},{32156, 380},{32205, 375},
370 {32255, 370},{32305, 365},{32347, 360},{32389, 355},{32435, 350},{32452, 345},{32470, 340},{32540, 335},{32590, 330},{32650, 325},
371 {32710, 320},{32740, 315},{32790, 310},{32830, 305},{32870, 300},{32920, 295},{32950, 290},{32990, 285},{33040, 280},{33090, 275},
372 {33130, 270},{33160, 265},{33180, 260},{33230, 255},{33270, 250},{33300, 245},{33330, 240},{33390, 235},{33440, 230},{33470, 225},
373 {33480, 220},{33550, 215},{33610, 210},{33650, 205},{33710, 200},{33730, 195},{33790, 190},{33830, 185},{33900, 180},{33940, 175},
374 {34010, 170},{34050, 165},{34100, 160},{34140, 155},{34190, 150},{34250, 145},{34300, 140},{34390, 135},{34450, 130},{34510, 125},
375 {34550, 120},{34610, 115},{34670, 110},{34730, 105},{34770, 100},{34850, 95},{34920, 90},{34990, 85},{35040, 80},{35120, 75},
376 {35140, 70},{35210, 65},{35290, 60},{35320, 55},{35350, 50},{35420, 45},{35500, 40},{35530, 35},{35560, 30},{35600, 25},
377 {35670, 20},{35700, 15},{35720, 10},{35770, 5},{35780, 0}
378 };
379
380 /*
381 {//AV2028 SR=22M, 2/3 CN=5.9
382 {32100, 920},{32200, 915},{32350, 910},{32390, 905},{32480, 900},{32550, 895},{32620, 890},{32680, 885},{32750, 880},{32830, 875},
383 {32930, 870},{33010, 865},{33100, 860},{33200, 855},{33310, 850},{33410, 845},{33520, 840},{33640, 835},{33770, 830},{33900, 825},
384 {34030, 820},{34150, 815},{34290, 810},{34390, 805},{34490, 800},{34580, 795},{34700, 790},{34800, 785},{34880, 780},{34940, 775},
385 {35030, 770},{35130, 765},{35180, 760},{35260, 755},{35310, 750},{35340, 745},{35380, 740},{35400, 735},{35450, 730},{35550, 725},
386 {35620, 720},{35700, 715},{35800, 710},{35890, 705},{36000, 700},{36120, 695},{36180, 690},{36280, 685},{36400, 680},{36570, 675},
387 {36730, 670},{36910, 665},{37060, 660},{37100, 655},{37260, 650},{37340, 645},{37410, 640},{37580, 635},{37670, 630},{37700, 625},
388 {37750, 620},{37800, 615},{37860, 610},{37980, 605},{38050, 600},{38170, 595},{38370, 590},{38540, 585},{38710, 580},{38870, 575},
389 {39020, 570},{39070, 565},{39100, 560},{39180, 555},{39280, 550},{39460, 545},{39510, 540},{39600, 535},{39620, 530},{39680, 525},
390 {39720, 520},{39830, 515},{39880, 510},{39930, 505},{39960, 500},{40000, 495},{40200, 490},{40360, 485},{40540, 480},{40730, 475},
391 {40880, 470},{41020, 465},{41150, 460},{41280, 455},{41410, 450},{41520, 445},{41620, 440},{41730, 435},{41840, 430},{41930, 425},
392 {42010, 420},{42100, 415},{42180, 410},{42260, 405},{42350, 400},{42440, 395},{42520, 390},{42580, 385},{42660, 380},{42730, 375},
393 {42800, 370},{42870, 365},{42940, 360},{43000, 355},{43060, 350},{43130, 345},{43180, 340},{43250, 335},{43310, 330},{43370, 325},
394 {43420, 320},{43460, 315},{43520, 310},{43570, 305},{43620, 300},{43660, 295},{43710, 290},{43750, 285},{43810, 280},{43860, 275},
395 {43910, 270},{43940, 265},{43990, 260},{44020, 255},{44060, 250},{44110, 245},{44140, 240},{44190, 235},{44230, 230},{44270, 225},
396 {44320, 220},{44370, 215},{44400, 210},{44450, 205},{44490, 200},{44530, 195},{44590, 190},{44630, 185},{44660, 180},{44720, 175},
397 {44750, 170},{44790, 165},{44830, 160},{44880, 155},{44910, 150},{44960, 145},{45000, 140},{45030, 135},{45070, 130},{45100, 125},
398 {45130, 120},{45160, 115},{45200, 110},{45240, 105},{45270, 100},{45300, 95},{45330, 90},{45360, 85},{45400, 80},{45430, 75},
399 {45460, 70},{45490, 65},{45530, 60},{45560, 55},{45590, 50},{45630, 45},{45670, 40},{45690, 35},{45740, 30},{45760, 25},
400 {45800, 20},{45830, 15},{45860, 10},{45880, 5},{45920, 0}
401 };
402 */
403
404 MS_U8 u8DemodLockFlag;
405 MS_U8 modulation_order;
406 static MS_BOOL _bDemodType=FALSE;//DVBS:FALSE ; S2:TRUE
407 //static MS_BOOL TPSLock = 0;
408 static MS_U32 u32ChkScanTimeStartDVBS = 0;
409 static MS_U8 g_dvbs_lock = 0;
410 //static float intern_dvb_s_qam_ref[] = {3.0, 0.0, 0.0, 0.0, 0.0, 80.0}; //16q,32q,64q,128q,256q, and others
411 static MS_U8 _u8_DVBS2_CurrentCodeRate;
412 static float _fPostBer=0;
413 static float _f_DVBS_CurrentSNR=0;
414 static MS_U8 _u8ToneBurstFlag=0;
415 static MS_U16 _u16BlindScanStartFreq=0;
416 static MS_U16 _u16BlindScanEndFreq=0;
417 static MS_U16 _u16TunerCenterFreq=0;
418 static MS_U16 _u16ChannelInfoIndex=0;
419 //Debug Only+
420 static MS_U16 _u16NextCenterFreq=0;
421 static MS_U16 _u16LockedSymbolRate=0;
422 static MS_U16 _u16LockedCenterFreq=0;
423 static MS_U16 _u16PreLockedHB=0;
424 static MS_U16 _u16PreLockedLB=0;
425 static MS_U16 _u16CurrentSymbolRate=0;
426 static MS_S16 _s16CurrentCFO=0;
427 static MS_U16 _u16CurrentStepSize=0;
428 //Debug Only-
429 static MS_U16 _u16ChannelInfoArray[2][1000];
430 //static MS_U32 _u32CurrentSR=0;
431 static MS_BOOL _bSerialTS=FALSE;
432 static MS_BOOL _bTSDataSwap=FALSE;
433
434 //Global Variables
435 S_CMDPKTREG gsCmdPacketDVBS;
436 //MS_U8 gCalIdacCh0, gCalIdacCh1;
437 static MS_BOOL bDMD_DVBS_NoChannelDetectedWithRFPower = FALSE;
438 static MS_U32 u32DMD_DVBS_NoChannelTimeAccWithRFPower = 0;
439 extern MS_U32 u32DMD_DVBS2_DJB_START_ADDR;
440 #ifdef INTERN_DVBS_LOAD_FW_FROM_CODE_MEMORY
441 MS_U8 INTERN_DVBS_table[] =
442 {
443 #include "fwDMD_INTERN_DVBS.dat"
444 };
445
446 #endif
447
448 MS_BOOL INTERN_DVBS_Show_Demod_Version(void);
449 MS_BOOL INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE *pQAMMode);
450 MS_BOOL INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE *pDemodType);
451 MS_BOOL INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE *pCodeRate);
452 MS_BOOL INTERN_DVBS_GetCurrentSymbolRate(MS_U32 *u32SymbolRate);
453 MS_BOOL INTERN_DVBS_GetCurrentSymbolRateOffset(MS_U16 *pData);
454
455 #if (INTERN_DVBS_INTERNAL_DEBUG)
456 void INTERN_DVBS_info(void);
457 MS_BOOL INTERN_DVBS_Show_AGC_Info(void);
458 #endif
459
460 //------------------------------------------------------------------
461 // System Info Function
462 //------------------------------------------------------------------
463 //=====================================================================================
INTERN_DVBS_DSPReg_Init(const MS_U8 * u8DVBS_DSPReg,MS_U8 u8Size)464 MS_U16 INTERN_DVBS_DSPReg_Init(const MS_U8 *u8DVBS_DSPReg, MS_U8 u8Size)
465 {
466 #if 0
467 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
468 #endif
469 MS_U8 status = true;
470 #if 0
471 MS_U16 u16DspAddr = 0;
472 #endif
473 DBG_INTERN_DVBS(printf("INTERN_DVBS_DSPReg_Init\n"));
474
475 #if 0//def MS_DEBUG
476 {
477 MS_U8 u8buffer[256];
478 printf("INTERN_DVBS_DSPReg_Init Reset\n");
479 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
480 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, 0);
481
482 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
483 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
484 printf("INTERN_DVBS_DSPReg_Init ReadBack, should be all 0\n");
485 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
486 printf("%x ", u8buffer[idx]);
487 printf("\n");
488
489 printf("INTERN_DVBS_DSPReg_Init Value\n");
490 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
491 printf("%x ", INTERN_DVBS_DSPREG[idx]);
492 printf("\n");
493 }
494 #endif
495
496 //for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
497 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBS_DSPREG[idx]);
498
499 // readback to confirm.
500 // ~read this to check mailbox initial values
501 #if 0
502 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
503 {
504 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &u8RegRead);
505 if (u8RegRead != INTERN_DVBS_DSPREG[idx])
506 {
507 DBG_INTERN_DVBS(printf("[Error]INTERN_DVBS_DSPReg_Init, idx=%d, drv_val=0x%x, firmware_val=0x%x\n",idx,INTERN_DVBS_DSPREG[idx],u8RegRead));
508 }
509 }
510 #endif
511 #if 0
512 if (u8DVBS_DSPReg != NULL)
513 {
514 if (1 == u8DVBS_DSPReg[0])
515 {
516 u8DVBS_DSPReg+=2;
517 for (idx = 0; idx<u8Size; idx++)
518 {
519 u16DspAddr = *u8DVBS_DSPReg;
520 u8DVBS_DSPReg++;
521 u16DspAddr = (u16DspAddr) + ((*u8DVBS_DSPReg)<<8);
522 u8DVBS_DSPReg++;
523 u8Mask = *u8DVBS_DSPReg;
524 u8DVBS_DSPReg++;
525 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
526 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBS_DSPReg) & (u8Mask));
527 u8DVBS_DSPReg++;
528 DBG_INTERN_DVBS(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
529 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
530 }
531 }
532 else
533 {
534 DBG_INTERN_DVBS(printf("FATAL: parameter version incorrect\n"));
535 }
536 }
537 #endif
538 #if 0//def MS_DEBUG
539 {
540 MS_U8 u8buffer[256];
541 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
542 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
543 printf("INTERN_DVBC_DSPReg_Init ReadBack\n");
544 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
545 printf("%x ", u8buffer[idx]);
546 printf("\n");
547 }
548 #endif
549
550 #if 0//def MS_DEBUG
551 {
552 MS_U8 u8buffer[256];
553 for (idx = 0; idx<128; idx++)
554 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2380+idx, &(u8buffer[idx]));
555 printf("INTERN_DVBS_DSPReg_Init ReadReg 0x2000~0x207F\n");
556 for (idx = 0; idx<128; idx++)
557 {
558 printf("%x ", u8buffer[idx]);
559 if ((idx & 0xF) == 0xF) printf("\n");
560 }
561 printf("\n");
562 }
563 #endif
564 return status;
565 }
566
567 /***********************************************************************************
568 Subject: Command Packet Interface
569 Function: INTERN_DVBS_Cmd_Packet_Send
570 Parmeter:
571 Return: MS_BOOL
572 Remark:
573 ************************************************************************************/
INTERN_DVBS_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)574 MS_BOOL INTERN_DVBS_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
575 {
576 MS_U8 status = true, indx;
577 MS_U8 reg_val, timeout = 0;
578 return true;
579
580 // ==== Command Phase ===================
581 DBG_INTERN_DVBS(printf("--->INTERN_DVBS (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
582 pCmdPacket->param[0],pCmdPacket->param[1],
583 pCmdPacket->param[2],pCmdPacket->param[3],
584 pCmdPacket->param[4],pCmdPacket->param[5] ));
585
586 // wait _BIT_END clear
587 do
588 {
589 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
590 if((reg_val & _BIT_END) != _BIT_END)
591 {
592 break;
593 }
594 MsOS_DelayTask(5);
595 if (timeout > 200)
596 {
597 DBG_INTERN_DVBS(printf("---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n"));
598 return false;
599 }
600 timeout++;
601 } while (1);
602
603 // set cmd_3:0 and _BIT_START
604 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
605 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
606 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
607
608
609 //DBG_INTERN_DVBS(printf("demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
610 // wait _BIT_START clear
611 do
612 {
613 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
614 if((reg_val & _BIT_START) != _BIT_START)
615 {
616 break;
617 }
618 MsOS_DelayTask(10);
619 if (timeout > 200)
620 {
621 DBG_INTERN_DVBS(printf("---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n"));
622 return false;
623 }
624 timeout++;
625 } while (1);
626
627 // ==== Data Phase ======================
628
629 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
630
631 for (indx = 0; indx < param_cnt; indx++)
632 {
633 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
634 //DBG_INTERN_DVBS(printf("demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
635
636 // set param[indx] and _BIT_DRQ
637 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
638 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
639 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
640
641 // wait _BIT_DRQ clear
642 do
643 {
644 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
645 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
646 {
647 break;
648 }
649 MsOS_DelayTask(5);
650 if (timeout > 200)
651 {
652 DBG_INTERN_DVBS(printf("---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n"));
653 return false;
654 }
655 timeout++;
656 } while (1);
657 }
658
659 // ==== End Phase =======================
660
661 // set _BIT_END to finish command
662 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
663 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
664
665 return status;
666 }
667
668 /***********************************************************************************
669 Subject: Command Packet Interface
670 Function: INTERN_DVBS_Cmd_Packet_Exe_Check
671 Parmeter:
672 Return: MS_BOOL
673 Remark:
674 ************************************************************************************/
INTERN_DVBS_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)675 MS_BOOL INTERN_DVBS_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
676 {
677 return TRUE;
678 }
679
680 /***********************************************************************************
681 Subject: SoftStop
682 Function: INTERN_DVBS_SoftStop
683 Parmeter:
684 Return: MS_BOOL
685 Remark:
686 ************************************************************************************/
INTERN_DVBS_SoftStop(void)687 MS_BOOL INTERN_DVBS_SoftStop ( void )
688 {
689 #if 1
690 MS_U16 u16WaitCnt=0;
691
692 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
693 {
694 DBG_INTERN_DVBS(printf(">> MB Busy!\n"));
695 return FALSE;
696 }
697
698 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
699
700 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
701 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
702
703 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
704 {
705 if (u16WaitCnt++ >= 0xFFF)// 0xFF)
706 {
707 DBG_INTERN_DVBS(printf(">> DVBT SoftStop Fail!\n"));
708 return FALSE;
709 }
710 }
711
712 //HAL_DMD_RIU_WriteByte(0x103460, 0x01); // reset VD_MCU
713 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
714 #endif
715 return TRUE;
716 }
717
718 /***********************************************************************************
719 Subject: Reset
720 Function: INTERN_DVBC_Reset
721 Parmeter:
722 Return: MS_BOOL
723 Remark:
724 ************************************************************************************/
725 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
726
INTERN_DVBS_Reset(void)727 MS_BOOL INTERN_DVBS_Reset ( void )// no midify
728 {
729 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_reset\n"));
730
731 DBG_INTERN_DVBS_TIME(printf("INTERN_DVBS_Reset, t = %d\n",MsOS_GetSystemTime()));
732
733 //INTERN_DVBS_SoftStop();
734
735
736 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
737
738 MsOS_DelayTask(1);
739 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
740
741 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
742 MsOS_DelayTask(5);
743
744 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
745 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
746
747 u32ChkScanTimeStartDVBS = MsOS_GetSystemTime();
748 g_dvbs_lock = 0;
749
750 return TRUE;
751 }
INTERN_DVBS_PowerSaving(void)752 MS_BOOL INTERN_DVBS_PowerSaving ( void )
753 {
754 MS_U8 i;
755
756 //---P2=0---/;
757 for( i = 0; i < 231; i++){
758 MDrv_SYS_DMD_VD_MBX_WriteReg(0x350A + i, 0x11);}
759 // `M3_RIU_W((`RIUBASE_DMD_CLKGEN>>1)+7'h40, 2'b01, 16'h0000);
760 MDrv_SYS_DMD_VD_MBX_WriteReg(0x3580, 0x00);
761
762 //---P2=1---/;
763 for( i = 0; i < 146; i++){
764 MDrv_SYS_DMD_VD_MBX_WriteReg(0xA202 + i, 0x11);}
765 // `M3_RIU_W((`RIUBASE_DMD_CLKGEN_EXT>>1)+7'h14, 2'b01, 16'h0003);
766 MDrv_SYS_DMD_VD_MBX_WriteReg(0xA228, 0x03);
767
768 // ================================================================
769 // DEMOD_1 CLOCK GATED
770 // ================================================================
771 //---P2=0---/;
772 for( i = 0; i <= 177; i++){
773 MDrv_SYS_DMD_VD_MBX_WriteReg(0x3635+ i, 0x11);}
774 // `M3_RIU_W((`RIUBASE_DMD_CLKGEN_1>>1)+7'h1b, 2'b01, 16'h000f);
775 MDrv_SYS_DMD_VD_MBX_WriteReg(0x3636, 0x0f);
776
777
778 // ================================================================
779 // SRAM Power Down
780 // ================================================================
781 // [ 0]reg_force_allsram_on = 1'b0
782 // [ 1]reg_force_allsram_on_demod_1 = 1'b0
783 // [ 2] = 1'b0
784 // [ 3]reg_demod_1_sram_sd_en = 1'b0
785 // [ 4]reg_manhattan_sram_share_sram_sd_en = 1'b0
786 // [ 5]reg_mulan_sram_share_sram_sd_en = 1'b0
787 // [ 6]reg_dvb_frontend_sram_sd_en = 1'b0
788 // [ 7]reg_dtmb_sram_sd_en = 1'b0
789 // [ 8]reg_dvbt_sram_sd_en = 1'b0
790 // [ 9]reg_atsc_sram_sd_en = 1'b0
791 // [10]reg_vif_sram_sd_en = 1'b0
792 // [11]reg_backend_sram_sd_en = 1'b0
793 // [12]reg_adcdma_sram_sd_en = 1'b0
794 // [13]reg_isdbt_sram_sd_en = 1'b0
795 // [14]reg_dvbt2_sram_sd_en = 1'b0
796 // [15]reg_dvbs2_sram_sd_en = 1'b0
797 // `M3_RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h48, 2'b11, 16'hfffc);
798 // `M3_RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h48, 2'b11, 16'hfffc);
799 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2091, 0xff);
800 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2090, 0xfc);
801
802 // all controlled by reg_mulan_sram_share_sram_sd_en
803 // reg_sram_pwr_ctrl_sel[15:0]
804 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h70, 2'b11, 16'h0000);
805 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h70, 2'b11, 16'h0000);
806 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e1, 0x00);
807 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e0, 0x00);
808 // reg_sram_pwr_ctrl_sel[31:16]
809 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h71, 2'b11, 16'h0000);
810 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h71, 2'b11, 16'h0000);
811 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e3, 0x00);
812 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e2, 0x00);
813 // reg_sram_pwr_ctrl_sel[47:32]
814 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h72, 2'b11, 16'h0000);
815 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h72, 2'b11, 16'h0000);
816 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e5, 0x00);
817 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e4, 0x00);
818 // reg_sram_pwr_ctrl_sel[63:48]
819 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h73, 2'b11, 16'h0000);
820 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h73, 2'b11, 16'h0000);
821 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e7, 0x00);
822 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e6, 0x00);
823 // reg_sram_pwr_ctrl_sel[79:64]
824 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h74, 2'b11, 16'h0000);
825 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h74, 2'b11, 16'h0000);
826 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e9, 0x00);
827 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e8, 0x00);
828
829 // $display("================================================================");
830 // $display("Reset");
831 // $display("================================================================");
832 // Release DVBT2 & dmd_ana_misc Reset
833 // [0] reg_atsc_on[0]
834 // [1] reg_dvbt_on[1]
835 // [2] reg_vif_on[2]
836 // [3] reg_isdbt_on[3]
837 // [4] reg_atsc_rst[4]
838 // [5] reg_dvbt_rst[5]
839 // [6] reg_vif_rst[6]
840 // [7] reg_get_adc[7]
841 // [8] reg_ce8x_gate[8]
842 // [9] reg_ce_gate[9]
843 // [10] reg_dac_clk_inv[10]
844 // [11] reg_vdmcu_clock_faster[11]
845 // [12] reg_vif_if_agc_sel[12]
846 // [13] reg_dmd_ana_misc_rst[13]
847 // [14] reg_adcd_wmask[14]
848 // [15] reg_sif_only[15]
849 // `M3_RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h01, 2'b11, 16'h2070);
850
851 // Release DTMB Reset & Enable Manhattan frontend Enable
852 // [0] reg_dtmb_on
853 // [1] reg_dtmb_rst
854 // [4] reg_manhattan_frontend_on //No used @ Maserati
855 // [5] reg_manhattan_dvb_srd_sw_rst (1'b1 for DTMB)
856 // `M3_RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h02, 2'b01, 16'h0022);
857
858 // ================================================================
859 // MPLL Power Down
860 // ================================================================
861 // Set MPLL_ADC_DIV_SE
862 // [0] : reg_mpll_adc_clk_cc_en
863 // [1] : reg_adc_clk_pd
864 // [2] : reg_mpll_div2_pd
865 // [3] : reg_mpll_div3_pd
866 // [4] : reg_mpll_div4_pd
867 // [5] : reg_mpll_div8_pd
868 // [6] : reg_mpll_div10_pd
869 // [7] : reg_mpll_div17_pd
870 // [13:8]: reg_mpll_adc_div_sel
871 // `M3_RIU_W((`RIUBASE_DMD_ANA_MISC_M3>>1)+7'h30, 2'b01, 16'h12fe);//Different
872 // `M3_RIU_W((`RIUBASE_DMD_ANA_MISC_M3>>1)+7'h30, 2'b01, 16'h12fe);//Different
873 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2e60, 0xfe);
874
875 // [2:0] : reg_mpll_ictrl set 3'h3
876 // [3] : reg_mpll_in_sel set 1'h0
877 // [4] : reg_mpll_xtal2adc_sel if 1'h1 ADC_CLK=XTAL.
878 // [5] : reg_mpll_xtal2next_pll_sel
879 // [6] : reg_mpll_vco_offset(T8), reg_mpll_adc_clk_cc_mode(T9)
880 // [7] : reg_mpll_pd set 1'b1
881 // [8] : reg_xtal_en set 1'b0
882 // [10:9]: reg_xtal_sel set 2'h3 XTAL strength
883 // [11] : reg_mpll_porst set 1'b1
884 // [12] : reg_mpll_reset set 1'b1
885 // [13] : reg_pd_dmpll_clk XTAL to MPLL clock reference power down
886 // [14] : reg_mpll_pdiv_clk_pd set 1'b0
887 // Set MPLL_RESET=MPLL_PORST=1
888 // `M3_RIU_W((`RIUBASE_DMD_ANA_MISC_M3>>1)+7'h35, 2'b11, 16'h1e83);//Different
889 // `M3_RIU_W((`RIUBASE_DMD_ANA_MISC_M3>>1)+7'h35, 2'b11, 16'h1e83);//Different
890 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2e6b, 0x1e);
891 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2e6a, 0x83);
892
893 return TRUE;
894 }
895 /***********************************************************************************
896 Subject: Exit
897 Function: INTERN_DVBC_Exit
898 Parmeter:
899 Return: MS_BOOL
900 Remark:
901 ************************************************************************************/
INTERN_DVBS_Exit(void)902 MS_BOOL INTERN_DVBS_Exit ( void )
903 {
904 MS_U8 u8Data=0;
905 MS_U8 u8Data_temp=0;
906
907 u8Data_temp=HAL_DMD_RIU_ReadByte(0x101E39);
908 HAL_DMD_RIU_WriteByte(0x101E39, 0);
909
910 u8Data=HAL_DMD_RIU_ReadByte(0x1128C0);
911 u8Data&=~(0x02);
912 HAL_DMD_RIU_WriteByte(0x1128C0, u8Data);//revert IQ Swap status
913
914 HAL_DMD_RIU_WriteByte(0x101E39, u8Data_temp);
915 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_Exit\n"));
916 INTERN_DVBS_SoftStop();
917 INTERN_DVBS_PowerSaving();
918
919 return TRUE;
920 }
921
922 /***********************************************************************************
923 Subject: Load DSP code to chip
924 Function: INTERN_DVBS_LoadDSPCode
925 Parmeter:
926 Return: MS_BOOL
927 Remark:
928 ************************************************************************************/
INTERN_DVBS_LoadDSPCode(void)929 static MS_BOOL INTERN_DVBS_LoadDSPCode(void)
930 {
931 MS_U8 udata = 0x00;
932 MS_U16 i;
933 MS_U16 fail_cnt=0;
934
935 #if (DBG_DUMP_LOAD_DSP_TIME==1)
936 MS_U32 u32Time;
937 #endif
938
939 //MDrv_Sys_DisableWatchDog();
940 /*
941 HAL_DMD_RIU_WriteByte(0x103480, 0x01);//reference GUI//reset
942 HAL_DMD_RIU_WriteByte(0x103481, 0x00);
943 HAL_DMD_RIU_WriteByte(0x103480, 0x00);
944 HAL_DMD_RIU_WriteByte(0x103483, 0x50);
945 HAL_DMD_RIU_WriteByte(0x103483, 0x51);
946 HAL_DMD_RIU_WriteByte(0x103484, 0x00);
947 HAL_DMD_RIU_WriteByte(0x103485, 0x00);
948 */
949 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
950 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
951 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
952 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
953 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
954 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
955
956 //// Load code thru VDMCU_IF ////
957 DBG_INTERN_DVBS(printf(">Load Code.....\n"));
958 for ( i = 0; i < sizeof(INTERN_DVBS_table); i++)
959 {
960 HAL_DMD_RIU_WriteByte(0x10348C, INTERN_DVBS_table[i]);
961 //HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBS_table[i]); // write data to VD MCU 51 code sram
962 }
963
964 //// Content verification ////
965 DBG_INTERN_DVBS(printf(">Verify Code...\n"));
966
967 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
968 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
969
970 for ( i = 0; i < sizeof(INTERN_DVBS_table); i++)
971 {
972 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
973 if (udata != INTERN_DVBS_table[i])
974 {
975 printf(">fail add = 0x%x\n", i);
976 printf(">code = 0x%x\n", INTERN_DVBS_table[i]);
977 printf(">data = 0x%x\n", udata);
978
979 if (fail_cnt > 10)
980 {
981 printf(">DVB-S DSP Loadcode fail!");
982 return false;
983 }
984 fail_cnt++;
985 }
986 }
987
988 #if 0 //use for Kris DJB with VCM
989 //====================================================================
990 // add S2 DRAM bufer start address into fixed location
991 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x30); // sram address low byte; 0x30 is defined in FW
992 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
993
994 //0x30~0x33
995 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBS2_DJB_START_ADDR);
996 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBS2_DJB_START_ADDR >> 8));
997 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBS2_DJB_START_ADDR >> 16));
998 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBS2_DJB_START_ADDR >> 24));
999
1000 printf("@@@@@ share dram address = 0x %x \n ",u32DMD_DVBS2_DJB_START_ADDR);
1001 //=====================================================================
1002 #endif
1003
1004 /*
1005 HAL_DMD_RIU_WriteByte(0x103483, 0x50);
1006 HAL_DMD_RIU_WriteByte(0x103483, 0x00);
1007 HAL_DMD_RIU_WriteByte(0x103480, 0x01);
1008 HAL_DMD_RIU_WriteByte(0x103481, 0x01);
1009 HAL_DMD_RIU_WriteByte(0x103480, 0x00);
1010 */
1011
1012 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
1013 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
1014 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
1015 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
1016
1017
1018 DBG_INTERN_DVBS(printf(">DSP Loadcode done."));
1019 #if 0
1020 INTERN_DVBS_Config(6875, 128, 36125, 0,1);
1021 INTERN_DVBS_Active(ENABLE);
1022 while(1);
1023 #endif
1024 //HAL_DMD_RIU_WriteByte(0x101E3E, 0x04); // DVBT = BIT1 -> 0x02
1025
1026 return TRUE;
1027 }
1028
1029 /***********************************************************************************
1030 Subject: DVB-S CLKGEN initialized function
1031 Function: INTERN_DVBS_Power_On_Initialization
1032 Parmeter:
1033 Return: MS_BOOL
1034 Remark:
1035 ************************************************************************************/
INTERN_DVBS_InitClkgen(MS_BOOL bRFAGCTristateEnable)1036 void INTERN_DVBS_InitClkgen(MS_BOOL bRFAGCTristateEnable)
1037 {
1038 MS_U8 u8Temp=0;
1039 // This file is translated by Steven Hung's riu2script.pl
1040
1041 // ==============================================================
1042 // Start demod top initial setting by HK MCU ......
1043 // ==============================================================
1044 // [8] : reg_chiptop_dummy_0 (reg_dmdtop_dmd_sel)
1045 // 1'b0->reg_DMDTOP control by HK_MCU.
1046 // 1'b1->reg_DMDTOP control by DMD_MCU.
1047 // [9] : reg_chiptop_dummy_0 (reg_dmd_ana_regsel)
1048 // 1'b0->reg_DMDANA control by HK_MCU.
1049 // 1'b1->reg_DMDANA control by DMD_MCU.
1050 // select HK MCU ......
1051 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0000);
1052 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0000);
1053 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
1054
1055
1056 // ==============================================================
1057 // Start TOP CLKGEN initial setting ......
1058 // ==============================================================
1059 // CLK_DMDMCU clock setting
1060 // reg_ckg_dmdmcu@0x0f[4:0]
1061 // [0] : disable clock
1062 // [1] : invert clock
1063 // [4:2]:
1064 // 000:170 MHz(MPLL_DIV_BUF)
1065 // 001:160MHz
1066 // 010:144MHz
1067 // 011:123MHz
1068 // 100:108MHz (Kriti:DVBT2)
1069 // 101:mem_clcok
1070 // 110:mem_clock div 2
1071 // 111:select XTAL
1072 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
1073 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
1074 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1075 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1076
1077
1078 // set parallel ts clock
1079 // [11] : reg_ckg_demod_test_in_en = 0
1080 // 0: select internal ADC CLK
1081 // 1: select external test-in clock
1082 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
1083 // 0: select gated clock
1084 // 1: select free-run clock
1085 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
1086 // 0: normal phase to pad
1087 // 1: invert phase to pad
1088 // [8] : reg_ckg_atsc_dvb_div_sel = 1
1089 // 0: select clk_dmplldiv5
1090 // 1: select clk_dmplldiv3
1091 // [4:0]: reg_ckg_dvbtm_ts_divnum = 11
1092 // Demod TS output clock phase tuning number
1093 // If (reg_ckg_tsout_ph_tun_num == reg_ckg_dvbtm_ts_divnum),
1094 // Demod TS output clock is equal Demod TS internal working clock.
1095 // => TS clock = (864/3)/(2*(5+1)) = 24MHz
1096 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1097 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1098 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1099 HAL_DMD_RIU_WriteByte(0x103300, 0x05);
1100
1101
1102 // enable DVBTC ts clock
1103 // [11:8]: reg_ckg_dvbtc_ts
1104 // [8] : disable clock
1105 // [9] : invert clock
1106 // [11:10]: Select clock source
1107 // 00:clk_atsc_dvb_div
1108 // 01:62 MHz
1109 // 10:54 MHz
1110 // 11:reserved
1111 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
1112 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
1113 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1114 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1115
1116
1117 // enable dvbc adc clock
1118 // [3:0]: reg_ckg_dvbtc_adc
1119 // [0] : disable clock
1120 // [1] : invert clock
1121 // [3:2]: Select clock source => for demod clkgen clk_dvbtc_adc
1122 // 00: clk_dmdadc
1123 // 01: clk_dmdadc_div2
1124 // 10: clk_dmdadc_div4
1125 // 11: DFT_CLK
1126 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
1127 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
1128 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1129 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1130
1131
1132 // ==============================================================
1133 // Start demod_0 CLKGEN setting ......
1134 // ==============================================================
1135 // enable atsc_adcd_sync clock
1136 // [3:0] : reg_ckg_atsc_adcd_sync
1137 // [0] : disable clock
1138 // [1] : invert clock
1139 // [3:2]: Select clock source
1140 // 00: clk_dmdadc_sync
1141 // 01: 1'b0
1142 // 10: 1'b0
1143 // 11: DFT_CLK
1144 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
1145 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
1146 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1147 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1148
1149 // DVBS2
1150 // @0x350c
1151 // [3:0] : reg_ckg_dvbs_outer1x
1152 // [0] : disable clock
1153 // [1] : invert clock
1154 // [3:2]: Select clock source
1155 // 00: adc_clk_buf
1156 // 01: dvb_clk86_buf
1157 // 10: dvb_clk43_buf
1158 // 11: 1'b0
1159 // [6:4] : reg_ckg_dvbs_outer2x
1160 // [4] : disable clock
1161 // [5] : invert clock
1162 // [6] : Select clock source
1163 // 00: adc_clk_buf
1164 // 01: 1'b0
1165 // 10: 1'b0
1166 // 11: DFT_CLK
1167 // [10:8]: reg_ckg_dvbs2_inner
1168 // [8] : disable clock
1169 // [9] : invert clock
1170 // [10]: Select clock source
1171 // 00: adc_clk_buf
1172 // 01: 1'b0
1173 // 10: 1'b0
1174 // 11: DFT_CLK
1175 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1176 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1177 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1178 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1179
1180
1181 // DVBS2
1182 // @0x350d
1183 // [11:8]: reg_ckg_dvbs2_oppro
1184 // [8] : disable clock
1185 // [9] : invert clock
1186 // [11:10]: Select clock source
1187 // 00: mpll_clk144_buf
1188 // 01: mpll_clk96_buf
1189 // 10: mpll_clk72_buf
1190 // 11: mpll_clk48_buf
1191 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0d, 2'b11, 16'h0000);
1192 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0d, 2'b11, 16'h0000);
1193 HAL_DMD_RIU_WriteByte(0x111f1b, 0x00);
1194 HAL_DMD_RIU_WriteByte(0x111f1a, 0x00);
1195
1196
1197 // @0x3510
1198 // [3:0] : reg_ckg_dvbtm_adc
1199 // N/A
1200 // [6:4] : reg_ckg_dvbt_inner1x
1201 // [4] : disable clock
1202 // [5] : invert clock
1203 // [6] : Select clock source
1204 // 00: dvb_clk24_buf
1205 // 01: dvb_clk21p5_buf
1206 // 10: 1'b0
1207 // 11: DFT_CLK
1208 // [10:8] reg_ckg_dvbt_inner2x
1209 // [8] : disable clock
1210 // [9] : invert clock
1211 // [10]: Select clock source
1212 // 00: dvb_clk48_buf
1213 // 01: dvb_clk43_buf
1214 // 10: 1'b0
1215 // 11: DFT_CLK
1216 // [14:12] reg_ckg_dvbt_inner4x
1217 // [12]: disable clock
1218 // [13]: invert clock
1219 // [14]: Select clock source
1220 // 00: dvb_clk96_buf
1221 // 01: dvb_clk86_buf
1222 // 10: 1'b0
1223 // 11: DFT_CLK
1224 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h1110);
1225 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h1110);
1226 HAL_DMD_RIU_WriteByte(0x111f21, 0x11);
1227 HAL_DMD_RIU_WriteByte(0x111f20, 0x10);
1228
1229 // @0x3511
1230 // [2:0] : reg_ckg_dvbt_outer1x
1231 // [0] : disable clock
1232 // [1] : invert clock
1233 // [2] : Select clock source
1234 // 00: dvb_clk48_buf
1235 // 01: dvb_clk43_buf
1236 // 10: 1'b0
1237 // 11: DFT_CLK
1238 // [6:4] : reg_ckg_dvbt_outer2x
1239 // [4] : disable clock
1240 // [5] : invert clock
1241 // [6] : Select clock source
1242 // 00: dvb_clk96_buf
1243 // 01: dvb_clk86_buf
1244 // 10: 1'b0
1245 // 11: DFT_CLK
1246 // [11:8]: reg_ckg_dvbtc_outer2x
1247 // [8] : disable clock
1248 // [9] : invert clock
1249 // [11:10]: Select clock source
1250 // 00: mpll_clk57p6_buf
1251 // 01: dvb_clk43_buf
1252 // 10: dvb_clk86_buf
1253 // 11: dvb_clk96_buf
1254 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0c11);
1255 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0c11);
1256 HAL_DMD_RIU_WriteByte(0x111f23, 0x0c);
1257 HAL_DMD_RIU_WriteByte(0x111f22, 0x11);
1258
1259
1260 // @0x3512
1261 // [11:8]: reg_ckg_acifir
1262 // [8] : disable clock
1263 // [9] : invert clock
1264 // [11:10]: Select clock source
1265 // 000: 1'b0
1266 // 001: clk_dmdadc
1267 // 010: clk_vif_ssc_mux
1268 // 011: 1'b0
1269 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b10, 16'h0400);
1270 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b10, 16'h0400);
1271 HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1272
1273
1274 // @0x3514
1275 // [12:8]: reg_ckg_dvbtm_sram_t1o2x_t22x
1276 // [8] : disable clock
1277 // [9] : invert clock
1278 // [12:10]: Select clock source
1279 // 000: dvb_clk48_buf
1280 // 001: dvb_clk43_buf
1281 // 010: 1'b0
1282 // 011: 1'b0
1283 // 100: 1'b0
1284 // 101: 1'b0
1285 // 110: 1'b0
1286 // 111: 1'b0
1287 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b11, 16'h0000);
1288 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b11, 16'h0000);
1289 HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
1290 HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1291
1292
1293 // @0x3516
1294 // [8:4] : reg_ckg_dvbtm_sram_adc_t22x
1295 // [4] : disable clock
1296 // [5] : invert clock
1297 // [8:6]: Select clock source
1298 // 000: dvb_clk48_buf
1299 // 001: dvb_clk43_buf
1300 // 010: 1'b0
1301 // 011: 1'b0
1302 // 100: adc_clk_buf
1303 // 101: 1'b0
1304 // 110: 1'b0
1305 // 111: 1'b0
1306 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h16, 2'b11, 16'h0001);
1307 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h16, 2'b11, 16'h0001);
1308 HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
1309 HAL_DMD_RIU_WriteByte(0x111f2c, 0x01);
1310
1311
1312 // @0x3517
1313 // [4:0] : reg_ckg_dvbtm_sram_t12x_t22x
1314 // [0] : disable clock
1315 // [1] : invert clock
1316 // [4:2]: Select clock source
1317 // 000: dvb_clk48_buf
1318 // 001: dvb_clk43_buf
1319 // 010: 1'b0
1320 // 011: 1'b0
1321 // 100: 1'b0
1322 // 101: 1'b0
1323 // 110: 1'b0
1324 // 111: 1'b0
1325 // [12:8] reg_ckg_dvbtm_sram_t12x_t24x
1326 // [8] : disable clock
1327 // [9] : invert clock
1328 // [12:10]: Select clock source
1329 // 000: dvb_clk96_buf
1330 // 001: dvb_clk86_buf
1331 // 010: dvb_clk48_buf
1332 // 011: dvb_clk43_buf
1333 // 100: 1'b0
1334 // 101: 1'b0
1335 // 110: 1'b0
1336 // 111: 1'b0
1337 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h17, 2'b11, 16'h0000);
1338 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h17, 2'b11, 16'h0000);
1339 HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
1340 HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
1341
1342
1343 // @0x3518
1344 // [4:0] : reg_ckg_dvbtm_sram_t14x_t24x
1345 // [0] : disable clock
1346 // [1] : invert clock
1347 // [4:2]: Select clock source
1348 // 000: dvb_clk96_buf
1349 // 001: dvb_clk96_buf
1350 // 010: 1'b0
1351 // 011: 1'b0
1352 // 100: 1'b0
1353 // 101: 1'b0
1354 // 110: 1'b0
1355 // 111: 1'b0
1356 // [12:8]: reg_ckg_dvbtm_ts_in
1357 // [8] : disable clock
1358 // [9] : invert clock
1359 // [12:10]: Select clock source
1360 // 000: clk_dvbtc_rs_p
1361 // 001: dvb_clk48_buf
1362 // 010: dvb_clk43_buf
1363 // 011: clk_dvbs_outer1x_pre_mux4
1364 // 100: clk_dvbs2_oppro_pre_mux4
1365 // 101: 1'b0
1366 // 110: 1'b0
1367 // 111: 1'b0
1368 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b11, 16'h0001);
1369 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b11, 16'h0001);
1370 HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1371 HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1372
1373
1374 // @0x3519
1375 // [2:0] : reg_ckg_tdp_jl_inner1x
1376 // [0] : disable clock
1377 // [1] : invert clock
1378 // [2] : Select clock source
1379 // 00: dvb_clk24_buf
1380 // 01: dvb_clk21p5_buf
1381 // 10: 1'b0
1382 // 11: DFT_CLK
1383 // [6:4] : reg_ckg_tdp_jl_inner4x
1384 // [4] : disable clock
1385 // [5] : invert clock
1386 // [6] : Select clock source
1387 // 00: dvb_clk96_buf
1388 // 01: dvb_clk86_buf
1389 // 10: 1'b0
1390 // 11: DFT_CLK
1391 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h19, 2'b11, 16'h3c00);
1392 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h19, 2'b11, 16'h3c00);
1393 HAL_DMD_RIU_WriteByte(0x111f33, 0x3c);
1394 HAL_DMD_RIU_WriteByte(0x111f32, 0x00);
1395
1396
1397 // @0x351a
1398 // [6:4] : reg_ckg_dvbt2_inner1x
1399 // [4] : disable clock
1400 // [5] : invert clock
1401 // [6] : Select clock source
1402 // 00: dvb_clk96_buf
1403 // 01: dvb_clk86_buf
1404 // 10: 1'b0
1405 // 11: DFT_CLK
1406 // [10:8]: reg_ckg_dvbt2_inner2x
1407 // [8] : disable clock
1408 // [9] : invert clock
1409 // [10]: Select clock source
1410 // 00: dvb_clk48_buf
1411 // 01: dvb_clk43_buf
1412 // 10: 1'b0
1413 // 11: DFT_CLK
1414 // [14:12]:reg_ckg_dvbt2_inner4x
1415 // [12] : disable clock
1416 // [13] : invert clock
1417 // [14] : Select clock source
1418 // 00: dvb_clk96_buf
1419 // 01: dvb_clk86_buf
1420 // 10: 1'b0
1421 // 11: DFT_CLK
1422 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1a, 2'b11, 16'h0000);
1423 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1a, 2'b11, 16'h0000);
1424 HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
1425 HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
1426
1427
1428 // @0x351b
1429 // [1:0] : reg_ckg_dvbt2_ldpc
1430 // DVBT2 LDPC gated clock control register
1431 // [0] = 1:clock enable.
1432 // [1] = 1:manual mode.
1433 // [3:2] : reg_ckg_dvbt2_bch
1434 // DVBT2 BCH gated clock control register;
1435 // [0] = 1:clock enable
1436 // [1] = 1:manual mode.
1437 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1b, 2'b11, 16'h0011);
1438 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1b, 2'b11, 16'h0011);
1439 HAL_DMD_RIU_WriteByte(0x111f37, 0x00);
1440 HAL_DMD_RIU_WriteByte(0x111f36, 0x11);
1441
1442
1443 // @0x351d
1444 // [4:0] : reg_ckg_dvbtm_adc_eq_1x
1445 // [0] : disable clock
1446 // [1] : invert clock
1447 // [2] : Select clock source
1448 // 00: adc_clk_buf
1449 // 01: 1'b0
1450 // 10: 1'b0
1451 // 11: DFT_CLK
1452 // [12:8]: reg_ckg_dvbtm_adc_eq_0p5x
1453 // [4] : disable clock
1454 // [5] : invert clock
1455 // [6]: Select clock source
1456 // 00: clk_adc_div2_buf
1457 // 01: 1'b0
1458 // 10: 1'b0
1459 // 11: DFT_CLK
1460 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1d, 2'b11, 16'h0000);
1461 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1d, 2'b11, 16'h0000);
1462 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1463 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1464
1465
1466 // @0x351e
1467 // [4:0] : reg_ckg_dvbtm_sram_t11x_t22x
1468 // [0] : disable clock
1469 // [1] : invert clock
1470 // [4:2]: Select clock source
1471 // 000: dvb_clk48_buf
1472 // 001: dvb_clk43_buf
1473 // 010: dvb_clk24_buf
1474 // 011: dvb_clk21p5_buf
1475 // 100: 1'b0
1476 // 101: 1'b0
1477 // 110: 1'b0
1478 // 111: 1'b0
1479 // [12:8]: reg_ckg_dvbtm_sram_t11x_t24x
1480 // [8] : disable clock
1481 // [9] : invert clock
1482 // [:2]: Select clock source
1483 // 000: dvb_clk48_buf
1484 // 001: dvb_clk43_buf
1485 // 010: dvb_clk24_buf
1486 // 011: dvb_clk21p5_buf
1487 // 100: 1'b0
1488 // 101: 1'b0
1489 // 110: 1'b0
1490 // 111: 1'b0
1491 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1e, 2'b11, 16'h0c04);
1492 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1e, 2'b11, 16'h0000);
1493 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1e, 2'b11, 16'h0000);
1494 HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
1495 HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
1496
1497
1498 // @0x3522
1499 // [3:0] : reg_ckg_dvbt_t2_inner0p5x_dvbc_eq1x
1500 // [0] : disable clock
1501 // [1] : invert clock
1502 // [2] : Select clock source
1503 // 00: dvb_clk12_buf
1504 // 01: dvb_clk10p75_buf
1505 // 10: 1'b0
1506 // 11: DFT_CLK
1507 // [7:4] : reg_ckg_dvbt_t2_inner2x_dvbc_eq4x
1508 // [4] : disable clock
1509 // [5] : invert clock
1510 // [6] : Select clock source
1511 // 00: dvb_clk48_buf
1512 // 01: dvb_clk43_buf
1513 // 10: 1'b0
1514 // 11: DFT_CLK
1515 // [11:8]: reg_ckg_dvbt_t2_inner1x
1516 // [8] : disable clock
1517 // [9] : invert clock
1518 // [11:10]: Select clock source
1519 // 00: dvb_clk24_buf
1520 // 01: dvb_clk21p5_buf
1521 // 10: 1'b0
1522 // 11: DFT_CLK
1523 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0111);
1524 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0111);
1525 HAL_DMD_RIU_WriteByte(0x111f45, 0x01);
1526 HAL_DMD_RIU_WriteByte(0x111f44, 0x11);
1527
1528 // @0x353a
1529 // [2:0] : reg_ckg_dvbtm_sram_t12x_t24x_srd1x_isdbt_inner2x
1530 // [0] : disable clock
1531 // [1] : invert clock
1532 // [2] : Select clock source
1533 // 00: clk_dvbtm_sram_t12x_t24x_srd1x_p
1534 // 01: clk_isdbt_inner2x_p
1535 // 10: 1'b0
1536 // 11: DFT_CLK
1537 // [6:4] : reg_ckg_dvbtm_sram_t12x_t24x_isdbt_inner2x
1538 // [4] : disable clock
1539 // [5] : invert clock
1540 // [6] : Select clock source
1541 // 00: clk_dvbtm_sram_t12x_t24x_p
1542 // 01: clk_isdbt_inner2x_p
1543 // 10: 1'b0
1544 // 11: DFT_CLK
1545 // [10:8]: reg_ckg_dvbtm_sram_t24x_isdbt_inner2x
1546 // [8] : disable clock
1547 // [9] : invert clock
1548 // [10]: Select clock source
1549 // 00: clk_dvbtm_sram_t14x_t24x_p
1550 // 01: clk_isdbt_inner2x_p
1551 // 10: 1'b0
1552 // 11: DFT_CLK
1553 // [14:12]: reg_ckg_dvbtm_sram_t12x_t24x_s2inner_isdbt_inner4x
1554 // [12] : disable clock
1555 // [13] : invert clock
1556 // [14] : Select clock source
1557 // 00: clk_dvbtm_sram_t12x_t24x_s2inner_p
1558 // 01: clk_isdbt_inner4x_p
1559 // 10: 1'b0
1560 // 11: DFT_CLK
1561 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3a, 2'b11, 16'h0110);
1562 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3a, 2'b11, 16'h0110);
1563 HAL_DMD_RIU_WriteByte(0x111f75, 0x01);
1564 HAL_DMD_RIU_WriteByte(0x111f74, 0x10);
1565
1566 // @0x353b
1567 // [2:0] : reg_ckg_dvbtm_sram_t12x_t24x_s2inner_isdbt_inner2x
1568 // [0] : disable clock
1569 // [1] : invert clock
1570 // [2] : Select clock source
1571 // 00: clk_dvbtm_sram_t12x_t24x_s2inner_p
1572 // 01: clk_isdbt_inner2x_p
1573 // 10: 1'b0
1574 // 11: DFT_CLK
1575 // [6:4] : reg_ckg_dvbtm_sram_t22x_isdbt_inner2x
1576 // [4] : disable clock
1577 // [5] : invert clock
1578 // [6] : Select clock source
1579 // 00: clk_dvbtm_sram_t12x_t22x_p
1580 // 01: clk_isdbt_inner2x_p
1581 // 10: 1'b0
1582 // 11: DFT_CLK
1583 // [10:8]: reg_ckg_dvbtm_sram_t14x_t24x_s2inner_isdbt_inner2x
1584 // [8] : disable clock
1585 // [9] : invert clock
1586 // [10]: Select clock source
1587 // 00: clk_dvbtm_sram_t14x_t24x_s2inner_p
1588 // 01: clk_isdbt_inner2x_p
1589 // 10: 1'b0
1590 // 11: DFT_CLK
1591 // [14:12]: reg_ckg_dvbtm_sram_t12x_t24x_srd1x_isdbt_inner4x
1592 // [12] : disable clock
1593 // [13] : invert clock
1594 // [14]: Select clock source
1595 // 00: clk_dvbtm_sram_t12x_t24x_srd1x_p
1596 // 01: clk_isdbt_inner4x_p
1597 // 10: 1'b0
1598 // 11: DFT_CLK
1599 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0010);
1600 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0010);
1601 HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
1602 HAL_DMD_RIU_WriteByte(0x111f76, 0x10);
1603
1604 // @0x353c
1605 // [2:0] : reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifssc_isdbt_inner4x
1606 // [0] : disable clock
1607 // [1] : invert clock
1608 // [2] : Select clock source
1609 // 00: clk_dvbtm_sram_t14x_t24x_srd1x_vifssc_p
1610 // 01: clk_isdbt_inner4x_p
1611 // 10: 1'b0
1612 // 11: DFT_CLK
1613 // [6:4] : reg_ckg_dvbtm_sram_t12x_t22x_isdbt_inner2x
1614 // [4] : disable clock
1615 // [5] : invert clock
1616 // [6] : Select clock source
1617 // 00: clk_dvbtm_sram_t12x_t22x_p
1618 // 01: clk_isdbt_inner2x_p
1619 // 10: 1'b0
1620 // 11: DFT_CLK
1621 // [10:8]: reg_ckg_dvbtm_sram_t11x_t22x_isdbt_inner2x
1622 // [8] : disable clock
1623 // [9] : invert clock
1624 // [10]: Select clock source
1625 // 00: clk_dvbtm_sram_t11x_t22x_p
1626 // 01: clk_isdbt_inner2x_p
1627 // 10: 1'b0
1628 // 11: DFT_CLK
1629 // [14:12]: reg_ckg_dvbtm_sram_t12x_t24x_isdbt_outer6x
1630 // [12] : disable clock
1631 // [13] : invert clock
1632 // [14]: Select clock source
1633 // 00: clk_dvbtm_sram_t12x_t24x_p
1634 // 01: clk_isdbt_outer6x_dvbt_outer2x_c_mux
1635 // 10: 1'b0
1636 // 11: DFT_CLK
1637 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3c, 2'b11, 16'h0110);
1638 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3c, 2'b11, 16'h0110);
1639 HAL_DMD_RIU_WriteByte(0x111f79, 0x01);
1640 HAL_DMD_RIU_WriteByte(0x111f78, 0x10);
1641
1642 // @0x353e
1643 // [2:0] : reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_isdbt_outer6x
1644 // [0] : disable clock
1645 // [1] : invert clock
1646 // [2] : Select clock source
1647 // 00: clk_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_mux8
1648 // 01: clk_isdbt_outer6x_p
1649 // 10: 1'b0
1650 // 11: DFT_CLK
1651 // [6:4] : reg_ckg_dvbtm_sram_t22x_miu
1652 // [4] : disable clock
1653 // [5] : invert clock
1654 // [6] : Select clock source
1655 // 00: clk_dvbt2_inner2x_p
1656 // 01: clk_miu_p
1657 // 10: 1'b0
1658 // 11: DFT_CLK
1659 // [10:8]: reg_ckg_dvbtm_sram_adc_t22x_isdbt_inner2x
1660 // [8] : disable clock
1661 // [9] : invert clock
1662 // [10]: Select clock source
1663 // 00: clk_dvbtm_sram_adc_t22x_p
1664 // 01: clk_isdbt_inner2x_p
1665 // 10: 1'b0
1666 // 11: DFT_CLK
1667 // [14:12]: reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_miu
1668 // [12] : disable clock
1669 // [13] : invert clock
1670 // [14]: Select clock source
1671 // 00: clk_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_mux8
1672 // 01: clk_miu_p
1673 // 10: 1'b0
1674 // 11: DFT_CLK
1675 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3e, 2'b11, 16'h1111);
1676 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3e, 2'b11, 16'h1111);
1677 HAL_DMD_RIU_WriteByte(0x111f7d, 0x11);
1678 HAL_DMD_RIU_WriteByte(0x111f7c, 0x11);
1679
1680 // @0x353f
1681 // [2:0] : reg_ckg_dvbs_outer2x_dvbt_outer2x_miu_isdbt_outer6x
1682 // [0] : disable clock
1683 // [1] : invert clock
1684 // [2] : Select clock source
1685 // 00: clk_dvbs_outer2x_dvbt_outer2x_miu_mux8
1686 // 01: clk_isdbt_outer6x_p
1687 // 10: 1'b0
1688 // 11: DFT_CLK
1689 // [6:4] : reg_ckg_dvbtm_sram_t22x_dvbtc_rs
1690 // [4] : disable clock
1691 // [5] : invert clock
1692 // [6] : Select clock source
1693 // 00: clk_dvbt2_inner2x_p
1694 // 01: clk_dvbtc_rs_p
1695 // 10: 1'b0
1696 // 11: DFT_CLK
1697 // [10:8]: reg_ckg_dvbtc_outer2x_isdbt_outer_rs
1698 // [8] : disable clock
1699 // [9] : invert clock
1700 // [10]: Select clock source
1701 // 00: clk_dvbtc_outer2x_p
1702 // 01: clk_isdbt_outer_rs_p
1703 // 10: 1'b0
1704 // 11: DFT_CLK
1705 // [14:12]: reg_ckg_dvbtm_sram_t22x_isdbt_outer6x_dvbt_outer2x
1706 // [12] : disable clock
1707 // [13] : invert clock
1708 // [14]: Select clock source
1709 // 00: clk_dvbtm_sram_t12x_t22x_p
1710 // 01: clk_isdbt_outer6x_dvbt_outer2x_mux
1711 // 10: 1'b0
1712 // 11: DFT_CLK
1713 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3f, 2'b11, 16'h1041);
1714 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3f, 2'b11, 16'h1041);
1715 HAL_DMD_RIU_WriteByte(0x111f7f, 0x10);
1716 HAL_DMD_RIU_WriteByte(0x111f7e, 0x41);
1717
1718
1719 // @0x3570
1720 // [4:0] : reg_ckg_dvbt_inner2x_srd0p5x
1721 // [0] : disable clock
1722 // [1] : invert clock
1723 // [3:2]: Select clock source
1724 // 00: dvb_clk48_buf
1725 // 01: dvb_clk43_buf
1726 // 10: clk_adc_div2_buf
1727 // 11: 1'b0
1728 // 11: 1'b0
1729 // [13:8]: reg_ckg_dvbtm_sram_t1outer1x_t24x
1730 // [8] : disable clock
1731 // [9] : invert clock
1732 // [12:10]: Select clock source
1733 // 000: dvb_clk96_buf
1734 // 001: dvb_clk86_buf
1735 // 010: dvb_clk48_buf
1736 // 011: dvb_clk43_buf
1737 // 100: 1'b0
1738 // 101: 1'b0
1739 // 110: 1'b0
1740 // 111: 1'b0
1741 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h70, 2'b11, 16'h0008);
1742 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h70, 2'b11, 16'h0008);
1743 HAL_DMD_RIU_WriteByte(0x111fe1, 0x00);
1744 HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1745
1746
1747 // @0x3571
1748 // [4:0] : reg_ckg_dvbtm_sram_t12x_t24x_srd1x
1749 // [0] : disable clock
1750 // [1] : invert clock
1751 // [3:2]: Select clock source
1752 // 000: dvb_clk96_buf
1753 // 001: dvb_clk86_buf
1754 // 010: dvb_clk48_buf
1755 // 011: dvb_clk43_buf
1756 // 100: adc_clk_buf
1757 // 101: 1'b0
1758 // 110: 1'b0
1759 // 111: 1'b0
1760 // [12:8]: reg_ckg_dvbtm_sram_t14x_t24x_srd1x
1761 // [8] : disable clock
1762 // [9] : invert clock
1763 // [12:10]: Select clock source
1764 // 000: dvb_clk96_buf
1765 // 001: dvb_clk86_buf
1766 // 010: adc_clk_buf
1767 // 011: 1'b0
1768 // 100: 1'b0
1769 // 101: 1'b0
1770 // 110: 1'b0
1771 // 111: 1'b0
1772 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h71, 2'b11, 16'h0810);
1773 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h71, 2'b11, 16'h0810);
1774 HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1775 HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1776
1777
1778 // @0x3572
1779 // [6:0] : reg_ckg_dvbt2_s2_bch_out
1780 // [0] : disable clock
1781 // [1] : invert clock
1782 // [2] : Select clock source
1783 // 00: dvb_clk48_buf
1784 // 01: dvb_clk43_buf
1785 // 10: 1'b0
1786 // 11: DFT_CLK
1787 // [12:8]: reg_ckg_dvbt2_outer2x
1788 // [8] : disable clock
1789 // [9] : invert clock
1790 // [12:10]: Select clock source
1791 // 000: mpll_clk144_buf
1792 // 001: mpll_clk108_buf
1793 // 010: mpll_clk96_buf
1794 // 011: mpll_clk72_buf
1795 // 100: mpll_clk54_buf
1796 // 101: mpll_clk48_buf
1797 // 110: mpll_clk36_buf
1798 // 111: mpll_clk24_buf
1799 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h72, 2'b11, 16'h0008);
1800 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h72, 2'b11, 16'h0008);
1801 HAL_DMD_RIU_WriteByte(0x111fe5, 0x00);
1802 HAL_DMD_RIU_WriteByte(0x111fe4, 0x08);
1803
1804
1805 // @0x3573
1806 // [3:0] : reg_ckg_dvbt2_inner4x_s2_inner
1807 // [0] : disable clock
1808 // [1] : invert clock
1809 // [2] : Select clock source
1810 // 00: dvb_clk96_buf
1811 // 01: dvb_clk86_buf
1812 // 10: 1'b0
1813 // 11: DFT_CLK
1814 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h73, 2'b11, 16'h0008);
1815 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h73, 2'b11, 16'h0008);
1816 HAL_DMD_RIU_WriteByte(0x111fe7, 0x00);
1817 HAL_DMD_RIU_WriteByte(0x111fe6, 0x08);
1818
1819
1820 // @0x3574
1821 // [4:0] reg_ckg_dvbtm_sram_t12x_t24x_s2inner
1822 // [0] : disable clock
1823 // [1] : invert clock
1824 // [4:2]:Select clock source
1825 // 000: dvb_clk96_buf
1826 // 001: dvb_clk86_buf
1827 // 010: dvb_clk48_buf
1828 // 011: dvb_clk43_buf
1829 // 100: adc_clk_buf
1830 // 101: 1'b0
1831 // 110: 1'b0
1832 // 111: 1'b0
1833 // [12:8] reg_ckg_dvbtm_sram_t14x_t24x_s2inner
1834 // [8] : disable clock
1835 // [9] : invert clock
1836 // [12:10]: Select clock source
1837 // 000: dvb_clk96_buf
1838 // 001: dvb_clk86_buf
1839 // 010: adc_clk_buf
1840 // 011: dvb_clk24_buf //JL SRAM Share (Windermere U02 ECO)
1841 // 100: dvb_clk21p5_buf //JL SRAM Share (Windermere U02 ECO)
1842 // 101: 1'b0
1843 // 110: 1'b0
1844 // 111: 1'b0
1845 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h74, 2'b11, 16'h0810);
1846 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h74, 2'b11, 16'h0810);
1847 HAL_DMD_RIU_WriteByte(0x111fe9, 0x08);
1848 HAL_DMD_RIU_WriteByte(0x111fe8, 0x10);
1849
1850
1851 // @0x3575
1852 // [4:0] : reg_ckg_dvbtc_rs
1853 // [0] : disable clock
1854 // [1] : invert clock
1855 // [4:2]:Select clock source
1856 // 000: mpll_clk216_buf
1857 // 001: mpll_clk172p8_buf
1858 // 010: mpll_clk144_buf
1859 // 011: mpll_clk288_buf
1860 // 100: dvb_clk96_buf
1861 // 101: dvb_clk86_buf
1862 // 110: mpll_clk57p6_buf
1863 // 111: dvb_clk43_buf
1864 // [11:8] : reg_ckg_dvbs_outer2x_dvbt_outer2x (N/A)
1865 // [15:12]: reg_ckg_dvbs_outer2x_dvbt_outer2x_miu
1866 // [12] : disable clock
1867 // [13] : invert clock
1868 // [15:14]:Select clock source
1869 // 000: 1'b0
1870 // 001: dvb_clk96_buf
1871 // 010: dvb_clk86_buf
1872 // 011: clk_miu
1873 // 100: 1'b0
1874 // 101: 1'b0
1875 // 110: 1'b0
1876 // 111: 1'b0
1877 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h75, 2'b11, 16'h0000);
1878 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h75, 2'b11, 16'h0000);
1879 HAL_DMD_RIU_WriteByte(0x111feb, 0x00);
1880 HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1881
1882
1883 // @0x3576
1884 // [4:0] : reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x
1885 // [0] : disable clock
1886 // [1] : invert clock
1887 // [4:2]:Select clock source
1888 // 000: 1'b0
1889 // 001: dvb_clk96_buf
1890 // 010: dvb_clk86_buf
1891 // 011: dvb_clk48_buf
1892 // 100: dvb_clk43_buf
1893 // 101: 1'b0
1894 // 110: 1'b0
1895 // 111: 1'b0
1896 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h76, 2'b11, 16'h0000);
1897 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h76, 2'b11, 16'h0000);
1898 HAL_DMD_RIU_WriteByte(0x111fed, 0x00);
1899 HAL_DMD_RIU_WriteByte(0x111fec, 0x00);
1900
1901
1902 // @0x3577
1903 // [3:0] : reg_ckg_dvbt2_inner4x_dvbtc_rs
1904 // [0] : disable clock
1905 // [1] : invert clock
1906 // [3:2]: Select clock source
1907 // 00: dvb_clk96_buf
1908 // 01: dvb_clk86_buf
1909 // 10: clk_dvbtc_rs_p
1910 // 11: 1'b0
1911 // [8:4] : reg_ckg_dvbtm_sram_adc_t22x_dvbtc_rs
1912 // [4] : disable clock
1913 // [5] : invert clock
1914 // [6] : Select clock source
1915 // 000: dvb_clk48_buf
1916 // 001: dvb_clk43_buf
1917 // 010: 1'b0
1918 // 011: adc_clk_buf
1919 // 100: 1'b0
1920 // 101: 1'b0
1921 // 110: 1'b0
1922 // 111: 1'b0
1923 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h77, 2'b11, 16'h0088);
1924 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h77, 2'b11, 16'h0088);
1925 HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1926 HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1927
1928
1929 // Maserati
1930 // @0x3578
1931 // [4:0] : reg_ckg_dvbt2_inner2x_srd0p5x
1932 // [0] : disable clock
1933 // [1] : invert clock
1934 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h78, 2'b01, 16'h0008);
1935 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h78, 2'b01, 16'h0008);
1936 HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1937
1938 // [3:0] : reg_ckg_sram_t22x_isdbt_inn2x_dtmb_inn2x
1939 // [0] : disable clock
1940 // [1] : invert clock
1941 // [3:2]:Select clock source
1942 // 000: clk_dvbtm_sram_t12x_t22x_p
1943 // 001: clk_isdbt_inner2x_p
1944 // 010: clk_share_dtmb_inner2x_isdbt_sram4_mux
1945 // 011:
1946 // [7:4] : reg_ckg_sram_t14x_t24x_s2inn_isdbt_inn2x_dtmb_inn6x
1947 // [4] : disable clock
1948 // [5] : invert clock
1949 // [7:6]:Select clock source
1950 // 000: clk_dvbtm_sram_t14x_t24x_s2inner_p
1951 // 001: clk_isdbt_inner2x_p
1952 // 010: clk_share_dtmb_inner6x_isdbt_sram3_mux
1953 // 011:
1954 // [11:8] : reg_ckg_sram_t14x_t24x_s2inn_isdbt_inn2x_dtmb_eq2x
1955 // [4] : disable clock
1956 // [5] : invert clock
1957 // [7:6]:Select clock source
1958 // 000: clk_dvbtm_sram_t14x_t24x_s2inner_p
1959 // 001: clk_isdbt_inner2x_p
1960 // 010: clk_share_dtmb_eq2x_isdbt_sram3_mux
1961 // 011:
1962 // [15:12]: reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifssc_isdbt_inner4x_dtmb_inner12x
1963 // [12] : disable clock
1964 // [13] : invert clock
1965 // [15:14]:Select clock source
1966 // 000: clk_dvbtm_sram_t14x_t24x_srd1x_vifssc_p
1967 // 001: clk_isdbt_inner4x_p
1968 // 010: clk_dvbtc_sram2_p
1969 // 011: clk_dtmb_eq2x_inner2x_12x_mux
1970 // `RIU_W((`RIUBASE_DEMOD_8>>1)+7'h48, 2'b11, 16'h0001);
1971 // `RIU_W((`RIUBASE_DEMOD_8>>1)+7'h48, 2'b11, 16'h0001);
1972 HAL_DMD_RIU_WriteByte(0x152991, 0x00);
1973 HAL_DMD_RIU_WriteByte(0x152990, 0x01);
1974 // ==============================================================
1975 // End demod top initial setting by HK MCU ......
1976 // ==============================================================
1977 //wriu 0x101e39 0x03
1978 HAL_DMD_RIU_WriteByte(0x101e39, 0x03);
1979
1980 //==========================================================
1981 //diseqc_out : PAD_GPIO15_I
1982 //swich to Diseqc out pin from GPIO
1983 //==========================================================
1984 //Bank: Reg_CHIP_TOP(0x101e)
1985 //reg_test_out_mode : addr h��12, [6:4] = 3��h0
1986 //reg_ts4config : addr h��40, [11:10] = 2��h0
1987 //reg_ts5config : addr h��40, [13:12] = 2��h0
1988 //reg_i2smutemode : addr h��2, [15:14] = 2��h0
1989 //reg_fifthuartmode : h��4, [3:2] = 2��h0
1990 //reg_od5thuart : h��55, [5:4] = 2��h0
1991 //reg_diseqc_out_config : ��h45, [1] = 1��b1
1992 u8Temp = HAL_DMD_RIU_ReadByte(0x101E8A);
1993 u8Temp|=0x02;
1994 HAL_DMD_RIU_WriteByte(0x101E8A, u8Temp);
1995
1996 // SRAM allocation 64K avoid change souce from T2 failed.
1997 HAL_DMD_RIU_WriteByte(0x111701,0x00);
1998 HAL_DMD_RIU_WriteByte(0x111700,0x00);
1999
2000 HAL_DMD_RIU_WriteByte(0x111705,0x00);
2001 HAL_DMD_RIU_WriteByte(0x111704,0x00);
2002
2003 HAL_DMD_RIU_WriteByte(0x111703,0xff);
2004 HAL_DMD_RIU_WriteByte(0x111702,0xff);
2005
2006 HAL_DMD_RIU_WriteByte(0x111707,0xff);
2007 HAL_DMD_RIU_WriteByte(0x111706,0xff);
2008
2009 //Diff from TV tool
2010 HAL_DMD_RIU_WriteByte(0x111708,0x01);
2011 HAL_DMD_RIU_WriteByte(0x111709,0x00);
2012
2013 HAL_DMD_RIU_WriteByte(0x11170a,0x0f);
2014 HAL_DMD_RIU_WriteByte(0x11170b,0x00);
2015
2016 HAL_DMD_RIU_WriteByte(0x111718,0x02);
2017 HAL_DMD_RIU_WriteByte(0x111719,0x00);
2018
2019 HAL_DMD_RIU_WriteByte(0x11171a,0x00);
2020 HAL_DMD_RIU_WriteByte(0x11171b,0x00);
2021
2022 HAL_DMD_RIU_WriteByte(0x1117e0,0x14);
2023 HAL_DMD_RIU_WriteByte(0x1117e1,0x14);
2024
2025 HAL_DMD_RIU_WriteByte(0x1117e4,0x00);
2026 HAL_DMD_RIU_WriteByte(0x1117e5,0x00);
2027
2028 HAL_DMD_RIU_WriteByte(0x1117e6,0x00);
2029 HAL_DMD_RIU_WriteByte(0x1117e7,0x00);
2030
2031 DBG_INTERN_DVBS(printf("INTERN_DVBS_InitClkgen\n"));
2032 }
2033
2034 /***********************************************************************************
2035 Subject: Power on initialized function
2036 Function: INTERN_DVBS_Power_On_Initialization
2037 Parmeter:
2038 Return: MS_BOOL
2039 Remark:
2040 ************************************************************************************/
INTERN_DVBS_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBS_DSPRegInitExt,MS_U8 u8DMD_DVBS_DSPRegInitSize)2041 MS_BOOL INTERN_DVBS_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBS_DSPRegInitExt, MS_U8 u8DMD_DVBS_DSPRegInitSize)
2042 {
2043 MS_U8 status = true;
2044 //MS_U8 u8ChipVersion;
2045
2046 DBG_INTERN_DVBS(printf("INTERN_DVBS_Power_On_Initialization\n"));
2047
2048 #if defined(PWS_ENABLE)
2049 Mapi_PWS_Stop_VDMCU();
2050 #endif
2051 INTERN_DVBS_InitClkgen(bRFAGCTristateEnable);//~~ no modify
2052 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);//~~ no modify
2053
2054 DBG_INTERN_DVBS(printf("@@@@@INTERN_DVBS_Power_On_Initialization1:bRFAGCTristateEnable=%d ;u8ADCIQMode=%d \n",bRFAGCTristateEnable,u8ADCIQMode));
2055 DBG_INTERN_DVBS(printf("@@@@@INTERN_DVBS_Power_On_Initialization2:u8PadSel=%d ;bPGAEnable=%d \n",u8PadSel,bPGAEnable));
2056 DBG_INTERN_DVBS(printf("@@@@@INTERN_DVBS_Power_On_Initialization2:u8PGAGain=%d \n",u8PGAGain));
2057
2058 //// Firmware download //////////
2059 DBG_INTERN_DVBS(printf("INTERN_DVBS Load DSP...\n"));
2060 //MsOS_DelayTask(100);
2061
2062 {
2063 if (INTERN_DVBS_LoadDSPCode() == FALSE)
2064 {
2065 DBG_INTERN_DVBS(printf("DVB-S Load DSP Code Fail\n"));
2066 return FALSE;
2067 }
2068 else
2069 {
2070 DBG_INTERN_DVBS(printf("DVB-S Load DSP Code OK\n"));
2071 }
2072 }
2073
2074 //// MCU Reset //////////
2075 if (INTERN_DVBS_Reset() == FALSE)
2076 {
2077 DBG_INTERN_DVBS(printf("INTERN_DVBS Reset...Fail\n"));
2078 return FALSE;
2079 }
2080 else
2081 {
2082 DBG_INTERN_DVBS(printf("INTERN_DVBS Reset...OK\n"));
2083 }
2084
2085
2086 status &= INTERN_DVBS_DSPReg_Init(u8DMD_DVBS_DSPRegInitExt, u8DMD_DVBS_DSPRegInitSize);
2087 //status &= INTERN_DVBS_Active(ENABLE);//enable this
2088
2089 //Read Demod FW Version.
2090 INTERN_DVBS_Show_Demod_Version();
2091
2092 return status;
2093 }
2094 /************************************************************************************************
2095 Subject: Driving control
2096 Function: INTERN_DVBC_Driving_Control
2097 Parmeter: bInversionEnable : TRUE For High
2098 Return: void
2099 Remark:
2100 *************************************************************************************************/
INTERN_DVBS_Driving_Control(MS_BOOL bEnable)2101 void INTERN_DVBS_Driving_Control(MS_BOOL bEnable)
2102 {
2103 MS_U8 u8Temp;
2104
2105 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
2106
2107 if (bEnable)
2108 {
2109 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
2110 }
2111 else
2112 {
2113 u8Temp = u8Temp & (~0x01);
2114 }
2115
2116 DBG_INTERN_DVBS(printf("---> INTERN_DVBS_Driving_Control(Bit0) = 0x%x \n",u8Temp));
2117 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
2118 }
2119
2120 /************************************************************************************************
2121 Subject: Clk Inversion control
2122 Function: INTERN_DVBS_Clk_Inversion_Control
2123 Parmeter: bInversionEnable : TRUE For Inversion Action
2124 Return: void
2125 Remark:
2126 *************************************************************************************************/
INTERN_DVBS_Clk_Inversion_Control(MS_BOOL bInversionEnable)2127 void INTERN_DVBS_Clk_Inversion_Control(MS_BOOL bInversionEnable)
2128 {
2129 MS_U8 u8Temp;
2130
2131 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
2132
2133 if (bInversionEnable)
2134 {
2135 u8Temp = u8Temp | 0x02; //bit 9: clk inv
2136 }
2137 else
2138 {
2139 u8Temp = u8Temp & (~0x02);
2140 }
2141
2142 DBG_INTERN_DVBS(printf("---> Inversion(Bit9) = 0x%x \n",u8Temp));
2143 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
2144 }
2145
2146 /************************************************************************************************
2147 Subject: Transport stream serial/parallel control
2148 Function: INTERN_DVBS_Serial_Control
2149 Parmeter: bEnable : TRUE For serial
2150 Return: MS_BOOL :
2151 Remark:
2152 *************************************************************************************************/
INTERN_DVBS_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)2153 MS_BOOL INTERN_DVBS_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
2154 {
2155 MS_U8 status = true;
2156 MS_U8 temp_val;
2157 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_ts... u8TSClk=%d\n", u8TSClk));
2158
2159 if (u8TSClk == 0xFF) u8TSClk=0x13;
2160 if (bEnable) //Serial mode for TS pad
2161 {
2162 // serial
2163 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
2164 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2165
2166 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
2167 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2168 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
2169 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2170 temp_val|=0x04;
2171 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2172 #else
2173 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
2174 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2175 temp_val|=0x07;
2176 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2177 #endif
2178 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
2179 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
2180
2181 //// INTERN_DVBS TS Control: Serial //////////
2182
2183 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, TS_SERIAL);
2184
2185 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2186 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 0);
2187 #else
2188 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 1);
2189 #endif
2190 gsCmdPacketDVBS.cmd_code = CMD_TS_CTRL;
2191
2192 gsCmdPacketDVBS.param[0] = TS_SERIAL;
2193 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2194 gsCmdPacketDVBS.param[1] = 0;//TS_CLK_NO_INV;
2195 #else
2196 gsCmdPacketDVBS.param[1] = 1;//TS_CLK_INVERSE;
2197 #endif
2198 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 2);
2199 }
2200 else
2201 {
2202 //parallel
2203 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
2204 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2205
2206 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2207 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2208 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2209 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
2210 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2211 temp_val|=0x05;
2212 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2213 #else
2214 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
2215 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2216 temp_val|=0x07;
2217 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2218 #endif
2219
2220 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
2221 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
2222
2223 //// INTERN_DVBS TS Control: Parallel //////////
2224
2225 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, TS_PARALLEL);
2226
2227 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2228 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 0);
2229 #else
2230 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 1);
2231 #endif
2232 //// INTERN_DVBC TS Control: Parallel //////////
2233 gsCmdPacketDVBS.cmd_code = CMD_TS_CTRL;
2234
2235 gsCmdPacketDVBS.param[0] = TS_PARALLEL;
2236 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2237 gsCmdPacketDVBS.param[1] = 0;//TS_CLK_NO_INV;
2238 #else
2239 gsCmdPacketDVBS.param[1] = 1;//TS_CLK_INVERSE;
2240 #endif
2241 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 2);
2242 }
2243
2244 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2245 DBG_INTERN_DVBS(printf("---> Inversion(Bit5) = %d \n",0 ));
2246 #else
2247 DBG_INTERN_DVBS(printf("---> Inversion(Bit5) = %d \n",1 ));
2248 #endif
2249
2250 INTERN_DVBS_Driving_Control(INTERN_DVBS_DTV_DRIVING_LEVEL);
2251 return status;
2252 }
2253
2254 /************************************************************************************************
2255 Subject: TS1 output control
2256 Function: INTERN_DVBS_PAD_TS1_Enable
2257 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
2258 Return: void
2259 Remark:
2260 *************************************************************************************************/
INTERN_DVBS_PAD_TS1_Enable(MS_BOOL flag)2261 void INTERN_DVBS_PAD_TS1_Enable(MS_BOOL flag)
2262 {
2263 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_TS1_Enable... \n"));
2264
2265 if(flag) // PAD_TS1 Enable TS CLK PAD
2266 {
2267 //printf("=== TS1_Enable ===\n");
2268 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
2269 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
2270 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
2271 }
2272 else // PAD_TS1 Disable TS CLK PAD
2273 {
2274 //printf("=== TS1_Disable ===\n");
2275 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
2276 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
2277 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
2278 }
2279 }
2280
2281 /************************************************************************************************
2282 Subject: channel change config
2283 Function: INTERN_DVBC_Config
2284 Parmeter: BW: bandwidth
2285 Return: MS_BOOL :
2286 Remark:
2287 *************************************************************************************************/
INTERN_DVBS_Config(MS_U32 u32SymbolRate,DMD_DVBS_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)2288 MS_BOOL INTERN_DVBS_Config(MS_U32 u32SymbolRate, DMD_DVBS_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
2289 {
2290
2291 MS_BOOL status= true;
2292 MS_U16 u16CenterFreq;
2293 // MS_U16 u16Fc = 0;
2294 MS_U8 temp_val;
2295 MS_U8 u8Data =0;
2296 MS_U8 u8counter = 0;
2297 MS_U32 u32CurrentSR;
2298
2299 u32CurrentSR = u32SymbolRate/1000; //KHz
2300 //u32SymbolRate= u32SymbolRate/1000;//to match fw format
2301 u16CenterFreq =u32IFFreq;
2302 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_config+, SR=%d, QAM=%d, u32IFFreq=%d, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n", u32CurrentSR, eQamMode, u32IFFreq, bSpecInv, bSerialTS, u8TSClk));
2303 DBG_INTERN_DVBS(printf("INTERN_DVBS_Config, t = %d\n",MsOS_GetSystemTime()));
2304
2305 u8TSClk=0x05;//if (u8TSClk == 0xFF) u8TSClk=0x13;//set a fater speed for initial condition
2306 status &= INTERN_DVBS_Reset();
2307
2308 u8DemodLockFlag=0;
2309
2310 // Symbol Rate
2311 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, u32CurrentSR&0xff);
2312 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, (u32CurrentSR>>8)&0xff);
2313 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, (u32CurrentSR>>16)&0xff);
2314 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config u32SymbolRate %d<<<\n", u32CurrentSR));
2315
2316 #if 0
2317 //======== check SR is right or not ===========
2318 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &u8Data);
2319 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L,u8Data));
2320 u32SR =u8Data;
2321 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &u8Data);
2322 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H,u8Data));
2323 u32SR =((U32)u8Data<<8)|u32SR ;
2324 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &u8Data);
2325 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MB_DMDTOP_DBG_5 addr=%d mailbox value=%d<<<\n", E_DMD_S2_MB_DMDTOP_DBG_5,u8Data));
2326 u32SR =((U32)u8Data<<16)|u32SR;
2327 //=================================================
2328 #endif
2329
2330 // IQ Swap ,ADCPLL IQ swap / DMDANA_IQ_SWAP
2331 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_IQ_SWAP, bSpecInv? 0x01:0x00);
2332 if(bSpecInv)
2333 {
2334 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DMDANA_REG_BASE+0xC0, &u8Data);//Demod\reg_dmdana.xls
2335 u8Data|=(0x02);
2336 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DMDANA_REG_BASE+0xC0, u8Data);
2337 }
2338
2339 // TS mode
2340 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, bSerialTS? 0x01:0x00);
2341 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config TS Serial %d<<<\n", bSerialTS));
2342 _bSerialTS = bSerialTS;
2343
2344 if (bSerialTS)
2345 {
2346 // serial
2347 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2348 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2349
2350 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
2351 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2352 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2353 temp_val|=0x04;
2354 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2355 #else
2356 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2357 temp_val|=0x07;
2358 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2359 #endif
2360 }
2361 else
2362 {
2363 //parallel
2364 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2365 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2366
2367 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2368 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2369 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2370 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2371 temp_val|=0x05;
2372 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2373 #else
2374 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2375 temp_val|=0x07;
2376 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2377 #endif
2378 }
2379 #if (INTERN_DVBS_INTERNAL_DEBUG == 1)
2380 INTERN_DVBS_Show_Demod_Version();
2381 #endif
2382
2383 //-----------------------------------------------------------
2384 //From INTERN_DVBS_Demod_Restart function.
2385
2386 //FW sw reset
2387 //[0]: 0: SW Reset, 1: Start state machine
2388 //[1]: 1: Blind scan enable, 0: manual scan
2389 //[2]: 1: Code flow track enable
2390 //[3]: 1: go to AGC state
2391 //[4]: 1: set DiSEqC
2392 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2393 u8Data = (u8Data&0xF0)|0x01;
2394 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2395 //DBG_INTERN_DVBS(printf(">>>REG write check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2396 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2397 //DBG_INTERN_DVBS(printf(">>>REG read check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2398
2399 u8counter = 20;
2400 while( ((u8Data&0x01) == 0x00) && (u8counter != 0) )
2401 {
2402 MsOS_DelayTask(1);
2403 printf("TOP_WR_DBG_90=0x%x, status=%d, u8counter=%d\n", u8Data, status, u8counter);
2404 u8Data|=0x01;
2405 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
2406 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
2407 DBG_INTERN_DVBS(printf(">>>(while)REG read check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2408 u8counter--;
2409 }
2410
2411 if((u8Data & 0x01)==0x00)
2412 {
2413 status = FALSE;
2414 }
2415
2416 DBG_INTERN_DVBS(printf("INTERN_DVBS_config done\n"));
2417 return status;
2418 }
2419 /************************************************************************************************
2420 Subject: channel change config
2421 Function: INTERN_DVBS_Blind_Scan_Config
2422 Parmeter: BW: bandwidth
2423 Return: MS_BOOL :
2424 Remark:
2425 *************************************************************************************************/
INTERN_DVBS_BlindScan_Config(MS_U32 u32SymbolRate,DMD_DVBS_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)2426 MS_BOOL INTERN_DVBS_BlindScan_Config(MS_U32 u32SymbolRate, DMD_DVBS_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
2427 {
2428
2429 MS_BOOL status= true;
2430 MS_U16 u16CenterFreq;
2431 // MS_U16 u16Fc = 0;
2432 MS_U8 temp_val;
2433 MS_U8 u8Data=0;
2434 MS_U16 u16WaitCount = 0;
2435 MS_U32 u32CurrentSR;
2436
2437 u32CurrentSR = u32SymbolRate/1000; //KHz
2438 //u32SymbolRate= u32SymbolRate/1000;//to match fw format
2439 u16CenterFreq =u32IFFreq;
2440 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_blindScan_Config+, SR=%d, QAM=%d, u32IFFreq=%d, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n", u32CurrentSR, eQamMode, u32IFFreq, bSpecInv, bSerialTS, u8TSClk));
2441 DBG_INTERN_DVBS(printf("INTERN_DVBS_blindScan_Config, t = %d\n",MsOS_GetSystemTime()));
2442
2443 //status &= INTERN_DVBS_Reset();
2444 g_dvbs_lock = 0;
2445 u8DemodLockFlag=0;
2446
2447 // Symbol Rate
2448 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, u32CurrentSR&0xff);
2449 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, (u32CurrentSR>>8)&0xff);
2450 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, (u32CurrentSR>>16)&0xff);
2451 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config u32SymbolRate %d<<<\n", u32CurrentSR));
2452
2453 #if 0
2454 //======== check SR is right or not ===========
2455 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &u8Data);
2456 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L,u8Data));
2457 u32SR =u8Data;
2458 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &u8Data);
2459 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H,u8Data));
2460 u32SR =((U32)u8Data<<8)|u32SR ;
2461 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &u8Data);
2462 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MB_DMDTOP_DBG_5 addr=%d mailbox value=%d<<<\n", E_DMD_S2_MB_DMDTOP_DBG_5,u8Data));
2463 u32SR =((U32)u8Data<<16)|u32SR;
2464 //=================================================
2465 #endif
2466
2467 // IQ Swap ,ADCPLL IQ swap / DMDANA_IQ_SWAP
2468 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_IQ_SWAP, bSpecInv? 0x01:0x00);
2469 if(bSpecInv)
2470 {
2471 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DMDANA_REG_BASE+0xC0, &u8Data);//Demod\reg_dmdana.xls
2472 u8Data|=(0x02);
2473 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DMDANA_REG_BASE+0xC0, u8Data);
2474 }
2475
2476 // TS mode
2477 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, bSerialTS? 0x01:0x00);
2478 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config TS Serial %d<<<\n", bSerialTS));
2479 _bSerialTS = bSerialTS;
2480 u8TSClk=0x05;//if (u8TSClk == 0xFF) u8TSClk=0x13;//set a fater speed for initial condition
2481
2482 if (bSerialTS)
2483 {
2484 // serial
2485 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2486 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2487
2488 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
2489 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2490 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2491 temp_val|=0x04;
2492 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2493 #else
2494 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2495 temp_val|=0x07;
2496 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2497 #endif
2498 }
2499 else
2500 {
2501 //parallel
2502 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2503 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2504
2505 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2506 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2507 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2508 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2509 temp_val|=0x05;
2510 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2511 #else
2512 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2513 temp_val|=0x07;
2514 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2515 #endif
2516 }
2517 #if (INTERN_DVBS_INTERNAL_DEBUG == 1)
2518 INTERN_DVBS_Show_Demod_Version();
2519 #endif
2520
2521 //-----------------------------------------------------------
2522 //From INTERN_DVBS_Demod_Restart function.
2523
2524 //enable send DiSEqC
2525 //[0]: 0: SW Reset, 1: Start state machine
2526 //[1]: 1: Blind scan enable, 0: manual scan
2527 //[2]: 1: Code flow track enable
2528 //[3]: 1: go to AGC state
2529 //[4]: 1: set DiSEqC
2530 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2531 u8Data |= 0x08;
2532 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2533
2534 u16WaitCount=0;
2535 do
2536 {
2537 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
2538 u16WaitCount++;
2539 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
2540 MsOS_DelayTask(1);
2541 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
2542
2543 // disable blind scan
2544 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2545 u8Data&=~(0x02);
2546 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2547
2548 // make state machine running from while in state 1 substate0
2549 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2550 u8Data&=~(0x08);
2551 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2552
2553
2554 DBG_INTERN_DVBS(printf("INTERN_DVBS_blindScan_Config done\n"));
2555 return status;
2556 }
2557
INTERN_DVBS_Power_ON_OFF(MS_U8 bPowerOn)2558 void INTERN_DVBS_Power_ON_OFF(MS_U8 bPowerOn)
2559 {
2560 bPowerOn = bPowerOn;
2561 }
2562
INTERN_DVBS_Power_Save(void)2563 MS_BOOL INTERN_DVBS_Power_Save(void)
2564 {
2565 return TRUE;
2566 }
2567 //------------------------------------------------------------------
2568 // END System Info Function
2569 //------------------------------------------------------------------
2570
2571 //------------------------------------------------------------------
2572 // Get And Show Info Function
2573 //------------------------------------------------------------------
2574 /************************************************************************************************
2575 Subject: enable hw to lock channel
2576 Function: INTERN_DVBS_Active
2577 Parmeter: bEnable
2578 Return: MS_BOOL
2579 Remark:
2580 *************************************************************************************************/
INTERN_DVBS_Active(MS_BOOL bEnable)2581 MS_BOOL INTERN_DVBS_Active(MS_BOOL bEnable)
2582 {
2583 MS_U8 status = TRUE;
2584 //MS_U8 u8Data;
2585
2586 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_Active\n"));
2587
2588 //// INTERN_DVBS Finite State Machine on/off //////////
2589 #if 0
2590 gsCmdPacketDVBC.cmd_code = CMD_FSM_CTRL;
2591
2592 gsCmdPacketDVBS.param[0] = (MS_U8)bEnable;
2593 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 1);
2594 #else
2595
2596 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
2597 #endif
2598
2599 bDMD_DVBS_NoChannelDetectedWithRFPower = FALSE;
2600 u32DMD_DVBS_NoChannelTimeAccWithRFPower = 0;
2601 return status;
2602 }
2603
INTERN_DVBS_GetTsDivNum(MS_FLOAT * fTSDivNum)2604 MS_BOOL INTERN_DVBS_GetTsDivNum(MS_FLOAT* fTSDivNum)
2605 {
2606 MS_U8 u8Data = 0;
2607 MS_BOOL status = true;
2608 MS_U32 u32SymbolRate=0;
2609 //float fSymbolRate;
2610 //MS_U8 ISSY_EN = 0;
2611 MS_U8 code_rate_idx = 0;
2612 MS_U8 pilot_flag = 0;
2613 MS_U8 fec_type_idx = 0;
2614 MS_U8 mod_type_idx = 0;
2615 MS_U16 k_bch_array[2][11] ={
2616 {16008, 21408, 25728, 32208, 38688, 43040, 48408, 51648, 53840, 57472, 58192},
2617 { 3072, 5232, 6312, 7032, 9552, 10632, 11712, 12432, 13152, 14232, 0}};
2618 MS_U16 n_ldpc_array[2] = {64800, 16200};
2619 MS_FLOAT pilot_term = 0;
2620 MS_FLOAT k_bch;
2621 MS_FLOAT n_ldpc;
2622 MS_FLOAT ts_div_num_offset = 2.0;
2623 //MS_U32 u32Time_start,u32Time_end;
2624 //MS_U32 u32temp;
2625 //MS_FLOAT pkt_interval;
2626 //MS_U8 time_counter=0;
2627
2628 INTERN_DVBS_GetCurrentSymbolRate(&u32SymbolRate);
2629 //fSymbolRate=u32SymbolRate+0.0;///1000.0;//Symbol Rate(KHz)
2630 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum u32SymbolRate=%d\n", u32SymbolRate));
2631 // DMD_DVBS_MODULATION_TYPE pQAMMode;
2632
2633 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//V
2634 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum GetCurrentDemodType E_DMD_S2_SYSTEM_TYPE=%d\n", u8Data));//u8Data:0 is S2; 1 is DVBS
2635
2636 if(!u8Data)//DVBS2
2637 {
2638 #if 0
2639 //Get DVBS2 Code Rate
2640 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);//V
2641 printf("[S2]INTERN_DVBS_GetTsDivNum DVBS2 E_DMD_S2_CODERATE=0x%x\n", u8Data);
2642 switch (u8Data)
2643 {
2644 case 0x03: //CR 1/2
2645 k_bch=32208.0;
2646 _u8_DVBS2_CurrentCodeRate = 5;
2647 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_2\n"));
2648 break;
2649 case 0x01: //CR 1/3
2650 k_bch=21408.0; //8PSK???
2651 _u8_DVBS2_CurrentCodeRate = 6;
2652 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_3\n"));
2653 break;
2654 case 0x05: //CR 2/3
2655 k_bch=43040.0;
2656 _u8_DVBS2_CurrentCodeRate = 7;
2657 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=2_3\n"));
2658 break;
2659 case 0x00: //CR 1/4
2660 k_bch=16008.0; //8PSK???
2661 _u8_DVBS2_CurrentCodeRate = 8;
2662 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_4\n"));
2663 break;
2664 case 0x06: //CR 3/4
2665 k_bch=48408.0;
2666 _u8_DVBS2_CurrentCodeRate = 9;
2667 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=3_4\n"));
2668 break;
2669 case 0x02: //CR 2/5
2670 k_bch=25728.0; //8PSK???
2671 _u8_DVBS2_CurrentCodeRate = 10;
2672 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=2_5\n"));
2673 break;
2674 case 0x04: //CR 3/5
2675 k_bch=38688.0;
2676 _u8_DVBS2_CurrentCodeRate = 11;
2677 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=3_5\n"));
2678 break;
2679 case 0x07: //CR 4/5
2680 k_bch=51648.0;
2681 _u8_DVBS2_CurrentCodeRate = 12;
2682 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=4_5\n"));
2683 break;
2684 case 0x08: //CR 5/6
2685 k_bch=53840.0;
2686 _u8_DVBS2_CurrentCodeRate = 13;
2687 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=5_6\n"));
2688 break;
2689 case 0x09: //CR 8/9
2690 k_bch=57472.0;
2691 _u8_DVBS2_CurrentCodeRate = 14;
2692 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=8_9\n"));
2693 break;
2694 case 0x0A: //CR 9/10
2695 k_bch=58192.0;
2696 _u8_DVBS2_CurrentCodeRate = 15;
2697 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=9_10\n"));
2698 break;
2699 default:
2700 k_bch=58192.0;
2701 _u8_DVBS2_CurrentCodeRate = 15;
2702 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate= default 9_10\n"));
2703 break;
2704 } //printf("INTERN_DVBS_GetTsDivNum k_bch=%ld\n", (MS_U32)k_bch);
2705 #endif
2706 //INTERN_DVBS_GetCurrentModulationType(&pQAMMode); //V
2707 //printf("INTERN_DVBS_GetTsDivNum Mod_order=%d\n", modulation_order);
2708
2709 // pilot_flag => 0 : off 1 : on
2710 // fec_type_idx => 0 : normal 1 : short
2711 // mod_type_idx => 0 : QPSK 1 : 8PSK 2 : 16APSK 3 : 32APSK
2712 // code_rate_idx => d0: 1/4, d1: 1/3, d2: 2/5, d3: 1/2, d4: 3/5, d5: 2/3, d6: 3/4, d7: 4/5, d8: 5/6, d9: 8/9, d10: 9/10
2713 //set TS clock rate
2714 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &code_rate_idx);
2715 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FEC_TYPE, &fec_type_idx);
2716 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MOD_TYPE, &mod_type_idx);
2717 modulation_order = mod_type_idx;
2718 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_PILOT_FLAG, &pilot_flag);
2719 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_PILOT_FLAG, &u8Data);
2720
2721 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_ISSY_ACTIVE, &ISSY_EN);
2722 //if(ISSY_EN==0)
2723 //{
2724 k_bch = k_bch_array[fec_type_idx][code_rate_idx];
2725 n_ldpc = n_ldpc_array[fec_type_idx];
2726 pilot_term = ((float) n_ldpc / modulation_order / 1440 * 36) * pilot_flag;
2727 if(_bSerialTS)//serial mode
2728 {
2729 *fTSDivNum =288000.0/(k_bch/((n_ldpc/modulation_order+90+pilot_term)/u32SymbolRate));
2730 *fTSDivNum = *fTSDivNum/2 -1;
2731 }
2732 else//parallel mode
2733 {
2734 *fTSDivNum = 288000.0/(k_bch/((n_ldpc/modulation_order+90+pilot_term)/u32SymbolRate)/8);
2735 *fTSDivNum = *fTSDivNum/2 -1;
2736 }
2737 *fTSDivNum-=ts_div_num_offset;
2738 //}
2739 #if 0
2740 else if(ISSY_EN==1)//ISSY = 1
2741 {
2742 //u32Time_start = msAPI_Timer_GetTime0();
2743 time_counter=0;
2744 do
2745 {
2746 MDrv_SYS_DMD_VD_MBX_ReadReg((0x3E00 + 0x4D*2), &u8Data);//DVBS2OPPRO_ISCR_CAL_DONE (_REG_DVBS2OPPRO(0x4D)+0)
2747 u8Data &= 0x01;
2748 // u32Time_end =msAPI_Timer_GetTime0();
2749 MsOS_DelayTask(1);
2750 time_counter = time_counter +1;
2751 }while( (u8Data!=0x01) && ( (time_counter )< 50) );
2752
2753 //read pkt interval
2754 MDrv_SYS_DMD_VD_MBX_ReadReg((0x3E00 + 0x70*2), &u8Data);
2755 u32temp = u8Data;
2756 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x70*2+1), &u8Data);
2757 u32temp |= (MS_U32)u8Data<<8;
2758 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x71*2), &u8Data);
2759 u32temp |= (MS_U32)u8Data<<16;
2760 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x71*2+1), &u8Data);
2761 u32temp |= (MS_U32)u8Data<<24;
2762 pkt_interval = (MS_FLOAT) u32temp / 1024.0;
2763 if(_bSerialTS)//serial mode
2764 {
2765 *fTSDivNum=288000.0 / (188*8*u32SymbolRate/pkt_interval) - ts_div_num_offset;
2766 *fTSDivNum = (*fTSDivNum-1)/2;
2767 }
2768 else
2769 {
2770 *fTSDivNum=288000.0 / (188*u32SymbolRate/pkt_interval) - ts_div_num_offset;
2771 *fTSDivNum = (*fTSDivNum-1)/2;
2772 }
2773
2774 }
2775
2776 else
2777 {
2778 *fTSDivNum =0x0A;
2779 }
2780
2781 if(*fTSDivNum>255)
2782 *fTSDivNum=255;
2783 if(*fTSDivNum<1)
2784 *fTSDivNum=1;
2785
2786 //printf("INTERN_DVBS_GetTsDivNum Pilot E_DMD_S2_MB_DMDTOP_DBG_9=%d\n", u8Data);
2787 /*if(u8Data) // Pilot ON
2788 printf(">>>INTERN_DVBS_GetTsDivNum Pilot ON<<<\n");
2789 else //Pilot off
2790 printf(">>>INTERN_DVBS_GetTsDivNum Pilot off<<<\n");
2791 */
2792 if(_bSerialTS)
2793 {
2794 if(u8Data)//if pilot ON
2795 {
2796 if(modulation_order==2)
2797 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90+36*22)/u32SymbolRate)) - 3);
2798 else if(modulation_order==3)
2799 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90+36*15)/u32SymbolRate)) - 3);
2800 }
2801 else
2802 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90)/u32SymbolRate)) - 3);
2803 }
2804 else//Parallel mode
2805 {
2806 if(u8Data)
2807 {
2808 if(modulation_order==2)
2809 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0+36*22)/u32SymbolRate)/8.0) - 3);
2810 else if(modulation_order==3)
2811 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0+36*15)/u32SymbolRate)/8.0) - 3);
2812 }
2813 else
2814 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0)/u32SymbolRate)/8.0) - 3);
2815 }
2816 #endif
2817 }
2818 else //S
2819 {
2820 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE + 0x3A*2, &u8Data);
2821 //u8_gCodeRate = (u8Data & 0x70)>>4;
2822 //DVBS Code Rate
2823 //switch (u8_gCodeRate)
2824 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
2825 switch (u8Data)
2826 {
2827 case 0x00: //CR 1/2
2828 _u8_DVBS2_CurrentCodeRate = 0;
2829 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=1_2\n"));
2830 if(_bSerialTS)
2831 *fTSDivNum = (288000.0/((1.0/2.0)*(188.0/204.0)*u32SymbolRate*2));
2832 else
2833 *fTSDivNum = (288000.0/((1.0/2.0)*(188.0/204.0)*u32SymbolRate*2/8.0));
2834
2835 *fTSDivNum = *fTSDivNum/2-1-5;
2836 break;
2837 case 0x01: //CR 2/3
2838 _u8_DVBS2_CurrentCodeRate = 1;
2839 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=2_3\n"));
2840 if(_bSerialTS)
2841 *fTSDivNum = (MS_U8)(288000.0/((2.0/3.0)*(188.0/204.0)*u32SymbolRate*2));
2842 else
2843 *fTSDivNum = (MS_U8)(288000.0/((2.0/3.0)*(188.0/204.0)*u32SymbolRate*2/8.0));
2844
2845 *fTSDivNum = *fTSDivNum/2-1-5;
2846 break;
2847 case 0x02: //CR 3/4
2848 _u8_DVBS2_CurrentCodeRate = 2;
2849 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=3_4\n"));
2850 if(_bSerialTS)
2851 *fTSDivNum = (288000.0/((3.0/4.0)*(188.0/204.0)*u32SymbolRate*2));
2852 else
2853 *fTSDivNum = (288000.0/((3.0/4.0)*(188.0/204.0)*u32SymbolRate*2/8.0));
2854
2855 *fTSDivNum = *fTSDivNum/2-1-5;
2856 break;
2857 case 0x03: //CR 5/6
2858 _u8_DVBS2_CurrentCodeRate = 3;
2859 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=5_6\n"));
2860 if(_bSerialTS)
2861 *fTSDivNum = (288000.0/((5.0/6.0)*(188.0/204.0)*u32SymbolRate*2));
2862 else
2863 *fTSDivNum = (288000.0/((5.0/6.0)*(188.0/204.0)*u32SymbolRate*2/8.0));
2864
2865 *fTSDivNum = *fTSDivNum/2-1-5;
2866 break;
2867 case 0x04: //CR 7/8
2868 _u8_DVBS2_CurrentCodeRate = 4;
2869 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=7_8\n"));
2870 if(_bSerialTS)
2871 *fTSDivNum =(288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2));
2872 else
2873 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2/8.0));
2874
2875 *fTSDivNum = *fTSDivNum/2-1-5;
2876 break;
2877 default:
2878 _u8_DVBS2_CurrentCodeRate = 4;
2879 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate= default 7_8\n"));
2880 if(_bSerialTS)
2881 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2));
2882 else
2883 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2/8.0));
2884
2885 *fTSDivNum = *fTSDivNum/2-1-5;
2886 break;
2887 }
2888 } //printf("INTERN_DVBS_GetTsDivNum u8TSClk = 0x%x\n", *u8TSDivNum);
2889 return status;
2890 }
2891
INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK_TYPE eType,float fCurrRFPowerDbm,float fNoChannelRFPowerDbm,MS_U32 u32TimeInterval)2892 MS_BOOL INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK_TYPE eType, float fCurrRFPowerDbm, float fNoChannelRFPowerDbm, MS_U32 u32TimeInterval)
2893 {
2894 MS_U8 u8Data =0; //MS_U8 u8Data2 =0;
2895 MS_U8 bRet = TRUE;
2896 MS_FLOAT fTSDivNum=0;
2897 #ifdef MS_DEBUG
2898 MS_U16 lockingtime;
2899 MS_U16 pkterr;
2900 #endif
2901 switch( eType )
2902 {
2903 case DMD_DVBS_GETLOCK:
2904 #if (INTERN_DVBS_INTERNAL_DEBUG)
2905 INTERN_DVBS_info();
2906 #endif
2907 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2908 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_GetLock manual tune=%d<<<\n", u8Data));
2909 if ((u8Data&0x02)==0x00)//manual mode
2910 {
2911 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);
2912 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_GetLock MailBox state=%d<<<\n", u8Data));
2913
2914 if((u8Data == 15) || (u8Data == 16))
2915 {
2916 if (u8Data==15)
2917 {
2918 _bDemodType=FALSE; //S
2919 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Demod DVBS Lock<<<\n"));
2920 }
2921 else if(u8Data==16)
2922 {
2923 _bDemodType=TRUE; //S2
2924 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Demod DVBS2 Lock<<<\n"));
2925 }
2926 if(g_dvbs_lock == 0)
2927 {
2928 g_dvbs_lock = 1;
2929 }
2930
2931 if(u8DemodLockFlag==0)
2932 {
2933 u8DemodLockFlag=1;
2934
2935 // caculate TS clock divider number
2936 INTERN_DVBS_GetTsDivNum(&fTSDivNum); //ts_div_num
2937
2938 if (fTSDivNum > 0x1F)
2939 fTSDivNum = 0x1F;
2940 else if (fTSDivNum < 0x00)
2941 fTSDivNum=0x00;
2942
2943 u8Data = (MS_U8)fTSDivNum;
2944 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_GetLock TsClkDivNum = 0x%x<<<\n", u8Data));
2945 HAL_DMD_RIU_WriteByte(0x103300, u8Data);
2946
2947 }
2948 DBG_INTERN_DVBS(printf("@INTERN_DVBS_Demod Lock+++\n"));
2949 #ifdef MS_DEBUG
2950 INTERN_DVBS_GetPacketErr(&pkterr);
2951 MDrv_SYS_DMD_VD_MBX_ReadReg( FRONTEND_REG_BASE+0x7c*2+1,&u8Data);
2952 lockingtime=u8Data;
2953 MDrv_SYS_DMD_VD_MBX_ReadReg( FRONTEND_REG_BASE+0x7c*2,&u8Data);
2954 lockingtime=((lockingtime<<8)|u8Data);
2955 DBG_INTERN_DVBS(printf("@INTERN_DVBS_Demod Locking time [%d]\n",lockingtime));
2956 #endif
2957 bRet = TRUE;
2958 }
2959 else
2960 {
2961 if(g_dvbs_lock == 1)
2962 {
2963 g_dvbs_lock = 0;
2964 u8DemodLockFlag=0;
2965 }
2966 DBG_INTERN_DVBS(printf("@INTERN_DVBS_Demod UnLock---\n"));
2967 bRet = FALSE;
2968 }
2969
2970 if(_bSerialTS==1)
2971 {
2972 if (bRet==FALSE)
2973 {
2974 _bTSDataSwap=FALSE;
2975 }
2976 else
2977 {
2978 if (_bTSDataSwap==FALSE)
2979 {
2980 _bTSDataSwap=TRUE;
2981 MDrv_SYS_DMD_VD_MBX_ReadReg( (DVBTM_REG_BASE + 0x20*2), &u8Data);//DVBTM_REG_BASE
2982 u8Data^=0x20;//h0020 h0020 5 5 reg_ts_data_reverse
2983 MDrv_SYS_DMD_VD_MBX_WriteReg( (DVBTM_REG_BASE + 0x20*2), u8Data);
2984 }
2985 }
2986 }
2987 }
2988 else
2989 {
2990 bRet = TRUE;
2991 }
2992 break;
2993
2994 default:
2995 bRet = FALSE;
2996 }
2997 return bRet;
2998 }
2999
INTERN_DVBS_GetTunrSignalLevel_PWR(void)3000 float INTERN_DVBS_GetTunrSignalLevel_PWR(void)// Need check debug out table
3001 {
3002 MS_BOOL status=TRUE;
3003 MS_U16 u16Data =0;
3004 MS_U8 u8Data =0;
3005 MS_U8 u8Index =0;
3006 float fCableLess = 0.0;
3007
3008 if (FALSE == INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0) )//Demod unlock
3009 {
3010 fCableLess = 0;
3011 }
3012
3013 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x11*2, &u8Data);//FRONTEND_AGC_DEBUG_SEL
3014 u8Data=(u8Data&0xF0)|0x03;
3015 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x11*2, u8Data);
3016
3017 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x02, &u8Data);//FRONTEND_LATCH
3018 u8Data|=0x80;
3019 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x02, u8Data);
3020
3021 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x12*2+1, &u8Data);//FRONTEND_AGC_DEBUG_OUT_R1
3022 u16Data=u8Data;
3023 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x12*2, &u8Data);//FRONTEND_AGC_DEBUG_OUT_R0
3024 u16Data=(u16Data<<8)|u8Data;
3025 //printf("===========================Tuner 65535-u16Data = %d\n", (65535-u16Data));
3026 //MsOS_DelayTask(400);
3027
3028 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x02, &u8Data);//FRONTEND_LOAD0
3029 u8Data&=~(0x80);
3030 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x02, u8Data);
3031
3032 if (status==FALSE)
3033 {
3034 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS GetSignalStrength fail!!! \n "));
3035 fCableLess = 0;
3036 }
3037
3038 //printf("#### INTERN_DVBS_GetTunrSignalLevel_PWR u16Data = %d\n", (int)u16Data);
3039 for (u8Index=0; u8Index < (sizeof(_u16SignalLevel)/sizeof(_u16SignalLevel[0])); u8Index++)
3040 {
3041 if ((65535 - u16Data) <= _u16SignalLevel[u8Index][0])
3042 {
3043 if (u8Index >=1)
3044 {
3045 fCableLess = (float)(_u16SignalLevel[u8Index][1])+((float)(_u16SignalLevel[u8Index][0] - (65535 - u16Data)) / (float)(_u16SignalLevel[u8Index][0] - _u16SignalLevel[u8Index-1][0]))*(float)(_u16SignalLevel[u8Index-1][1] - _u16SignalLevel[u8Index][1]);
3046 break;
3047 }
3048 else
3049 {
3050 fCableLess = _u16SignalLevel[u8Index][1];
3051 break;
3052 }
3053 }
3054 }
3055 //---------------------------------------------------
3056 /*
3057 if (fCableLess >= 350)
3058 fCableLess = fCableLess - 35;
3059 else if ((fCableLess < 350) && (fCableLess >= 250))
3060 fCableLess = fCableLess - 25;
3061 else
3062 fCableLess = fCableLess - 5;
3063 */
3064
3065 if (fCableLess < 0)
3066 fCableLess = 0;
3067 if (fCableLess > 920)
3068 fCableLess = 920;
3069
3070 fCableLess = (-1.0)*(fCableLess/10.0);
3071
3072 DBG_INTERN_DVBS(printf("INTERN_DVBS GetSignalStrength %f\n", fCableLess));
3073
3074 return fCableLess;
3075 }
3076
3077 /****************************************************************************
3078 Subject: To get the Post viterbi BER
3079 Function: INTERN_DVBS_GetPostViterbiBer
3080 Parmeter: Quility
3081 Return: E_RESULT_SUCCESS
3082 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBC_VIT_STATUS_NG
3083 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
3084 We will not read the Period, and have the "/256/8"
3085 *****************************************************************************/
INTERN_DVBS_GetPostViterbiBer(float * postber)3086 MS_BOOL INTERN_DVBS_GetPostViterbiBer(float *postber)//POST BER //V
3087 {
3088 MS_BOOL status = true;
3089 MS_U8 reg = 0, reg_frz = 0;
3090 MS_U16 BitErrPeriod;
3091 MS_U32 BitErr;
3092
3093 /////////// Post-Viterbi BER /////////////After Viterbi
3094
3095 // freeze ,DVBSRS_BACKEND_BIT_ERR_NUM_FREEZE
3096 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1*2+1, ®_frz);//h0001 h0001 8 8 reg_ber_en
3097 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x1*2+1, reg_frz|0x01);
3098
3099 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0 ,DVBSFEC_BIT_ERR_SBLPRD_7_0
3100 // 0x47 [15:8] reg_bit_err_sblprd_15_8
3101 //KRIS register table
3102 //h0018 h0018 7 0 reg_bit_err_sblprd_7_0
3103 //h0018 h0018 15 8 reg_bit_err_sblprd_15_8
3104 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x18*2+1, ®);
3105 BitErrPeriod = reg;
3106
3107 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x18*2, ®);
3108 BitErrPeriod = (BitErrPeriod << 8)|reg;
3109
3110
3111 //h001d h001d 7 0 reg_bit_err_num_7_0
3112 //h001d h001d 15 8 reg_bit_err_num_15_8
3113 //h001e h001e 7 0 reg_bit_err_num_23_16
3114 //h001e h001e 15 8 reg_bit_err_num_31_24
3115
3116 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1E*2+1, ®);
3117 BitErr = reg;
3118 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1E*2, ®);
3119 BitErr = (BitErr << 8)|reg;
3120 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1D*2+1, ®);
3121 BitErr = (BitErr << 8)|reg;
3122 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1D*2, ®);
3123 BitErr = (BitErr << 8)|reg;
3124
3125 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
3126 reg_frz=reg_frz&(~0x01);
3127 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x1*2+1, reg_frz);
3128
3129 if (BitErrPeriod == 0 ) //PRD
3130 BitErrPeriod = 1;
3131
3132 if (BitErr <= 0 )
3133 *postber = 0.5f / ((float)BitErrPeriod*128*188*8);
3134 else
3135 *postber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
3136
3137 if (*postber <= 0.0f)
3138 *postber = 1.0e-10f;
3139
3140 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS PostVitBER = %8.3e \n", *postber));
3141
3142 return status;
3143 }
3144
3145
INTERN_DVBS_GetPreViterbiBer(float * preber)3146 MS_BOOL INTERN_DVBS_GetPreViterbiBer(float *preber)//PER BER // not yet
3147 {
3148 MS_BOOL status = true;
3149 //MS_U8 reg = 0, reg_frz = 0;
3150 //MS_U16 BitErrPeriod;
3151 //MS_U32 BitErr;
3152
3153 #if 0
3154 /////////// Pre-Viterbi BER /////////////Before Viterbi
3155
3156 // freeze ,DVBSRS_BACKEND_BIT_ERR_NUM_FREEZE
3157 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x10, ®_frz);
3158 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSTFEC_REG_BASE+0x10, reg_frz|0x08);
3159
3160 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0 ,DVBSFEC_BIT_ERR_SBLPRD_7_0
3161 // 0x47 [15:8] reg_bit_err_sblprd_15_8
3162 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x19, ®);
3163 BitErrPeriod = reg;
3164
3165 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x18, ®);
3166 BitErrPeriod = (BitErrPeriod << 8)|reg;
3167
3168 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x17, ®);
3169 BitErrPeriod = (BitErrPeriod << 8)|reg;
3170
3171 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x16, ®);
3172 BitErrPeriod = (BitErrPeriod << 8)|reg;
3173 BitErrPeriod = (BitErrPeriod & 0x3FFF);
3174
3175 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
3176 // 0x6b [15:8] reg_bit_err_num_15_8
3177 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
3178 // 0x6d [15:8] reg_bit_err_num_31_24
3179 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x1F, ®);
3180 BitErr = reg;
3181
3182 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x1E, ®);
3183 BitErr = (BitErr << 8)|reg;
3184
3185 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
3186 reg_frz=reg_frz&(~0x08);
3187 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x10, reg_frz);
3188
3189 if (BitErrPeriod ==0 )//protect 0
3190 BitErrPeriod=1;
3191 if (BitErr <=0 )
3192 *perber=0.5f / (float)BitErrPeriod / 256;
3193 else
3194 *perber=(float)BitErr / (float)BitErrPeriod / 256;
3195
3196 if (*perber <= 0.0f)
3197 *perber = 1.0e-10f;
3198
3199 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS PerVitBER = %8.3e \n", *perber));
3200 #endif
3201
3202 return status;
3203 }
3204
3205 /****************************************************************************
3206 Subject: To get the Packet error
3207 Function: INTERN_DVBS_GetPacketErr
3208 Parmeter: pktErr
3209 Return: E_RESULT_SUCCESS
3210 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
3211 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
3212 We will not read the Period, and have the "/256/8"
3213 *****************************************************************************/
INTERN_DVBS_GetPacketErr(MS_U16 * pktErr)3214 MS_BOOL INTERN_DVBS_GetPacketErr(MS_U16 *pktErr)//V
3215 {
3216 MS_BOOL status = true;
3217 MS_U8 u8Data = 0;
3218 MS_U16 u16PktErr = 0;
3219
3220 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);
3221 if(!u8Data) //DVB-S2
3222 {
3223 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x02*2, &u8Data);//DVBS2FEC_OUTER_FREEZE (_REG_DVBS2FEC(0x02)+0) //[0]
3224 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE+0x02*2, u8Data|0x01);
3225
3226 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x26*2+1, &u8Data);//DVBS2FEC_BCH_EFLAG2_SUM1 (_REG_DVBS2FEC(0x2B)+1)
3227 u16PktErr = u8Data;
3228 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x26*2, &u8Data);
3229 u16PktErr = (u16PktErr << 8)|u8Data;
3230
3231 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x02*2, &u8Data);
3232 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE+0x02*2, u8Data&(~0x01));
3233 }
3234 else
3235 { //DVB-S
3236 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x19*2, &u8Data); //0x19 [7] reg_bit_err_num_freeze
3237 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x19*2, u8Data|0x80);
3238
3239 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(REG_BACKEND+0x33*2+1, &u8Data);// DVBSFEC_UNCRT_PKT_NUM_15_8 (_REG_DVBSFEC(0x1F)+1)
3240 u16PktErr = u8Data;
3241 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(REG_BACKEND+0x33*2, &u8Data);
3242 u16PktErr = (u16PktErr << 8)|u8Data;
3243
3244 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x19*2, &u8Data); //0x19 [7] reg_bit_err_num_freeze
3245 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x19*2, u8Data&(~0x80));
3246 }
3247 *pktErr = u16PktErr;
3248
3249 DBG_INTERN_DVBS(printf("INTERN_DVBS PktErr = %d \n", (int)u16PktErr));
3250
3251 return status;
3252 }
3253
3254 /****************************************************************************
3255 Subject: Read the signal to noise ratio (SNR)
3256 Function: INTERN_DVBS_GetSNR
3257 Parmeter: None
3258 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
3259 Remark:
3260 *****************************************************************************/
INTERN_DVBS_GetSNR(float * f_snr)3261 MS_BOOL INTERN_DVBS_GetSNR(float *f_snr)//V
3262 {
3263 MS_BOOL status= TRUE;
3264 MS_U8 u8Data =0, reg_frz =0;
3265 //NDA SNR
3266 MS_U32 u32NDA_SNR_A =0;
3267 MS_U32 u32NDA_SNR_AB =0;
3268 //NDA SNR
3269 float NDA_SNR_A =0.0;
3270 float NDA_SNR_AB =0.0;
3271 float NDA_SNR =0.0;
3272 double NDA_SNR_LINEAR=0.0;
3273 //float snr_poly =0.0;
3274 //float Fixed_SNR =0.0;
3275
3276 if (INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0)== FALSE)
3277 {
3278 return 0;
3279 }
3280
3281 // freeze
3282 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE+0x04*2, ®_frz);
3283 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_INNER_REG_BASE+0x04*2, reg_frz|0x10);//INNE_LATCH bit[4]
3284
3285 //NDA SNR_A
3286 // read Linear_SNR
3287 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x47*2, &u8Data);
3288 u32NDA_SNR_A=(u8Data&0x03);
3289 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x46*2 + 1, &u8Data);
3290 u32NDA_SNR_A=(u32NDA_SNR_A<<8)|u8Data;
3291 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x46*2, &u8Data);
3292 u32NDA_SNR_A=(u32NDA_SNR_A<<8)|u8Data;
3293 //NDA SNR_AB
3294 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x49*2+1, &u8Data);
3295 u32NDA_SNR_AB=(u8Data&0x3F);
3296 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x49*2, &u8Data);
3297 u32NDA_SNR_AB = (u32NDA_SNR_AB<<8)|u8Data;
3298 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x48*2 + 1, &u8Data);
3299 u32NDA_SNR_AB=(u32NDA_SNR_AB<<8)|u8Data;
3300 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x48*2, &u8Data);
3301 u32NDA_SNR_AB=(u32NDA_SNR_AB<<8)|u8Data;
3302
3303 //UN_freeze
3304 reg_frz=reg_frz&(~0x10);
3305 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_INNER_REG_BASE+0x08, reg_frz);
3306
3307 if (status== FALSE)
3308 {
3309 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetSNR Fail! \n"));
3310 return 0;
3311 }
3312 //NDA SNR
3313 NDA_SNR_A=(float)u32NDA_SNR_A/65536;
3314 NDA_SNR_AB=(float)u32NDA_SNR_AB/4194304;
3315 //
3316 //since support 16,32APSK we need to add judgement
3317 if(modulation_order==4)
3318 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB/(2-1.252295758529242));//for 16APSK CR2/3
3319 else if(modulation_order==5)//(2-1.41333232789)
3320 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB/(2-1.41333232789));//for 32APSK CR3/4
3321 else
3322 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB);
3323
3324 NDA_SNR_LINEAR =(1/((NDA_SNR_A/NDA_SNR_AB)-1)) ;
3325
3326 if(NDA_SNR_LINEAR<=0)
3327 NDA_SNR=1.0;
3328 else
3329 NDA_SNR=10*log10(NDA_SNR_LINEAR);
3330
3331 DBG_INTERN_DVBS(printf("[DVBS]: NDA_SNR ================================: %.1f\n", NDA_SNR));
3332 _f_DVBS_CurrentSNR = NDA_SNR;
3333 /*
3334 //[DVBS/S2, QPSK/8PSK, 1/2~9/10 the same CN]
3335 snr_poly = 0.0; //use Polynomial curve fitting to fix SNR
3336 snr_poly = 0.005261367463671*pow(NDA_SNR, 3)-0.116517828301214*pow(NDA_SNR, 2)+0.744836970505452*pow(NDA_SNR, 1)-0.86727609780167;
3337 Fixed_SNR = NDA_SNR + snr_poly;
3338 //printf("[DVBS]: NDA_SNR + snr_poly =====================: %.1f\n", Fixed_SNR);
3339
3340 if (Fixed_SNR < 17.0)
3341 Fixed_SNR = Fixed_SNR;
3342 else if ((Fixed_SNR < 20.0) && (Fixed_SNR >= 17.0))
3343 Fixed_SNR = Fixed_SNR - 0.8;
3344 else if ((Fixed_SNR < 22.5) && (Fixed_SNR >= 20.0))
3345 Fixed_SNR = Fixed_SNR - 2.0;
3346 else if ((Fixed_SNR < 27.0) && (Fixed_SNR >= 22.5))
3347 Fixed_SNR = Fixed_SNR - 3.0;
3348 else if ((Fixed_SNR < 29.0) && (Fixed_SNR >= 27.0))
3349 Fixed_SNR = Fixed_SNR - 3.5;
3350 else if (Fixed_SNR >= 29.0)
3351 Fixed_SNR = Fixed_SNR - 3.0;
3352
3353 if (Fixed_SNR < 1.0)
3354 Fixed_SNR = 1.0;
3355 if (Fixed_SNR > 30.0)
3356 Fixed_SNR = 30.0;
3357 */
3358 *f_snr = NDA_SNR;
3359 //printf("[DVBS]: NDA_SNR=============================: %.1f\n", NDA_SNR);
3360
3361 return status;
3362 }
3363
3364 //SSI
INTERN_DVBS_GetSignalStrength(MS_U16 * pu16SignalBar,const DMD_DVBS_InitData * sDMD_DVBS_InitData,MS_U8 u8SarValue,float fRFPowerDbm)3365 MS_BOOL INTERN_DVBS_GetSignalStrength(MS_U16 *pu16SignalBar, const DMD_DVBS_InitData *sDMD_DVBS_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
3366 {
3367 //-1.2~-92.2 dBm
3368 MS_BOOL status = true;
3369 MS_U8 u8Data =0;
3370 MS_U8 _u8_DVBS2_CurrentCodeRateLocal = 0;
3371 float ch_power_db=0.0f, ch_power_db_rel=0.0f;
3372
3373 DBG_INTERN_DVBS_TIME(printf("INTERN_DVBS_GetSignalStrength, t=%d, RF level=%f, Table=%x\n",MsOS_GetSystemTime(), fRFPowerDbm, (MS_U32)(sDMD_DVBS_InitData->pTuner_RfagcSsi)));
3374
3375 // if (INTERN_DVBC_Lock(COFDM_TPS_LOCK))
3376 // if (INTERN_DVBC_Lock(COFDM_AGC_LOCK))
3377 // Actually, it's more reasonable, that signal level depended on cable input power level
3378 // thougth the signal isn't dvb-t signal.
3379 //
3380 // use pointer of IFAGC table to identify
3381 // case 1: RFAGC from SAR, IFAGC controlled by demod
3382 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
3383 //status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
3384 // sDMD_DVBS_InitData->pTuner_RfagcSsi, sDMD_DVBS_InitData->u16Tuner_RfagcSsi_Size,
3385 // sDMD_DVBS_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBS_InitData->u16Tuner_IfagcSsi_HiRef_Size,
3386 // sDMD_DVBS_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBS_InitData->u16Tuner_IfagcSsi_LoRef_Size,
3387 // sDMD_DVBS_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBS_InitData->u16Tuner_IfagcErr_HiRef_Size,
3388 // sDMD_DVBS_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBS_InitData->u16Tuner_IfagcErr_LoRef_Size);
3389 ch_power_db = INTERN_DVBS_GetTunrSignalLevel_PWR();
3390 //printf("@@@@@@@@@ ch_power_db = %f \n", ch_power_db);
3391
3392 MS_U8 u8Data2 = 0;
3393 MS_U8 _u8_DVBS2_CurrentConstellationLocal = 0;
3394 DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3395
3396
3397 status &= INTERN_DVBS_GetCurrentDemodType(&pDemodType);
3398
3399 if((MS_U8)pDemodType == (MS_U8)DMD_SAT_DVBS)//S
3400 {
3401 float fDVBS_SSI_Pref[]=
3402 {
3403 //0, 1, 2, 3, 4
3404 -78.9, -77.15, -76.14, -75.19, -74.57,//QPSK
3405 };
3406 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE + 0x84, &u8Data);
3407 _u8_DVBS2_CurrentCodeRateLocal = (u8Data & 0x07);
3408 ch_power_db_rel = ch_power_db - fDVBS_SSI_Pref[_u8_DVBS2_CurrentCodeRateLocal];
3409 }
3410 else
3411 {
3412 float fDVBS2_SSI_Pref[][11]=
3413 {
3414 // 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
3415 //1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10
3416 {-85.17, -84.08, -83.15, -81.86, -80.63, -79.77, -78.84, -78.19, -77.69, -76.68, -76.46}, //QPSK
3417 { 0.0, 0.0, 0.0, 0.0, -77.36, -76.24, -74.95, 0.0, -73.52, -72.18, -71.84} //8PSK
3418 };
3419
3420 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
3421 _u8_DVBS2_CurrentCodeRateLocal = (u8Data & 0x3C)>>2;
3422
3423 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
3424 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD6, &u8Data2);
3425
3426 if(((u8Data & 0x03)==0x01) && ((u8Data2 & 0x80)==0x00))
3427 {
3428 _u8_DVBS2_CurrentConstellationLocal = DMD_DVBS_QPSK;
3429 }
3430 else if (((u8Data & 0x03)==0x01) && ((u8Data2 & 0x80)==0x80))
3431 {
3432 _u8_DVBS2_CurrentConstellationLocal = DMD_DVBS_8PSK;//8PSK
3433 }
3434 ch_power_db_rel = ch_power_db - fDVBS2_SSI_Pref[_u8_DVBS2_CurrentConstellationLocal][_u8_DVBS2_CurrentCodeRateLocal];
3435 }
3436
3437 if(ch_power_db_rel <= -15.0f)
3438 {
3439 *pu16SignalBar = 0;
3440 }
3441 else if (ch_power_db_rel <= 0.0f)
3442 {
3443 *pu16SignalBar = (MS_U16)(2.0f/3 * (ch_power_db_rel+15.0f));
3444 }
3445 else if (ch_power_db_rel <= 20.0f)
3446 {
3447 *pu16SignalBar = (MS_U16)(4.0f * ch_power_db_rel + 10.0f);
3448 }
3449 else if (ch_power_db_rel <= 35.0f)
3450 {
3451 *pu16SignalBar = (MS_U16)(2.0f/3 * (ch_power_db_rel-20.0f) + 90.0);
3452 }
3453 else
3454 {
3455 *pu16SignalBar = 100;
3456 }
3457
3458 DBG_INTERN_DVBS(printf(">>>>>Signal Strength(SSI) = %d\n", (int)*pu16SignalBar));
3459
3460 return status;
3461 }
3462
3463 //SQI
3464 /****************************************************************************
3465 Subject: To get the DVT Signal quility
3466 Function: INTERN_DVBS_GetSignalQuality
3467 Parmeter: Quility
3468 Return: E_RESULT_SUCCESS
3469 E_RESULT_FAILURE
3470 Remark: Here we have 4 level range
3471 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
3472 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
3473 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
3474 <4>.4th Range => Quality <10
3475 *****************************************************************************/
INTERN_DVBS_GetSignalQuality(MS_U16 * quality,const DMD_DVBS_InitData * sDMD_DVBS_InitData,MS_U8 u8SarValue,float fRFPowerDbm)3476 MS_BOOL INTERN_DVBS_GetSignalQuality(MS_U16 *quality, const DMD_DVBS_InitData *sDMD_DVBS_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
3477 {
3478
3479 float fber = 0.0;
3480 //float log_ber;
3481 MS_BOOL status = TRUE;
3482 float f_snr = 0.0, ber_sqi = 0.0, cn_rel = 0.0;
3483 MS_U8 u8Data =0;
3484 MS_U16 u16Data =0;
3485 DMD_DVBS_CODE_RATE_TYPE _u8_DVBS2_CurrentCodeRateLocal ;
3486 MS_U16 bchpkt_error,BCH_Eflag2_Window;
3487 //fRFPowerDbm = fRFPowerDbm;
3488 float snr_poly =0.0;
3489 float Fixed_SNR =0.0;
3490 double eFlag_PER=0.0;
3491
3492 if (TRUE == INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0))
3493 {
3494 if(_bDemodType) //S2
3495 {
3496
3497 //INTERN_DVBS_GetSNR(&f_snr);
3498 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_7, &u8Data);
3499 u16Data=u8Data;
3500 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_6, &u8Data);
3501 u16Data = (u16Data<<8)|u8Data;
3502 f_snr=(float)u16Data/256.0;
3503 snr_poly = 0.005261367463671*pow(f_snr, 3)-0.116517828301214*pow(f_snr, 2)+0.744836970505452*pow(f_snr, 1)-0.86727609780167;
3504 Fixed_SNR = f_snr + snr_poly;
3505
3506 if (Fixed_SNR < 17.0)
3507 Fixed_SNR = Fixed_SNR;
3508 else if ((Fixed_SNR < 20.0) && (Fixed_SNR >= 17.0))
3509 Fixed_SNR = Fixed_SNR - 0.8;
3510 else if ((Fixed_SNR < 22.5) && (Fixed_SNR >= 20.0))
3511 Fixed_SNR = Fixed_SNR - 2.0;
3512 else if ((Fixed_SNR < 27.0) && (Fixed_SNR >= 22.5))
3513 Fixed_SNR = Fixed_SNR - 3.0;
3514 else if ((Fixed_SNR < 29.0) && (Fixed_SNR >= 27.0))
3515 Fixed_SNR = Fixed_SNR - 3.5;
3516 else if (Fixed_SNR >= 29.0)
3517 Fixed_SNR = Fixed_SNR - 3.0;
3518
3519
3520 if (Fixed_SNR < 1.0)
3521 Fixed_SNR = 1.0;
3522 if (Fixed_SNR > 30.0)
3523 Fixed_SNR = 30.0;
3524
3525 //BCH EFLAG2_Window, window size 0x2000
3526 BCH_Eflag2_Window=0x2000;
3527 MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE + 0x25*2 + 1, (BCH_Eflag2_Window>>8));
3528 MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE + 0x25*2 , (BCH_Eflag2_Window&0xff));
3529 INTERN_DVBS_GetPacketErr(&bchpkt_error);
3530 eFlag_PER = (float)(bchpkt_error)/(float)(BCH_Eflag2_Window);
3531 if(eFlag_PER>0)
3532 fber = 0.089267531133002*pow(eFlag_PER, 2) + 0.019640560289510*eFlag_PER + 0.0000001;
3533 else
3534 fber = 0;
3535
3536 #ifdef MSOS_TYPE_LINUX
3537 //log_ber = ( - 1) *log10f(1 / fber);
3538 if (fber > 1.0E-1)
3539 ber_sqi = (log10f(1.0f/fber))*20.0f + 8.0f;
3540 else if(fber > 8.5E-7)
3541 ber_sqi = (log10f(1.0f/fber))*20.0f - 30.0f;
3542 else
3543 ber_sqi = 100.0;
3544 #else
3545 //log_ber = ( - 1) *Log10Approx(1 / fber);
3546 if (fber > 1.0E-1)
3547 ber_sqi = (Log10Approx(1.0f/fber))*20.0f + 8.0f;
3548 else if(fber > 8.5E-7)
3549 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 30.0f;
3550 else
3551 ber_sqi = 100.0;
3552
3553 #endif
3554
3555 *quality = Fixed_SNR/30*ber_sqi;
3556 DBG_INTERN_DVBS(printf(" Fixed_SNR %f\n",Fixed_SNR));
3557 DBG_INTERN_DVBS(printf(" BCH_Eflag2_Window %d\n",BCH_Eflag2_Window));
3558 DBG_INTERN_DVBS(printf(" eFlag_PER [%f]\n fber [%8.3e]\n ber_sqi [%f]\n",eFlag_PER,fber,ber_sqi));
3559 }
3560 else //S
3561 {
3562 if (INTERN_DVBS_GetPostViterbiBer(&fber) == FALSE)//ViterbiBer
3563 {
3564 DBG_INTERN_DVBS(printf("\nGetPostViterbiBer Fail!"));
3565 return FALSE;
3566 }
3567 _fPostBer=fber;
3568
3569
3570 if (status==FALSE)
3571 {
3572 DBG_INTERN_DVBS(printf("MSB131X_DTV_GetSignalQuality GetPostViterbiBer Fail!\n"));
3573 return 0;
3574 }
3575 float fDVBS_SQI_CNref[]=
3576 { //0, 1, 2, 3, 4
3577 4.2, 5.9, 6, 6.9, 7.5,//QPSK
3578 };
3579
3580 INTERN_DVBS_GetCurrentDemodCodeRate(&_u8_DVBS2_CurrentCodeRateLocal);
3581 #if 0
3582 #ifdef MSOS_TYPE_LINUX
3583 log_ber = ( - 1.0f) *log10f(1.0f / fber); //BY modify
3584 #else
3585 log_ber = ( - 1.0f) *Log10Approx(1.0f / fber); //BY modify
3586 #endif
3587 DBG_INTERN_DVBS(printf("\nLog(BER) = %f\n",log_ber));
3588 #endif
3589 if (fber > 2.5E-2)
3590 ber_sqi = 0.0;
3591 else if(fber > 8.5E-7)
3592 #ifdef MSOS_TYPE_LINUX
3593 ber_sqi = (log10f(1.0f/fber))*20.0f - 32.0f; //40.0f;
3594 #else
3595 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 32.0f;//40.0f;
3596 #endif
3597 else
3598 ber_sqi = 100.0;
3599
3600 //status &= INTERN_DVBS_GetSNR(&f_snr);
3601 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_7, &u8Data);
3602 u16Data=u8Data;
3603 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_6, &u8Data);
3604 u16Data = (u16Data<<8)|u8Data;
3605 f_snr=(float)u16Data/256.0;
3606 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS GetSNR = %d \n", (int)f_snr));
3607
3608 cn_rel = f_snr - fDVBS_SQI_CNref[_u8_DVBS2_CurrentCodeRateLocal];
3609
3610 DBG_INTERN_DVBS(printf(" fber = %f\n",fber));
3611 DBG_INTERN_DVBS(printf(" f_snr = %f\n",f_snr));
3612 DBG_INTERN_DVBS(printf(" cn_nordig_s1 = %f\n",fDVBS_SQI_CNref[_u8_DVBS2_CurrentCodeRateLocal]));
3613 DBG_INTERN_DVBS(printf(" cn_rel = %f\n",cn_rel));
3614 DBG_INTERN_DVBS(printf(" ber_sqi = %f\n",ber_sqi));
3615
3616 if (cn_rel < -7.0f)
3617 {
3618 *quality = 0;
3619 }
3620 else if (cn_rel < 3.0)
3621 {
3622 *quality = (MS_U16)(ber_sqi*((cn_rel - 3.0)/10.0 + 1.0));
3623 }
3624 else
3625 {
3626 *quality = (MS_U16)ber_sqi;
3627 }
3628
3629
3630 }
3631 //INTERN_DVBS_GetTunrSignalLevel_PWR();//For Debug.
3632 DBG_INTERN_DVBS(printf(">>>>>Signal Quility(SQI) = %d\n", *quality));
3633 return TRUE;
3634 }
3635 else
3636 {
3637 *quality = 0;
3638 }
3639
3640 return TRUE;
3641 }
3642
3643 /****************************************************************************
3644 Subject: To get the Cell ID
3645 Function: INTERN_DVBS_Get_CELL_ID
3646 Parmeter: point to return parameter cell_id
3647
3648 Return: TRUE
3649 FALSE
3650 Remark:
3651 *****************************************************************************/
INTERN_DVBS_Get_CELL_ID(MS_U16 * cell_id)3652 MS_BOOL INTERN_DVBS_Get_CELL_ID(MS_U16 *cell_id)
3653 {
3654 MS_BOOL status = true;
3655 MS_U8 value1 = 0;
3656 MS_U8 value2 = 0;
3657
3658 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [15:8]
3659 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [7:0]
3660
3661 *cell_id = ((MS_U16)value1<<8)|value2;
3662 return status;
3663 }
3664
3665 /****************************************************************************
3666 Subject: To get the DVBC Carrier Freq Offset
3667 Function: INTERN_DVBS_Get_FreqOffset
3668 Parmeter: Frequency offset (in KHz), bandwidth
3669 Return: E_RESULT_SUCCESS
3670 E_RESULT_FAILURE
3671 Remark:
3672 *****************************************************************************/
INTERN_DVBS_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)3673 MS_BOOL INTERN_DVBS_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
3674 {
3675 //MS_U8 u8Data;
3676 //MS_U16 u16Data;
3677 //MS_S16 s16CFO;
3678 //float FreqOffset;
3679 //MS_U32 u32FreqOffset = 0;
3680 //MS_U8 reg = 0;
3681 MS_BOOL status = TRUE;
3682 #if 0
3683 DBG_INTERN_DVBS(printf(">>> INTERN_DVBS_Get_FreqOffset DVBS_Estimated_CFO <<<\n"));
3684 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_97, &u8Data);
3685 u16Data=u8Data;
3686 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_96, &u8Data);
3687 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset
3688 if (u16Data >= 0x8000)
3689 {
3690 u16Data=0x10000- u16Data;
3691 s16CFO=-1*u16Data;
3692 }
3693 else
3694 {
3695 s16CFO=u16Data;
3696 }
3697 DBG_INTERN_DVBS(printf(">>> INTERN_DVBS_Get_FreqOffset CFO = %d[KHz] <<<\n", s16CFO));
3698 if(abs(s16CFO)%1000 >= 500)
3699 {
3700 if(s16CFO < 0)
3701 *pFreqOff=(s16CFO/1000)-1.0;
3702 else
3703 *pFreqOff=(s16CFO/1000)+1.0;
3704 }
3705 else
3706 *pFreqOff = s16CFO/1000;
3707 DBG_INTERN_DVBS(printf(">>> INTERN_DVBS_Get_FreqOffset *pFreqOff = %d[MHz] <<<\n", (MS_S16)*pFreqOff));
3708 // no use.
3709 u8BW = u8BW;
3710 /*
3711 printf("INTERN_DVBS_Get_FreqOffset\n");//DBG_INTERN_DVBS(printf("INTERN_DVBS_Get_FreqOffset\n"));
3712
3713 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x1C*2 + 1, 0x08);
3714
3715 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x05, ®);
3716 reg|=0x80;
3717 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x05, reg);
3718
3719 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x23*2, ®);
3720 u32FreqOffset=reg;
3721 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x22*2 + 1, ®);
3722 u32FreqOffset=(u32FreqOffset<<8)|reg;
3723 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x22*2, ®);
3724 u32FreqOffset=(u32FreqOffset<<8)|reg;
3725
3726 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x05, ®);
3727 reg&=~(0x80);
3728 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x05, reg);
3729
3730 FreqOffset=(float)u32FreqOffset;
3731 if (FreqOffset>=2048)
3732 {
3733 FreqOffset=FreqOffset-4096;
3734 }
3735 FreqOffset=(FreqOffset/4096)*SAMPLING_RATE_FS;
3736
3737 *pFreqOff = FreqOffset/1000; //KHz
3738 printf("INTERN_DVBS_Get_FreqOffset:%d[MHz]\n", (MS_S16)FreqOffset/1000);//DBG_INTERN_DVBS(printf("INTERN_DVBS_Get_FreqOffset:%f[MHz]\n", FreqOffset/1000));
3739 */
3740 #endif
3741 return status;
3742 }
3743
3744 /****************************************************************************
3745 Subject: To get the current modulation type at the DVB-S Demod
3746 Function: INTERN_DVBS_GetCurrentModulationType
3747 Parmeter: pointer for return QAM type
3748
3749 Return: TRUE
3750 FALSE
3751 Remark:
3752 *****************************************************************************/
INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE * pQAMMode)3753 MS_BOOL INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE *pQAMMode)
3754 {
3755 MS_U8 u8Data=0;
3756 MS_U16 u16tmp=0;
3757 MS_U8 MOD_type;
3758 MS_BOOL status = true;
3759 //DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3760
3761 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentModulationType\n"));
3762
3763 //status &= INTERN_DVBS_GetCurrentDemodType(&pDemodType);
3764
3765 // read code rate, pilot on/off, long/short FEC type, and modulation type for calculating TOP_DVBTM_TS_CLK_DIVNUM
3766 // pilot_flag => 0 : off 1 : on
3767 // fec_type_idx => 0 : normal 1 : short
3768 // mod_type_idx => 0 : QPSK 1 : 8PSK 2 : 16APSK
3769 // code_rate_idx => 0 : 1/4 1 : 1/3 2 : 2/5 3 : 1/2 4 : 3/5 5 : 2/3
3770 // 6 : 3/4 7 : 4/5 8 : 5/6 9 : 8/9 10 : 9/10
3771 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//V
3772 if(u8Data)
3773 {
3774 *pQAMMode = DMD_DVBS_QPSK;
3775 modulation_order=2;
3776 printf("INTERN_DVBS_GetCurrentModulationType [dvbs]ModulationType=DVBS_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS_QPSK\n"));
3777 //return TRUE;
3778 }
3779 else //S2
3780 {
3781 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x96, &u8Data);
3782 //printf(">>> INTERN_DVBS_GetCurrentModulationType INNER 0x4B = 0x%x <<<\n", u8Data);
3783 //if((u8Data & 0x0F)==0x02) //QPSK
3784 /*MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MOD_TYPE, &u8Data1);
3785 printf("@@@@@E_DMD_S2_MOD_TYPE = %d \n ",u8Data1);
3786 printf("@@@@@ E_DMD_S2_MOD_TYPE=%d \n",E_DMD_S2_MOD_TYPE);
3787
3788 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_IS_ID, &u8Data1);
3789 printf("@@@@@E_DMD_S2_IS_ID = %d \n ",u8Data1);
3790 printf("@@@@@ E_DMD_S2_IS_ID=%d \n",E_DMD_S2_IS_ID);*/
3791
3792 // INNER_DEBUG_SEL
3793 MDrv_SYS_DMD_VD_MBX_ReadReg(0x3b00+0x04*2+1, &u8Data);
3794 u8Data = u8Data & 0xc0;
3795 MDrv_SYS_DMD_VD_MBX_WriteReg(0x3b00+0x04*2+1, u8Data);
3796
3797 // reg_plscdec_debug_out
3798 // PLSCDEC info
3799 //[0:4] PLSC MODCOD
3800 //[5] dummy frame
3801 //[6] reserve frame
3802 //[7:9] modulation type
3803 //[10:13] code rate type
3804 //[14] FEC type
3805 //[15] pilot type
3806 MDrv_SYS_DMD_VD_MBX_ReadReg(0x3b00+0x6b*2 , &u8Data);
3807 u16tmp = (MS_U16)u8Data;
3808 MDrv_SYS_DMD_VD_MBX_ReadReg(0x3b00+0x6b*2+1 , &u8Data);
3809 u16tmp |= (MS_U16)u8Data << 8;
3810 MOD_type = ((MS_U8)(u16tmp>>7)&0x07); // 2:QPSK, 3:8PSK, 4:16APSK, 5:32APSK
3811
3812 if(MOD_type==2)
3813 {
3814 *pQAMMode = DMD_DVBS_QPSK;
3815 modulation_order=2;
3816 printf("INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS2_QPSK\n"));
3817 //return TRUE;
3818 }
3819 else if(MOD_type==3)
3820 {
3821 *pQAMMode = DMD_DVBS_8PSK;
3822 modulation_order=3;
3823 printf("INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_8PSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS2_8PSK\n"));
3824 //return TRUE;
3825 }
3826 else if(MOD_type==4)
3827 {
3828 *pQAMMode = DMD_DVBS_16APSK;
3829 modulation_order=4;
3830 printf("INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_16APSK\n");
3831 }
3832 else
3833 {
3834 *pQAMMode = DMD_DVBS_QPSK;
3835 modulation_order=2;
3836 printf("INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=NOT SUPPORT\n");
3837 return FALSE;
3838 }
3839
3840 }
3841
3842 return status;
3843 /*#else
3844 *pQAMMode = DMD_DVBS_QPSK;
3845 printf("[dvbs]ModulationType=DVBS_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS_QPSK\n"));
3846 //return true;
3847 #endif*/
3848 }
3849
3850 /****************************************************************************
3851 Subject: To get the current DemodType at the DVB-S Demod
3852 Function: INTERN_DVBS_GetCurrentDemodType
3853 Parmeter: pointer for return DVBS/DVBS2 type
3854
3855 Return: TRUE
3856 FALSE
3857 Remark:
3858 *****************************************************************************/
INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE * pDemodType)3859 MS_BOOL INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE *pDemodType)//V
3860 {
3861 MS_U8 u8Data=0;
3862 MS_BOOL status = true;
3863
3864 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentDemodType\n"));
3865
3866 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x80, &u8Data);//status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x80, &u8Data);
3867 //printf(">>> INTERN_DVBS_GetCurrentDemodType INNER 0x40 = 0x%x <<<\n", u8Data);
3868 //if ((u8Data & 0x01) == 0)
3869 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//E_DMD_S2_SYSTEM_TYPE 0: S2 ; 1 :S
3870 if(!u8Data) //S2
3871 {
3872 *pDemodType = DMD_SAT_DVBS2;
3873 DBG_INTERN_DVBS(printf("[dvbs]DemodType=DVBS2\n"));
3874 }
3875 else //S
3876 {
3877 *pDemodType = DMD_SAT_DVBS;
3878 DBG_INTERN_DVBS(printf("[dvbs]DemodType=DVBS\n"));
3879 }
3880 return status;
3881 }
3882 /****************************************************************************
3883 Subject: To get the current CodeRate at the DVB-S Demod
3884 Function: INTERN_DVBS_GetCurrentCodeRate
3885 Parmeter: pointer for return Code Rate type
3886
3887 Return: TRUE
3888 FALSE
3889 Remark:
3890 *****************************************************************************/
INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE * pCodeRate)3891 MS_BOOL INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE *pCodeRate)
3892 {
3893 MS_U8 u8Data = 0;//, u8_gCodeRate = 0;
3894 MS_BOOL status = true;
3895
3896 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate\n"));
3897 //DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3898 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);
3899 //status &= INTERN_DVBS_GetCurrentDemodType(&pDemodType);
3900 if(!u8Data)
3901 //if((MS_U8)pDemodType == (MS_U8)DMD_SAT_DVBS2 ) //S2
3902 {
3903 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
3904 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
3905 //u8_gCodeRate = (u8Data & 0x3C);
3906 //_u8_DVBS2_CurrentCodeRate = 0;
3907 switch (u8Data)
3908 //switch (u8_gCodeRate)
3909 {
3910 case 0x03:
3911 *pCodeRate = DMD_CONV_CODE_RATE_1_2;
3912 _u8_DVBS2_CurrentCodeRate = 5;//0;
3913 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=1_2\n"));
3914 break;
3915 case 0x01:
3916 *pCodeRate = DMD_CONV_CODE_RATE_1_3;
3917 _u8_DVBS2_CurrentCodeRate = 6;//1;
3918 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=1_3\n"));
3919 break;
3920 case 0x05:
3921 *pCodeRate = DMD_CONV_CODE_RATE_2_3;
3922 _u8_DVBS2_CurrentCodeRate = 7;//2;
3923 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=2_3\n"));
3924 break;
3925 case 0x00:
3926 *pCodeRate = DMD_CONV_CODE_RATE_1_4;
3927 _u8_DVBS2_CurrentCodeRate = 8;//3;
3928 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=1_4\n"));
3929 break;
3930 case 0x06:
3931 *pCodeRate = DMD_CONV_CODE_RATE_3_4;
3932 _u8_DVBS2_CurrentCodeRate = 9;//4;
3933 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=3_4\n"));
3934 break;
3935 case 0x02:
3936 *pCodeRate = DMD_CONV_CODE_RATE_2_5;
3937 _u8_DVBS2_CurrentCodeRate = 10;//5;
3938 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=2_5\n"));
3939 break;
3940 case 0x04:
3941 *pCodeRate = DMD_CONV_CODE_RATE_3_5;
3942 _u8_DVBS2_CurrentCodeRate = 11;//6;
3943 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=3_5\n"));
3944 break;
3945 case 0x07:
3946 *pCodeRate = DMD_CONV_CODE_RATE_4_5;
3947 _u8_DVBS2_CurrentCodeRate = 12;//7;
3948 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=4_5\n"));
3949 break;
3950 case 0x08:
3951 *pCodeRate = DMD_CONV_CODE_RATE_5_6;
3952 _u8_DVBS2_CurrentCodeRate = 13;//8;
3953 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=5_6\n"));
3954 break;
3955 case 0x09:
3956 *pCodeRate = DMD_CONV_CODE_RATE_8_9;
3957 _u8_DVBS2_CurrentCodeRate = 14;//9;
3958 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=8_9\n"));
3959 break;
3960 case 0x0a:
3961 *pCodeRate = DMD_CONV_CODE_RATE_9_10;
3962 _u8_DVBS2_CurrentCodeRate = 15;//10;
3963 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=9_10\n"));
3964 break;
3965 default:
3966 *pCodeRate = DMD_CONV_CODE_RATE_9_10;
3967 _u8_DVBS2_CurrentCodeRate = 15;//10;
3968 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=DVBS2_Default\n"));
3969 }
3970 }
3971 else //S
3972 {
3973 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
3974 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE + 0x3A*2, &u8Data);
3975 //u8_gCodeRate = (u8Data & 0x70)>>4;
3976 switch (u8Data)
3977 //switch (u8_gCodeRate)
3978 {
3979 case 0x00:
3980 *pCodeRate = DMD_CONV_CODE_RATE_1_2;
3981 _u8_DVBS2_CurrentCodeRate = 0;
3982 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate=1_2\n"));
3983 break;
3984 case 0x01:
3985 *pCodeRate = DMD_CONV_CODE_RATE_2_3;
3986 _u8_DVBS2_CurrentCodeRate = 1;
3987 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate=2_3\n"));
3988 break;
3989 case 0x02:
3990 *pCodeRate = DMD_CONV_CODE_RATE_3_4;
3991 _u8_DVBS2_CurrentCodeRate = 2;
3992 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate=3_4\n"));
3993 break;
3994 case 0x03:
3995 *pCodeRate = DMD_CONV_CODE_RATE_5_6;
3996 _u8_DVBS2_CurrentCodeRate = 3;
3997 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate=5_6\n"));
3998 break;
3999 case 0x04:
4000 *pCodeRate = DMD_CONV_CODE_RATE_7_8;
4001 _u8_DVBS2_CurrentCodeRate = 4;
4002 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate=7_8\n"));
4003 break;
4004 default:
4005 *pCodeRate = DMD_CONV_CODE_RATE_7_8;
4006 _u8_DVBS2_CurrentCodeRate = 4;
4007 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate=DVBS_Default\n"));
4008 }
4009 }
4010 return status;
4011 }
4012
4013 /****************************************************************************
4014 Subject: To get the current symbol rate at the DVB-S Demod
4015 Function: INTERN_DVBS_GetCurrentSymbolRate
4016 Parmeter: pointer pData for return Symbolrate
4017
4018 Return: TRUE
4019 FALSE
4020 Remark:
4021 *****************************************************************************/
INTERN_DVBS_GetCurrentSymbolRate(MS_U32 * u32SymbolRate)4022 MS_BOOL INTERN_DVBS_GetCurrentSymbolRate(MS_U32 *u32SymbolRate)
4023 {
4024 MS_U8 tmp = 0;
4025 MS_U16 u16SymbolRateTmp = 0;
4026
4027 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &tmp);
4028 u16SymbolRateTmp = tmp;
4029 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &tmp);
4030 u16SymbolRateTmp = (u16SymbolRateTmp<<8)|tmp;
4031
4032 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &tmp);
4033 *u32SymbolRate = (tmp<<16)|u16SymbolRateTmp;
4034
4035 DBG_INTERN_DVBS_LOCK(printf("[dvbs]Symbol Rate=%d\n",*u32SymbolRate));
4036
4037 return TRUE;
4038 }
4039
INTERN_DVBS_Version(MS_U16 * ver)4040 MS_BOOL INTERN_DVBS_Version(MS_U16 *ver)
4041 {
4042 MS_U8 status = true;
4043 MS_U8 tmp = 0;
4044 MS_U16 u16_INTERN_DVBS_Version;
4045
4046 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FW_VERSION_L, &tmp);
4047 u16_INTERN_DVBS_Version = tmp;
4048 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FW_VERSION_H, &tmp);
4049 u16_INTERN_DVBS_Version = u16_INTERN_DVBS_Version<<8|tmp;
4050 *ver = u16_INTERN_DVBS_Version;
4051
4052 return status;
4053 }
4054
INTERN_DVBS_Show_Demod_Version(void)4055 MS_BOOL INTERN_DVBS_Show_Demod_Version(void)
4056 {
4057 MS_BOOL status = true;
4058 MS_U16 u16_INTERN_DVBS_Version;
4059
4060 status &= INTERN_DVBS_Version(&u16_INTERN_DVBS_Version);
4061
4062 // printf(">>> [Macan]Demod FW Version: R%d.%d <<<\n", ((u16_INTERN_DVBS_Version>>8)&0x00FF),(u16_INTERN_DVBS_Version&0x00FF));
4063 printf(">>> Demod FW Version: R%d.%d <<<\n", ((u16_INTERN_DVBS_Version>>8)&0x00FF),(u16_INTERN_DVBS_Version&0x00FF));
4064
4065
4066 return status;
4067 }
4068
INTERN_DVBS_GetRollOff(MS_U8 * pRollOff)4069 MS_BOOL INTERN_DVBS_GetRollOff(MS_U8 *pRollOff)
4070 {
4071 MS_BOOL status=TRUE;
4072 MS_U8 u8Data=0;
4073
4074 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x1E, &u8Data);//#define INNER_TR_ROLLOFF (_REG_INNER(0x0F)+0)
4075 if ((u8Data&0x03)==0x00)
4076 *pRollOff = 0; //Rolloff 0.35
4077 else if (((u8Data&0x03)==0x01) || ((u8Data&0x03)==0x03))
4078 *pRollOff = 1; //Rolloff 0.25
4079 else
4080 *pRollOff = 2; //Rolloff 0.20
4081 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetRollOff:%d\n", *pRollOff));
4082
4083 return status;
4084 }
4085
INTERN_DVBS_Get_DTV_SQuality_BAR(MS_U8 * u8_gSQValue)4086 MS_BOOL INTERN_DVBS_Get_DTV_SQuality_BAR(MS_U8 *u8_gSQValue)
4087 {
4088 MS_BOOL status=TRUE;
4089 MS_U16 u16_gSignalQualityValue;
4090 MS_U16 _u16_packetError;
4091
4092 status = INTERN_DVBS_GetSignalQuality(&u16_gSignalQualityValue,0,0,0);
4093 status = INTERN_DVBS_GetPacketErr(&_u16_packetError);
4094
4095 if ((_u16_packetError >= 1) && (u16_gSignalQualityValue > 30)) //Average
4096 {
4097 *u8_gSQValue = 30;
4098 }
4099 else if ((_u16_packetError >= 1) && (u16_gSignalQualityValue > 10)) //Poor
4100 {
4101 *u8_gSQValue = 10;
4102 }
4103
4104 return status;
4105 }
4106
4107 /****************************************************************************
4108 ** Function: Read demod related information
4109 ** Polling after demod lock
4110 ** GAIN & DCR /Fine CFO & PR & IIS & IQB & SNR /PacketErr & BER
4111 ****************************************************************************/
INTERN_DVBS_Show_AGC_Info(void)4112 MS_BOOL INTERN_DVBS_Show_AGC_Info(void)
4113 {
4114 MS_BOOL status = TRUE;
4115
4116 //MS_U8 tmp = 0;
4117 //MS_U8 agc_k = 0,d0_k = 0,d0_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0,d3_k = 0,d3_ref = 0;
4118 //MS_U16 if_agc_gain = 0,d0_gain = 0,d1_gain = 0,d2_gain = 0,d3_gain = 0, agc_ref = 0;
4119 //MS_U16 if_agc_err = 0;
4120 #if 0
4121 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x08*2 + 1,&agc_k);
4122 agc_k = ((agc_k & 0xF0)>>4);
4123 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x09*2 + 1,&tmp);
4124 agc_ref = tmp;
4125 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0xE8,&tmp);
4126 //agc_ref = (agc_ref<<8)|tmp;
4127 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x38*2,&d0_k);
4128 d0_k = ((d0_k & 0xF0)>>4);
4129 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x38*2 + 1,&d0_ref);
4130 d0_ref = (d0_ref & 0xFF);
4131 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x58*2,&d1_k);
4132 d1_k = (d1_k & 0xF0)>>4;
4133 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x58*2 + 1,&d1_ref);
4134 d1_ref = (d1_ref & 0xFF);
4135 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5E*2,&d2_k);
4136 d2_k = ((d2_k & 0xF0)>>4);
4137 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x5E*2 + 1,&d2_ref);
4138 d2_ref = (d2_ref & 0xFF);
4139 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6A*2,&d3_k);
4140 d3_k = ((d3_k & 0xF0)>>4);
4141 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref);
4142 d3_ref = (d3_ref & 0xFF);
4143
4144
4145 // select IF gain to read
4146 //Debug Select
4147 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x13*2, &tmp);
4148 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x13*2, (tmp&0xF0)|0x03);
4149 //IF_AGC_GAIN
4150 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2 + 1, &tmp);
4151 if_agc_gain = tmp;
4152 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2, &tmp);
4153 if_agc_gain = (if_agc_gain<<8)|tmp;
4154
4155
4156 // select d0 gain to read.
4157 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x74*2 + 1, &tmp);
4158 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x74*2 + 1, (tmp&0xF0)|0x03);
4159 //DAGC0_GAIN
4160 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3D*2, &tmp);
4161 d0_gain = tmp;
4162 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3C*2 + 1, &tmp);
4163 d0_gain = (d0_gain<<8)|tmp;
4164 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3C*2, &tmp);
4165 d0_gain = (d0_gain<<4)|(tmp>>4);
4166
4167
4168 // select d1 gain to read.
4169 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x8C, &tmp);
4170 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x8C, (tmp&0xF0)|0x00);
4171 //DAGC1_GAIN
4172 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5C*2 + 1, &tmp);
4173 d1_gain = tmp;
4174 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5C*2, &tmp);
4175 d1_gain = (d1_gain<<8)|tmp;
4176
4177
4178 // select d2 gain to read.
4179 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x06, &tmp);
4180 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT_REG_BASE + 0x06, (tmp&0xF0)|0x03);
4181 //DAGC2_GAIN
4182 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x62*2 + 1, &tmp);
4183 d2_gain = tmp;
4184 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x62*2, &tmp);
4185 d2_gain = (d2_gain<<8)|tmp;
4186
4187
4188 // select d3 gain to read.
4189 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp);
4190 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03);
4191 //DAGC3_GAIN
4192 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6F*2, &tmp);
4193 d3_gain = tmp;
4194 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6E*2 + 1, &tmp);
4195 d3_gain = (d3_gain<<8)|tmp;
4196 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6E*2, &tmp);
4197 d3_gain = (d3_gain<<4)|(tmp>>4);
4198
4199
4200 // select IF gain err to read
4201 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x13*2, &tmp);
4202 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x13*2, (tmp&0xF0)|0x00);
4203
4204 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2 + 1, &tmp);
4205 if_agc_err = tmp;
4206 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2, &tmp);
4207 if_agc_err = (if_agc_err<<8)|tmp;
4208
4209
4210 DBG_INTERN_DVBS(printf("[dvbs]agc_k=0x%x, agc_ref=0x%x, d0_k=0x%x, d0_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x, d3_k=0x%x, d3_ref=0x%x\n",
4211 agc_k, agc_ref, d0_k, d0_ref, d1_k, d1_ref, d2_k, d2_ref, d3_k, d3_ref));
4212
4213 DBG_INTERN_DVBS(printf("[dvbs]agc_g=0x%x, d0_g=0x%x, d1_g=0x%x, d2_g=0x%x, d3_g=0x%x, agc_err=0x%x\n", if_agc_gain, d0_gain, d1_gain, d2_gain, d3_gain, if_agc_err));
4214
4215 DBG_INTERN_DVBS(printf("[dvbs]agc_k=0x%x, agc_ref=0x%x, d0_k=0x%x, d0_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x, d3_k=0x%x, d3_ref=0x%x\n",
4216 agc_k, agc_ref, d0_k, d0_ref, d1_k, d1_ref, d2_k, d2_ref, d3_k, d3_ref));
4217
4218 DBG_INTERN_DVBS(printf("[dvbs]agc_g=0x%x, d0_g=0x%x, d1_g=0x%x, d2_g=0x%x, d3_g=0x%x, agc_err=0x%x\n", if_agc_gain, d0_gain, d1_gain, d2_gain, d3_gain, if_agc_err));
4219 #endif
4220 return status;
4221 }
4222
INTERN_DVBS_info(void)4223 void INTERN_DVBS_info(void)
4224 {
4225 //status &= INTERN_DVBS_Show_Demod_Version();
4226 //status &= INTERN_DVBS_Demod_Get_Debug_Info_get_once();
4227 //status &= INTERN_DVBS_Demod_Get_Debug_Info_polling();
4228 }
4229
INTERN_DVBS_Demod_Get_Debug_Info_get_once(void)4230 MS_BOOL INTERN_DVBS_Demod_Get_Debug_Info_get_once(void)
4231 {
4232 MS_BOOL status = TRUE;
4233 //MS_U8 u8Data = 0;
4234 //MS_U16 u16Data = 0, u16Address = 0;
4235 //float psd_smooth_factor;
4236 //float srd_right_bottom_value, srd_right_top_value, srd_left_bottom_value, srd_left_top_value;
4237 //MS_U16 u32temp5;
4238 //MS_U16 srd_left, srd_right, srd_left_top, srd_left_bottom, srd_right_top, srd_right_bottom;
4239
4240 #if 0
4241 //Lock Flag
4242 printf("========================================================================\n");
4243 printf("Debug Message Flag [Lock Flag]==========================================\n");
4244
4245 u16Address = (AGC_LOCK>>16)&0xffff;
4246 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4247 if ((u16Data&(AGC_LOCK&0xffff))!=(AGC_LOCK&0xffff))
4248 printf("[DVBS]: AGC LOCK ======================: Fail. \n");
4249 else
4250 printf("[DVBS]: AGC LOCK ======================: OK. \n");
4251
4252 u16Address = (DAGC0_LOCK>>16)&0xffff;
4253 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4254 if ((u16Data&(DAGC0_LOCK&0xffff))!=(DAGC0_LOCK&0xffff))
4255 printf("[DVBS]: DAGC0 LOCK ====================: Fail. \n");
4256 else
4257 printf("[DVBS]: DAGC0 LOCK ====================: OK. \n");
4258
4259 u16Address = (DAGC1_LOCK>>16)&0xffff;
4260 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4261 if ((u16Data&(DAGC1_LOCK&0xffff))!=(DAGC1_LOCK&0xffff))
4262 printf("[DVBS]: DAGC1 LOCK ====================: Fail. \n");
4263 else
4264 printf("[DVBS]: DAGC1 LOCK ====================: OK. \n");
4265
4266 u16Address = (DAGC2_LOCK>>16)&0xffff;
4267 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4268 if ((u16Data&(DAGC2_LOCK&0xffff))!=(DAGC2_LOCK&0xffff))
4269 printf("[DVBS]: DAGC2 LOCK ====================: Fail. \n");
4270 else
4271 printf("[DVBS]: DAGC2 LOCK ====================: OK. \n");
4272
4273 u16Address = (DAGC3_LOCK>>16)&0xffff;
4274 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4275 if ((u16Data&(DAGC3_LOCK&0xffff))!=(DAGC3_LOCK&0xffff))
4276 printf("[DVBS]: DAGC3 LOCK ====================: Fail. \n");
4277 else
4278 printf("[DVBS]: DAGC3 LOCK ====================: OK. \n");
4279
4280 u16Address = (DCR_LOCK>>16)&0xffff;
4281 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4282 if ((u16Data&(DCR_LOCK&0xffff))!=(DCR_LOCK&0xffff))
4283 printf("[DVBS]: DCR LOCK ======================: Fail. \n");
4284 else
4285 printf("[DVBS]: DCR LOCK ======================: OK. \n");
4286 //Mark Coarse SRD
4287 //Mark Fine SRD
4288 /*
4289 u16Address = (CLOSE_COARSE_CFO_LOCK>>16)&0xffff;
4290 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4291 if ((u16Data&(CLOSE_COARSE_CFO_LOCK&0xffff))!=(CLOSE_COARSE_CFO_LOCK&0xffff))
4292 printf("[DVBS]: Close CFO =====================: Fail. \n");
4293 else
4294 printf("[DVBS]: Close CFO =====================: OK. \n");
4295 */
4296 u16Address = (TR_LOCK>>16)&0xffff;
4297 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4298 if ((u16Data&(TR_LOCK&0xffff))!=(TR_LOCK&0xffff))
4299 printf("[DVBS]: TR LOCK =======================: Fail. \n");
4300 else
4301 printf("[DVBS]: TR LOCK =======================: OK. \n");
4302
4303 u16Address = (FRAME_SYNC_ACQUIRE>>16)&0xffff;
4304 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4305 if ((u16Data&(FRAME_SYNC_ACQUIRE&0xffff))!=(FRAME_SYNC_ACQUIRE&0xffff))
4306 printf("[DVBS]: FS Acquire ====================: Fail. \n");
4307 else
4308 printf("[DVBS]: FS Acquire ====================: OK. \n");
4309
4310 u16Address = (PR_LOCK>>16)&0xffff;
4311 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4312 if ((u16Data&(PR_LOCK&0xffff))!=(PR_LOCK&0xffff))
4313 printf("[DVBS]: PR LOCK =======================: Fail. \n");
4314 else
4315 printf("[DVBS]: PR LOCK =======================: OK. \n");
4316
4317 u16Address = (EQ_LOCK>>16)&0xffff;
4318 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4319 if ((u16Data&(EQ_LOCK&0xffff))!=(EQ_LOCK&0xffff))
4320 printf("[DVBS]: EQ LOCK =======================: Fail. \n");
4321 else
4322 printf("[DVBS]: EQ LOCK =======================: OK. \n");
4323
4324 u16Address = (P_SYNC_LOCK>>16)&0xffff;
4325 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4326 if ((u16Data&0x0002)!=0x0002)
4327 printf("[DVBS]: P_sync ========================: Fail. \n");
4328 else
4329 printf("[DVBS]: P_sync ========================: OK. \n");
4330
4331 u16Address = (IN_SYNC_LOCK>>16)&0xffff;
4332 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4333 if ((u16Data&0x8000)!=0x8000)
4334 printf("[DVBS]: In_sync =======================: Fail. \n");
4335 else
4336 printf("[DVBS]: In_sync =======================: OK. \n");
4337 //---------------------------------------------------------
4338 //Lock Time
4339 printf("------------------------------------------------------------------------\n");
4340 printf("Debug Message [Lock Time]===============================================\n");
4341
4342 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_05, &u8Data);
4343 printf("[DVBS]: AGC Lock Time =================: %d\n",u8Data&0x00FF);
4344 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_06, &u8Data);
4345 printf("[DVBS]: DCR Lock Time =================: %d\n",u8Data&0x00FF);
4346 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_2, &u8Data);
4347 printf("[DVBS]: TR Lock Time ==================: %d\n",u8Data&0x00FF);
4348 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_3, &u8Data);
4349 printf("[DVBS]: FS Lock Time ==================: %d\n",u8Data&0x00FF);
4350 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_4, &u8Data);
4351 printf("[DVBS]: PR Lock Time ==================: %d\n",u8Data&0x00FF);
4352 //printf("[DVBS]: PLSC Lock Time ================: %d\n",(u16Data>>8)&0x00FF);//No used
4353 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_6, &u8Data);
4354 printf("[DVBS]: EQ Lock Time ==================: %d\n",u8Data&0x00FF);
4355 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_7, &u8Data);
4356 printf("[DVBS]: FEC Lock Time =================: %d\n",u8Data&0x00FF);
4357
4358 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_0, &u8Data);
4359 printf("[DVBS]: CSRD ==========================: %d\n",u8Data&0x00FF);
4360 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_1, &u8Data);
4361 printf("[DVBS]: FSRD ==========================: %d\n",u8Data&0x00FF);
4362 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_01, &u8Data);
4363 printf("[DVBS]: CCFO ==========================: %d\n",u8Data&0x00FF);
4364 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_02, &u8Data);
4365 printf("[DVBS]: FCFO ==========================: %d\n",u8Data&0x00FF);
4366 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);
4367 printf("[DVBS]: State =========================: %d\n",u8Data&0x00FF);
4368 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SUBSTATE_FLAG, &u8Data);
4369 printf("[DVBS]: SubState ======================: %d\n",u8Data&0x00FF);
4370
4371 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00H, &u8Data);
4372 u16Data = u8Data;
4373 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00L, &u8Data);
4374 u16Data = (u16Data<<8)|u8Data;
4375 printf("[DVBS]: DBG1: =========================: 0x%x\n",u16Data);
4376 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01H, &u8Data);
4377 u16Data = u8Data;
4378 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01L, &u8Data);
4379 u16Data = (u16Data<<8)|u8Data;
4380 printf("[DVBS]: DBG2: =========================: 0x%x\n",u16Data);
4381 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE02H, &u8Data);
4382 u16Data = u8Data;
4383 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE02L, &u8Data);
4384 u16Data = (u16Data<<8)|u8Data;
4385 printf("[DVBS]: DBG3: =========================: 0x%x\n",u16Data);
4386 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE03H, &u8Data);
4387 u16Data = u8Data;
4388 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE03L, &u8Data);
4389 u16Data = (u16Data<<8)|u8Data;
4390 printf("[DVBS]: DBG4: =========================: 0x%x\n",u16Data);
4391 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE04H, &u8Data);
4392 u16Data = u8Data;
4393 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE04L, &u8Data);
4394 u16Data = (u16Data<<8)|u8Data;
4395 printf("[DVBS]: DBG5: =========================: 0x%x\n",u16Data);
4396 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE05H, &u8Data);
4397 u16Data = u8Data;
4398 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE05L, &u8Data);
4399 u16Data = (u16Data<<8)|u8Data;
4400 printf("[DVBS]: DBG6: =========================: 0x%x\n",u16Data);
4401 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE06H, &u8Data);
4402 u16Data = u8Data;
4403 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE06L, &u8Data);
4404 u16Data = (u16Data<<8)|u8Data;
4405 printf("[DVBS]: EQ Sum: =======================: 0x%x\n",u16Data);
4406 //---------------------------------------------------------
4407 //FIQ Status
4408 printf("------------------------------------------------------------------------\n");
4409 printf("Debug Message [FIQ Status]==============================================\n");
4410 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00H, &u8Data);
4411 u16Data = u8Data;
4412 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00L, &u8Data);
4413 u16Data = (u16Data<<8)|u8Data;
4414
4415 if ((u16Data&0x0001)==0x0000)
4416 printf("[DVBS]: AGC Lock ======================: Fail. \n");
4417 else
4418 printf("[DVBS]: AGC Lock ======================: OK. \n");
4419
4420 if ((u16Data&0x0002)==0x0000)
4421 printf("[DVBS]: Hum Detect ====================: Fail. \n");
4422 else
4423 printf("[DVBS]: Hum Detect ====================: OK. \n");
4424
4425 if ((u16Data&0x0004)==0x0000)
4426 printf("[DVBS]: DCR Lock ======================: Fail. \n");
4427 else
4428 printf("[DVBS]: DCR Lock ======================: OK. \n");
4429
4430 if ((u16Data&0x0008)==0x0000)
4431 printf("[DVBS]: IIS Detect ====================: Fail. \n");
4432 else
4433 printf("[DVBS]: IIS Detect ====================: OK. \n");
4434
4435 if ((u16Data&0x0010)==0x0000)
4436 printf("[DVBS]: DAGC0 Lock ====================: Fail. \n");
4437 else
4438 printf("[DVBS]: DAGC0 Lock ====================: OK. \n");
4439
4440 if ((u16Data&0x0020)==0x0000)
4441 printf("[DVBS]: DAGC1 Lock ====================: Fail. \n");
4442 else
4443 printf("[DVBS]: DAGC1 Lock ====================: OK. \n");
4444
4445 if ((u16Data&0x0040)==0x0000)
4446 printf("[DVBS]: DAGC2 Lock ====================: Fail. \n");
4447 else
4448 printf("[DVBS]: DAGC2 Lock ====================: OK. \n");
4449
4450 if ((u16Data&0x0080)==0x0000)
4451 printf("[DVBS]: CCI Detect ====================: Fail. \n");
4452 else
4453 printf("[DVBS]: CCI Detect ====================: OK. \n");
4454
4455 if ((u16Data&0x0100)==0x0000)
4456 printf("[DVBS]: SRD Coarse Done ===============: Fail. \n");
4457 else
4458 printf("[DVBS]: SRD Coarse Done ===============: OK. \n");
4459
4460 if ((u16Data&0x0200)==0x0000)
4461 printf("[DVBS]: SRD Fine Done =================: Fail. \n");
4462 else
4463 printf("[DVBS]: SRD Fine Done =================: OK. \n");
4464
4465 if ((u16Data&0x0400)==0x0000)
4466 printf("[DVBS]: EQ Lock =======================: Fail. \n");
4467 else
4468 printf("[DVBS]: EQ Lock =======================: OK. \n");
4469
4470 if ((u16Data&0x0800)==0x0000)
4471 printf("[DVBS]: FineFE Done ===================: Fail. \n");
4472 else
4473 printf("[DVBS]: FineFE Done ===================: OK. \n");
4474
4475 if ((u16Data&0x1000)==0x0000)
4476 printf("[DVBS]: PR Lock =======================: Fail. \n");
4477 else
4478 printf("[DVBS]: PR Lock =======================: OK. \n");
4479
4480 if ((u16Data&0x2000)==0x0000)
4481 printf("[DVBS]: Reserved Frame ================: Fail. \n");
4482 else
4483 printf("[DVBS]: Reserved Frame ================: OK. \n");
4484
4485 if ((u16Data&0x4000)==0x0000)
4486 printf("[DVBS]: Dummy Frame ===================: Fail. \n");
4487 else
4488 printf("[DVBS]: Dummy Frame ===================: OK. \n");
4489
4490 if ((u16Data&0x8000)==0x0000)
4491 printf("[DVBS]: PLSC Done =====================: Fail. \n");
4492 else
4493 printf("[DVBS]: PLSC Done =====================: OK. \n");
4494
4495 printf("------------------------------------------------------------------------\n");
4496 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01H, &u8Data);
4497 u16Data = u8Data;
4498 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01L, &u8Data);
4499 u16Data = (u16Data<<8)|u8Data;
4500 if ((u16Data&0x0001)==0x0000)
4501 printf("[DVBS]: FS Get Info From Len ==========: Fail. \n");
4502 else
4503 printf("[DVBS]: FS Get Info From Len ==========: OK. \n");
4504
4505 if ((u16Data&0x0002)==0x0000)
4506 printf("[DVBS]: IQ Swap Detect ================: Fail. \n");
4507 else
4508 printf("[DVBS]: IQ Swap Detect ================: OK. \n");
4509
4510 if ((u16Data&0x0004)==0x0000)
4511 printf("[DVBS]: FS Acquisition ================: Fail. \n");
4512 else
4513 printf("[DVBS]: FS Acquisition ================: OK. \n");
4514
4515 if ((u16Data&0x0008)==0x0000)
4516 printf("[DVBS]: TR Lock =======================: Fail. \n");
4517 else
4518 printf("[DVBS]: TR Lock =======================: OK. \n");
4519
4520 if ((u16Data&0x0010)==0x0000)
4521 printf("[DVBS]: CLCFE Lock ====================: Fail. \n");
4522 else
4523 printf("[DVBS]: CLCFE Lock ====================: OK. \n");
4524
4525 if ((u16Data&0x0020)==0x0000)
4526 printf("[DVBS]: OLCFE Lock ====================: Fail. \n");
4527 else
4528 printf("[DVBS]: OLCFE Lock ====================: OK. \n");
4529
4530 if ((u16Data&0x0040)==0x0000)
4531 printf("[DVBS]: Fsync Found ===================: Fail. \n");
4532 else
4533 printf("[DVBS]: Fsync Found ===================: OK. \n");
4534
4535 if ((u16Data&0x0080)==0x0000)
4536 printf("[DVBS]: Fsync Lock ====================: Fail. \n");
4537 else
4538 printf("[DVBS]: Fsync Lock ====================: OK. \n");
4539
4540 if ((u16Data&0x0100)==0x0000)
4541 printf("[DVBS]: Fsync Fail Search =============: Fail. \n");
4542 else
4543 printf("[DVBS]: Fsync Fail Search =============: OK. \n");
4544
4545 if ((u16Data&0x0200)==0x0000)
4546 printf("[DVBS]: Fsync Fail Lock ===============: Fail. \n");
4547 else
4548 printf("[DVBS]: Fsync Fail Lock ===============: OK. \n");
4549
4550 if ((u16Data&0x0400)==0x0000)
4551 printf("[DVBS]: False Alarm ===================: Fail. \n");
4552 else
4553 printf("[DVBS]: False Alarm ===================: OK. \n");
4554
4555 if ((u16Data&0x0800)==0x0000)
4556 printf("[DVBS]: Viterbi In Sync ===============: Fail. \n");
4557 else
4558 printf("[DVBS]: Viterbi In Sync ===============: OK. \n");
4559
4560 if ((u16Data&0x1000)==0x0000)
4561 printf("[DVBS]: Uncrt Over ====================: Fail. \n");
4562 else
4563 printf("[DVBS]: Uncrt Over ====================: OK. \n");
4564
4565 if ((u16Data&0x2000)==0x0000)
4566 printf("[DVBS]: CLK Cnt Over ==================: Fail. \n");
4567 else
4568 printf("[DVBS]: CLK Cnt Over ==================: OK. \n");
4569
4570 //if ((u16Data&0x4000)==0x0000)
4571 // printf("[DVBS]: Data In Ready FIFO ============: Fail. \n");
4572 //else
4573 // printf("[DVBS]: Data In Ready FIFO ============: OK. \n");
4574
4575 //if ((u16Data&0x8000)==0x0000)
4576 // printf("[DVBS]: IIR Buff Busy =================: Fail. \n");
4577 //else
4578 // printf("[DVBS]: IIR Buff Busy =================: OK. \n");
4579
4580 /*
4581 printf("------------------------------------------------------------------------\n");
4582 u16Address = 0x0B64;
4583 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address+1, &u8Data);
4584 u16Data = u8Data;
4585 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address , &u8Data);
4586 u16Data = (u16Data<<8)|u8Data;
4587 if ((u16Data&0x0001)==0x0000)
4588 printf("[DVBS]: IIR Busy LDPC =================: Fail. \n");
4589 else
4590 printf("[DVBS]: IIR Busy LDPC =================: OK. \n");
4591
4592 if ((u16Data&0x0002)==0x0000)
4593 printf("[DVBS]: BCH Busy ======================: Fail. \n");
4594 else
4595 printf("[DVBS]: BCH Busy ======================: OK. \n");
4596
4597 if ((u16Data&0x0004)==0x0000)
4598 printf("[DVBS]: Oppro Ready Out ===============: Fail. \n");
4599 else
4600 printf("[DVBS]: Oppro Ready Out ===============: OK. \n");
4601
4602 if ((u16Data&0x0008)==0x0000)
4603 printf("[DVBS]: LDPC Win ======================: Fail. \n");
4604 else
4605 printf("[DVBS]: LDPC Win ======================: OK. \n");
4606
4607 if ((u16Data&0x0010)==0x0000)
4608 printf("[DVBS]: LDPC Error ====================: Fail. \n");
4609 else
4610 printf("[DVBS]: LDPC Error ====================: OK. \n");
4611
4612 if ((u16Data&0x0020)==0x0000)
4613 printf("[DVBS]: Out BCH Error =================: Fail. \n");
4614 else
4615 printf("[DVBS]: Out BCH Error =================: OK. \n");
4616
4617 if ((u16Data&0x0040)==0x0000)
4618 printf("[DVBS]: Descr BCH FEC Num Error =======: Fail. \n");
4619 else
4620 printf("[DVBS]: Descr BCH FEC Num Error =======: OK. \n");
4621
4622 if ((u16Data&0x0080)==0x0000)
4623 printf("[DVBS]: Descr BCH Data Num Error ======: Fail. \n");
4624 else
4625 printf("[DVBS]: Descr BCH Data Num Error ======: OK. \n");
4626
4627 if ((u16Data&0x0100)==0x0000)
4628 printf("[DVBS]: Packet Error Out ==============: Fail. \n");
4629 else
4630 printf("[DVBS]: Packet Error Out ==============: OK. \n");
4631
4632 if ((u16Data&0x0200)==0x0000)
4633 printf("[DVBS]: BBH CRC Error =================: Fail. \n");
4634 else
4635 printf("[DVBS]: BBH CRC Error =================: OK. \n");
4636
4637 if ((u16Data&0x0400)==0x0000)
4638 printf("[DVBS]: BBH Decode Done ===============: Fail. \n");
4639 else
4640 printf("[DVBS]: BBH Decode Done ===============: OK. \n");
4641
4642 if ((u16Data&0x0800)==0x0000)
4643 printf("[DVBS]: ISRC Calculate Done ===========: Fail. \n");
4644 else
4645 printf("[DVBS]: ISRC Calculate Done ===========: OK. \n");
4646
4647 if ((u16Data&0x1000)==0x0000)
4648 printf("[DVBS]: Syncd Check Error =============: Fail. \n");
4649 else
4650 printf("[DVBS]: Syncd Check Error =============: OK. \n");
4651
4652 //if ((u16Data&0x2000)==0x0000)
4653 // printf("[DVBS]: Syncd Check Error======: Fail. \n");
4654 //else
4655 // printf("[DVBS]: Syncd Check Error======: OK. \n");
4656
4657 if ((u16Data&0x4000)==0x0000)
4658 printf("[DVBS]: Demap Init ====================: Fail. \n");
4659 else
4660 printf("[DVBS]: Demap Init ====================: OK. \n");
4661 */
4662 //Spectrum Information
4663 printf("------------------------------------------------------------------------\n");
4664
4665 u16Address = 0x2836;
4666 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4667 psd_smooth_factor=(u16Data>>8)&0x7F;
4668
4669 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
4670 u16Data = u8Data;
4671 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
4672 u16Data = (u16Data<<8)|u8Data;
4673 u32temp5=u16Data;
4674 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13H, &u8Data);
4675 u16Data = u8Data;
4676 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
4677 u16Data = (u16Data<<8)|u8Data;
4678 u32temp5|=(u16Data<<16);
4679 if (psd_smooth_factor!=0)
4680 srd_left_top_value=(float)u32temp5/256.0/psd_smooth_factor;
4681 else
4682 srd_left_top_value=0;
4683
4684 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
4685 u16Data = u8Data;
4686 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
4687 u16Data = (u16Data<<8)|u8Data;
4688 u32temp5=u16Data;
4689 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
4690 u16Data = u8Data;
4691 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
4692 u16Data = (u16Data<<8)|u8Data;
4693 u32temp5|=(u16Data<<16);
4694 if (psd_smooth_factor!=0)
4695 srd_left_bottom_value=(float)u32temp5/256.0/psd_smooth_factor;
4696 else
4697 srd_left_bottom_value=0;
4698
4699 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
4700 u16Data = u8Data;
4701 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
4702 u16Data = (u16Data<<8)|u8Data;
4703 u32temp5=u16Data;
4704 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE17H, &u8Data);
4705 u16Data = u8Data;
4706 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE17L, &u8Data);
4707 u16Data = (u16Data<<8)|u8Data;
4708 u32temp5|=(u16Data<<16);
4709 if (psd_smooth_factor!=0)
4710 srd_right_top_value=(float)u32temp5/256.0/psd_smooth_factor;
4711 else
4712 srd_right_top_value=0;
4713
4714 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18H, &u8Data);
4715 u16Data = u8Data;
4716 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18L, &u8Data);
4717 u16Data = (u16Data<<8)|u8Data;
4718 u32temp5=u16Data;
4719 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19H, &u8Data);
4720 u16Data = u8Data;
4721 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19L, &u8Data);
4722 u16Data = (u16Data<<8)|u8Data;
4723 u32temp5|=(u16Data<<16);
4724 if (psd_smooth_factor!=0)
4725 srd_right_bottom_value=(float)u32temp5/256.0/psd_smooth_factor;
4726 else
4727 srd_right_bottom_value=0;
4728
4729 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1AH, &u8Data);
4730 u16Data = u8Data;
4731 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1AL, &u8Data);
4732 u16Data = (u16Data<<8)|u8Data;
4733 srd_left=u16Data;
4734 printf("[DVBS]: FFT Left ======================: %d, %f\n", srd_left, srd_left_top_value - srd_left_bottom_value);
4735 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1BH, &u8Data);
4736 u16Data = u8Data;
4737 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1BL, &u8Data);
4738 u16Data = (u16Data<<8)|u8Data;
4739 srd_right=u16Data;
4740 printf("[DVBS]: FFT Right =====================: %d, %f\n", srd_right, srd_right_top_value - srd_right_bottom_value);
4741 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1CH, &u8Data);
4742 u16Data = u8Data;
4743 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1CL, &u8Data);
4744 u16Data = (u16Data<<8)|u8Data;
4745 srd_left_top=u16Data;
4746 printf("[DVBS]: FFT Left Top ==================: %d, %f\n", srd_left_top, srd_left_top_value);
4747 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1DH, &u8Data);
4748 u16Data = u8Data;
4749 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1DL, &u8Data);
4750 u16Data = (u16Data<<8)|u8Data;
4751 srd_left_bottom=u16Data;
4752 printf("[DVBS]: FFT Left Bottom ===============: %d, %f\n", srd_left_bottom, srd_left_bottom_value);
4753 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1EH, &u8Data);
4754 u16Data = u8Data;
4755 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1EL, &u8Data);
4756 u16Data = (u16Data<<8)|u8Data;
4757 srd_right_top=u16Data;
4758 printf("[DVBS]: FFT Right Top =================: %d, %f\n", srd_right_top, srd_right_top_value);
4759 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1FH, &u8Data);
4760 u16Data = u8Data;
4761 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1FL, &u8Data);
4762 u16Data = (u16Data<<8)|u8Data;
4763 srd_right_bottom=u16Data;
4764 printf("[DVBS]: FFT Right Bottom ==============: %d, %f\n", srd_right_bottom, srd_right_bottom_value);
4765
4766 printf("-----------------------------------------\n");
4767 printf("[DVBS]: Left-Bottom ===================: %d\n", srd_left-srd_left_bottom);
4768 printf("[DVBS]: Left-Top ======================: %d\n", srd_left_top - srd_left);
4769 printf("[DVBS]: Right-Top =====================: %d\n", srd_right - srd_right_top);
4770 printf("[DVBS]: Right-Bottom ==================: %d\n", srd_right_bottom - srd_right);
4771
4772 if (psd_smooth_factor!=0)
4773 {
4774 if ((srd_left_top-srd_left_bottom)!=0)
4775 printf("[DVBS]: Left Slope ====================: %f\n", (srd_left_top_value - srd_left_bottom_value)/(srd_left_top-srd_left_bottom));
4776 else
4777 printf("[DVBS]: Left Slope ====================: %f\n", 0.000000);
4778
4779 if((srd_right_bottom - srd_right_top)!=0)
4780 printf("[DVBS]: Right Slope ===================: %f\n", (srd_right_top_value - srd_right_bottom_value)/(srd_right_bottom - srd_right_top));
4781 else
4782 printf("[DVBS]: Right Slope ===================: %f\n", 0.000000);
4783
4784 if (((srd_right_top_value - srd_right_bottom_value)!=0)&&((srd_right_bottom - srd_right_top))!=0)
4785 printf("[DVBS]: Slope Ratio ===================: %f\n", ((srd_left_top_value - srd_left_bottom_value)/(srd_left_top-srd_left_bottom))/((srd_right_top_value - srd_right_bottom_value)/(srd_right_bottom - srd_right_top)));
4786 else
4787 printf("[DVBS]: Slope Ratio ===================: %f\n", 0.000000);
4788 }
4789 else
4790 {
4791 printf("[DVBS]: Left Slope ======================: %d\n", 0);
4792 printf("[DVBS]: Right Slope =====================: %d\n", 0);
4793 printf("[DVBS]: Slope Ratio =====================: %d\n", 0);
4794 }
4795 #endif
4796 return status;
4797 }
4798
INTERN_DVBS_Demod_Get_Debug_Info_polling(void)4799 MS_BOOL INTERN_DVBS_Demod_Get_Debug_Info_polling(void)
4800 {
4801 MS_BOOL bRet = FALSE;
4802 #if 0
4803 MS_U8 u8Data = 0;
4804 MS_U16 u16Data = 0;
4805 MS_U16 u16Address = 0;
4806 MS_U32 u32DebugInfo_Fb = 0; //Fb, SymbolRate
4807 MS_U32 u32DebugInfo_Fs = 96000; //Fs, 96000k
4808 float AGC_IF_Gain;
4809 float DAGC0_Gain, DAGC1_Gain, DAGC2_Gain, DAGC3_Gain, DAGC0_Peak_Mean, DAGC1_Peak_Mean, DAGC2_Peak_Mean, DAGC3_Peak_Mean;
4810 short AGC_Err, DAGC0_Err, DAGC1_Err, DAGC2_Err, DAGC3_Err;
4811 float DCR_Offset_I, DCR_Offset_Q;
4812 float FineCFO_loop_input_value, FineCFO_loop_out_value;
4813 double FineCFO_loop_ki_value, TR_loop_ki;
4814 float PR_in_value, PR_out_value, PR_loop_ki, PR_loopback_ki;
4815 float IQB_Phase, IQB_Gain;
4816 MS_U16 IIS_cnt, ConvegenceLen;
4817 float Linear_SNR_dd, SNR_dd_dB, Linear_SNR_da, SNR_da_dB, SNR_nda_dB, Linear_SNR;
4818 float Packet_Err, BER;
4819 float TR_Indicator_ff, TR_SFO_Converge, Fs_value, Fb_value;
4820 float TR_Loop_Output, TR_Loop_Ki, TR_loop_input, TR_tmp0, TR_tmp1, TR_tmp2;
4821 float Eq_variance_da, Eq_variance_dd;
4822 float ndasnr_ratio, ndasnr_a, ndasnr_ab;
4823 MS_U16 BitErr, BitErrPeriod;
4824 MS_BOOL BEROver;
4825
4826 //Fb
4827 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
4828 //bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
4829 if((u8Data&0x02)==0x00) //Manual Tune
4830 {
4831 u32DebugInfo_Fb = 0x0;//_u32CurrentSR;
4832 }
4833 else //Blind Scan
4834 {
4835 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
4836 u16Data = u8Data;
4837 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
4838 u16Data = (u16Data<<8)|u8Data;
4839 u32DebugInfo_Fb = u16Data;
4840 }
4841 printf("++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
4842 printf("Fs ====================================: %lu [kHz]\n",u32DebugInfo_Fs);
4843 printf("Fb ====================================: %lu [kHz]\n",u32DebugInfo_Fb);
4844 //---------------------------------------------------------
4845 //Page1-GAIN & DCR
4846 //---------------------------------------------------------
4847 //GAIN
4848 printf("\n");
4849 printf("========================================================================\n");
4850 printf("Debug Message [GAIN & DCR]==============================================\n");
4851
4852 //Debug select
4853 u16Address = (DEBUG_SEL_IF_AGC_GAIN>>16)&0xffff;
4854 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4855 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_IF_AGC_GAIN)&0xffff);
4856 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4857
4858 //Freeze and dump
4859 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4860 //AGC_IF_GAIN
4861 u16Address = (DEBUG_OUT_AGC)&0xffff;
4862 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4863 AGC_IF_Gain=u16Data;
4864 //Unfreeze
4865 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4866
4867 AGC_IF_Gain=AGC_IF_Gain/0x8000; //(16, 15)
4868 printf("[DVBS]: AGC_IF_Gain ===================: %f\n", AGC_IF_Gain);
4869 //---------------------------------------------------------
4870 //Debug select
4871 u16Address = (DEBUG_SEL_DAGC0_GAIN>>16)&0xffff;
4872 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4873 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_GAIN)&0xffff);
4874 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4875
4876 //Freeze and dump
4877 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4878 //DAGC0_GAIN
4879 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
4880 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4881 u16Data = (u16Data>>4);
4882 DAGC0_Gain=(u16Data&0x0fff);
4883 //Unfreeze
4884 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4885 //---------------------------------------------------------
4886 //Debug select
4887 u16Address = (DEBUG_SEL_DAGC1_GAIN>>16)&0xffff;
4888 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4889 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_GAIN)&0xffff);
4890 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4891
4892 //Freeze and dump
4893 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4894 //DAGC1_GAIN
4895 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
4896 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4897 DAGC1_Gain=(u16Data&0x07ff);
4898 //Unfreeze
4899 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4900 //---------------------------------------------------------
4901 //Debug select
4902 u16Address = (DEBUG_SEL_DAGC2_GAIN>>16)&0xffff;
4903 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4904 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_GAIN)&0xffff);
4905 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4906
4907 //Freeze and dump
4908 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4909 //DAGC2_GAIN
4910 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
4911 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4912 DAGC2_Gain=(u16Data&0x0fff);
4913 //Unfreeze
4914 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4915 //---------------------------------------------------------
4916 //Debug select
4917 u16Address = (DEBUG_SEL_DAGC3_GAIN>>16)&0xffff;
4918 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4919 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_GAIN)&0xffff);
4920 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4921
4922 //Freeze and dump
4923 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4924 //DAGC3_GAIN
4925 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
4926 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4927 u16Data = (u16Data>>4);
4928 DAGC3_Gain=(u16Data&0x0fff);
4929 //Unfreeze
4930 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4931 //---------------------------------------------------------
4932
4933 DAGC0_Gain=DAGC0_Gain/0x200; //<12,9>
4934 DAGC1_Gain=DAGC1_Gain/0x200; //<11,9>
4935 DAGC2_Gain=DAGC2_Gain/0x200; //<12,9>
4936 DAGC3_Gain=DAGC3_Gain/0x200; //<12,9>
4937 printf("[DVBS]: DAGC0_Gain ====================: %f\n", DAGC0_Gain);
4938 printf("[DVBS]: DAGC1_Gain ====================: %f\n", DAGC1_Gain);
4939 printf("[DVBS]: DAGC2_Gain ====================: %f\n", DAGC2_Gain);
4940 printf("[DVBS]: DAGC3_Gain ====================: %f\n", DAGC3_Gain);
4941
4942 //---------------------------------------------------------
4943 //ERROR
4944 //Debug select
4945 u16Address = (DEBUG_SEL_AGC_ERR>>16)&0xffff;
4946 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4947 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_AGC_ERR)&0xffff);
4948 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4949
4950 //Freeze and dump
4951 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4952 //AGC_ERR
4953 u16Address = (DEBUG_OUT_AGC)&0xffff;
4954 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4955 AGC_Err=(u16Data&0x03ff);
4956 //Unfreeze
4957 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4958
4959 //Debug select
4960 u16Address = (DEBUG_SEL_DAGC0_ERR>>16)&0xffff;
4961 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4962 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_ERR)&0xffff);
4963 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4964
4965 //Freeze and dump
4966 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4967 //DAGC0_ERR
4968 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
4969 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4970 u16Data = (u16Data>>4);
4971 DAGC0_Err=(u16Data&0x7fff);
4972 //Unfreeze
4973 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4974
4975 //Debug select
4976 u16Address = (DEBUG_SEL_DAGC1_ERR>>16)&0xffff;
4977 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4978 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_ERR)&0xffff);
4979 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4980
4981 //Freeze and dump
4982 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4983 //DAGC1_ERR
4984 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
4985 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4986 DAGC1_Err=(u16Data&0x7fff);
4987 //Unfreeze
4988 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4989
4990 //Debug select
4991 u16Address = (DEBUG_SEL_DAGC2_ERR>>16)&0xffff;
4992 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4993 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_ERR)&0xffff);
4994 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4995
4996 //Freeze and dump
4997 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4998 //DAGC2_ERR
4999 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
5000 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5001 DAGC2_Err=(u16Data&0x7fff);
5002 //Unfreeze
5003 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5004
5005 //Debug select
5006 u16Address = (DEBUG_SEL_DAGC3_ERR>>16)&0xffff;
5007 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5008 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_ERR)&0xffff);
5009 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5010
5011 //Freeze and dump
5012 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5013 //DAGC3_ERR
5014 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
5015 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5016 u16Data = (u16Data>>4);
5017 DAGC3_Err=(u16Data&0x7fff);
5018 //Unfreeze
5019 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5020
5021 if (AGC_Err>=0x200)
5022 AGC_Err=AGC_Err-0x400;
5023 if (DAGC0_Err>=0x4000)
5024 DAGC0_Err=DAGC0_Err-0x8000;
5025 if (DAGC1_Err>=0x4000)
5026 DAGC1_Err=DAGC1_Err-0x8000;
5027 if (DAGC2_Err>=0x4000)
5028 DAGC2_Err=DAGC2_Err-0x8000;
5029 if (DAGC3_Err>=0x4000)
5030 DAGC3_Err=DAGC3_Err-0x8000;
5031
5032 printf("[DVBS]: AGC_Err =========================: %.3f\n", (float)AGC_Err);
5033 printf("[DVBS]: DAGC0_Err =======================: %.3f\n", (float)DAGC0_Err);
5034 printf("[DVBS]: DAGC1_Err =======================: %.3f\n", (float)DAGC1_Err);
5035 printf("[DVBS]: DAGC2_Err =======================: %.3f\n", (float)DAGC2_Err);
5036 printf("[DVBS]: DAGC3_Err =======================: %.3f\n", (float)DAGC3_Err);
5037 //---------------------------------------------------------
5038 //PEAK_MEAN
5039 //Debug select
5040 u16Address = (DEBUG_SEL_DAGC0_PEAK_MEAN>>16)&0xffff;
5041 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5042 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_PEAK_MEAN)&0xffff);
5043 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5044
5045 //Freeze and dump
5046 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5047 //DAGC0_PEAK_MEAN
5048 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
5049 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5050 u16Data = (u16Data>>4);
5051 DAGC0_Peak_Mean=(u16Data&0x0fff);
5052 //Unfreeze
5053 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5054
5055 //Debug select
5056 u16Address = (DEBUG_SEL_DAGC1_PEAK_MEAN>>16)&0xffff;
5057 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5058 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_PEAK_MEAN)&0xffff);
5059 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5060
5061 //Freeze and dump
5062 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5063 //DAGC1_PEAK_MEAN
5064 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
5065 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5066 DAGC1_Peak_Mean=(u16Data&0x0fff);
5067 //Unfreeze
5068 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5069
5070 //Debug select
5071 u16Address = (DEBUG_SEL_DAGC2_PEAK_MEAN>>16)&0xffff;
5072 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5073 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_PEAK_MEAN)&0xffff);
5074 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5075
5076 //Freeze and dump
5077 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5078 //DAGC2_PEAK_MEAN
5079 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
5080 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5081 DAGC2_Peak_Mean=(u16Data&0x0fff);
5082 //Unfreeze
5083 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5084
5085 //Debug select
5086 u16Address = (DEBUG_SEL_DAGC3_PEAK_MEAN>>16)&0xffff;
5087 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5088 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_PEAK_MEAN)&0xffff);
5089 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5090
5091 //Freeze and dump
5092 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5093 //DAGC3_PEAK_MEAN
5094 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
5095 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5096 u16Data = (u16Data>>4);
5097 DAGC3_Peak_Mean=(u16Data&0x0fff);
5098 //Unfreeze
5099 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5100
5101
5102 DAGC0_Peak_Mean = DAGC0_Peak_Mean / 0x800; //<12,11>
5103 DAGC1_Peak_Mean = DAGC1_Peak_Mean / 0x800; //<12,11>
5104 DAGC2_Peak_Mean = DAGC2_Peak_Mean / 0x800; //<12,11>
5105 DAGC3_Peak_Mean = DAGC3_Peak_Mean / 0x800; //<12,11>
5106
5107 printf("[DVBS]: DAGC0_Peak_Mean ===============: %f\n", DAGC0_Peak_Mean);
5108 printf("[DVBS]: DAGC1_Peak_Mean ===============: %f\n", DAGC1_Peak_Mean);
5109 printf("[DVBS]: DAGC2_Peak_Mean ===============: %f\n", DAGC2_Peak_Mean);
5110 printf("[DVBS]: DAGC3_Peak_Mean ===============: %f\n", DAGC3_Peak_Mean);
5111 //---------------------------------------------------------
5112 //Freeze and dump
5113 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5114
5115 u16Address = (DCR_OFFSET)&0xffff;
5116 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5117
5118 DCR_Offset_I=(u16Data&0xff);
5119 if (DCR_Offset_I >= 0x80)
5120 DCR_Offset_I = DCR_Offset_I-0x100;
5121 DCR_Offset_I = DCR_Offset_I/0x80;
5122
5123 DCR_Offset_Q=(u16Data>>8)&0xff;
5124 if (DCR_Offset_Q >= 0x80)
5125 DCR_Offset_Q = DCR_Offset_Q-0x100;
5126 DCR_Offset_Q = DCR_Offset_Q/0x80;
5127
5128 //Unfreeze
5129 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5130
5131 printf("[DVBS]: DCR_Offset_I ==================: %f\n", DCR_Offset_I);
5132 printf("[DVBS]: DCR_Offset_Q ==================: %f\n", DCR_Offset_Q);
5133 //---------------------------------------------------------
5134 ////Page1-FineCFO & PR & IIS & IQB
5135 //---------------------------------------------------------
5136 //FineCFO
5137 printf("------------------------------------------------------------------------\n");
5138 printf("Debug Message [FineCFO & PR & IIS & IQB & SNR Status]===================\n");
5139 //Debug Select
5140 u16Address = INNER_DEBUG_SEL;
5141 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5142 u16Data=((u16Data&0xC0FF)|0x0400);
5143 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5144
5145 //Freeze and dump
5146 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5147
5148 u16Address = INNEREXT_FINEFE_DBG_OUT0;
5149 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5150 FineCFO_loop_out_value=u16Data;
5151 u16Address = INNEREXT_FINEFE_DBG_OUT2;
5152 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5153 FineCFO_loop_out_value=(FineCFO_loop_out_value+(float)u16Data*pow(2.0, 16));
5154
5155 //Too large.Use 10Bit
5156 u16Address = INNEREXT_FINEFE_KI_FF0;
5157 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5158 FineCFO_loop_ki_value=u16Data;
5159 u16Address = INNEREXT_FINEFE_KI_FF2;
5160 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5161 FineCFO_loop_ki_value=(FineCFO_loop_ki_value+(float)u16Data*pow(2.0, 16));
5162 u16Address = INNEREXT_FINEFE_KI_FF4;
5163 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5164 FineCFO_loop_ki_value=(FineCFO_loop_ki_value+(double)(u16Data&0x00FF)*pow(2.0, 32));
5165 //Unfreeze
5166 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5167
5168 //---------------------------------------------------------
5169 //Debug Select
5170 u16Address = INNER_DEBUG_SEL;
5171 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5172 u16Data=((u16Data&0xC0FF)|0x0100);
5173 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5174
5175 //Freeze and dump
5176 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5177
5178 u16Address = INNEREXT_FINEFE_DBG_OUT0;
5179 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5180 FineCFO_loop_input_value=u16Data;
5181 u16Address = INNEREXT_FINEFE_DBG_OUT2;
5182 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5183 FineCFO_loop_input_value=(FineCFO_loop_input_value+(float)u16Data*pow(2.0, 16));
5184
5185 //Unfreeze
5186 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5187
5188 FineCFO_loop_ki_value = FineCFO_loop_ki_value/1024;
5189
5190 if (FineCFO_loop_out_value > 8388608)
5191 FineCFO_loop_out_value=FineCFO_loop_out_value - 16777216;
5192 if (FineCFO_loop_ki_value > 536870912)//549755813888/1024)
5193 FineCFO_loop_ki_value=FineCFO_loop_ki_value - 1073741824;//1099511627776/1024;
5194 if (FineCFO_loop_input_value> 1048576)
5195 FineCFO_loop_input_value=FineCFO_loop_input_value - 2097152;
5196
5197 FineCFO_loop_out_value = ((float)FineCFO_loop_out_value/16777216);
5198 FineCFO_loop_ki_value = ((double)FineCFO_loop_ki_value/67108864*u32DebugInfo_Fb);//68719476736/1024*Fb
5199 FineCFO_loop_input_value = ((float)FineCFO_loop_input_value/2097152);
5200
5201 printf("[DVBS]: FineCFO_loop_out_value ========: %f \n", FineCFO_loop_out_value);
5202 printf("[DVBS]: FineCFO_loop_ki_value =========: %f \n", FineCFO_loop_ki_value);
5203 printf("[DVBS]: FineCFO_loop_input_value ======: %f \n", FineCFO_loop_input_value);
5204
5205 //---------------------------------------------------------
5206 //Phase Recovery
5207 //Debug select
5208 u16Address = INNER_DEBUG_SEL;
5209 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5210 u16Data=(((u16Data&0x00FF)|0x0600)&0xffff);
5211 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5212
5213 //Freeze and dump
5214 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5215
5216 u16Address = INNER_PR_DEBUG_OUT0;
5217 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5218 PR_out_value=u16Data;
5219 if (PR_out_value>=0x1000)
5220 PR_out_value=PR_out_value-0x2000;
5221
5222 //Unfreeze
5223 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5224 //---------------------------------------------------------
5225 //Debug select
5226 u16Address = INNER_DEBUG_SEL;
5227 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5228 u16Data=(((u16Data&0x00FF)|0x0100)&0xffff);
5229 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5230
5231 //Freeze and dump
5232 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5233
5234 u16Address = INNER_PR_DEBUG_OUT0;
5235 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5236 PR_in_value=u16Data;
5237 u16Address = INNER_PR_DEBUG_OUT2;
5238 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5239 PR_in_value=(((u16Data&0x000F)<<16)|(MS_U16)PR_in_value);
5240 if (PR_in_value>=0x80000)
5241 PR_in_value=PR_in_value-0x100000;
5242
5243 //Unfreeze
5244 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5245 //---------------------------------------------------------
5246 //Debug select
5247 u16Address = INNER_DEBUG_SEL;
5248 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5249 u16Data=(((u16Data&0xC0FF)|0x0400)&0xffff);
5250 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5251
5252 //Freeze and dump
5253 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5254
5255 u16Address = INNER_PR_DEBUG_OUT0;
5256 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5257 PR_loop_ki=u16Data;
5258 u16Address = INNER_PR_DEBUG_OUT2;
5259 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5260 PR_loop_ki=(((u16Data&0x00FF)<<16)+PR_loop_ki);
5261 if (PR_loop_ki>=0x800000)
5262 PR_loop_ki=PR_loop_ki-0x1000000;
5263
5264 //Unfreeze
5265 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5266 //---------------------------------------------------------
5267 //Debug select
5268 u16Address = INNER_DEBUG_SEL;
5269 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5270 u16Data=(((u16Data&0x00FF)|0x0500)&0xffff);
5271 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5272
5273 //Freeze and dump
5274 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5275
5276 u16Address = INNER_PR_DEBUG_OUT0;
5277 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5278 PR_loopback_ki=u16Data;
5279 u16Address = INNER_PR_DEBUG_OUT2;
5280 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5281 PR_loopback_ki=(((u16Data&0x00FF)<<16)+PR_loopback_ki);
5282 if (PR_loopback_ki>=0x800000)
5283 PR_loopback_ki=PR_loopback_ki-0x1000000;
5284
5285 //Unfreeze
5286 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5287
5288 PR_out_value = ((float)PR_out_value/4096);
5289 PR_in_value = ((float)PR_in_value/131072);
5290 PR_loop_ki = ((float)PR_loop_ki/67108864*u32DebugInfo_Fb);
5291 PR_loopback_ki = ((float)PR_loopback_ki/67108864*u32DebugInfo_Fb);
5292
5293 printf("[DVBS]: PR_out_value ==================: %f\n", PR_out_value);
5294 printf("[DVBS]: PR_in_value ===================: %f\n", PR_in_value);
5295 printf("[DVBS]: PR_loop_ki ====================: %f\n", PR_loop_ki);
5296 printf("[DVBS]: PR_loopback_ki ================: %f\n", PR_loopback_ki);
5297 //---------------------------------------------------------
5298 //IIS
5299 //Freeze and dump
5300 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5301
5302 u16Address = (IIS_COUNT0)&0xffff;
5303 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5304 IIS_cnt=u16Data;
5305 u16Address = (IIS_COUNT2)&0xffff;
5306 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5307 IIS_cnt=(u16Data&0x1f)<<16|IIS_cnt;
5308
5309 printf("[DVBS]: IIS_cnt =======================: %d\n", IIS_cnt);
5310
5311 //Unfreeze
5312 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5313 //IQB
5314 //Freeze and dump
5315 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5316
5317 u16Address = (IQB_PHASE)&0xffff;
5318 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5319 IQB_Phase=u16Data&0x3FF;
5320 if (IQB_Phase>=0x200)
5321 IQB_Phase=IQB_Phase-0x400;
5322 IQB_Phase=IQB_Phase/0x400*180;
5323
5324 u16Address = (IQB_GAIN)&0xffff;
5325 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5326 IQB_Gain=u16Data&0x7FF;
5327 IQB_Gain=IQB_Gain/0x400;
5328
5329 printf("[DVBS]: IQB_Phase =====================: %f\n", IQB_Phase);
5330 printf("[DVBS]: IQB_Gain ======================: %f\n", IQB_Gain);
5331
5332 //Unfreeze
5333 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5334 //---------------------------------------------------------
5335 //SNR
5336 //Freeze and dump
5337 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5338
5339 Eq_variance_da=0;
5340 u16Address = 0x249E;
5341 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5342 Eq_variance_da=u16Data;
5343 u16Address = 0x24A0;
5344 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5345 Eq_variance_da=((float)(u16Data&0x03fff)*pow(2.0, 16)+Eq_variance_da)/pow(2.0, 29);
5346
5347 if (Eq_variance_da==0)
5348 Eq_variance_da=1;
5349 Linear_SNR_da=1.0/Eq_variance_da;
5350 SNR_da_dB=10*log10(Linear_SNR_da);
5351
5352 Eq_variance_dd=0;
5353 u16Address = 0x24A2;
5354 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5355 Eq_variance_dd=u16Data;
5356 u16Address = 0x24A4;
5357 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5358 Eq_variance_dd=(((float)(u16Data&0x3fff)*65536)+Eq_variance_dd)/pow(2.0, 29);
5359
5360 if (Eq_variance_dd==0)
5361 Eq_variance_dd=1;
5362 Linear_SNR_dd=1.0/Eq_variance_dd;
5363 SNR_dd_dB=10*log10(Linear_SNR_dd);
5364
5365 ndasnr_a=0;
5366 u16Address = 0x248C;
5367 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5368 ndasnr_a=u16Data;
5369 u16Address = 0x248E;
5370 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5371 ndasnr_a=(((float)(u16Data&0x0003)*pow(2.0, 16))+ndasnr_a)/65536;
5372
5373 ndasnr_ab=0;
5374 u16Address = 0x2490;
5375 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5376 ndasnr_ab=u16Data;
5377 u16Address = 0x2492;
5378 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5379 ndasnr_ab=(((float)(u16Data&0x03ff)*pow(2.0, 16))+ndasnr_ab)/4194304;
5380
5381 ndasnr_ab=sqrt(ndasnr_ab);
5382 if (ndasnr_ab==0)
5383 ndasnr_ab=1;
5384 ndasnr_ratio=(float)ndasnr_a/ndasnr_ab;
5385 if (ndasnr_ratio> 1)
5386 SNR_nda_dB=10*log10(1/(ndasnr_ratio - 1));
5387 else
5388 SNR_nda_dB=0;
5389
5390 u16Address = 0x24BA;
5391 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5392 Linear_SNR=u16Data;
5393 u16Address = 0x24BC;
5394 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5395 Linear_SNR=(((float)(u16Data&0x0007)*pow(2.0, 16))+Linear_SNR)/64;
5396 if (Linear_SNR==0)
5397 Linear_SNR=1;
5398 Linear_SNR=10*log10(Linear_SNR);
5399
5400 //Unfreeze
5401 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5402 printf("[DVBS]: SNR ===========================: %.2f\n", Linear_SNR);
5403 printf("[DVBS]: SNR_DA_dB =====================: %.2f\n", SNR_da_dB);
5404 printf("[DVBS]: SNR_DD_dB =====================: %.2f\n", SNR_dd_dB);
5405 printf("[DVBS]: SNR_NDA_dB ====================: %.2f\n", SNR_nda_dB);
5406 //---------------------------------------------------------
5407 printf("------------------------------------------------------------------------\n");
5408 printf("Debug Message [DVBS - PacketErr & BER]==================================\n");
5409 //BER
5410 //freeze
5411 u16Address = 0x2103;
5412 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5413 u16Data=u16Data|0x0001;
5414 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5415
5416 // bank 17 0x18 [7:0] reg_bit_err_sblprd_7_0 [15:8] reg_bit_err_sblprd_15_8
5417 u16Address = 0x2166;
5418 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5419 Packet_Err=u16Data;
5420
5421 printf("[DVBS]: Packet Err ====================: %.3E\n", Packet_Err);
5422
5423 /////////// Post-Viterbi BER /////////////
5424 // bank 7 0x18 [7:0] reg_bit_err_sblprd_7_0
5425 // [15:8] reg_bit_err_sblprd_15_8
5426 u16Address = 0x2146;
5427 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5428 BitErrPeriod=u16Data;
5429
5430 // bank 17 0x1D [7:0] reg_bit_err_num_7_0 [15:8] reg_bit_err_num_15_8
5431 // bank 17 0x1E [7:0] reg_bit_err_num_23_16 [15:8] reg_bit_err_num_31_24
5432 u16Address = 0x216A;
5433 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5434 BitErr=u16Data;
5435 u16Address = 0x216C;
5436 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5437 BitErr=(u16Data<<16)|BitErr;
5438
5439 if (BitErrPeriod ==0 )//protect 0
5440 BitErrPeriod=1;
5441 if (BitErr <=0 )
5442 BER=0.5 / (float)(BitErrPeriod*128*188*8);
5443 else
5444 BER=(float)(BitErr) / (float)(BitErrPeriod*128*188*8);
5445
5446 printf("[DVBS]: Post-Viterbi BER ==============: %.3E\n", BER);
5447
5448 // bank 7 0x19 [7] reg_bit_err_num_freeze
5449 u16Address = 0x2103;
5450 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5451 u16Data=u16Data&(~0x0001);
5452 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5453
5454 /////////// Pre-Viterbi BER /////////////
5455 // bank 17 0x08 [3] reg_rd_freezeber
5456 u16Address = 0x2110;
5457 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5458 u16Data=u16Data|0x0008;
5459 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5460
5461 // bank 17 0x0b [7:0] reg_ber_timerl [15:8] reg_ber_timerm
5462 // bank 17 0x0c [5:0] reg_ber_timerh
5463 u16Address = 0x2116;
5464 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5465 BitErrPeriod=u16Data;
5466 u16Address = 0x2118;
5467 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5468 BitErrPeriod=((u16Data&0x3f)<<16)|BitErrPeriod;
5469
5470 // bank 17 0x0f [7:0] reg_ber_7_0 [15:8] reg_ber_15_8
5471 u16Address = 0x211E;
5472 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5473 BitErr=u16Data;
5474
5475 // bank 17 0x0D [13:8] reg_cor_intstat_reg
5476 u16Address = 0x211A;
5477 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5478 if (u16Data & 0x1000)
5479 {
5480 BEROver = true;
5481 }
5482 else
5483 {
5484 BEROver = false;
5485 }
5486
5487 if (BitErrPeriod ==0 )//protect 0
5488 BitErrPeriod=1;
5489 if (BitErr <=0 )
5490 BER=0.5 / (float)(BitErrPeriod) / 256;
5491 else
5492 BER=(float)(BitErr) / (float)(BitErrPeriod) / 256;
5493 printf("[DVBS]: Pre-Viterbi BER ===============: %.3E\n", BER);
5494
5495 // bank 17 0x08 [3] reg_rd_freezeber
5496 u16Address = 0x2110;
5497 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5498 u16Data=u16Data&(~0x0008);
5499 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5500
5501 u16Address = 0x2188;
5502 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5503 ConvegenceLen = ((u16Data>>8)&0xFF);
5504 printf("[DVBS]: ConvegenceLen =================: %d\n", ConvegenceLen);
5505
5506 //---------------------------------------------------------
5507 //Timing Recovery
5508 //Debug select
5509 u16Address = (INNER_DEBUG_SEL_TR>>16)&0xffff;
5510 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5511 u16Data=(((u16Data&0x00ff)|INNER_DEBUG_SEL_TR)&0xffff);
5512 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5513
5514 //Freeze and dump
5515 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5516
5517 u16Address = (TR_INDICATOR_FF0)&0xffff;
5518 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5519 TR_Indicator_ff=u16Data;
5520 u16Address = (TR_INDICATOR_FF0)&0xffff;
5521 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5522 TR_Indicator_ff=((u16Data<<16) | (MS_U16)TR_Indicator_ff)&0x7fffff;
5523 if (TR_Indicator_ff >= 0x400000)
5524 TR_Indicator_ff=TR_Indicator_ff - 0x800000;
5525
5526 //Unfreeze
5527 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5528
5529 //Debug select
5530 u16Address = (DEBUG_SEL_TR_SFO_CONVERGE>>16)&0xffff;
5531 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5532 u16Data=(((u16Data&0x00ff)|DEBUG_SEL_TR_SFO_CONVERGE)&0xffff);
5533 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5534
5535 //Freeze and dump
5536 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5537
5538 u16Address = (TR_INDICATOR_FF0)&0xffff;
5539 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5540 TR_SFO_Converge=u16Data;
5541 u16Address = (TR_INDICATOR_FF0)&0xffff;
5542 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5543 TR_SFO_Converge=((u16Data<<16) | (MS_U16)TR_SFO_Converge)&0x7fffff;
5544 if (TR_SFO_Converge >= 0x400000)
5545 TR_SFO_Converge=TR_SFO_Converge - 0x800000;
5546
5547 u16Address = INNER_TR_LOPF_VALUE_DEBUG0;
5548 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5549 TR_loop_ki=u16Data;
5550 u16Address = INNER_TR_LOPF_VALUE_DEBUG2;
5551 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5552 TR_loop_ki=((float)u16Data*pow(2.0, 16))+TR_loop_ki;
5553 u16Address = INNER_TR_LOPF_VALUE_DEBUG4;
5554 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5555 TR_loop_ki=(((double)(u16Data&0x01ff)*pow(2.0, 32))+ TR_loop_ki);
5556 if (TR_loop_ki>=pow(2.0, 40))
5557 TR_loop_ki=TR_loop_ki-pow(2.0, 41);
5558
5559 //Unfreeze
5560 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5561
5562 //Debug select
5563 u16Address = (DEBUG_SEL_TR_INPUT>>16)&0xffff;
5564 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5565 u16Data=(((u16Data&0x00ff)|DEBUG_SEL_TR_INPUT)&0xffff);
5566 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5567
5568 //Freeze and dump
5569 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5570
5571 u16Address = (TR_INDICATOR_FF0)&0xffff;
5572 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5573 TR_loop_input=u16Data;
5574 //banknum=(TR_INDICATOR_FF1>>8)&0xff;
5575 //addr=(TR_INDICATOR_FF1)&0xff;
5576 //if(InformRead(banknum, addr, &data)==FALSE) return;
5577 //TR_loop_input=((float)((data&0x00ff)<<16) + TR_loop_input);
5578 if (TR_loop_input >= 0x8000)
5579 TR_loop_input=TR_loop_input - 0x10000;
5580
5581 //Unfreeze
5582 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5583
5584 Fs_value=u32DebugInfo_Fs;
5585 Fb_value=u32DebugInfo_Fb;
5586 TR_tmp0=(float)TR_SFO_Converge/0x200000;
5587 TR_tmp2=TR_loop_ki/pow(2.0, 39);
5588 TR_tmp1=(float)Fs_value/2/Fb_value;
5589
5590 TR_Indicator_ff = (TR_Indicator_ff/0x400);
5591 TR_Loop_Output = (TR_tmp0/TR_tmp1*1000000);
5592 TR_Loop_Ki = (TR_tmp2/TR_tmp1*1000000);
5593 TR_loop_input = (TR_loop_input/0x8000);
5594
5595 printf("[DVBS]: TR_Indicator_ff================: %f \n", TR_Indicator_ff);
5596 printf("[DVBS]: TR_Loop_Output=================: %f [ppm]\n", TR_Loop_Output);
5597 printf("[DVBS]: TR_Loop_Ki=====================: %f [ppm]\n", TR_Loop_Ki);
5598 printf("[DVBS]: TR_loop_input==================: %f \n", TR_loop_input);
5599 #endif
5600 bRet=true;
5601 return bRet;
5602 }
5603
5604 //------------------------------------------------------------------
5605 // END Get And Show Info Function
5606 //------------------------------------------------------------------
5607
5608 //------------------------------------------------------------------
5609 // BlindScan Function
5610 //------------------------------------------------------------------
INTERN_DVBS_BlindScan_Start(MS_U16 u16StartFreq,MS_U16 u16EndFreq)5611 MS_BOOL INTERN_DVBS_BlindScan_Start(MS_U16 u16StartFreq,MS_U16 u16EndFreq)
5612 {
5613 MS_BOOL status=TRUE;
5614 MS_U8 u8Data=0;
5615
5616 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_Start+\n"));
5617
5618 _u16BlindScanStartFreq=u16StartFreq;
5619 _u16BlindScanEndFreq=u16EndFreq;
5620 _u16TunerCenterFreq=0;
5621 _u16ChannelInfoIndex=0;
5622
5623 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5624 u8Data&=0xd0;
5625 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5626
5627 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)_u16BlindScanStartFreq&0x00ff);
5628 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(_u16BlindScanStartFreq>>8)&0x00ff);
5629
5630 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_Start- _u16BlindScanStartFreq%d u16StartFreq %d u16EndFreq %d\n", _u16BlindScanStartFreq, u16StartFreq, u16EndFreq));
5631
5632 return status;
5633 }
5634
INTERN_DVBS_BlindScan_NextFreq(MS_BOOL * bBlindScanEnd)5635 MS_BOOL INTERN_DVBS_BlindScan_NextFreq(MS_BOOL* bBlindScanEnd)
5636 {
5637 MS_BOOL status=TRUE;
5638 MS_U8 u8Data=0;
5639
5640 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq+\n"));
5641
5642 * bBlindScanEnd=FALSE;
5643
5644 if (_u16TunerCenterFreq >=_u16BlindScanEndFreq)
5645 {
5646 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq . _u16TunerCenterFreq %d _u16BlindScanEndFreq%d\n", _u16TunerCenterFreq, _u16BlindScanEndFreq));
5647 * bBlindScanEnd=TRUE;
5648
5649 return status;
5650 }
5651 //Set Tuner Frequency
5652 MsOS_DelayTask(10);
5653
5654 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5655 if ((u8Data&0x02)==0x00)//Manual Tune
5656 {
5657 u8Data&=~(0x28);
5658 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5659 u8Data|=0x02;
5660 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5661 u8Data|=0x01;
5662 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5663 }
5664 else
5665 {
5666 u8Data&=~(0x28);
5667 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5668 }
5669
5670 return status;
5671 }
5672
INTERN_DVBS_BlindScan_GetTunerFreq(MS_U16 * u16TunerCenterFreq,MS_U16 * u16TunerCutOffFreq)5673 MS_BOOL INTERN_DVBS_BlindScan_GetTunerFreq(MS_U16 *u16TunerCenterFreq, MS_U16 *u16TunerCutOffFreq)
5674 {
5675 MS_BOOL status=TRUE;
5676 MS_U8 u8Data=0;
5677 MS_U16 u16WaitCount;
5678 MS_U16 u16TunerCutOff;
5679
5680 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_GetTunerFreq+\n"));
5681
5682 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5683 if ((u8Data&0x02)==0x02)
5684 {
5685 u8Data|=0x08;
5686 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5687 u16WaitCount=0;
5688 do
5689 {
5690 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
5691 u16WaitCount++;
5692 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
5693 MsOS_DelayTask(1);
5694 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
5695 }
5696 else if((u8Data&0x01)==0x01)
5697 {
5698 u8Data|=0x20;
5699 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5700 u16WaitCount=0;
5701 do
5702 {
5703 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
5704 u16WaitCount++;
5705 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
5706 MsOS_DelayTask(1);
5707 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
5708 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5709 u8Data|=0x02;
5710 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5711 }
5712 u16WaitCount=0;
5713
5714 _u16TunerCenterFreq=0;
5715
5716 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, &u8Data);
5717 //printf("INTERN_DVBS_BlindScan_GetTunerFreq E_DMD_S2_BS_Tuner_Center_Freq_H=%d\n", u8Data);//RRRRR
5718 _u16TunerCenterFreq=u8Data;
5719 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, &u8Data);
5720 //printf("INTERN_DVBS_BlindScan_GetTunerFreq E_DMD_S2_BS_Tuner_Center_Freq_L=%d\n", u8Data);//RRRRR
5721 _u16TunerCenterFreq=(_u16TunerCenterFreq<<8)|u8Data;
5722
5723 *u16TunerCenterFreq = _u16TunerCenterFreq;
5724 //claire test
5725 u16TunerCutOff=44000;
5726 if(_u16TunerCenterFreq<=990)//980
5727 {
5728
5729 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_BALANCE_TRACK, &u8Data);
5730 if(u8Data==0x01)
5731 {
5732 if(_u16TunerCenterFreq<970)//970
5733 {
5734 u16TunerCutOff=10000;
5735 }
5736 else
5737 {
5738 u16TunerCutOff=20000;
5739 }
5740 u8Data=0x02;
5741 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_BALANCE_TRACK, u8Data);
5742 }
5743 else if(u8Data==0x02)
5744 {
5745 u8Data=0x00;
5746 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_BALANCE_TRACK, u8Data);
5747 }
5748 }
5749 *u16TunerCutOffFreq = u16TunerCutOff;
5750
5751 //end claire test
5752
5753 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_GetTunerFreq- _u16TunerCenterFreq:%d\n", _u16TunerCenterFreq));
5754
5755
5756 return status;
5757 }
5758
INTERN_DVBS_BlindScan_WaitCurFreqFinished(MS_U8 * u8Progress,MS_U8 * u8FindNum)5759 MS_BOOL INTERN_DVBS_BlindScan_WaitCurFreqFinished(MS_U8* u8Progress,MS_U8 *u8FindNum)
5760 {
5761 MS_BOOL status=TRUE;
5762 MS_U32 u32Data=0;
5763 MS_U16 u16Data=0;
5764 MS_U8 u8Data=0, u8Data2=0;
5765 MS_U16 u16WaitCount;
5766
5767 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_WaitCurFreqFinished+\n"));
5768
5769 u16WaitCount=0;
5770 *u8FindNum=0;
5771 *u8Progress=0;
5772
5773 do
5774 {
5775 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data); //State=BlindScan
5776 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_BLINDSCAN_CHECK, &u8Data2); //SubState=BlindScan
5777 u16WaitCount++;
5778 DBG_INTERN_DVBS(printf("INTERN_DVBS_BlindScan_WaitCurFreqFinished State: 0x%x Status: 0x%x u16WaitCount:%d\n", u8Data, u8Data2, u16WaitCount));
5779 //printf("INTERN_DVBS_BlindScan_WaitCurFreqFinished State: 0x%x Status: 0x%x u16WaitCount:%d\n", u8Data, u8Data2, u16WaitCount);
5780
5781 MsOS_DelayTask(1);
5782 }while(((u8Data!=17)||(u8Data2!=0xff))&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));//E_DMD_S2_STATE_FLAG
5783
5784
5785
5786 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DUMMY_REG_2, &u8Data);
5787 u16Data=u8Data;
5788
5789
5790 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_WaitCurFreqFinished OuterCheckStatus:0x%x\n", u16Data));
5791
5792 if (u16WaitCount>=INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
5793 {
5794 status=false;
5795 printf("Debug blind scan wait finished time out!!!!\n");
5796 }
5797 else
5798 {
5799
5800 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SUBSTATE_FLAG, &u8Data);//SubState
5801 if (u8Data==0)
5802 {
5803
5804 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
5805 u32Data=u8Data;
5806 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
5807 u32Data=(u32Data<<8)|u8Data;
5808 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
5809 u32Data=(u32Data<<8)|u8Data;
5810 _u16ChannelInfoArray[0][_u16ChannelInfoIndex]=((u32Data+500)/1000);
5811 _u16LockedCenterFreq=((u32Data+500)/1000); //Center Freq
5812
5813
5814 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
5815 u16Data=u8Data;
5816 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
5817 u16Data=(u16Data<<8)|u8Data;
5818 _u16ChannelInfoArray[1][_u16ChannelInfoIndex]=(u16Data);//Symbol Rate
5819 _u16LockedSymbolRate=u16Data;
5820 _u16ChannelInfoIndex++;
5821 *u8FindNum=_u16ChannelInfoIndex;
5822 //printf("claire debug blind scan: find TP frequency %d SR %d index %d\n",_u16LockedCenterFreq,_u16LockedSymbolRate,_u16ChannelInfoIndex);
5823
5824
5825 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
5826 u16Data=u8Data;
5827 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
5828 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset_Locked
5829 if (u16Data*1000 >= 0x8000)
5830 {
5831 u16Data=0x10000- u16Data*1000;
5832 _s16CurrentCFO=-1*u16Data/1000;
5833 }
5834 else
5835 {
5836 _s16CurrentCFO=u16Data;
5837 }
5838
5839 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
5840 u16Data=u8Data;
5841 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
5842 u16Data=(u16Data<<8)|u8Data;
5843 _u16CurrentStepSize=u16Data; //Tuner_Frequency_Step
5844
5845
5846 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18H, &u8Data);
5847 u16Data=u8Data;
5848 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18L, &u8Data);
5849 u16Data=(u16Data<<8)|u8Data;
5850 _u16PreLockedHB=u16Data; //Pre_Scanned_HB
5851
5852
5853 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19H, &u8Data);
5854 u16Data=u8Data;
5855 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19L, &u8Data);
5856 u16Data=(u16Data<<8)|u8Data;
5857 _u16PreLockedLB=u16Data; //Pre_Scanned_LB
5858
5859
5860 DBG_INTERN_DVBS(printf("Current Locked CF:%d BW:%d BWH:%d BWL:%d CFO:%d Step:%d\n", _u16LockedCenterFreq, _u16LockedSymbolRate,_u16PreLockedHB, _u16PreLockedLB, _s16CurrentCFO, _u16CurrentStepSize));
5861 }
5862 else if (u8Data==1)
5863 {
5864 //printf("claire debug blind scan: no find TP\n");
5865
5866
5867 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, &u8Data);
5868 u16Data=u8Data;
5869 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, &u8Data);
5870 u16Data=(u16Data<<8)|u8Data;
5871 _u16NextCenterFreq=u16Data;
5872
5873
5874 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
5875 u16Data=u8Data;
5876 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
5877 u16Data=(u16Data<<8)|u8Data;
5878 _u16PreLockedHB=u16Data; //Pre_Scanned_HB
5879
5880
5881
5882 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13H, &u8Data);
5883 u16Data=u8Data;
5884 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
5885 u16Data=(u16Data<<8)|u8Data;
5886 _u16PreLockedLB=u16Data; //Pre_Scanned_LB
5887
5888
5889 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
5890 u16Data=u8Data;
5891 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
5892 u16Data=(u16Data<<8)|u8Data;
5893 _u16CurrentSymbolRate=u16Data; //Fine_Symbol_Rate
5894
5895
5896 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
5897 u16Data=u8Data;
5898 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
5899 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset
5900 if (u16Data*1000 >= 0x8000)
5901 {
5902 u16Data=0x1000- u16Data*1000;
5903 _s16CurrentCFO=-1*u16Data/1000;
5904 }
5905 else
5906 {
5907 _s16CurrentCFO=u16Data;
5908 }
5909
5910 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
5911 u16Data=u8Data;
5912 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
5913 u16Data=(u16Data<<8)|u8Data;
5914 _u16CurrentStepSize=u16Data; //Tuner_Frequency_Step
5915
5916
5917 DBG_INTERN_DVBS(printf("Pre Locked CF:%d BW:%d HBW:%d LBW:%d Current CF:%d BW:%d CFO:%d Step:%d\n", _u16LockedCenterFreq, _u16LockedSymbolRate,_u16PreLockedHB, _u16PreLockedLB, _u16NextCenterFreq-_u16CurrentStepSize, _u16CurrentSymbolRate, _s16CurrentCFO, _u16CurrentStepSize));
5918 }
5919 }
5920 *u8Progress=100;
5921
5922 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_WaitCurFreqFinished- u8Progress: %d u8FindNum %d\n", *u8Progress, *u8FindNum));
5923
5924 return status;
5925 }
5926
INTERN_DVBS_BlindScan_Cancel(void)5927 MS_BOOL INTERN_DVBS_BlindScan_Cancel(void)
5928 {
5929 MS_BOOL status=TRUE;
5930 MS_U8 u8Data=0;
5931 MS_U16 u16Data;
5932
5933 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_Cancel+\n"));
5934
5935 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5936 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
5937 u8Data&=0xF0;
5938 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5939 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
5940
5941 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E1, 0x00);
5942 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E0, 0x00);
5943 u16Data = 0x0000;
5944 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)u16Data&0x00ff);
5945 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(u16Data>>8)&0x00ff);
5946
5947 _u16TunerCenterFreq=0;
5948 _u16ChannelInfoIndex=0;
5949
5950 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_Cancel-\n"));
5951
5952 return status;
5953 }
5954
INTERN_DVBS_BlindScan_End(void)5955 MS_BOOL INTERN_DVBS_BlindScan_End(void)
5956 {
5957 MS_BOOL status=TRUE;
5958 MS_U8 u8Data=0;
5959 MS_U16 u16Data;
5960
5961 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_End+\n"));
5962
5963 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5964 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
5965 u8Data&=0xF0;
5966 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5967 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
5968
5969 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E1, 0x00);
5970 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E0, 0x00);
5971 u16Data = 0x0000;
5972 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)u16Data&0x00ff);
5973 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(u16Data>>8)&0x00ff);
5974
5975 _u16TunerCenterFreq=0;
5976 _u16ChannelInfoIndex=0;
5977
5978 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_End-\n"));
5979
5980 return status;
5981 }
5982
INTERN_DVBS_BlindScan_GetChannel(MS_U16 u16ReadStart,MS_U16 * u16TPNum,HAL_DEMOD_MS_FE_CARRIER_PARAM * pTable)5983 MS_BOOL INTERN_DVBS_BlindScan_GetChannel(MS_U16 u16ReadStart,MS_U16* u16TPNum,HAL_DEMOD_MS_FE_CARRIER_PARAM *pTable)
5984 {
5985 MS_BOOL status=TRUE;
5986 MS_U16 u16TableIndex;
5987
5988 *u16TPNum=_u16ChannelInfoIndex-u16ReadStart;
5989 for(u16TableIndex = 0; u16TableIndex < (*u16TPNum); u16TableIndex++)
5990 {
5991 pTable[u16TableIndex].u32Frequency = _u16ChannelInfoArray[0][_u16ChannelInfoIndex-1];
5992 pTable[u16TableIndex].SatParam.u32SymbolRate = _u16ChannelInfoArray[1][_u16ChannelInfoIndex-1];
5993 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_GetChannel Freq: %d SymbolRate: %d\n", pTable[u16TableIndex].u32Frequency, pTable[u16TableIndex].SatParam.u32SymbolRate));
5994 }
5995 DBG_INTERN_DVBS(printf("INTERN_DVBS_u16TPNum:%d\n", *u16TPNum));
5996
5997 return status;
5998 }
5999
INTERN_DVBS_BlindScan_GetCurrentFreq(MS_U32 * u32CurrentFeq)6000 MS_BOOL INTERN_DVBS_BlindScan_GetCurrentFreq(MS_U32 *u32CurrentFeq)
6001 {
6002 MS_BOOL status=TRUE;
6003 DBG_INTERN_DVBS(printf("INTERN_DVBS_BlindScan_GetCurrentFreq+\n"));
6004
6005 *u32CurrentFeq=_u16TunerCenterFreq;
6006 DBG_INTERN_DVBS(printf("INTERN_DVBS_BlindScan_GetCurrentFreq-: %d\n", _u16TunerCenterFreq));
6007 return status;
6008 }
6009 //------------------------------------------------------------------
6010 // END BlindScan Function
6011 //------------------------------------------------------------------
6012
6013 //------------------------------------------------------------------
6014 // DiSEqc Function
6015 //------------------------------------------------------------------
INTERN_DVBS_DiSEqC_Init(void)6016 MS_BOOL INTERN_DVBS_DiSEqC_Init(void)
6017 {
6018 MS_BOOL status = true;
6019 MS_U8 u8Data = 0;
6020
6021 //Clear status
6022 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6023 u8Data=(u8Data|0x3E)&(~0x3E);
6024 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6025
6026 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, 0x00);
6027 //Tone En
6028 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC0, &u8Data);
6029 u8Data=(u8Data&(~0x06))|(0x06);
6030 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, u8Data);
6031
6032 DBG_INTERN_DVBS(printf("INTERN_DVBS_DiSEqC_Init\n"));
6033
6034 return status;
6035 }
6036
INTERN_DVBS_DiSEqC_SetTone(MS_BOOL bTone1)6037 MS_BOOL INTERN_DVBS_DiSEqC_SetTone(MS_BOOL bTone1)
6038 {
6039 MS_BOOL status=TRUE;
6040 MS_U8 u8Data=0;
6041 MS_U8 u8ReSet22k=0;
6042
6043 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC4, 0x01);//0x62;DVBS2_DISEQC_TX1
6044 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, 0x4E);//0x60
6045 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCC, 0x88);//0x66
6046
6047 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);//0x61
6048 u8ReSet22k=u8Data;
6049
6050 if (bTone1==TRUE)
6051 {
6052 //Tone burst 1
6053 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, 0x19);
6054 _u8ToneBurstFlag=1;
6055 }
6056 else
6057 {
6058 //Tone burst 0
6059 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, 0x11);
6060 _u8ToneBurstFlag=2;
6061 }
6062 //DIG_DISEQC_TX_EN
6063 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6064 //u8Data=u8Data&~(0x01);//Tx Disable
6065 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6066
6067 MsOS_DelayTask(1);
6068 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);//0x66 high byte DVBS2_DISEQC_TX_EN
6069 u8Data=u8Data|0x3E; //Status clear
6070 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6071 MsOS_DelayTask(10);
6072 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6073 u8Data=u8Data&~(0x3E);
6074 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6075 MsOS_DelayTask(1);
6076
6077 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6078 u8Data=u8Data|0x01; //Tx Enable
6079 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6080
6081 MsOS_DelayTask(30);//(100)
6082 //For ToneBurst 22k issue.
6083 u8Data=u8ReSet22k;
6084 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);//0x61
6085
6086 DBG_INTERN_DVBS(printf("INTERN_DVBS_DiSEqC_SetTone:%d\n", bTone1));
6087 //MsOS_DelayTask(100);
6088 return status;
6089 }
6090
INTERN_DVBS_DiSEqC_SetLNBOut(MS_BOOL bLow)6091 MS_BOOL INTERN_DVBS_DiSEqC_SetLNBOut(MS_BOOL bLow)
6092 {
6093 MS_BOOL status=TRUE;
6094 MS_U8 u8Data=0;
6095
6096 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6097 if (bLow==TRUE)
6098 {
6099 u8Data=(u8Data|0x40); //13V
6100 }
6101 else
6102 {
6103 u8Data=(u8Data&(~0x40));//18V
6104 }
6105 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);
6106
6107 return status;
6108 }
6109
INTERN_DVBS_DiSEqC_GetLNBOut(MS_BOOL * bLNBOutLow)6110 MS_BOOL INTERN_DVBS_DiSEqC_GetLNBOut(MS_BOOL* bLNBOutLow)
6111 {
6112 MS_BOOL status=TRUE;
6113 MS_U8 u8Data=0;
6114
6115 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6116 if( (u8Data&0x40)==0x40)
6117 {
6118 * bLNBOutLow=TRUE;
6119 }
6120 else
6121 {
6122 * bLNBOutLow=FALSE;
6123 }
6124
6125 return status;
6126 }
6127
INTERN_DVBS_DiSEqC_Set22kOnOff(MS_BOOL b22kOn)6128 MS_BOOL INTERN_DVBS_DiSEqC_Set22kOnOff(MS_BOOL b22kOn)
6129 {
6130 MS_BOOL status=TRUE;
6131 MS_U8 u8Data=0;
6132
6133 //Set DiSeqC 22K
6134 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCC, 0x44); //Set 11K-->22K
6135
6136 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6137
6138 if (b22kOn==TRUE)
6139 {
6140 u8Data=(u8Data&0xc7);
6141 u8Data=(u8Data|0x08);
6142 }
6143 else
6144 {
6145 u8Data=(u8Data&0xc7);
6146 }
6147 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);
6148
6149 DBG_INTERN_DVBS(printf("INTERN_DVBS_DiSEqC_Set22kOnOff:%d\n", b22kOn));
6150 return status;
6151 }
6152
INTERN_DVBS_DiSEqC_Get22kOnOff(MS_BOOL * b22kOn)6153 MS_BOOL INTERN_DVBS_DiSEqC_Get22kOnOff(MS_BOOL* b22kOn)
6154 {
6155 MS_BOOL status=TRUE;
6156 MS_U8 u8Data=0;
6157
6158 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6159 if ((u8Data&0x38)==0x08)
6160 {
6161 *b22kOn=TRUE;
6162 }
6163 else
6164 {
6165 *b22kOn=FALSE;
6166 }
6167
6168 return status;
6169 }
6170
INTERN_DVBS_DiSEqC_SendCmd(MS_U8 * pCmd,MS_U8 u8CmdSize)6171 MS_BOOL INTERN_DVBS_DiSEqC_SendCmd(MS_U8* pCmd,MS_U8 u8CmdSize)
6172 {
6173 MS_BOOL status=TRUE;
6174 MS_U8 u8Data;
6175 MS_U8 u8Index;
6176 MS_U16 u16WaitCount;
6177 /*
6178 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6179 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6180 u8Data=(u8Data&~(0x10));
6181 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6182 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6183 */
6184 #if 0 //For Unicable command timing
6185 u16WaitCount=0;
6186 do
6187 {
6188 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data);
6189 //printf(">>> INTERN_DVBS_DiSEqC_SendCmd DiSEqC Status = 0x%x <<<\n", u8Data);
6190 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6191 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6192 MsOS_DelayTask(1);
6193 u16WaitCount++;
6194 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
6195
6196 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
6197 {
6198 DBG_INTERN_DVBS(printf("INTERN_DVBS DiSEqC Send Command Busy!!!\n"));
6199 return FALSE;
6200 }
6201 #endif
6202
6203 //u16Address=0x0BC4;
6204 for (u8Index=0; u8Index < u8CmdSize; u8Index++)
6205 {
6206 u8Data=*(pCmd+u8Index);
6207 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC4 + u8Index, u8Data);//#define DVBS2_DISEQC_TX1 (_REG_DVBS2(0x62)+0)//[7:0]
6208 DBG_INTERN_DVBS(printf("=============INTERN_DVBS_DiSEqC_SendCmd(Demod1) = 0x%X\n",u8Data));
6209 }
6210
6211 //set DiSEqC Tx Length, Odd Enable, Tone Burst Mode
6212 u8Data=((u8CmdSize-1)&0x07)|0x40;
6213 if (_u8ToneBurstFlag==1)
6214 {
6215 u8Data|=0x80;//0x20;
6216 }
6217 else if (_u8ToneBurstFlag==2)
6218 {
6219 u8Data|=0x20;//0x80;
6220 }
6221 _u8ToneBurstFlag=0;
6222 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_8, u8Data);
6223
6224 //add this only for check mailbox R/W
6225 #if 1
6226 DBG_INTERN_DVBS(printf(" Write into E_DMD_S2_MB_DMDTOP_DBG_8 = 0x%X!!!\n",u8Data));
6227 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_8, &u8Data);
6228 DBG_INTERN_DVBS(printf(" Read from E_DMD_S2_MB_DMDTOP_DBG_8 = 0x%X!!!\n",u8Data));
6229 #endif
6230
6231 MsOS_DelayTask(25);//MsOS_DelayTask(10);
6232 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);//#define TOP_WR_DBG_90 (_REG_DMDTOP(0x3A)+0)
6233 //u8Data=u8Data|0x10;
6234 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data|0x10);//enable DiSEqC_Data_Tx
6235 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); DBG_INTERN_DVBS(printf(">>>+++ INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X +++<<<\n",u8Data));
6236 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); DBG_INTERN_DVBS(printf(">>>+++ INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d +++<<<\n",u8Data));
6237
6238 #if 1 //For Unicable command timing???
6239 u16WaitCount=0;
6240 do
6241 {
6242 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); DBG_INTERN_DVBS(printf(">>>*** INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X ***<<<\n",u8Data));
6243 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); DBG_INTERN_DVBS(printf(">>>*** INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d ***<<<\n",u8Data));
6244 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6245 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6246 MsOS_DelayTask(1);
6247 u16WaitCount++;
6248 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)) ;
6249
6250 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
6251 {
6252 DBG_INTERN_DVBS(printf("INTERN_DVBS DiSEqC Send Command Busy!!!\n"));
6253 return FALSE;
6254 }
6255 else
6256 {
6257 DBG_INTERN_DVBS(printf("INTERN_DVBS DiSEqC Send Command Success!!!\n"));
6258 return TRUE;
6259 }
6260
6261
6262 #endif
6263 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); printf(">>>--- INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X ---<<<\n",u8Data);
6264 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); printf(">>>--- INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d ---<<<\n",u8Data+1);
6265
6266 return status;
6267 }
6268
INTERN_DVBS_DiSEqC_SetTxToneMode(MS_BOOL bTxTone22kOff)6269 MS_BOOL INTERN_DVBS_DiSEqC_SetTxToneMode(MS_BOOL bTxTone22kOff)
6270 {
6271 MS_BOOL status=TRUE;
6272 MS_U8 u8Data=0;
6273
6274 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xD7, &u8Data);//h006b h006b 15 15 reg_diseqc_tx_tone_mode
6275 if (bTxTone22kOff==TRUE)
6276 {
6277 u8Data=(u8Data|0x80); //1: without 22K.
6278 }
6279 else
6280 {
6281 u8Data=(u8Data&(~0x80)); //0: with 22K.
6282 }
6283 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xD7, u8Data);
6284
6285 return status;
6286 }
6287
INTERN_DVBS_UnicableAGCCheckPower(MS_BOOL pbAGCCheckPower)6288 MS_BOOL INTERN_DVBS_UnicableAGCCheckPower(MS_BOOL pbAGCCheckPower)
6289 {
6290 //MS_BOOL status = TRUE;
6291 MS_U8 u8Data=0;
6292
6293 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, 0x00);
6294
6295 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6296 u8Data &= 0xFE;//clean bit0
6297 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6298
6299 if (pbAGCCheckPower == FALSE)//0
6300 {
6301 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6302 u8Data &= 0xFE;//clean bit0
6303 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6304 //printf("CMD=MS_FALSE==============================\n");
6305 }
6306 else
6307 {
6308 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6309 u8Data |= 0x01; //bit1=1
6310 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6311 //printf("CMD=MS_TRUE==============================\n");
6312 }
6313
6314 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6315 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6316 u8Data &= 0xF0;
6317 u8Data |= 0x01;
6318 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6319 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6320 MsOS_DelayTask(500);
6321
6322 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6323 u8Data &= 0x80; //Read bit7
6324 if (u8Data == 0x80)
6325 {
6326 u8Data = 0x00;
6327 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6328 u8Data = 0x00;
6329 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6330 return TRUE;
6331 }
6332 else
6333 {
6334 u8Data = 0x00;
6335 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6336 u8Data = 0x00;
6337 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6338 return FALSE;
6339 }
6340 }
6341
6342 //------------------------------------------------------------------
6343 // END DiSEqc Function
6344 //------------------------------------------------------------------
6345 //------------------------------------------------------------------
6346 // R/W Function
6347 //------------------------------------------------------------------
INTERN_DVBS_WriteReg2bytes(MS_U16 u16Addr,MS_U16 u16Data)6348 MS_BOOL INTERN_DVBS_WriteReg2bytes(MS_U16 u16Addr, MS_U16 u16Data)
6349 {
6350 MS_BOOL bRet= TRUE;
6351 bRet &= MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr, (MS_U8)u16Data&0x00ff);
6352 bRet &= MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr + 0x0001, (MS_U8)(u16Data>>8)&0x00ff);
6353 return bRet;
6354 }
6355
INTERN_DVBS_ReadReg2bytes(MS_U16 u16Addr,MS_U16 * pu16Data)6356 MS_BOOL INTERN_DVBS_ReadReg2bytes(MS_U16 u16Addr, MS_U16 *pu16Data)
6357 {
6358 MS_BOOL bRet= TRUE;
6359 MS_U8 u8Data =0;
6360 MS_U16 u16Data =0;
6361
6362 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr + 0x0001, &u8Data);
6363 u16Data = u8Data;
6364 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr, &u8Data);
6365 *pu16Data = (u16Data<<8)|u8Data;
6366
6367 return bRet;
6368 }
6369
6370 //Frontend Freeze
INTERN_DVBS_DTV_FrontendSetFreeze(void)6371 MS_BOOL INTERN_DVBS_DTV_FrontendSetFreeze(void)
6372 {
6373 MS_BOOL bRet= TRUE;
6374 MS_U16 u16Address;
6375 MS_U16 u16Data=0;
6376
6377 u16Address = (FRONTEND_FREEZE_DUMP>>16)&0xffff;
6378 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6379 u16Data|=(FRONTEND_FREEZE_DUMP&0xffff);
6380 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6381
6382 return bRet;
6383 }
6384
INTERN_DVBS_DTV_FrontendUnFreeze(void)6385 MS_BOOL INTERN_DVBS_DTV_FrontendUnFreeze(void)
6386 {
6387 MS_BOOL bRet= TRUE;
6388 MS_U16 u16Address;
6389 MS_U16 u16Data=0;
6390
6391 u16Address = (FRONTEND_FREEZE_DUMP>>16)&0xffff;
6392 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6393 u16Data&=~(FRONTEND_FREEZE_DUMP&0xffff);
6394 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6395
6396 return bRet;
6397 }
6398
6399 //Inner Freeze
INTERN_DVBS_DTV_InnerSetFreeze(void)6400 MS_BOOL INTERN_DVBS_DTV_InnerSetFreeze(void)
6401 {
6402 MS_BOOL bRet= TRUE;
6403 MS_U16 u16Address;
6404 MS_U16 u16Data=0;
6405
6406 u16Address = (INNER_FREEZE_DUMP>>16)&0xffff;
6407 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6408 u16Data|=(INNER_FREEZE_DUMP&0xffff);
6409 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6410
6411 return bRet;
6412 }
6413
INTERN_DVBS_DTV_InnerUnFreeze(void)6414 MS_BOOL INTERN_DVBS_DTV_InnerUnFreeze(void)
6415 {
6416 MS_BOOL bRet= TRUE;
6417 MS_U16 u16Address;
6418 MS_U16 u16Data=0;
6419
6420 u16Address = (INNER_FREEZE_DUMP>>16)&0xffff;
6421 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6422 u16Data&=~(INNER_FREEZE_DUMP&0xffff);
6423 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6424
6425 return bRet;
6426 }
6427 //------------------------------------------------------------------
6428 // END R/W Function
6429 //------------------------------------------------------------------
6430
6431
6432 /***********************************************************************************
6433 Subject: read register
6434 Function: MDrv_1210_IIC_Bypass_Mode
6435 Parmeter:
6436 Return:
6437 Remark:
6438 ************************************************************************************/
6439 //void MDrv_1210_IIC_Bypass_Mode(MS_BOOL enable)
6440 //{
6441 // UNUSED(enable);
6442 // if (enable)
6443 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x10); // IIC by-pass mode on
6444 // else
6445 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x00); // IIC by-pass mode off
6446 //}
6447
6448