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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102 //0312
103
104 #define _INTERN_DVBS_C_
105 #ifdef MSOS_TYPE_LINUX
106 #include <math.h>
107 #endif
108 #include "ULog.h"
109 #include "MsCommon.h"
110 #include "MsIRQ.h"
111 #include "MsOS.h"
112 //#include "apiPWS.h"
113
114 #include "MsTypes.h"
115 #include "drvBDMA.h"
116 //#include "drvIIC.h"
117 //#include "msAPI_Tuner.h"
118 //#include "msAPI_MIU.h"
119 //#include "BinInfo.h"
120 //#include "halVif.h"
121 #include "drvDMD_INTERN_DVBS.h"
122 #include "halDMD_INTERN_DVBS.h"
123 #include "halDMD_INTERN_common.h"
124
125 #include "drvMMIO.h"
126 //#include "TDAG4D01A_SSI_DVBT.c"
127 #include "drvDMD_VD_MBX.h"
128 //-----------------------------------------------------------------------
129 #define BIN_ID_INTERN_DVBS_DEMOD BIN_ID_INTERN_DVBS
130
131 //For DVBS
132 //#define DVBT2FEC_REG_BASE 0x3300
133 #define DVBS2OPPRO_REG_BASE 0x3E00
134 #define TOP_REG_BASE 0x2000 //DMDTOP
135 #define REG_BACKEND 0x1F00//_REG_BACKEND
136 #define DVBSFEC_REG_BASE 0x3F00
137 #define DVBS2FEC_REG_BASE 0x3300
138 #define DVBS2_REG_BASE 0x3A00
139 #define DVBS2_INNER_REG_BASE 0x3B00
140 #define DVBS2_INNER_EXT_REG_BASE 0x3C00
141 #define DVBS2_INNER_EXT2_REG_BASE 0x3D00
142 //#define DVBSTFEC_REG_BASE 0x2300 //DVBTFEC
143 #define FRONTEND_REG_BASE 0x2800
144 #define FRONTENDEXT_REG_BASE 0x2900
145 #define FRONTENDEXT2_REG_BASE 0x2A00
146 #define DMDANA_REG_BASE 0x2E00 //DMDDTOP//reg_dmdana.xls
147 #define DVBTM_REG_BASE 0x3400
148
149 #define SAMPLING_RATE_FS (144000)//(108000)//(96000)
150 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000)
151 #define INTERN_DVBS_TUNER_WAIT_TIMEOUT (50)
152
153 //#define DVBS2_Function (1)
154 //#define MSB131X_ADCPLL_IQ_SWAP 0
155 //#define INTERN_DVBS_TS_DATA_SWAP 0
156
157 #define MS_DEBUG //enable debug dump
158
159 #ifdef MS_DEBUG
160 #define DBG_INTERN_DVBS(x) x
161 #define DBG_GET_SIGNAL_DVBS(x) x
162 #define DBG_INTERN_DVBS_TIME(x) x
163 #define DBG_INTERN_DVBS_LOCK(x) x
164 #define INTERN_DVBS_INTERNAL_DEBUG 1
165 #else
166 #define DBG_INTERN_DVBS(x) //x
167 #define DBG_GET_SIGNAL_DVBS(x) //x
168 #define DBG_INTERN_DVBS_TIME(x) //x
169 #define DBG_INTERN_DVBS_LOCK(x) //x
170 #define INTERN_DVBS_INTERNAL_DEBUG 0
171 #endif
172 //----------------------------------------------------------
173 #define DBG_DUMP_LOAD_DSP_TIME 0
174
175
176 #define SIGNAL_LEVEL_OFFSET 0.00f
177 #define TAKEOVERPOINT -60.0f
178 #define TAKEOVERRANGE 0.5f
179 #define LOG10_OFFSET -0.21f
180 #define INTERN_DVBS_USE_SAR_3_ENABLE 0
181 //extern MS_U32 msAPI_Timer_GetTime0(void);
182 //#define INTERN_DVBS_GET_TIME msAPI_Timer_GetTime0()
183
184
185 //Debug Info
186 //Lock/Done Flag
187 #define AGC_LOCK 0x28170100
188 #define DAGC0_LOCK 0x283B0001
189 #define DAGC1_LOCK 0x285B0001
190 #define DAGC2_LOCK 0x28620001 //ACIDAGC 1 2
191 #define DAGC3_LOCK 0x286E0001
192 #define DCR_LOCK 0x28220100
193 #define COARSE_SYMBOL_RATE_DONE 0x2A200001 //CSRD 1 2
194 #define FINE_SYMBOL_RATE_DONE 0x2A200008 //FSRD 1 2
195 #define POWER4CFO_DONE 0x29280100 //POWER4CFO 1 2
196 //#define CLOSE_COARSE_CFO_LOCK 0x244E0001
197 #define TR_LOCK 0x3B0E0100 //TR 1 2
198 #define PR_LOCK 0x3B401000
199 #define FRAME_SYNC_ACQUIRE 0x3B300001
200 #define EQ_LOCK 0x3B5A1000
201 #define P_SYNC_LOCK 0x22160002
202 #define IN_SYNC_LOCK 0x3F0D8000
203
204 //AGC / DAGC
205 #define DEBUG_SEL_IF_AGC_GAIN 0x28260003
206 #define DEBUG_SEL_AGC_ERR 0x28260004
207 #define DEBUG_OUT_AGC 0x2828
208
209 #define DEBUG_SEL_DAGC0_GAIN 0x28E80003
210 #define DEBUG_SEL_DAGC0_ERR 0x28E80001
211 #define DEBUG_SEL_DAGC0_PEAK_MEAN 0x28E80005
212 #define DEBUG_OUT_DAGC0 0x2878
213
214 #define DEBUG_SEL_DAGC1_GAIN 0x28E80003//???
215 #define DEBUG_SEL_DAGC1_ERR 0x28E80001
216 #define DEBUG_SEL_DAGC1_PEAK_MEAN 0x28E80005
217 #define DEBUG_OUT_DAGC1 0x28B8
218
219 #define DEBUG_SEL_DAGC2_GAIN 0x28E80003
220 #define DEBUG_SEL_DAGC2_ERR 0x28E80001
221 #define DEBUG_SEL_DAGC2_PEAK_MEAN 0x28E80005
222 #define DEBUG_OUT_DAGC2 0x28C4
223
224 #define DEBUG_SEL_DAGC3_GAIN 0x29DA0003
225 #define DEBUG_SEL_DAGC3_ERR 0x29DA0001
226 #define DEBUG_SEL_DAGC3_PEAK_MEAN 0x29DA0005
227 #define DEBUG_OUT_DAGC3 0x29DC
228
229 #define INNER_DEBUG_SEL_TR 0x24080D00 //TR
230 #define DEBUG_SEL_TR_SFO_CONVERGE 0x24080B00
231 #define DEBUG_SEL_TR_INPUT 0x24080F00
232
233 #define FRONTEND_FREEZE_DUMP 0x27028000
234 #define INNER_FREEZE_DUMP 0x24080010
235
236 #define DCR_OFFSET 0x2740
237 #define INNER_DEBUG_SEL 0x2408
238 #define INNEREXT_FINEFE_DBG_OUT0 0x2550
239 #define INNEREXT_FINEFE_DBG_OUT2 0x2552
240 #define INNEREXT_FINEFE_KI_FF0 0x2556
241 #define INNEREXT_FINEFE_KI_FF2 0x2558
242 #define INNEREXT_FINEFE_KI_FF4 0x255A
243 #define INNER_PR_DEBUG_OUT0 0x2486
244 #define INNER_PR_DEBUG_OUT2 0x2488
245
246 #define IIS_COUNT0 0x2746
247 #define IIS_COUNT2 0x2748
248 #define IQB_PHASE 0x2766
249 #define IQB_GAIN 0x2768
250 #define TR_INDICATOR_FF0 0x2454
251 #define TR_INDICATOR_FF2 0x2456
252 #define INNER_TR_LOPF_VALUE_DEBUG0 0x2444
253 #define INNER_TR_LOPF_VALUE_DEBUG2 0x2446
254 #define INNER_TR_LOPF_VALUE_DEBUG4 0x2448
255 //------------------------------------------------------------
256 //Init Mailbox parameter.
257 #define INTERN_DVBS_TS_SERIAL_INVERSION 0
258 //For Parameter Init Setting
259 #define A_S2_ZIF_EN 0x01 //[0]
260 #define A_S2_RF_AGC_EN 0x00 //[0]
261 #define A_S2_DCR_EN 0x00 //[0] 0=Auto :1=Force
262 #define A_S2_IQB_EN 0x01 //[2]
263 #define A_S2_IIS_EN 0x00 //[0]
264 #define A_S2_CCI_EN 0x00 //[0] 0:1=Enable
265 #define A_S2_FORCE_ACI_SELECT 0xFF //[3:0] 0xFF=OFF(internal default)
266 #define A_S2_IQ_SWAP 0x01 //[0]
267 #define A_S2_AGC_REF_EXT_0 0x00 //[7:0] //0x00 0x90
268 #define A_S2_AGC_REF_EXT_1 0x02 //[11:8] //0x02 0x07
269 #define A_S2_AGC_K 0x07 //[15:12]
270 #define A_S2_ADCI_GAIN 0x0F //[4:0]
271 #define A_S2_ADCQ_GAIN 0x0F //[12:8]
272 #define A_S2_SRD_SIG_SRCH_RNG 0x6A //[7:0]
273 #define A_S2_SRD_DC_EXC_RNG 0x16 //[7:0]
274 //FRONTENDEXT_SRD_FRC_CFO
275 #define A_S2_FORCE_CFO_0 0x00 //[7:0]
276 #define A_S2_FORCE_CFO_1 0x00 //[11:8]
277 #define A_S2_DECIMATION_NUM 0x00 //[3:0] 00=(Internal Default)
278 #define A_S2_PSD_SMTH_TAP 0x29 //[6:0] Bit7 no define.
279 //CCI Parameter
280 //Set_Tuner_BW=(((U16)REG_BASE[DIG_SWUSE1FH]<<8)|REG_BASE[DIG_SWUSE1FL]);
281 #define A_S2_CCI_FREQN_0_L 0x00 //[7:0]
282 #define A_S2_CCI_FREQN_0_H 0x00 //[11:8]
283 #define A_S2_CCI_FREQN_1_L 0x00 //[7:0]
284 #define A_S2_CCI_FREQN_1_H 0x00 //[11:8]
285 #define A_S2_CCI_FREQN_2_L 0x00 //[7:0]
286 #define A_S2_CCI_FREQN_2_H 0x00 //[11:8]
287 //Inner TR Parameter
288 #define A_S2_TR_LOPF_KP 0x00 //[4:0] 00=(Internal Default)
289 #define A_S2_TR_LOPF_KI 0x00 //[4:0] 00=(Internal Default)
290 //Inner FineFE Parameter
291 #define A_S2_FINEFE_KI_SWITCH_0 0x00 //[15:12] 00=(Internal Default)
292 #define A_S2_FINEFE_KI_SWITCH_1 0x00 //[3:0] 00=(Internal Default)
293 #define A_S2_FINEFE_KI_SWITCH_2 0x00 //[7:4] 00=(Internal Default)
294 #define A_S2_FINEFE_KI_SWITCH_3 0x00 //[11:8] 00=(Internal Default)
295 #define A_S2_FINEFE_KI_SWITCH_4 0x00 //[15:12] 00=(Internal Default)
296 //Inner PR KP Parameter
297 #define A_S2_PR_KP_SWITCH_0 0x00 //[11:8] 00=(Internal Default)
298 #define A_S2_PR_KP_SWITCH_1 0x00 //[15:12] 00=(Internal Default)
299 #define A_S2_PR_KP_SWITCH_2 0x00 //[3:0] 00=(Internal Default)
300 #define A_S2_PR_KP_SWITCH_3 0x00 //[7:4] 00=(Internal Default)
301 #define A_S2_PR_KP_SWITCH_4 0x00 //[11:8] 00=(Internal Default)
302 //Inner FS Parameter
303 #define A_S2_FS_GAMMA 0x10 //[7:0]
304 #define A_S2_FS_ALPHA0 0x10 //[7:0]
305 #define A_S2_FS_ALPHA1 0x10 //[7:0]
306 #define A_S2_FS_ALPHA2 0x10 //[7:0]
307 #define A_S2_FS_ALPHA3 0x10 //[7:0]
308
309 #define A_S2_FS_H_MODE_SEL 0x01 //[0]
310 #define A_S2_FS_OBSWIN 0x08 //[12:8]
311 #define A_S2_FS_PEAK_DET_TH_L 0x00 //[7:0]
312 #define A_S2_FS_PEAK_DET_TH_H 0x01 //[15:8]
313 #define A_S2_FS_CONFIRM_NUM 0x01 //[3:0]
314 //Inner EQ Parameter
315 #define A_S2_EQ_MU_FFE_DA 0x00 //[3:0] 00=(Internal Default)
316 #define A_S2_EQ_MU_FFE_DD 0x00 //[7:4] 00=(Internal Default)
317 #define A_S2_EQ_ALPHA_SNR_DA 0x00 //[7:4] 00=(Internal Default)
318 #define A_S2_EQ_ALPHA_SNR_DD 0x00 //[11:8] 00=(Internal Default)
319 //Outer FEC Parameter
320 #define A_S2_FEC_ALFA 0x00 //[12:8]
321 #define A_S2_FEC_BETA 0x01 //[7:4]
322 #define A_S2_FEC_SCALING_LLR 0x00 //[7:0] 00=(Internal Default)
323 //TS Parameter
324 #if INTERN_DVBS_TS_SERIAL_INVERSION
325 #define A_S2_TS_SERIAL 0x01 //[0]
326 #else
327 #define A_S2_TS_SERIAL 0x00 //[0]
328 #endif
329 #define A_S2_TS_CLK_RATE 0x00
330 #define A_S2_TS_OUT_INV 0x00 //[5]
331 #define A_S2_TS_DATA_SWAP 0x00 //[5]
332 //Rev Parameter
333
334 #define A_S2_FW_VERSION_L 0x00 //From FW
335 #define A_S2_FW_VERSION_H 0x00 //From FW
336 #define A_S2_CHIP_VERSION 0x01
337 #define A_S2_FS_L 0x00
338 #define A_S2_FS_H 0x00
339 #define A_S2_MANUAL_TUNE_SYMBOLRATE_L 0x20
340 #define A_S2_MANUAL_TUNE_SYMBOLRATE_H 0x4E
341
342 MS_U8 INTERN_DVBS_DSPREG[] =
343 {
344 A_S2_ZIF_EN, A_S2_RF_AGC_EN, A_S2_DCR_EN, A_S2_IQB_EN, A_S2_IIS_EN, A_S2_CCI_EN, A_S2_FORCE_ACI_SELECT, A_S2_IQ_SWAP, // 00H ~ 07H
345 A_S2_AGC_REF_EXT_0, A_S2_AGC_REF_EXT_1, A_S2_AGC_K, A_S2_ADCI_GAIN, A_S2_ADCQ_GAIN, A_S2_SRD_SIG_SRCH_RNG, A_S2_SRD_DC_EXC_RNG, A_S2_FORCE_CFO_0, // 08H ~ 0FH
346 A_S2_FORCE_CFO_1, A_S2_DECIMATION_NUM, A_S2_PSD_SMTH_TAP, A_S2_CCI_FREQN_0_L, A_S2_CCI_FREQN_0_H, A_S2_CCI_FREQN_1_L, A_S2_CCI_FREQN_1_H, A_S2_CCI_FREQN_2_L, // 10H ~ 17H
347 A_S2_CCI_FREQN_2_H, A_S2_TR_LOPF_KP, A_S2_TR_LOPF_KI, A_S2_FINEFE_KI_SWITCH_0, A_S2_FINEFE_KI_SWITCH_1, A_S2_FINEFE_KI_SWITCH_2, A_S2_FINEFE_KI_SWITCH_3, A_S2_FINEFE_KI_SWITCH_4, // 18H ~ 1FH
348 A_S2_PR_KP_SWITCH_0, A_S2_PR_KP_SWITCH_1, A_S2_PR_KP_SWITCH_2, A_S2_PR_KP_SWITCH_3, A_S2_PR_KP_SWITCH_4, A_S2_FS_GAMMA, A_S2_FS_ALPHA0, A_S2_FS_ALPHA1, // 20H ~ 27H
349 A_S2_FS_ALPHA2, A_S2_FS_ALPHA3, A_S2_FS_H_MODE_SEL, A_S2_FS_OBSWIN, A_S2_FS_PEAK_DET_TH_L, A_S2_FS_PEAK_DET_TH_H, A_S2_FS_CONFIRM_NUM, A_S2_EQ_MU_FFE_DA, // 28h ~ 2FH
350 A_S2_EQ_MU_FFE_DD, A_S2_EQ_ALPHA_SNR_DA, A_S2_EQ_ALPHA_SNR_DD, A_S2_FEC_ALFA, A_S2_FEC_BETA, A_S2_FEC_SCALING_LLR, A_S2_TS_SERIAL, A_S2_TS_CLK_RATE, // 30H ~ 37H
351 A_S2_TS_OUT_INV, A_S2_TS_DATA_SWAP, A_S2_FW_VERSION_L, A_S2_FW_VERSION_H, A_S2_CHIP_VERSION, A_S2_FS_L, A_S2_FS_H, A_S2_MANUAL_TUNE_SYMBOLRATE_L, // 38H ~ 3CH
352 A_S2_MANUAL_TUNE_SYMBOLRATE_H,
353 };
354
355 /****************************************************************
356 *Local Variables *
357 ****************************************************************/
358
359 /*
360 static MS_U16 _u16SignalLevel[185][2]=
361 {//AV2028 SR=22M, 2/3 CN=5.9
362 {32100, 920},{32200, 915},{32350, 910},{32390, 905},{32480, 900},{32550, 895},{32620, 890},{32680, 885},{32750, 880},{32830, 875},
363 {32930, 870},{33010, 865},{33100, 860},{33200, 855},{33310, 850},{33410, 845},{33520, 840},{33640, 835},{33770, 830},{33900, 825},
364 {34030, 820},{34150, 815},{34290, 810},{34390, 805},{34490, 800},{34580, 795},{34700, 790},{34800, 785},{34880, 780},{34940, 775},
365 {35030, 770},{35130, 765},{35180, 760},{35260, 755},{35310, 750},{35340, 745},{35380, 740},{35400, 735},{35450, 730},{35550, 725},
366 {35620, 720},{35700, 715},{35800, 710},{35890, 705},{36000, 700},{36120, 695},{36180, 690},{36280, 685},{36400, 680},{36570, 675},
367 {36730, 670},{36910, 665},{37060, 660},{37100, 655},{37260, 650},{37340, 645},{37410, 640},{37580, 635},{37670, 630},{37700, 625},
368 {37750, 620},{37800, 615},{37860, 610},{37980, 605},{38050, 600},{38170, 595},{38370, 590},{38540, 585},{38710, 580},{38870, 575},
369 {39020, 570},{39070, 565},{39100, 560},{39180, 555},{39280, 550},{39460, 545},{39510, 540},{39600, 535},{39620, 530},{39680, 525},
370 {39720, 520},{39830, 515},{39880, 510},{39930, 505},{39960, 500},{40000, 495},{40200, 490},{40360, 485},{40540, 480},{40730, 475},
371 {40880, 470},{41020, 465},{41150, 460},{41280, 455},{41410, 450},{41520, 445},{41620, 440},{41730, 435},{41840, 430},{41930, 425},
372 {42010, 420},{42100, 415},{42180, 410},{42260, 405},{42350, 400},{42440, 395},{42520, 390},{42580, 385},{42660, 380},{42730, 375},
373 {42800, 370},{42870, 365},{42940, 360},{43000, 355},{43060, 350},{43130, 345},{43180, 340},{43250, 335},{43310, 330},{43370, 325},
374 {43420, 320},{43460, 315},{43520, 310},{43570, 305},{43620, 300},{43660, 295},{43710, 290},{43750, 285},{43810, 280},{43860, 275},
375 {43910, 270},{43940, 265},{43990, 260},{44020, 255},{44060, 250},{44110, 245},{44140, 240},{44190, 235},{44230, 230},{44270, 225},
376 {44320, 220},{44370, 215},{44400, 210},{44450, 205},{44490, 200},{44530, 195},{44590, 190},{44630, 185},{44660, 180},{44720, 175},
377 {44750, 170},{44790, 165},{44830, 160},{44880, 155},{44910, 150},{44960, 145},{45000, 140},{45030, 135},{45070, 130},{45100, 125},
378 {45130, 120},{45160, 115},{45200, 110},{45240, 105},{45270, 100},{45300, 95},{45330, 90},{45360, 85},{45400, 80},{45430, 75},
379 {45460, 70},{45490, 65},{45530, 60},{45560, 55},{45590, 50},{45630, 45},{45670, 40},{45690, 35},{45740, 30},{45760, 25},
380 {45800, 20},{45830, 15},{45860, 10},{45880, 5},{45920, 0}
381 };
382 */
383 MS_U8 u8DemodLockFlag;
384 MS_U8 modulation_order;
385 MS_BOOL _bDemodType=FALSE;//DVBS:FALSE ; S2:TRUE
386 //static MS_BOOL TPSLock = 0;
387 static MS_U32 u32ChkScanTimeStartDVBS = 0;
388 MS_U8 g_dvbs_lock = 0;
389 //static float intern_dvb_s_qam_ref[] = {3.0, 0.0, 0.0, 0.0, 0.0, 80.0}; //16q,32q,64q,128q,256q, and others
390 static MS_U8 _u8_DVBS2_CurrentCodeRate;
391 static MS_U8 _u8ToneBurstFlag=0;
392
393 //static float _fPostBer=0;
394 //static float _f_DVBS_CurrentSNR=0;
395 static MS_U16 _u16BlindScanStartFreq=0;
396 static MS_U16 _u16BlindScanEndFreq=0;
397 static MS_U16 _u16TunerCenterFreq=0;
398 MS_U16 _u16ChannelInfoIndex=0;
399 //Debug Only+
400 static MS_U16 _u16NextCenterFreq=0;
401 MS_U16 _u16LockedSymbolRate=0;
402 MS_U16 _u16LockedCenterFreq=0;
403 static MS_U16 _u16PreLockedHB=0;
404 static MS_U16 _u16PreLockedLB=0;
405 static MS_U16 _u16CurrentSymbolRate=0;
406 MS_S16 _s16CurrentCFO=0;
407 static MS_U16 _u16CurrentStepSize=0;
408 //Debug Only-
409 MS_U16 _u16ChannelInfoArray[2][1000];
410
411 //static MS_U32 _u32CurrentSR=0;
412 static MS_BOOL _bSerialTS=FALSE;
413 static MS_BOOL _bTSDataSwap=FALSE;
414
415 //Global Variables
416 S_CMDPKTREG gsCmdPacketDVBS;
417 //MS_U8 gCalIdacCh0, gCalIdacCh1;
418 static MS_BOOL bDMD_DVBS_NoChannelDetectedWithRFPower = FALSE;
419 static MS_U32 u32DMD_DVBS_NoChannelTimeAccWithRFPower = 0;
420 extern MS_U32 u32DMD_DVBS2_DJB_START_ADDR;
421 #ifdef INTERN_DVBS_LOAD_FW_FROM_CODE_MEMORY
422 MS_U8 INTERN_DVBS_table[] =
423 {
424 #include "fwDMD_INTERN_DVBS.dat"
425 };
426
427 #endif
428
429 MS_BOOL INTERN_DVBS_Show_Demod_Version(void);
430 MS_BOOL INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE *pQAMMode);
431 MS_BOOL INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE *pDemodType);
432 MS_BOOL INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE *pCodeRate);
433 MS_BOOL INTERN_DVBS_GetCurrentSymbolRate(MS_U32 *u32SymbolRate);
434 MS_BOOL INTERN_DVBS_GetCurrentSymbolRateOffset(MS_U16 *pData);
435
436 #if (INTERN_DVBS_INTERNAL_DEBUG)
437 void INTERN_DVBS_info(void);
438 MS_BOOL INTERN_DVBS_Show_AGC_Info(void);
439 #endif
440
441 //------------------------------------------------------------------
442 // System Info Function
443 //------------------------------------------------------------------
444 //=====================================================================================
INTERN_DVBS_DSPReg_Init(const MS_U8 * u8DVBS_DSPReg,MS_U8 u8Size)445 MS_U16 INTERN_DVBS_DSPReg_Init(const MS_U8 *u8DVBS_DSPReg, MS_U8 u8Size)
446 {
447 #if 0
448 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
449 #endif
450 MS_U8 status = true;
451 #if 0
452 MS_U16 u16DspAddr = 0;
453 #endif
454 DBG_INTERN_DVBS(printf("INTERN_DVBS_DSPReg_Init\n"));
455
456 #if 0//def MS_DEBUG
457 {
458 MS_U8 u8buffer[256];
459 printf("INTERN_DVBS_DSPReg_Init Reset\n");
460 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
461 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, 0);
462
463 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
464 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
465 printf("INTERN_DVBS_DSPReg_Init ReadBack, should be all 0\n");
466 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
467 printf("%x ", u8buffer[idx]);
468 printf("\n");
469
470 printf("INTERN_DVBS_DSPReg_Init Value\n");
471 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
472 printf("%x ", INTERN_DVBS_DSPREG[idx]);
473 printf("\n");
474 }
475 #endif
476
477 //for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
478 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBS_DSPREG[idx]);
479
480 // readback to confirm.
481 // ~read this to check mailbox initial values
482 #if 0
483 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
484 {
485 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &u8RegRead);
486 if (u8RegRead != INTERN_DVBS_DSPREG[idx])
487 {
488 DBG_INTERN_DVBS(printf("[Error]INTERN_DVBS_DSPReg_Init, idx=%d, drv_val=0x%x, firmware_val=0x%x\n",idx,INTERN_DVBS_DSPREG[idx],u8RegRead));
489 }
490 }
491 #endif
492 #if 0
493 if (u8DVBS_DSPReg != NULL)
494 {
495 if (1 == u8DVBS_DSPReg[0])
496 {
497 u8DVBS_DSPReg+=2;
498 for (idx = 0; idx<u8Size; idx++)
499 {
500 u16DspAddr = *u8DVBS_DSPReg;
501 u8DVBS_DSPReg++;
502 u16DspAddr = (u16DspAddr) + ((*u8DVBS_DSPReg)<<8);
503 u8DVBS_DSPReg++;
504 u8Mask = *u8DVBS_DSPReg;
505 u8DVBS_DSPReg++;
506 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
507 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBS_DSPReg) & (u8Mask));
508 u8DVBS_DSPReg++;
509 DBG_INTERN_DVBS(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
510 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
511 }
512 }
513 else
514 {
515 DBG_INTERN_DVBS(printf("FATAL: parameter version incorrect\n"));
516 }
517 }
518 #endif
519 #if 0//def MS_DEBUG
520 {
521 MS_U8 u8buffer[256];
522 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
523 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
524 printf("INTERN_DVBC_DSPReg_Init ReadBack\n");
525 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
526 printf("%x ", u8buffer[idx]);
527 printf("\n");
528 }
529 #endif
530
531 #if 0//def MS_DEBUG
532 {
533 MS_U8 u8buffer[256];
534 for (idx = 0; idx<128; idx++)
535 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2380+idx, &(u8buffer[idx]));
536 printf("INTERN_DVBS_DSPReg_Init ReadReg 0x2000~0x207F\n");
537 for (idx = 0; idx<128; idx++)
538 {
539 printf("%x ", u8buffer[idx]);
540 if ((idx & 0xF) == 0xF) printf("\n");
541 }
542 printf("\n");
543 }
544 #endif
545 return status;
546 }
547
548 /***********************************************************************************
549 Subject: Command Packet Interface
550 Function: INTERN_DVBS_Cmd_Packet_Send
551 Parmeter:
552 Return: MS_BOOL
553 Remark:
554 ************************************************************************************/
INTERN_DVBS_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)555 MS_BOOL INTERN_DVBS_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
556 {
557 MS_U8 status = true, indx;
558 MS_U8 reg_val, timeout = 0;
559 return true;
560
561 // ==== Command Phase ===================
562 DBG_INTERN_DVBS(ULOGD("DEMOD","--->INTERN_DVBS (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
563 pCmdPacket->param[0],pCmdPacket->param[1],
564 pCmdPacket->param[2],pCmdPacket->param[3],
565 pCmdPacket->param[4],pCmdPacket->param[5] ));
566
567 // wait _BIT_END clear
568 do
569 {
570 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
571 if((reg_val & _BIT_END) != _BIT_END)
572 {
573 break;
574 }
575 MsOS_DelayTask(5);
576 if (timeout > 200)
577 {
578 DBG_INTERN_DVBS(ULOGD("DEMOD","---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n"));
579 return false;
580 }
581 timeout++;
582 } while (1);
583
584 // set cmd_3:0 and _BIT_START
585 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
586 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
587 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
588
589
590 //DBG_INTERN_DVBS(printf("demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
591 // wait _BIT_START clear
592 do
593 {
594 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
595 if((reg_val & _BIT_START) != _BIT_START)
596 {
597 break;
598 }
599 MsOS_DelayTask(10);
600 if (timeout > 200)
601 {
602 DBG_INTERN_DVBS(ULOGD("DEMOD","---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n"));
603 return false;
604 }
605 timeout++;
606 } while (1);
607
608 // ==== Data Phase ======================
609
610 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
611
612 for (indx = 0; indx < param_cnt; indx++)
613 {
614 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
615 //DBG_INTERN_DVBS(printf("demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
616
617 // set param[indx] and _BIT_DRQ
618 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
619 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
620 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
621
622 // wait _BIT_DRQ clear
623 do
624 {
625 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
626 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
627 {
628 break;
629 }
630 MsOS_DelayTask(5);
631 if (timeout > 200)
632 {
633 DBG_INTERN_DVBS(ULOGD("DEMOD","---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n"));
634 return false;
635 }
636 timeout++;
637 } while (1);
638 }
639
640 // ==== End Phase =======================
641
642 // set _BIT_END to finish command
643 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
644 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
645
646 return status;
647 }
648
649 /***********************************************************************************
650 Subject: Command Packet Interface
651 Function: INTERN_DVBS_Cmd_Packet_Exe_Check
652 Parmeter:
653 Return: MS_BOOL
654 Remark:
655 ************************************************************************************/
INTERN_DVBS_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)656 MS_BOOL INTERN_DVBS_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
657 {
658 return TRUE;
659 }
660
661 /***********************************************************************************
662 Subject: SoftStop
663 Function: INTERN_DVBS_SoftStop
664 Parmeter:
665 Return: MS_BOOL
666 Remark:
667 ************************************************************************************/
INTERN_DVBS_SoftStop(void)668 MS_BOOL INTERN_DVBS_SoftStop ( void )
669 {
670 #if 1
671 MS_U16 u16WaitCnt=0;
672
673 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
674 {
675 DBG_INTERN_DVBS(ULOGD("DEMOD",">> MB Busy!\n"));
676 return FALSE;
677 }
678
679 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
680
681 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
682 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
683
684 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
685 {
686 if (u16WaitCnt++ >= 0xFFF)// 0xFF)
687 {
688 DBG_INTERN_DVBS(ULOGD("DEMOD",">> DVBT SoftStop Fail!\n"));
689 return FALSE;
690 }
691 }
692
693 //HAL_DMD_RIU_WriteByte(0x103460, 0x01); // reset VD_MCU
694 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
695 #endif
696 return TRUE;
697 }
698
699 /***********************************************************************************
700 Subject: Reset
701 Function: INTERN_DVBC_Reset
702 Parmeter:
703 Return: MS_BOOL
704 Remark:
705 ************************************************************************************/
706 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
707
INTERN_DVBS_Reset(void)708 MS_BOOL INTERN_DVBS_Reset ( void )// no midify
709 {
710 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_reset\n"));
711
712 DBG_INTERN_DVBS_TIME(ULOGD("DEMOD","INTERN_DVBS_Reset, t = %d\n",(int)MsOS_GetSystemTime()));
713
714 //INTERN_DVBS_SoftStop();
715
716
717 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
718
719 MsOS_DelayTask(1);
720 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
721
722 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
723 MsOS_DelayTask(5);
724
725 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
726 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
727
728 u32ChkScanTimeStartDVBS = MsOS_GetSystemTime();
729 g_dvbs_lock = 0;
730
731 return TRUE;
732 }
INTERN_DVBS_PowerSaving(void)733 MS_BOOL INTERN_DVBS_PowerSaving ( void )
734 {
735 MS_U8 i;
736
737 //---P2=0---/;
738 for( i = 0; i < 231; i++){
739 MDrv_SYS_DMD_VD_MBX_WriteReg(0x350A + i, 0x11);}
740 // `M3_RIU_W((`RIUBASE_DMD_CLKGEN>>1)+7'h40, 2'b01, 16'h0000);
741 MDrv_SYS_DMD_VD_MBX_WriteReg(0x3580, 0x00);
742
743 //---P2=1---/;
744 for( i = 0; i < 146; i++){
745 MDrv_SYS_DMD_VD_MBX_WriteReg(0xA202 + i, 0x11);}
746 // `M3_RIU_W((`RIUBASE_DMD_CLKGEN_EXT>>1)+7'h14, 2'b01, 16'h0003);
747 MDrv_SYS_DMD_VD_MBX_WriteReg(0xA228, 0x03);
748
749 // ================================================================
750 // DEMOD_1 CLOCK GATED
751 // ================================================================
752 //---P2=0---/;
753 for( i = 0; i <= 177; i++){
754 MDrv_SYS_DMD_VD_MBX_WriteReg(0x3635+ i, 0x11);}
755 // `M3_RIU_W((`RIUBASE_DMD_CLKGEN_1>>1)+7'h1b, 2'b01, 16'h000f);
756 MDrv_SYS_DMD_VD_MBX_WriteReg(0x3636, 0x0f);
757
758
759 // ================================================================
760 // SRAM Power Down
761 // ================================================================
762 // [ 0]reg_force_allsram_on = 1'b0
763 // [ 1]reg_force_allsram_on_demod_1 = 1'b0
764 // [ 2] = 1'b0
765 // [ 3]reg_demod_1_sram_sd_en = 1'b0
766 // [ 4]reg_manhattan_sram_share_sram_sd_en = 1'b0
767 // [ 5]reg_mulan_sram_share_sram_sd_en = 1'b0
768 // [ 6]reg_dvb_frontend_sram_sd_en = 1'b0
769 // [ 7]reg_dtmb_sram_sd_en = 1'b0
770 // [ 8]reg_dvbt_sram_sd_en = 1'b0
771 // [ 9]reg_atsc_sram_sd_en = 1'b0
772 // [10]reg_vif_sram_sd_en = 1'b0
773 // [11]reg_backend_sram_sd_en = 1'b0
774 // [12]reg_adcdma_sram_sd_en = 1'b0
775 // [13]reg_isdbt_sram_sd_en = 1'b0
776 // [14]reg_dvbt2_sram_sd_en = 1'b0
777 // [15]reg_dvbs2_sram_sd_en = 1'b0
778 // `M3_RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h48, 2'b11, 16'hfffc);
779 // `M3_RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h48, 2'b11, 16'hfffc);
780 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2091, 0xff);
781 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2090, 0xfc);
782
783 // all controlled by reg_mulan_sram_share_sram_sd_en
784 // reg_sram_pwr_ctrl_sel[15:0]
785 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h70, 2'b11, 16'h0000);
786 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h70, 2'b11, 16'h0000);
787 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e1, 0x00);
788 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e0, 0x00);
789 // reg_sram_pwr_ctrl_sel[31:16]
790 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h71, 2'b11, 16'h0000);
791 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h71, 2'b11, 16'h0000);
792 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e3, 0x00);
793 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e2, 0x00);
794 // reg_sram_pwr_ctrl_sel[47:32]
795 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h72, 2'b11, 16'h0000);
796 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h72, 2'b11, 16'h0000);
797 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e5, 0x00);
798 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e4, 0x00);
799 // reg_sram_pwr_ctrl_sel[63:48]
800 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h73, 2'b11, 16'h0000);
801 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h73, 2'b11, 16'h0000);
802 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e7, 0x00);
803 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e6, 0x00);
804 // reg_sram_pwr_ctrl_sel[79:64]
805 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h74, 2'b11, 16'h0000);
806 // `M3_RIU_W( (`RIUBASE_DMD_TOP_EXT>>1)+7'h74, 2'b11, 16'h0000);
807 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e9, 0x00);
808 MDrv_SYS_DMD_VD_MBX_WriteReg (0xA1e8, 0x00);
809
810 // $display("================================================================");
811 // $display("Reset");
812 // $display("================================================================");
813 // Release DVBT2 & dmd_ana_misc Reset
814 // [0] reg_atsc_on[0]
815 // [1] reg_dvbt_on[1]
816 // [2] reg_vif_on[2]
817 // [3] reg_isdbt_on[3]
818 // [4] reg_atsc_rst[4]
819 // [5] reg_dvbt_rst[5]
820 // [6] reg_vif_rst[6]
821 // [7] reg_get_adc[7]
822 // [8] reg_ce8x_gate[8]
823 // [9] reg_ce_gate[9]
824 // [10] reg_dac_clk_inv[10]
825 // [11] reg_vdmcu_clock_faster[11]
826 // [12] reg_vif_if_agc_sel[12]
827 // [13] reg_dmd_ana_misc_rst[13]
828 // [14] reg_adcd_wmask[14]
829 // [15] reg_sif_only[15]
830 // `M3_RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h01, 2'b11, 16'h2070);
831
832 // Release DTMB Reset & Enable Manhattan frontend Enable
833 // [0] reg_dtmb_on
834 // [1] reg_dtmb_rst
835 // [4] reg_manhattan_frontend_on //No used @ Maserati
836 // [5] reg_manhattan_dvb_srd_sw_rst (1'b1 for DTMB)
837 // `M3_RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h02, 2'b01, 16'h0022);
838
839 // ================================================================
840 // MPLL Power Down
841 // ================================================================
842 // Set MPLL_ADC_DIV_SE
843 // [0] : reg_mpll_adc_clk_cc_en
844 // [1] : reg_adc_clk_pd
845 // [2] : reg_mpll_div2_pd
846 // [3] : reg_mpll_div3_pd
847 // [4] : reg_mpll_div4_pd
848 // [5] : reg_mpll_div8_pd
849 // [6] : reg_mpll_div10_pd
850 // [7] : reg_mpll_div17_pd
851 // [13:8]: reg_mpll_adc_div_sel
852 // `M3_RIU_W((`RIUBASE_DMD_ANA_MISC_M3>>1)+7'h30, 2'b01, 16'h12fe);//Different
853 // `M3_RIU_W((`RIUBASE_DMD_ANA_MISC_M3>>1)+7'h30, 2'b01, 16'h12fe);//Different
854 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2e60, 0xfe);
855
856 // [2:0] : reg_mpll_ictrl set 3'h3
857 // [3] : reg_mpll_in_sel set 1'h0
858 // [4] : reg_mpll_xtal2adc_sel if 1'h1 ADC_CLK=XTAL.
859 // [5] : reg_mpll_xtal2next_pll_sel
860 // [6] : reg_mpll_vco_offset(T8), reg_mpll_adc_clk_cc_mode(T9)
861 // [7] : reg_mpll_pd set 1'b1
862 // [8] : reg_xtal_en set 1'b0
863 // [10:9]: reg_xtal_sel set 2'h3 XTAL strength
864 // [11] : reg_mpll_porst set 1'b1
865 // [12] : reg_mpll_reset set 1'b1
866 // [13] : reg_pd_dmpll_clk XTAL to MPLL clock reference power down
867 // [14] : reg_mpll_pdiv_clk_pd set 1'b0
868 // Set MPLL_RESET=MPLL_PORST=1
869 // `M3_RIU_W((`RIUBASE_DMD_ANA_MISC_M3>>1)+7'h35, 2'b11, 16'h1e83);//Different
870 // `M3_RIU_W((`RIUBASE_DMD_ANA_MISC_M3>>1)+7'h35, 2'b11, 16'h1e83);//Different
871 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2e6b, 0x1e);
872 MDrv_SYS_DMD_VD_MBX_WriteReg (0x2e6a, 0x83);
873
874 return TRUE;
875 }
876 /***********************************************************************************
877 Subject: Exit
878 Function: INTERN_DVBC_Exit
879 Parmeter:
880 Return: MS_BOOL
881 Remark:
882 ************************************************************************************/
INTERN_DVBS_Exit(void)883 MS_BOOL INTERN_DVBS_Exit ( void )
884 {
885 MS_U8 u8Data=0;
886 MS_U8 u8Data_temp=0;
887
888 u8Data_temp=HAL_DMD_RIU_ReadByte(0x101E39);
889 HAL_DMD_RIU_WriteByte(0x101E39, 0);
890
891 u8Data=HAL_DMD_RIU_ReadByte(0x1128C0);
892 u8Data&=~(0x02);
893 HAL_DMD_RIU_WriteByte(0x1128C0, u8Data);//revert IQ Swap status
894
895 HAL_DMD_RIU_WriteByte(0x101E39, u8Data_temp);
896 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_Exit\n"));
897 INTERN_DVBS_SoftStop();
898 INTERN_DVBS_PowerSaving();
899
900 return TRUE;
901 }
902
903 /***********************************************************************************
904 Subject: Load DSP code to chip
905 Function: INTERN_DVBS_LoadDSPCode
906 Parmeter:
907 Return: MS_BOOL
908 Remark:
909 ************************************************************************************/
INTERN_DVBS_LoadDSPCode(void)910 static MS_BOOL INTERN_DVBS_LoadDSPCode(void)
911 {
912 MS_U8 udata = 0x00;
913 MS_U16 i;
914 MS_U16 fail_cnt=0;
915
916 #if (DBG_DUMP_LOAD_DSP_TIME==1)
917 MS_U32 u32Time;
918 #endif
919
920 //MDrv_Sys_DisableWatchDog();
921 /*
922 HAL_DMD_RIU_WriteByte(0x103480, 0x01);//reference GUI//reset
923 HAL_DMD_RIU_WriteByte(0x103481, 0x00);
924 HAL_DMD_RIU_WriteByte(0x103480, 0x00);
925 HAL_DMD_RIU_WriteByte(0x103483, 0x50);
926 HAL_DMD_RIU_WriteByte(0x103483, 0x51);
927 HAL_DMD_RIU_WriteByte(0x103484, 0x00);
928 HAL_DMD_RIU_WriteByte(0x103485, 0x00);
929 */
930 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
931 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
932 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
933 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
934 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
935 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
936
937 //// Load code thru VDMCU_IF ////
938 DBG_INTERN_DVBS(printf(">Load Code.....\n"));
939 for ( i = 0; i < sizeof(INTERN_DVBS_table); i++)
940 {
941 HAL_DMD_RIU_WriteByte(0x10348C, INTERN_DVBS_table[i]);
942 //HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBS_table[i]); // write data to VD MCU 51 code sram
943 }
944
945 //// Content verification ////
946 DBG_INTERN_DVBS(ULOGD("DEMOD",">Verify Code...\n"));
947
948 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
949 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
950
951 for ( i = 0; i < sizeof(INTERN_DVBS_table); i++)
952 {
953 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
954 if (udata != INTERN_DVBS_table[i])
955 {
956 ULOGD("DEMOD",">fail add = 0x%x\n", i);
957 ULOGD("DEMOD",">code = 0x%x\n", INTERN_DVBS_table[i]);
958 ULOGD("DEMOD",">data = 0x%x\n", udata);
959
960 if (fail_cnt > 10)
961 {
962 ULOGD("DEMOD",">DVB-S DSP Loadcode fail!");
963 return false;
964 }
965 fail_cnt++;
966 }
967 }
968
969 #if 0 //use for Kris DJB with VCM
970 //====================================================================
971 // add S2 DRAM bufer start address into fixed location
972 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x30); // sram address low byte; 0x30 is defined in FW
973 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
974
975 //0x30~0x33
976 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBS2_DJB_START_ADDR);
977 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBS2_DJB_START_ADDR >> 8));
978 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBS2_DJB_START_ADDR >> 16));
979 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBS2_DJB_START_ADDR >> 24));
980
981 printf("@@@@@ share dram address = 0x %x \n ",u32DMD_DVBS2_DJB_START_ADDR);
982 //=====================================================================
983 #endif
984
985 /*
986 HAL_DMD_RIU_WriteByte(0x103483, 0x50);
987 HAL_DMD_RIU_WriteByte(0x103483, 0x00);
988 HAL_DMD_RIU_WriteByte(0x103480, 0x01);
989 HAL_DMD_RIU_WriteByte(0x103481, 0x01);
990 HAL_DMD_RIU_WriteByte(0x103480, 0x00);
991 */
992
993 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
994 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
995 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
996 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
997
998
999 DBG_INTERN_DVBS(ULOGD("DEMOD",">DSP Loadcode done."));
1000 #if 0
1001 INTERN_DVBS_Config(6875, 128, 36125, 0,1);
1002 INTERN_DVBS_Active(ENABLE);
1003 while(1);
1004 #endif
1005 //HAL_DMD_RIU_WriteByte(0x101E3E, 0x04); // DVBT = BIT1 -> 0x02
1006
1007 return TRUE;
1008 }
1009
1010 /***********************************************************************************
1011 Subject: DVB-S CLKGEN initialized function
1012 Function: INTERN_DVBS_Power_On_Initialization
1013 Parmeter:
1014 Return: MS_BOOL
1015 Remark:
1016 ************************************************************************************/
INTERN_DVBS_InitClkgen(MS_BOOL bRFAGCTristateEnable)1017 void INTERN_DVBS_InitClkgen(MS_BOOL bRFAGCTristateEnable)
1018 {
1019 MS_U8 u8Temp=0;
1020 // This file is translated by Steven Hung's riu2script.pl
1021
1022 // ==============================================================
1023 // Start demod top initial setting by HK MCU ......
1024 // ==============================================================
1025 // [8] : reg_chiptop_dummy_0 (reg_dmdtop_dmd_sel)
1026 // 1'b0->reg_DMDTOP control by HK_MCU.
1027 // 1'b1->reg_DMDTOP control by DMD_MCU.
1028 // [9] : reg_chiptop_dummy_0 (reg_dmd_ana_regsel)
1029 // 1'b0->reg_DMDANA control by HK_MCU.
1030 // 1'b1->reg_DMDANA control by DMD_MCU.
1031 // select HK MCU ......
1032 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0000);
1033 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0000);
1034 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
1035
1036
1037 // ==============================================================
1038 // Start TOP CLKGEN initial setting ......
1039 // ==============================================================
1040 // CLK_DMDMCU clock setting
1041 // reg_ckg_dmdmcu@0x0f[4:0]
1042 // [0] : disable clock
1043 // [1] : invert clock
1044 // [4:2]:
1045 // 000:170 MHz(MPLL_DIV_BUF)
1046 // 001:160MHz
1047 // 010:144MHz
1048 // 011:123MHz
1049 // 100:108MHz (Kriti:DVBT2)
1050 // 101:mem_clcok
1051 // 110:mem_clock div 2
1052 // 111:select XTAL
1053 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
1054 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
1055 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1056 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1057
1058
1059 // set parallel ts clock
1060 // [11] : reg_ckg_demod_test_in_en = 0
1061 // 0: select internal ADC CLK
1062 // 1: select external test-in clock
1063 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
1064 // 0: select gated clock
1065 // 1: select free-run clock
1066 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
1067 // 0: normal phase to pad
1068 // 1: invert phase to pad
1069 // [8] : reg_ckg_atsc_dvb_div_sel = 1
1070 // 0: select clk_dmplldiv5
1071 // 1: select clk_dmplldiv3
1072 // [4:0]: reg_ckg_dvbtm_ts_divnum = 11
1073 // Demod TS output clock phase tuning number
1074 // If (reg_ckg_tsout_ph_tun_num == reg_ckg_dvbtm_ts_divnum),
1075 // Demod TS output clock is equal Demod TS internal working clock.
1076 // => TS clock = (864/3)/(2*(5+1)) = 24MHz
1077 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1078 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1079 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1080 HAL_DMD_RIU_WriteByte(0x103300, 0x05);
1081
1082
1083 // enable DVBTC ts clock
1084 // [11:8]: reg_ckg_dvbtc_ts
1085 // [8] : disable clock
1086 // [9] : invert clock
1087 // [11:10]: Select clock source
1088 // 00:clk_atsc_dvb_div
1089 // 01:62 MHz
1090 // 10:54 MHz
1091 // 11:reserved
1092 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
1093 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
1094 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1095 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1096
1097
1098 // enable dvbc adc clock
1099 // [3:0]: reg_ckg_dvbtc_adc
1100 // [0] : disable clock
1101 // [1] : invert clock
1102 // [3:2]: Select clock source => for demod clkgen clk_dvbtc_adc
1103 // 00: clk_dmdadc
1104 // 01: clk_dmdadc_div2
1105 // 10: clk_dmdadc_div4
1106 // 11: DFT_CLK
1107 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
1108 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
1109 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1110 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1111 // [Maxim] enable ADCI clock & ADCQ clock
1112 // h0010 h0010 3 0 reg_ckg_dvbtc_adc_i 3 0 4 h1
1113 // h0010 h0010 11 8 reg_ckg_dvbtc_adc_q 3 0 4 h1
1114 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h10, 2'b11, 16'h0000); // enable dvbc adc clock
1115 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h10, 2'b11, 16'h0000); // enable dvbc adc clock
1116 HAL_DMD_RIU_WriteByte(0x103321, 0x00);
1117 HAL_DMD_RIU_WriteByte(0x103320, 0x00);
1118 // ==============================================================
1119 // Start demod_0 CLKGEN setting ......
1120 // ==============================================================
1121 // enable atsc_adcd_sync clock
1122 // [3:0] : reg_ckg_atsc_adcd_sync
1123 // [0] : disable clock
1124 // [1] : invert clock
1125 // [3:2]: Select clock source
1126 // 00: clk_dmdadc_sync
1127 // 01: 1'b0
1128 // 10: 1'b0
1129 // 11: DFT_CLK
1130 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
1131 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
1132 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1133 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1134
1135 // DVBS2
1136 // @0x350c
1137 // [3:0] : reg_ckg_dvbs_outer1x
1138 // [0] : disable clock
1139 // [1] : invert clock
1140 // [3:2]: Select clock source
1141 // 00: adc_clk_buf
1142 // 01: dvb_clk86_buf
1143 // 10: dvb_clk43_buf
1144 // 11: 1'b0
1145 // [6:4] : reg_ckg_dvbs_outer2x
1146 // [4] : disable clock
1147 // [5] : invert clock
1148 // [6] : Select clock source
1149 // 00: adc_clk_buf
1150 // 01: 1'b0
1151 // 10: 1'b0
1152 // 11: DFT_CLK
1153 // [10:8]: reg_ckg_dvbs2_inner
1154 // [8] : disable clock
1155 // [9] : invert clock
1156 // [10]: Select clock source
1157 // 00: adc_clk_buf
1158 // 01: 1'b0
1159 // 10: 1'b0
1160 // 11: DFT_CLK
1161 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1162 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1163 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1164 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1165
1166
1167 // DVBS2
1168 // @0x350d
1169 // [11:8]: reg_ckg_dvbs2_oppro
1170 // [8] : disable clock
1171 // [9] : invert clock
1172 // [11:10]: Select clock source
1173 // 00: mpll_clk144_buf
1174 // 01: mpll_clk96_buf
1175 // 10: mpll_clk72_buf
1176 // 11: mpll_clk48_buf
1177 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0d, 2'b11, 16'h0000);
1178 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0d, 2'b11, 16'h0000);
1179 HAL_DMD_RIU_WriteByte(0x111f1b, 0x00);
1180 HAL_DMD_RIU_WriteByte(0x111f1a, 0x00);
1181
1182
1183 // @0x3510
1184 // [3:0] : reg_ckg_dvbtm_adc
1185 // N/A
1186 // [6:4] : reg_ckg_dvbt_inner1x
1187 // [4] : disable clock
1188 // [5] : invert clock
1189 // [6] : Select clock source
1190 // 00: dvb_clk24_buf
1191 // 01: dvb_clk21p5_buf
1192 // 10: 1'b0
1193 // 11: DFT_CLK
1194 // [10:8] reg_ckg_dvbt_inner2x
1195 // [8] : disable clock
1196 // [9] : invert clock
1197 // [10]: Select clock source
1198 // 00: dvb_clk48_buf
1199 // 01: dvb_clk43_buf
1200 // 10: 1'b0
1201 // 11: DFT_CLK
1202 // [14:12] reg_ckg_dvbt_inner4x
1203 // [12]: disable clock
1204 // [13]: invert clock
1205 // [14]: Select clock source
1206 // 00: dvb_clk96_buf
1207 // 01: dvb_clk86_buf
1208 // 10: 1'b0
1209 // 11: DFT_CLK
1210 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h1110);
1211 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h1110);
1212 HAL_DMD_RIU_WriteByte(0x111f21, 0x11);
1213 HAL_DMD_RIU_WriteByte(0x111f20, 0x10);
1214
1215 // @0x3511
1216 // [2:0] : reg_ckg_dvbt_outer1x
1217 // [0] : disable clock
1218 // [1] : invert clock
1219 // [2] : Select clock source
1220 // 00: dvb_clk48_buf
1221 // 01: dvb_clk43_buf
1222 // 10: 1'b0
1223 // 11: DFT_CLK
1224 // [6:4] : reg_ckg_dvbt_outer2x
1225 // [4] : disable clock
1226 // [5] : invert clock
1227 // [6] : Select clock source
1228 // 00: dvb_clk96_buf
1229 // 01: dvb_clk86_buf
1230 // 10: 1'b0
1231 // 11: DFT_CLK
1232 // [11:8]: reg_ckg_dvbtc_outer2x
1233 // [8] : disable clock
1234 // [9] : invert clock
1235 // [11:10]: Select clock source
1236 // 00: mpll_clk57p6_buf
1237 // 01: dvb_clk43_buf
1238 // 10: dvb_clk86_buf
1239 // 11: dvb_clk96_buf
1240 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0c11);
1241 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0c11);
1242 HAL_DMD_RIU_WriteByte(0x111f23, 0x0c);
1243 HAL_DMD_RIU_WriteByte(0x111f22, 0x11);
1244
1245
1246 // @0x3512
1247 // [11:8]: reg_ckg_acifir
1248 // [8] : disable clock
1249 // [9] : invert clock
1250 // [11:10]: Select clock source
1251 // 000: 1'b0
1252 // 001: clk_dmdadc
1253 // 010: clk_vif_ssc_mux
1254 // 011: 1'b0
1255 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b10, 16'h0400);
1256 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b10, 16'h0400);
1257 HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1258
1259
1260 // @0x3514
1261 // [12:8]: reg_ckg_dvbtm_sram_t1o2x_t22x
1262 // [8] : disable clock
1263 // [9] : invert clock
1264 // [12:10]: Select clock source
1265 // 000: dvb_clk48_buf
1266 // 001: dvb_clk43_buf
1267 // 010: 1'b0
1268 // 011: 1'b0
1269 // 100: 1'b0
1270 // 101: 1'b0
1271 // 110: 1'b0
1272 // 111: 1'b0
1273 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b11, 16'h0000);
1274 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b11, 16'h0000);
1275 HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
1276 HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1277
1278
1279 // @0x3516
1280 // [8:4] : reg_ckg_dvbtm_sram_adc_t22x
1281 // [4] : disable clock
1282 // [5] : invert clock
1283 // [8:6]: Select clock source
1284 // 000: dvb_clk48_buf
1285 // 001: dvb_clk43_buf
1286 // 010: 1'b0
1287 // 011: 1'b0
1288 // 100: adc_clk_buf
1289 // 101: 1'b0
1290 // 110: 1'b0
1291 // 111: 1'b0
1292 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h16, 2'b11, 16'h0001);
1293 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h16, 2'b11, 16'h0001);
1294 HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
1295 HAL_DMD_RIU_WriteByte(0x111f2c, 0x01);
1296
1297
1298 // @0x3517
1299 // [4:0] : reg_ckg_dvbtm_sram_t12x_t22x
1300 // [0] : disable clock
1301 // [1] : invert clock
1302 // [4:2]: Select clock source
1303 // 000: dvb_clk48_buf
1304 // 001: dvb_clk43_buf
1305 // 010: 1'b0
1306 // 011: 1'b0
1307 // 100: 1'b0
1308 // 101: 1'b0
1309 // 110: 1'b0
1310 // 111: 1'b0
1311 // [12:8] reg_ckg_dvbtm_sram_t12x_t24x
1312 // [8] : disable clock
1313 // [9] : invert clock
1314 // [12:10]: Select clock source
1315 // 000: dvb_clk96_buf
1316 // 001: dvb_clk86_buf
1317 // 010: dvb_clk48_buf
1318 // 011: dvb_clk43_buf
1319 // 100: 1'b0
1320 // 101: 1'b0
1321 // 110: 1'b0
1322 // 111: 1'b0
1323 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h17, 2'b11, 16'h0000);
1324 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h17, 2'b11, 16'h0000);
1325 HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
1326 HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
1327
1328
1329 // @0x3518
1330 // [4:0] : reg_ckg_dvbtm_sram_t14x_t24x
1331 // [0] : disable clock
1332 // [1] : invert clock
1333 // [4:2]: Select clock source
1334 // 000: dvb_clk96_buf
1335 // 001: dvb_clk96_buf
1336 // 010: 1'b0
1337 // 011: 1'b0
1338 // 100: 1'b0
1339 // 101: 1'b0
1340 // 110: 1'b0
1341 // 111: 1'b0
1342 // [12:8]: reg_ckg_dvbtm_ts_in
1343 // [8] : disable clock
1344 // [9] : invert clock
1345 // [12:10]: Select clock source
1346 // 000: clk_dvbtc_rs_p
1347 // 001: dvb_clk48_buf
1348 // 010: dvb_clk43_buf
1349 // 011: clk_dvbs_outer1x_pre_mux4
1350 // 100: clk_dvbs2_oppro_pre_mux4
1351 // 101: 1'b0
1352 // 110: 1'b0
1353 // 111: 1'b0
1354 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b11, 16'h0001);
1355 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b11, 16'h0001);
1356 HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1357 HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1358
1359
1360 // @0x3519
1361 // [2:0] : reg_ckg_tdp_jl_inner1x
1362 // [0] : disable clock
1363 // [1] : invert clock
1364 // [2] : Select clock source
1365 // 00: dvb_clk24_buf
1366 // 01: dvb_clk21p5_buf
1367 // 10: 1'b0
1368 // 11: DFT_CLK
1369 // [6:4] : reg_ckg_tdp_jl_inner4x
1370 // [4] : disable clock
1371 // [5] : invert clock
1372 // [6] : Select clock source
1373 // 00: dvb_clk96_buf
1374 // 01: dvb_clk86_buf
1375 // 10: 1'b0
1376 // 11: DFT_CLK
1377 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h19, 2'b11, 16'h3c00);
1378 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h19, 2'b11, 16'h3c00);
1379 HAL_DMD_RIU_WriteByte(0x111f33, 0x3c);
1380 HAL_DMD_RIU_WriteByte(0x111f32, 0x00);
1381
1382
1383 // @0x351a
1384 // [6:4] : reg_ckg_dvbt2_inner1x
1385 // [4] : disable clock
1386 // [5] : invert clock
1387 // [6] : Select clock source
1388 // 00: dvb_clk96_buf
1389 // 01: dvb_clk86_buf
1390 // 10: 1'b0
1391 // 11: DFT_CLK
1392 // [10:8]: reg_ckg_dvbt2_inner2x
1393 // [8] : disable clock
1394 // [9] : invert clock
1395 // [10]: Select clock source
1396 // 00: dvb_clk48_buf
1397 // 01: dvb_clk43_buf
1398 // 10: 1'b0
1399 // 11: DFT_CLK
1400 // [14:12]:reg_ckg_dvbt2_inner4x
1401 // [12] : disable clock
1402 // [13] : invert clock
1403 // [14] : Select clock source
1404 // 00: dvb_clk96_buf
1405 // 01: dvb_clk86_buf
1406 // 10: 1'b0
1407 // 11: DFT_CLK
1408 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1a, 2'b11, 16'h0000);
1409 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1a, 2'b11, 16'h0000);
1410 HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
1411 HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
1412
1413
1414 // @0x351b
1415 // [1:0] : reg_ckg_dvbt2_ldpc
1416 // DVBT2 LDPC gated clock control register
1417 // [0] = 1:clock enable.
1418 // [1] = 1:manual mode.
1419 // [3:2] : reg_ckg_dvbt2_bch
1420 // DVBT2 BCH gated clock control register;
1421 // [0] = 1:clock enable
1422 // [1] = 1:manual mode.
1423 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1b, 2'b11, 16'h0011);
1424 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1b, 2'b11, 16'h0011);
1425 HAL_DMD_RIU_WriteByte(0x111f37, 0x00);
1426 HAL_DMD_RIU_WriteByte(0x111f36, 0x11);
1427
1428
1429 // @0x351d
1430 // [4:0] : reg_ckg_dvbtm_adc_eq_1x
1431 // [0] : disable clock
1432 // [1] : invert clock
1433 // [2] : Select clock source
1434 // 00: adc_clk_buf
1435 // 01: 1'b0
1436 // 10: 1'b0
1437 // 11: DFT_CLK
1438 // [12:8]: reg_ckg_dvbtm_adc_eq_0p5x
1439 // [4] : disable clock
1440 // [5] : invert clock
1441 // [6]: Select clock source
1442 // 00: clk_adc_div2_buf
1443 // 01: 1'b0
1444 // 10: 1'b0
1445 // 11: DFT_CLK
1446 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1d, 2'b11, 16'h0000);
1447 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1d, 2'b11, 16'h0000);
1448 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1449 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1450
1451
1452 // @0x351e
1453 // [4:0] : reg_ckg_dvbtm_sram_t11x_t22x
1454 // [0] : disable clock
1455 // [1] : invert clock
1456 // [4:2]: Select clock source
1457 // 000: dvb_clk48_buf
1458 // 001: dvb_clk43_buf
1459 // 010: dvb_clk24_buf
1460 // 011: dvb_clk21p5_buf
1461 // 100: 1'b0
1462 // 101: 1'b0
1463 // 110: 1'b0
1464 // 111: 1'b0
1465 // [12:8]: reg_ckg_dvbtm_sram_t11x_t24x
1466 // [8] : disable clock
1467 // [9] : invert clock
1468 // [:2]: Select clock source
1469 // 000: dvb_clk48_buf
1470 // 001: dvb_clk43_buf
1471 // 010: dvb_clk24_buf
1472 // 011: dvb_clk21p5_buf
1473 // 100: 1'b0
1474 // 101: 1'b0
1475 // 110: 1'b0
1476 // 111: 1'b0
1477 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1e, 2'b11, 16'h0c04);
1478 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1e, 2'b11, 16'h0000);
1479 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1e, 2'b11, 16'h0000);
1480 HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
1481 HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
1482
1483
1484 // @0x3522
1485 // [3:0] : reg_ckg_dvbt_t2_inner0p5x_dvbc_eq1x
1486 // [0] : disable clock
1487 // [1] : invert clock
1488 // [2] : Select clock source
1489 // 00: dvb_clk12_buf
1490 // 01: dvb_clk10p75_buf
1491 // 10: 1'b0
1492 // 11: DFT_CLK
1493 // [7:4] : reg_ckg_dvbt_t2_inner2x_dvbc_eq4x
1494 // [4] : disable clock
1495 // [5] : invert clock
1496 // [6] : Select clock source
1497 // 00: dvb_clk48_buf
1498 // 01: dvb_clk43_buf
1499 // 10: 1'b0
1500 // 11: DFT_CLK
1501 // [11:8]: reg_ckg_dvbt_t2_inner1x
1502 // [8] : disable clock
1503 // [9] : invert clock
1504 // [11:10]: Select clock source
1505 // 00: dvb_clk24_buf
1506 // 01: dvb_clk21p5_buf
1507 // 10: 1'b0
1508 // 11: DFT_CLK
1509 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0111);
1510 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0111);
1511 HAL_DMD_RIU_WriteByte(0x111f45, 0x01);
1512 HAL_DMD_RIU_WriteByte(0x111f44, 0x11);
1513
1514 // @0x353a
1515 // [2:0] : reg_ckg_dvbtm_sram_t12x_t24x_srd1x_isdbt_inner2x
1516 // [0] : disable clock
1517 // [1] : invert clock
1518 // [2] : Select clock source
1519 // 00: clk_dvbtm_sram_t12x_t24x_srd1x_p
1520 // 01: clk_isdbt_inner2x_p
1521 // 10: 1'b0
1522 // 11: DFT_CLK
1523 // [6:4] : reg_ckg_dvbtm_sram_t12x_t24x_isdbt_inner2x
1524 // [4] : disable clock
1525 // [5] : invert clock
1526 // [6] : Select clock source
1527 // 00: clk_dvbtm_sram_t12x_t24x_p
1528 // 01: clk_isdbt_inner2x_p
1529 // 10: 1'b0
1530 // 11: DFT_CLK
1531 // [10:8]: reg_ckg_dvbtm_sram_t24x_isdbt_inner2x
1532 // [8] : disable clock
1533 // [9] : invert clock
1534 // [10]: Select clock source
1535 // 00: clk_dvbtm_sram_t14x_t24x_p
1536 // 01: clk_isdbt_inner2x_p
1537 // 10: 1'b0
1538 // 11: DFT_CLK
1539 // [14:12]: reg_ckg_dvbtm_sram_t12x_t24x_s2inner_isdbt_inner4x
1540 // [12] : disable clock
1541 // [13] : invert clock
1542 // [14] : Select clock source
1543 // 00: clk_dvbtm_sram_t12x_t24x_s2inner_p
1544 // 01: clk_isdbt_inner4x_p
1545 // 10: 1'b0
1546 // 11: DFT_CLK
1547 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3a, 2'b11, 16'h0110);
1548 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3a, 2'b11, 16'h0110);
1549 HAL_DMD_RIU_WriteByte(0x111f75, 0x01);
1550 HAL_DMD_RIU_WriteByte(0x111f74, 0x10);
1551
1552 // @0x353b
1553 // [2:0] : reg_ckg_dvbtm_sram_t12x_t24x_s2inner_isdbt_inner2x
1554 // [0] : disable clock
1555 // [1] : invert clock
1556 // [2] : Select clock source
1557 // 00: clk_dvbtm_sram_t12x_t24x_s2inner_p
1558 // 01: clk_isdbt_inner2x_p
1559 // 10: 1'b0
1560 // 11: DFT_CLK
1561 // [6:4] : reg_ckg_dvbtm_sram_t22x_isdbt_inner2x
1562 // [4] : disable clock
1563 // [5] : invert clock
1564 // [6] : Select clock source
1565 // 00: clk_dvbtm_sram_t12x_t22x_p
1566 // 01: clk_isdbt_inner2x_p
1567 // 10: 1'b0
1568 // 11: DFT_CLK
1569 // [10:8]: reg_ckg_dvbtm_sram_t14x_t24x_s2inner_isdbt_inner2x
1570 // [8] : disable clock
1571 // [9] : invert clock
1572 // [10]: Select clock source
1573 // 00: clk_dvbtm_sram_t14x_t24x_s2inner_p
1574 // 01: clk_isdbt_inner2x_p
1575 // 10: 1'b0
1576 // 11: DFT_CLK
1577 // [14:12]: reg_ckg_dvbtm_sram_t12x_t24x_srd1x_isdbt_inner4x
1578 // [12] : disable clock
1579 // [13] : invert clock
1580 // [14]: Select clock source
1581 // 00: clk_dvbtm_sram_t12x_t24x_srd1x_p
1582 // 01: clk_isdbt_inner4x_p
1583 // 10: 1'b0
1584 // 11: DFT_CLK
1585 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0010);
1586 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0010);
1587 HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
1588 HAL_DMD_RIU_WriteByte(0x111f76, 0x10);
1589
1590 // @0x353c
1591 // [2:0] : reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifssc_isdbt_inner4x
1592 // [0] : disable clock
1593 // [1] : invert clock
1594 // [2] : Select clock source
1595 // 00: clk_dvbtm_sram_t14x_t24x_srd1x_vifssc_p
1596 // 01: clk_isdbt_inner4x_p
1597 // 10: 1'b0
1598 // 11: DFT_CLK
1599 // [6:4] : reg_ckg_dvbtm_sram_t12x_t22x_isdbt_inner2x
1600 // [4] : disable clock
1601 // [5] : invert clock
1602 // [6] : Select clock source
1603 // 00: clk_dvbtm_sram_t12x_t22x_p
1604 // 01: clk_isdbt_inner2x_p
1605 // 10: 1'b0
1606 // 11: DFT_CLK
1607 // [10:8]: reg_ckg_dvbtm_sram_t11x_t22x_isdbt_inner2x
1608 // [8] : disable clock
1609 // [9] : invert clock
1610 // [10]: Select clock source
1611 // 00: clk_dvbtm_sram_t11x_t22x_p
1612 // 01: clk_isdbt_inner2x_p
1613 // 10: 1'b0
1614 // 11: DFT_CLK
1615 // [14:12]: reg_ckg_dvbtm_sram_t12x_t24x_isdbt_outer6x
1616 // [12] : disable clock
1617 // [13] : invert clock
1618 // [14]: Select clock source
1619 // 00: clk_dvbtm_sram_t12x_t24x_p
1620 // 01: clk_isdbt_outer6x_dvbt_outer2x_c_mux
1621 // 10: 1'b0
1622 // 11: DFT_CLK
1623 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3c, 2'b11, 16'h0110);
1624 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3c, 2'b11, 16'h0110);
1625 HAL_DMD_RIU_WriteByte(0x111f79, 0x01);
1626 HAL_DMD_RIU_WriteByte(0x111f78, 0x10);
1627
1628 // @0x353e
1629 // [2:0] : reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_isdbt_outer6x
1630 // [0] : disable clock
1631 // [1] : invert clock
1632 // [2] : Select clock source
1633 // 00: clk_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_mux8
1634 // 01: clk_isdbt_outer6x_p
1635 // 10: 1'b0
1636 // 11: DFT_CLK
1637 // [6:4] : reg_ckg_dvbtm_sram_t22x_miu
1638 // [4] : disable clock
1639 // [5] : invert clock
1640 // [6] : Select clock source
1641 // 00: clk_dvbt2_inner2x_p
1642 // 01: clk_miu_p
1643 // 10: 1'b0
1644 // 11: DFT_CLK
1645 // [10:8]: reg_ckg_dvbtm_sram_adc_t22x_isdbt_inner2x
1646 // [8] : disable clock
1647 // [9] : invert clock
1648 // [10]: Select clock source
1649 // 00: clk_dvbtm_sram_adc_t22x_p
1650 // 01: clk_isdbt_inner2x_p
1651 // 10: 1'b0
1652 // 11: DFT_CLK
1653 // [14:12]: reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_miu
1654 // [12] : disable clock
1655 // [13] : invert clock
1656 // [14]: Select clock source
1657 // 00: clk_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_mux8
1658 // 01: clk_miu_p
1659 // 10: 1'b0
1660 // 11: DFT_CLK
1661 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3e, 2'b11, 16'h1111);
1662 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3e, 2'b11, 16'h1111);
1663 HAL_DMD_RIU_WriteByte(0x111f7d, 0x11);
1664 HAL_DMD_RIU_WriteByte(0x111f7c, 0x11);
1665
1666 // @0x353f
1667 // [2:0] : reg_ckg_dvbs_outer2x_dvbt_outer2x_miu_isdbt_outer6x
1668 // [0] : disable clock
1669 // [1] : invert clock
1670 // [2] : Select clock source
1671 // 00: clk_dvbs_outer2x_dvbt_outer2x_miu_mux8
1672 // 01: clk_isdbt_outer6x_p
1673 // 10: 1'b0
1674 // 11: DFT_CLK
1675 // [6:4] : reg_ckg_dvbtm_sram_t22x_dvbtc_rs
1676 // [4] : disable clock
1677 // [5] : invert clock
1678 // [6] : Select clock source
1679 // 00: clk_dvbt2_inner2x_p
1680 // 01: clk_dvbtc_rs_p
1681 // 10: 1'b0
1682 // 11: DFT_CLK
1683 // [10:8]: reg_ckg_dvbtc_outer2x_isdbt_outer_rs
1684 // [8] : disable clock
1685 // [9] : invert clock
1686 // [10]: Select clock source
1687 // 00: clk_dvbtc_outer2x_p
1688 // 01: clk_isdbt_outer_rs_p
1689 // 10: 1'b0
1690 // 11: DFT_CLK
1691 // [14:12]: reg_ckg_dvbtm_sram_t22x_isdbt_outer6x_dvbt_outer2x
1692 // [12] : disable clock
1693 // [13] : invert clock
1694 // [14]: Select clock source
1695 // 00: clk_dvbtm_sram_t12x_t22x_p
1696 // 01: clk_isdbt_outer6x_dvbt_outer2x_mux
1697 // 10: 1'b0
1698 // 11: DFT_CLK
1699 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3f, 2'b11, 16'h1041);
1700 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3f, 2'b11, 16'h1041);
1701 HAL_DMD_RIU_WriteByte(0x111f7f, 0x10);
1702 HAL_DMD_RIU_WriteByte(0x111f7e, 0x41);
1703
1704
1705 // @0x3570
1706 // [4:0] : reg_ckg_dvbt_inner2x_srd0p5x
1707 // [0] : disable clock
1708 // [1] : invert clock
1709 // [3:2]: Select clock source
1710 // 00: dvb_clk48_buf
1711 // 01: dvb_clk43_buf
1712 // 10: clk_adc_div2_buf
1713 // 11: 1'b0
1714 // 11: 1'b0
1715 // [13:8]: reg_ckg_dvbtm_sram_t1outer1x_t24x
1716 // [8] : disable clock
1717 // [9] : invert clock
1718 // [12:10]: Select clock source
1719 // 000: dvb_clk96_buf
1720 // 001: dvb_clk86_buf
1721 // 010: dvb_clk48_buf
1722 // 011: dvb_clk43_buf
1723 // 100: 1'b0
1724 // 101: 1'b0
1725 // 110: 1'b0
1726 // 111: 1'b0
1727 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h70, 2'b11, 16'h0008);
1728 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h70, 2'b11, 16'h0008);
1729 HAL_DMD_RIU_WriteByte(0x111fe1, 0x00);
1730 HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1731
1732
1733 // @0x3571
1734 // [4:0] : reg_ckg_dvbtm_sram_t12x_t24x_srd1x
1735 // [0] : disable clock
1736 // [1] : invert clock
1737 // [3:2]: Select clock source
1738 // 000: dvb_clk96_buf
1739 // 001: dvb_clk86_buf
1740 // 010: dvb_clk48_buf
1741 // 011: dvb_clk43_buf
1742 // 100: adc_clk_buf
1743 // 101: 1'b0
1744 // 110: 1'b0
1745 // 111: 1'b0
1746 // [12:8]: reg_ckg_dvbtm_sram_t14x_t24x_srd1x
1747 // [8] : disable clock
1748 // [9] : invert clock
1749 // [12:10]: Select clock source
1750 // 000: dvb_clk96_buf
1751 // 001: dvb_clk86_buf
1752 // 010: adc_clk_buf
1753 // 011: 1'b0
1754 // 100: 1'b0
1755 // 101: 1'b0
1756 // 110: 1'b0
1757 // 111: 1'b0
1758 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h71, 2'b11, 16'h0810);
1759 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h71, 2'b11, 16'h0810);
1760 HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1761 HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1762
1763
1764 // @0x3572
1765 // [6:0] : reg_ckg_dvbt2_s2_bch_out
1766 // [0] : disable clock
1767 // [1] : invert clock
1768 // [2] : Select clock source
1769 // 00: dvb_clk48_buf
1770 // 01: dvb_clk43_buf
1771 // 10: 1'b0
1772 // 11: DFT_CLK
1773 // [12:8]: reg_ckg_dvbt2_outer2x
1774 // [8] : disable clock
1775 // [9] : invert clock
1776 // [12:10]: Select clock source
1777 // 000: mpll_clk144_buf
1778 // 001: mpll_clk108_buf
1779 // 010: mpll_clk96_buf
1780 // 011: mpll_clk72_buf
1781 // 100: mpll_clk54_buf
1782 // 101: mpll_clk48_buf
1783 // 110: mpll_clk36_buf
1784 // 111: mpll_clk24_buf
1785 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h72, 2'b11, 16'h0008);
1786 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h72, 2'b11, 16'h0008);
1787 HAL_DMD_RIU_WriteByte(0x111fe5, 0x00);
1788 HAL_DMD_RIU_WriteByte(0x111fe4, 0x08);
1789
1790
1791 // @0x3573
1792 // [3:0] : reg_ckg_dvbt2_inner4x_s2_inner
1793 // [0] : disable clock
1794 // [1] : invert clock
1795 // [2] : Select clock source
1796 // 00: dvb_clk96_buf
1797 // 01: dvb_clk86_buf
1798 // 10: 1'b0
1799 // 11: DFT_CLK
1800 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h73, 2'b11, 16'h0008);
1801 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h73, 2'b11, 16'h0008);
1802 HAL_DMD_RIU_WriteByte(0x111fe7, 0x00);
1803 HAL_DMD_RIU_WriteByte(0x111fe6, 0x08);
1804
1805
1806 // @0x3574
1807 // [4:0] reg_ckg_dvbtm_sram_t12x_t24x_s2inner
1808 // [0] : disable clock
1809 // [1] : invert clock
1810 // [4:2]:Select clock source
1811 // 000: dvb_clk96_buf
1812 // 001: dvb_clk86_buf
1813 // 010: dvb_clk48_buf
1814 // 011: dvb_clk43_buf
1815 // 100: adc_clk_buf
1816 // 101: 1'b0
1817 // 110: 1'b0
1818 // 111: 1'b0
1819 // [12:8] reg_ckg_dvbtm_sram_t14x_t24x_s2inner
1820 // [8] : disable clock
1821 // [9] : invert clock
1822 // [12:10]: Select clock source
1823 // 000: dvb_clk96_buf
1824 // 001: dvb_clk86_buf
1825 // 010: adc_clk_buf
1826 // 011: dvb_clk24_buf //JL SRAM Share (Windermere U02 ECO)
1827 // 100: dvb_clk21p5_buf //JL SRAM Share (Windermere U02 ECO)
1828 // 101: 1'b0
1829 // 110: 1'b0
1830 // 111: 1'b0
1831 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h74, 2'b11, 16'h0810);
1832 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h74, 2'b11, 16'h0810);
1833 HAL_DMD_RIU_WriteByte(0x111fe9, 0x08);
1834 HAL_DMD_RIU_WriteByte(0x111fe8, 0x10);
1835
1836
1837 // @0x3575
1838 // [4:0] : reg_ckg_dvbtc_rs
1839 // [0] : disable clock
1840 // [1] : invert clock
1841 // [4:2]:Select clock source
1842 // 000: mpll_clk216_buf
1843 // 001: mpll_clk172p8_buf
1844 // 010: mpll_clk144_buf
1845 // 011: mpll_clk288_buf
1846 // 100: dvb_clk96_buf
1847 // 101: dvb_clk86_buf
1848 // 110: mpll_clk57p6_buf
1849 // 111: dvb_clk43_buf
1850 // [11:8] : reg_ckg_dvbs_outer2x_dvbt_outer2x (N/A)
1851 // [15:12]: reg_ckg_dvbs_outer2x_dvbt_outer2x_miu
1852 // [12] : disable clock
1853 // [13] : invert clock
1854 // [15:14]:Select clock source
1855 // 000: 1'b0
1856 // 001: dvb_clk96_buf
1857 // 010: dvb_clk86_buf
1858 // 011: clk_miu
1859 // 100: 1'b0
1860 // 101: 1'b0
1861 // 110: 1'b0
1862 // 111: 1'b0
1863 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h75, 2'b11, 16'h0000);
1864 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h75, 2'b11, 16'h0000);
1865 HAL_DMD_RIU_WriteByte(0x111feb, 0x00);
1866 HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1867
1868
1869 // @0x3576
1870 // [4:0] : reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x
1871 // [0] : disable clock
1872 // [1] : invert clock
1873 // [4:2]:Select clock source
1874 // 000: 1'b0
1875 // 001: dvb_clk96_buf
1876 // 010: dvb_clk86_buf
1877 // 011: dvb_clk48_buf
1878 // 100: dvb_clk43_buf
1879 // 101: 1'b0
1880 // 110: 1'b0
1881 // 111: 1'b0
1882 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h76, 2'b11, 16'h0000);
1883 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h76, 2'b11, 16'h0000);
1884 HAL_DMD_RIU_WriteByte(0x111fed, 0x00);
1885 HAL_DMD_RIU_WriteByte(0x111fec, 0x00);
1886
1887
1888 // @0x3577
1889 // [3:0] : reg_ckg_dvbt2_inner4x_dvbtc_rs
1890 // [0] : disable clock
1891 // [1] : invert clock
1892 // [3:2]: Select clock source
1893 // 00: dvb_clk96_buf
1894 // 01: dvb_clk86_buf
1895 // 10: clk_dvbtc_rs_p
1896 // 11: 1'b0
1897 // [8:4] : reg_ckg_dvbtm_sram_adc_t22x_dvbtc_rs
1898 // [4] : disable clock
1899 // [5] : invert clock
1900 // [6] : Select clock source
1901 // 000: dvb_clk48_buf
1902 // 001: dvb_clk43_buf
1903 // 010: 1'b0
1904 // 011: adc_clk_buf
1905 // 100: 1'b0
1906 // 101: 1'b0
1907 // 110: 1'b0
1908 // 111: 1'b0
1909 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h77, 2'b11, 16'h0088);
1910 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h77, 2'b11, 16'h0088);
1911 HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1912 HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1913
1914
1915 // Maserati
1916 // @0x3578
1917 // [4:0] : reg_ckg_dvbt2_inner2x_srd0p5x
1918 // [0] : disable clock
1919 // [1] : invert clock
1920 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h78, 2'b01, 16'h0008);
1921 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h78, 2'b01, 16'h0008);
1922 HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1923
1924 // [3:0] : reg_ckg_sram_t22x_isdbt_inn2x_dtmb_inn2x
1925 // [0] : disable clock
1926 // [1] : invert clock
1927 // [3:2]:Select clock source
1928 // 000: clk_dvbtm_sram_t12x_t22x_p
1929 // 001: clk_isdbt_inner2x_p
1930 // 010: clk_share_dtmb_inner2x_isdbt_sram4_mux
1931 // 011:
1932 // [7:4] : reg_ckg_sram_t14x_t24x_s2inn_isdbt_inn2x_dtmb_inn6x
1933 // [4] : disable clock
1934 // [5] : invert clock
1935 // [7:6]:Select clock source
1936 // 000: clk_dvbtm_sram_t14x_t24x_s2inner_p
1937 // 001: clk_isdbt_inner2x_p
1938 // 010: clk_share_dtmb_inner6x_isdbt_sram3_mux
1939 // 011:
1940 // [11:8] : reg_ckg_sram_t14x_t24x_s2inn_isdbt_inn2x_dtmb_eq2x
1941 // [4] : disable clock
1942 // [5] : invert clock
1943 // [7:6]:Select clock source
1944 // 000: clk_dvbtm_sram_t14x_t24x_s2inner_p
1945 // 001: clk_isdbt_inner2x_p
1946 // 010: clk_share_dtmb_eq2x_isdbt_sram3_mux
1947 // 011:
1948 // [15:12]: reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifssc_isdbt_inner4x_dtmb_inner12x
1949 // [12] : disable clock
1950 // [13] : invert clock
1951 // [15:14]:Select clock source
1952 // 000: clk_dvbtm_sram_t14x_t24x_srd1x_vifssc_p
1953 // 001: clk_isdbt_inner4x_p
1954 // 010: clk_dvbtc_sram2_p
1955 // 011: clk_dtmb_eq2x_inner2x_12x_mux
1956 // `RIU_W((`RIUBASE_DEMOD_8>>1)+7'h48, 2'b11, 16'h0001);
1957 // `RIU_W((`RIUBASE_DEMOD_8>>1)+7'h48, 2'b11, 16'h0001);
1958 HAL_DMD_RIU_WriteByte(0x152991, 0x00);
1959 HAL_DMD_RIU_WriteByte(0x152990, 0x01);
1960 // ==============================================================
1961 // End demod top initial setting by HK MCU ......
1962 // ==============================================================
1963 //wriu 0x101e39 0x03
1964 HAL_DMD_RIU_WriteByte(0x101e39, 0x03);
1965
1966 //==========================================================
1967 //diseqc_out : PAD_GPIO15_I
1968 //swich to Diseqc out pin from GPIO
1969 //==========================================================
1970 //Bank: Reg_CHIP_TOP(0x101e)
1971 //reg_test_out_mode : addr h��12, [6:4] = 3��h0
1972 //reg_ts4config : addr h��40, [11:10] = 2��h0
1973 //reg_ts5config : addr h��40, [13:12] = 2��h0
1974 //reg_i2smutemode : addr h��2, [15:14] = 2��h0
1975 //reg_fifthuartmode : h��4, [3:2] = 2��h0
1976 //reg_od5thuart : h��55, [5:4] = 2��h0
1977 //reg_diseqc_out_config : ��h45, [1] = 1��b1
1978 u8Temp = HAL_DMD_RIU_ReadByte(0x101E8A);
1979 u8Temp|=0x02;
1980 HAL_DMD_RIU_WriteByte(0x101E8A, u8Temp);
1981
1982 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1983
1984 // SRAM allocation 64K avoid change souce from T2 failed.
1985 HAL_DMD_RIU_WriteByte(0x111701,0x00);
1986 HAL_DMD_RIU_WriteByte(0x111700,0x00);
1987
1988 HAL_DMD_RIU_WriteByte(0x111705,0x00);
1989 HAL_DMD_RIU_WriteByte(0x111704,0x00);
1990
1991 HAL_DMD_RIU_WriteByte(0x111703,0xff);
1992 HAL_DMD_RIU_WriteByte(0x111702,0xff);
1993
1994 HAL_DMD_RIU_WriteByte(0x111707,0xff);
1995 HAL_DMD_RIU_WriteByte(0x111706,0xff);
1996
1997 //Diff from TV tool
1998 HAL_DMD_RIU_WriteByte(0x111708,0x01);
1999 HAL_DMD_RIU_WriteByte(0x111709,0x00);
2000
2001 HAL_DMD_RIU_WriteByte(0x11170a,0x0f);
2002 HAL_DMD_RIU_WriteByte(0x11170b,0x00);
2003
2004 HAL_DMD_RIU_WriteByte(0x111718,0x02);
2005 HAL_DMD_RIU_WriteByte(0x111719,0x00);
2006
2007 HAL_DMD_RIU_WriteByte(0x11171a,0x00);
2008 HAL_DMD_RIU_WriteByte(0x11171b,0x00);
2009
2010 HAL_DMD_RIU_WriteByte(0x1117e0,0x14);
2011 HAL_DMD_RIU_WriteByte(0x1117e1,0x14);
2012
2013 HAL_DMD_RIU_WriteByte(0x1117e4,0x00);
2014 HAL_DMD_RIU_WriteByte(0x1117e5,0x00);
2015
2016 HAL_DMD_RIU_WriteByte(0x1117e6,0x00);
2017 HAL_DMD_RIU_WriteByte(0x1117e7,0x00);
2018
2019 // SRAM End Address
2020 HAL_DMD_RIU_WriteByte(0x111707,0xff);
2021 HAL_DMD_RIU_WriteByte(0x111706,0xff);
2022
2023 // DRAM Disable
2024 HAL_DMD_RIU_WriteByte(0x111718,HAL_DMD_RIU_ReadByte(0x111718)&(~0x04));
2025
2026 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_InitClkgen\n"));
2027 }
2028
2029 /***********************************************************************************
2030 Subject: Power on initialized function
2031 Function: INTERN_DVBS_Power_On_Initialization
2032 Parmeter:
2033 Return: MS_BOOL
2034 Remark:
2035 ************************************************************************************/
INTERN_DVBS_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBS_DSPRegInitExt,MS_U8 u8DMD_DVBS_DSPRegInitSize)2036 MS_BOOL INTERN_DVBS_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBS_DSPRegInitExt, MS_U8 u8DMD_DVBS_DSPRegInitSize)
2037 {
2038 MS_U8 status = true;
2039 //MS_U8 u8ChipVersion;
2040
2041 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_Power_On_Initialization\n"));
2042
2043 #if defined(PWS_ENABLE)
2044 Mapi_PWS_Stop_VDMCU();
2045 #endif
2046 INTERN_DVBS_InitClkgen(bRFAGCTristateEnable);//~~ no modify
2047 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);//~~ no modify
2048
2049 DBG_INTERN_DVBS(ULOGD("DEMOD","@@@@@INTERN_DVBS_Power_On_Initialization1:bRFAGCTristateEnable=%d ;u8ADCIQMode=%d \n",bRFAGCTristateEnable,u8ADCIQMode));
2050 DBG_INTERN_DVBS(ULOGD("DEMOD","@@@@@INTERN_DVBS_Power_On_Initialization2:u8PadSel=%d ;bPGAEnable=%d \n",u8PadSel,bPGAEnable));
2051 DBG_INTERN_DVBS(ULOGD("DEMOD","@@@@@INTERN_DVBS_Power_On_Initialization2:u8PGAGain=%d \n",u8PGAGain));
2052
2053 //// Firmware download //////////
2054 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS Load DSP...\n"));
2055 //MsOS_DelayTask(100);
2056
2057 {
2058 if (INTERN_DVBS_LoadDSPCode() == FALSE)
2059 {
2060 DBG_INTERN_DVBS(ULOGD("DEMOD","DVB-S Load DSP Code Fail\n"));
2061 return FALSE;
2062 }
2063 else
2064 {
2065 DBG_INTERN_DVBS(ULOGD("DEMOD","DVB-S Load DSP Code OK\n"));
2066 }
2067 }
2068
2069 //// MCU Reset //////////
2070 if (INTERN_DVBS_Reset() == FALSE)
2071 {
2072 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS Reset...Fail\n"));
2073 return FALSE;
2074 }
2075 else
2076 {
2077 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS Reset...OK\n"));
2078 }
2079
2080
2081 status &= INTERN_DVBS_DSPReg_Init(u8DMD_DVBS_DSPRegInitExt, u8DMD_DVBS_DSPRegInitSize);
2082 //status &= INTERN_DVBS_Active(ENABLE);//enable this
2083
2084 //Read Demod FW Version.
2085 INTERN_DVBS_Show_Demod_Version();
2086
2087 return status;
2088 }
2089 /************************************************************************************************
2090 Subject: Driving control
2091 Function: INTERN_DVBC_Driving_Control
2092 Parmeter: bInversionEnable : TRUE For High
2093 Return: void
2094 Remark:
2095 *************************************************************************************************/
INTERN_DVBS_Driving_Control(MS_BOOL bEnable)2096 void INTERN_DVBS_Driving_Control(MS_BOOL bEnable)
2097 {
2098 MS_U8 u8Temp;
2099
2100 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
2101
2102 if (bEnable)
2103 {
2104 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
2105 }
2106 else
2107 {
2108 u8Temp = u8Temp & (~0x01);
2109 }
2110
2111 DBG_INTERN_DVBS(ULOGD("DEMOD","---> INTERN_DVBS_Driving_Control(Bit0) = 0x%x \n",u8Temp));
2112 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
2113 }
2114
2115 /************************************************************************************************
2116 Subject: Clk Inversion control
2117 Function: INTERN_DVBS_Clk_Inversion_Control
2118 Parmeter: bInversionEnable : TRUE For Inversion Action
2119 Return: void
2120 Remark:
2121 *************************************************************************************************/
INTERN_DVBS_Clk_Inversion_Control(MS_BOOL bInversionEnable)2122 void INTERN_DVBS_Clk_Inversion_Control(MS_BOOL bInversionEnable)
2123 {
2124 MS_U8 u8Temp;
2125
2126 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
2127
2128 if (bInversionEnable)
2129 {
2130 u8Temp = u8Temp | 0x02; //bit 9: clk inv
2131 }
2132 else
2133 {
2134 u8Temp = u8Temp & (~0x02);
2135 }
2136
2137 DBG_INTERN_DVBS(ULOGD("DEMOD","---> Inversion(Bit9) = 0x%x \n",u8Temp));
2138 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
2139 }
2140
2141 /************************************************************************************************
2142 Subject: Transport stream serial/parallel control
2143 Function: INTERN_DVBS_Serial_Control
2144 Parmeter: bEnable : TRUE For serial
2145 Return: MS_BOOL :
2146 Remark:
2147 *************************************************************************************************/
INTERN_DVBS_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)2148 MS_BOOL INTERN_DVBS_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
2149 {
2150 MS_U8 status = true;
2151 MS_U8 temp_val;
2152 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_ts... u8TSClk=%d\n", u8TSClk));
2153
2154 if (u8TSClk == 0xFF) u8TSClk=0x13;
2155 if (bEnable) //Serial mode for TS pad
2156 {
2157 // serial
2158 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
2159 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2160
2161 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
2162 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2163 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
2164 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2165 temp_val|=0x04;
2166 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2167 #else
2168 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
2169 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2170 temp_val|=0x07;
2171 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2172 #endif
2173 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
2174 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
2175
2176 //// INTERN_DVBS TS Control: Serial //////////
2177
2178 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, TS_SERIAL);
2179
2180 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2181 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 0);
2182 #else
2183 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 1);
2184 #endif
2185 gsCmdPacketDVBS.cmd_code = CMD_TS_CTRL;
2186
2187 gsCmdPacketDVBS.param[0] = TS_SERIAL;
2188 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2189 gsCmdPacketDVBS.param[1] = 0;//TS_CLK_NO_INV;
2190 #else
2191 gsCmdPacketDVBS.param[1] = 1;//TS_CLK_INVERSE;
2192 #endif
2193 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 2);
2194 }
2195 else
2196 {
2197 //parallel
2198 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
2199 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2200
2201 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2202 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2203 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2204 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
2205 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2206 temp_val|=0x05;
2207 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2208 #else
2209 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
2210 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2211 temp_val|=0x07;
2212 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2213 #endif
2214
2215 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
2216 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
2217
2218 //// INTERN_DVBS TS Control: Parallel //////////
2219
2220 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, TS_PARALLEL);
2221
2222 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2223 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 0);
2224 #else
2225 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 1);
2226 #endif
2227 //// INTERN_DVBC TS Control: Parallel //////////
2228 gsCmdPacketDVBS.cmd_code = CMD_TS_CTRL;
2229
2230 gsCmdPacketDVBS.param[0] = TS_PARALLEL;
2231 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2232 gsCmdPacketDVBS.param[1] = 0;//TS_CLK_NO_INV;
2233 #else
2234 gsCmdPacketDVBS.param[1] = 1;//TS_CLK_INVERSE;
2235 #endif
2236 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 2);
2237 }
2238
2239 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2240 DBG_INTERN_DVBS(ULOGD("DEMOD","---> Inversion(Bit5) = %d \n",0 ));
2241 #else
2242 DBG_INTERN_DVBS(ULOGD("DEMOD","---> Inversion(Bit5) = %d \n",1 ));
2243 #endif
2244
2245 INTERN_DVBS_Driving_Control(INTERN_DVBS_DTV_DRIVING_LEVEL);
2246 return status;
2247 }
2248
2249 /************************************************************************************************
2250 Subject: TS1 output control
2251 Function: INTERN_DVBS_PAD_TS1_Enable
2252 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
2253 Return: void
2254 Remark:
2255 *************************************************************************************************/
INTERN_DVBS_PAD_TS1_Enable(MS_BOOL flag)2256 void INTERN_DVBS_PAD_TS1_Enable(MS_BOOL flag)
2257 {
2258 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_TS1_Enable... \n"));
2259
2260 if(flag) // PAD_TS1 Enable TS CLK PAD
2261 {
2262 //printf("=== TS1_Enable ===\n");
2263 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
2264 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
2265 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
2266 }
2267 else // PAD_TS1 Disable TS CLK PAD
2268 {
2269 //printf("=== TS1_Disable ===\n");
2270 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
2271 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
2272 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
2273 }
2274 }
2275
2276 /************************************************************************************************
2277 Subject: channel change config
2278 Function: INTERN_DVBC_Config
2279 Parmeter: BW: bandwidth
2280 Return: MS_BOOL :
2281 Remark:
2282 *************************************************************************************************/
INTERN_DVBS_Config(MS_U32 u32SymbolRate,DMD_DVBS_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)2283 MS_BOOL INTERN_DVBS_Config(MS_U32 u32SymbolRate, DMD_DVBS_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
2284 {
2285
2286 MS_BOOL status= true;
2287 MS_U16 u16CenterFreq;
2288 // MS_U16 u16Fc = 0;
2289 MS_U8 temp_val;
2290 MS_U8 u8Data =0;
2291 MS_U8 u8counter = 0;
2292 //MS_U32 u32CurrentSR;
2293
2294 //u32CurrentSR = u32SymbolRate/1000; //KHz
2295
2296 //u32SymbolRate= u32SymbolRate/1000;//to match fw format
2297 u16CenterFreq =u32IFFreq;
2298 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_config+, QAM=%d, u32IFFreq=%d, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n", eQamMode, (int)u32IFFreq, bSpecInv, bSerialTS, u8TSClk));
2299 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_Config, t = %d\n",(int)MsOS_GetSystemTime()));
2300
2301 u8TSClk=0x05;//if (u8TSClk == 0xFF) u8TSClk=0x13;//set a fater speed for initial condition
2302 status &= INTERN_DVBS_Reset();
2303
2304 u8DemodLockFlag=0;
2305 /*
2306 // Symbol Rate
2307 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, u32CurrentSR&0xff);
2308 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, (u32CurrentSR>>8)&0xff);
2309 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, (u32CurrentSR>>16)&0xff);
2310 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config u32SymbolRate %d<<<\n", u32CurrentSR));
2311 */
2312 #if 0
2313 //======== check SR is right or not ===========
2314 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &u8Data);
2315 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L,u8Data));
2316 u32SR =u8Data;
2317 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &u8Data);
2318 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H,u8Data));
2319 u32SR =((U32)u8Data<<8)|u32SR ;
2320 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &u8Data);
2321 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MB_DMDTOP_DBG_5 addr=%d mailbox value=%d<<<\n", E_DMD_S2_MB_DMDTOP_DBG_5,u8Data));
2322 u32SR =((U32)u8Data<<16)|u32SR;
2323 //=================================================
2324 #endif
2325
2326 // IQ Swap ,ADCPLL IQ swap / DMDANA_IQ_SWAP
2327 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_IQ_SWAP, bSpecInv? 0x01:0x00);
2328 if(bSpecInv)
2329 {
2330 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DMDANA_REG_BASE+0xC0, &u8Data);//Demod\reg_dmdana.xls
2331 u8Data|=(0x02);
2332 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DMDANA_REG_BASE+0xC0, u8Data);
2333 }
2334
2335 // TS mode
2336 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, bSerialTS? 0x01:0x00);
2337 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Config TS Serial %d<<<\n", bSerialTS));
2338 _bSerialTS = bSerialTS;
2339
2340 if (bSerialTS)
2341 {
2342 // serial
2343 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2344 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2345
2346 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
2347 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2348 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2349 temp_val|=0x04;
2350 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2351 #else
2352 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2353 temp_val|=0x07;
2354 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2355 #endif
2356 }
2357 else
2358 {
2359 //parallel
2360 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2361 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2362
2363 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2364 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2365 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2366 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2367 temp_val|=0x05;
2368 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2369 #else
2370 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2371 temp_val|=0x07;
2372 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2373 #endif
2374 }
2375 #if (INTERN_DVBS_INTERNAL_DEBUG == 1)
2376 INTERN_DVBS_Show_Demod_Version();
2377 #endif
2378
2379 //-----------------------------------------------------------
2380 //From INTERN_DVBS_Demod_Restart function.
2381
2382 //FW sw reset
2383 //[0]: 0: SW Reset, 1: Start state machine
2384 //[1]: 1: Blind scan enable, 0: manual scan
2385 //[2]: 1: Code flow track enable
2386 //[3]: 1: go to AGC state
2387 //[4]: 1: set DiSEqC
2388 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2389 u8Data = (u8Data&0xF0)|0x01;
2390 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2391 //DBG_INTERN_DVBS(printf(">>>REG write check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2392 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2393 //DBG_INTERN_DVBS(printf(">>>REG read check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2394
2395 u8counter = 20;
2396 while( ((u8Data&0x01) == 0x00) && (u8counter != 0) )
2397 {
2398 MsOS_DelayTask(1);
2399 ULOGD("DEMOD","TOP_WR_DBG_90=0x%x, status=%d, u8counter=%d\n", u8Data, status, u8counter);
2400 u8Data|=0x01;
2401 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
2402 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
2403 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>(while)REG read check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2404 u8counter--;
2405 }
2406
2407 if((u8Data & 0x01)==0x00)
2408 {
2409 status = FALSE;
2410 }
2411
2412 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_config done\n"));
2413 return status;
2414 }
2415 /************************************************************************************************
2416 Subject: channel change config
2417 Function: INTERN_DVBS_Blind_Scan_Config
2418 Parmeter: BW: bandwidth
2419 Return: MS_BOOL :
2420 Remark:
2421 *************************************************************************************************/
INTERN_DVBS_BlindScan_Config(MS_U32 u32SymbolRate,DMD_DVBS_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)2422 MS_BOOL INTERN_DVBS_BlindScan_Config(MS_U32 u32SymbolRate, DMD_DVBS_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
2423 {
2424
2425 MS_BOOL status= true;
2426 MS_U16 u16CenterFreq;
2427 // MS_U16 u16Fc = 0;
2428 MS_U8 temp_val;
2429 MS_U8 u8Data=0;
2430 MS_U16 u16WaitCount = 0;
2431
2432 //MS_U32 u32CurrentSR;
2433
2434 //u32CurrentSR = u32SymbolRate/1000; //KHz
2435
2436 //u32SymbolRate= u32SymbolRate/1000;//to match fw format
2437 u16CenterFreq =u32IFFreq;
2438
2439 //DBG_INTERN_DVBS(printf(" @INTERN_DVBS_blindScan_Config+, SR=%d, QAM=%d, u32IFFreq=%d, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n", u32CurrentSR, eQamMode, u32IFFreq, bSpecInv, bSerialTS, u8TSClk));
2440 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_blindScan_Config, t = %d\n",(int)MsOS_GetSystemTime()));
2441
2442 //status &= INTERN_DVBS_Reset();
2443 /*
2444 g_dvbs_lock = 0;
2445 u8DemodLockFlag=0;
2446 // Symbol Rate
2447 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, u32CurrentSR&0xff);
2448 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, (u32CurrentSR>>8)&0xff);
2449 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, (u32CurrentSR>>16)&0xff);
2450 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config u32SymbolRate %d<<<\n", u32CurrentSR));
2451 */
2452 #if 0
2453 //======== check SR is right or not ===========
2454 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &u8Data);
2455 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L,u8Data));
2456 u32SR =u8Data;
2457 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &u8Data);
2458 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H,u8Data));
2459 u32SR =((U32)u8Data<<8)|u32SR ;
2460 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &u8Data);
2461 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MB_DMDTOP_DBG_5 addr=%d mailbox value=%d<<<\n", E_DMD_S2_MB_DMDTOP_DBG_5,u8Data));
2462 u32SR =((U32)u8Data<<16)|u32SR;
2463 //=================================================
2464 #endif
2465
2466 // IQ Swap ,ADCPLL IQ swap / DMDANA_IQ_SWAP
2467 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_IQ_SWAP, bSpecInv? 0x01:0x00);
2468 if(bSpecInv)
2469 {
2470 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DMDANA_REG_BASE+0xC0, &u8Data);//Demod\reg_dmdana.xls
2471 u8Data|=(0x02);
2472 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DMDANA_REG_BASE+0xC0, u8Data);
2473 }
2474
2475 // TS mode
2476 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, bSerialTS? 0x01:0x00);
2477 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Config TS Serial %d<<<\n", bSerialTS));
2478 _bSerialTS = bSerialTS;
2479 u8TSClk=0x05;//if (u8TSClk == 0xFF) u8TSClk=0x13;//set a fater speed for initial condition
2480
2481 if (bSerialTS)
2482 {
2483 // serial
2484 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2485 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2486
2487 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
2488 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2489 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2490 temp_val|=0x04;
2491 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2492 #else
2493 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2494 temp_val|=0x07;
2495 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2496 #endif
2497 }
2498 else
2499 {
2500 //parallel
2501 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2502 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2503
2504 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2505 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2506 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2507 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2508 temp_val|=0x05;
2509 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2510 #else
2511 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2512 temp_val|=0x07;
2513 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2514 #endif
2515 }
2516 #if (INTERN_DVBS_INTERNAL_DEBUG == 1)
2517 INTERN_DVBS_Show_Demod_Version();
2518 #endif
2519
2520 //-----------------------------------------------------------
2521 //From INTERN_DVBS_Demod_Restart function.
2522
2523 //enable send DiSEqC
2524 //[0]: 0: SW Reset, 1: Start state machine
2525 //[1]: 1: Blind scan enable, 0: manual scan
2526 //[2]: 1: Code flow track enable
2527 //[3]: 1: go to AGC state
2528 //[4]: 1: set DiSEqC
2529 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2530 u8Data |= 0x08;
2531 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2532
2533 u16WaitCount=0;
2534 do
2535 {
2536 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
2537 u16WaitCount++;
2538 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
2539 MsOS_DelayTask(1);
2540 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
2541
2542 // disable blind scan
2543 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2544 u8Data&=~(0x02);
2545 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2546
2547 //disble send DiSEqC
2548 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2549 u8Data&=~(0x08);
2550 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2551
2552
2553 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_blindScan_Config done\n"));
2554 return status;
2555 }
2556
INTERN_DVBS_Power_ON_OFF(MS_U8 bPowerOn)2557 void INTERN_DVBS_Power_ON_OFF(MS_U8 bPowerOn)
2558 {
2559 bPowerOn = bPowerOn;
2560 }
2561
INTERN_DVBS_Power_Save(void)2562 MS_BOOL INTERN_DVBS_Power_Save(void)
2563 {
2564 return TRUE;
2565 }
2566 //------------------------------------------------------------------
2567 // END System Info Function
2568 //------------------------------------------------------------------
2569
2570 //------------------------------------------------------------------
2571 // Get And Show Info Function
2572 //------------------------------------------------------------------
2573 /************************************************************************************************
2574 Subject: enable hw to lock channel
2575 Function: INTERN_DVBS_Active
2576 Parmeter: bEnable
2577 Return: MS_BOOL
2578 Remark:
2579 *************************************************************************************************/
INTERN_DVBS_Active(MS_BOOL bEnable)2580 MS_BOOL INTERN_DVBS_Active(MS_BOOL bEnable)
2581 {
2582 MS_U8 status = TRUE;
2583 //MS_U8 u8Data;
2584
2585 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_Active\n"));
2586
2587 //// INTERN_DVBS Finite State Machine on/off //////////
2588 #if 0
2589 gsCmdPacketDVBC.cmd_code = CMD_FSM_CTRL;
2590
2591 gsCmdPacketDVBS.param[0] = (MS_U8)bEnable;
2592 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 1);
2593 #else
2594
2595 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
2596 #endif
2597
2598 bDMD_DVBS_NoChannelDetectedWithRFPower = FALSE;
2599 u32DMD_DVBS_NoChannelTimeAccWithRFPower = 0;
2600 return status;
2601 }
2602
INTERN_DVBS_GetTsDivNum(MS_U32 * u32SymbolRate,MS_U8 * system_type_reg,MS_U8 * code_rate_idx,MS_U8 * fec_type_idx,MS_U8 * pilot_flag,MS_U32 * u32temp,MS_U8 * code_rate_reg)2603 MS_BOOL INTERN_DVBS_GetTsDivNum(MS_U32 *u32SymbolRate, MS_U8* system_type_reg, MS_U8 *code_rate_idx, MS_U8 *fec_type_idx, MS_U8 *pilot_flag, MS_U32 *u32temp, MS_U8 *code_rate_reg)
2604 {
2605 MS_U8 u8Data = 0;
2606 MS_BOOL status = true;
2607 //MS_U32 u32SymbolRate=0;
2608 //float fSymbolRate;
2609 //MS_U8 ISSY_EN = 0;
2610 //MS_U8 code_rate_idx = 0;
2611 //MS_U8 pilot_flag = 0;
2612 // MS_U8 fec_type_idx = 0;
2613 MS_U8 mod_type_idx = 0;
2614 //MS_U16 k_bch_array[2][11] ={
2615 // {16008, 21408, 25728, 32208, 38688, 43040, 48408, 51648, 53840, 57472, 58192},
2616 // { 3072, 5232, 6312, 7032, 9552, 10632, 11712, 12432, 13152, 14232, 0}};
2617 //MS_U16 n_ldpc_array[2] = {64800, 16200};
2618 //MS_FLOAT pilot_term = 0;
2619 //MS_FLOAT k_bch;
2620 //MS_FLOAT n_ldpc;
2621 //MS_FLOAT ts_div_num_offset = 2.0;
2622 //MS_U32 u32Time_start,u32Time_end;
2623 //MS_U32 u32temp;
2624 //MS_FLOAT pkt_interval;
2625 //MS_U8 time_counter=0;
2626
2627 INTERN_DVBS_GetCurrentSymbolRate(u32SymbolRate);
2628 //fSymbolRate=u32SymbolRate+0.0;///1000.0;//Symbol Rate(KHz)
2629 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum u32SymbolRate=%d\n", (int)*u32SymbolRate));
2630 // DMD_DVBS_MODULATION_TYPE pQAMMode;
2631
2632 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//V
2633 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum GetCurrentDemodType E_DMD_S2_SYSTEM_TYPE=%d\n", u8Data));//u8Data:0 is S2; 1 is DVBS
2634 *system_type_reg=u8Data;
2635 if(!u8Data)//DVBS2
2636 {
2637 /*
2638 //Get DVBS2 Code Rate
2639 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);//V
2640 printf("[S2]INTERN_DVBS_GetTsDivNum DVBS2 E_DMD_S2_CODERATE=0x%x\n", u8Data);
2641 switch (u8Data)
2642 {
2643 case 0x03: //CR 1/2
2644 k_bch=32208.0;
2645 _u8_DVBS2_CurrentCodeRate = 5;
2646 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_2\n"));
2647 break;
2648 case 0x01: //CR 1/3
2649 k_bch=21408.0; //8PSK???
2650 _u8_DVBS2_CurrentCodeRate = 6;
2651 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_3\n"));
2652 break;
2653 case 0x05: //CR 2/3
2654 k_bch=43040.0;
2655 _u8_DVBS2_CurrentCodeRate = 7;
2656 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=2_3\n"));
2657 break;
2658 case 0x00: //CR 1/4
2659 k_bch=16008.0; //8PSK???
2660 _u8_DVBS2_CurrentCodeRate = 8;
2661 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_4\n"));
2662 break;
2663 case 0x06: //CR 3/4
2664 k_bch=48408.0;
2665 _u8_DVBS2_CurrentCodeRate = 9;
2666 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=3_4\n"));
2667 break;
2668 case 0x02: //CR 2/5
2669 k_bch=25728.0; //8PSK???
2670 _u8_DVBS2_CurrentCodeRate = 10;
2671 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=2_5\n"));
2672 break;
2673 case 0x04: //CR 3/5
2674 k_bch=38688.0;
2675 _u8_DVBS2_CurrentCodeRate = 11;
2676 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=3_5\n"));
2677 break;
2678 case 0x07: //CR 4/5
2679 k_bch=51648.0;
2680 _u8_DVBS2_CurrentCodeRate = 12;
2681 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=4_5\n"));
2682 break;
2683 case 0x08: //CR 5/6
2684 k_bch=53840.0;
2685 _u8_DVBS2_CurrentCodeRate = 13;
2686 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=5_6\n"));
2687 break;
2688 case 0x09: //CR 8/9
2689 k_bch=57472.0;
2690 _u8_DVBS2_CurrentCodeRate = 14;
2691 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=8_9\n"));
2692 break;
2693 case 0x0A: //CR 9/10
2694 k_bch=58192.0;
2695 _u8_DVBS2_CurrentCodeRate = 15;
2696 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=9_10\n"));
2697 break;
2698 default:
2699 k_bch=58192.0;
2700 _u8_DVBS2_CurrentCodeRate = 15;
2701 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate= default 9_10\n"));
2702 break;
2703 } //printf("INTERN_DVBS_GetTsDivNum k_bch=%ld\n", (MS_U32)k_bch);
2704 */
2705 //INTERN_DVBS_GetCurrentModulationType(&pQAMMode); //V
2706 //printf("INTERN_DVBS_GetTsDivNum Mod_order=%d\n", modulation_order);
2707
2708 // pilot_flag => 0 : off 1 : on
2709 // fec_type_idx => 0 : normal 1 : short
2710 // mod_type_idx => 0 : QPSK 1 : 8PSK 2 : 16APSK 3 : 32APSK
2711 // code_rate_idx => d0: 1/4, d1: 1/3, d2: 2/5, d3: 1/2, d4: 3/5, d5: 2/3, d6: 3/4, d7: 4/5, d8: 5/6, d9: 8/9, d10: 9/10
2712 //set TS clock rate
2713 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, code_rate_idx);
2714 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FEC_TYPE, fec_type_idx);
2715 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MOD_TYPE, &mod_type_idx);
2716 modulation_order = mod_type_idx;
2717 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_PILOT_FLAG, pilot_flag);
2718 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_PILOT_FLAG, &u8Data);
2719
2720 /*
2721 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_ISSY_ACTIVE, ISSY_EN);
2722 if(*ISSY_EN==0)
2723 {
2724 k_bch = k_bch_array[fec_type_idx][code_rate_idx];
2725 n_ldpc = n_ldpc_array[fec_type_idx];
2726 pilot_term = ((float) n_ldpc / modulation_order / 1440 * 36) * pilot_flag;
2727 if(sDMD_DVBS_Info.bSerialTS)//serial mode
2728 {
2729 *fTSDivNum =(288000.0/(k_bch/((n_ldpc/modulation_order+90+pilot_term)/u32SymbolRate)) - ts_div_num_offset);
2730 *fTSDivNum = (*fTSDivNum-1)/2;// since 288/(2(fTSDivNum+1)) = 288/TS_RATE = A ==> fTSDivNum = (A-1)/2
2731 }
2732 else//parallel mode
2733 {
2734 *fTSDivNum = (288000.0/(k_bch/((n_ldpc/modulation_order+90+pilot_term)/u32SymbolRate)/8) - ts_div_num_offset);
2735 *fTSDivNum = (*fTSDivNum-1)/2;
2736 }
2737 }
2738 else if(*ISSY_EN==1)//ISSY = 1
2739 {
2740 //u32Time_start = msAPI_Timer_GetTime0();
2741 time_counter=0;
2742 do
2743 {
2744 MDrv_SYS_DMD_VD_MBX_ReadReg((0x3E00 + 0x4D*2), &u8Data);//DVBS2OPPRO_ISCR_CAL_DONE (_REG_DVBS2OPPRO(0x4D)+0)
2745 u8Data &= 0x01;
2746 // u32Time_end =msAPI_Timer_GetTime0();
2747 MsOS_DelayTask(1);
2748 time_counter = time_counter +1;
2749 }while( (u8Data!=0x01) && ( (time_counter )< 50) );
2750
2751 //read pkt interval
2752 MDrv_SYS_DMD_VD_MBX_ReadReg((0x3E00 + 0x70*2), &u8Data);
2753 *u32temp = u8Data;
2754 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x70*2+1), &u8Data);
2755 *u32temp |= (MS_U32)u8Data<<8;
2756 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x71*2), &u8Data);
2757 *u32temp |= (MS_U32)u8Data<<16;
2758 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x71*2+1), &u8Data);
2759 *u32temp |= (MS_U32)u8Data<<24;
2760
2761 pkt_interval = (MS_FLOAT) u32temp / 1024.0;
2762 if(sDMD_DVBS_Info.bSerialTS)//serial mode
2763 {
2764 *fTSDivNum=288000.0 / (188*8*u32SymbolRate/pkt_interval) - ts_div_num_offset;
2765 *fTSDivNum = (*fTSDivNum-1)/2;
2766 }
2767 else
2768 {
2769 *fTSDivNum=288000.0 / (188*u32SymbolRate/pkt_interval) - ts_div_num_offset;
2770 *fTSDivNum = (*fTSDivNum-1)/2;
2771 }
2772
2773 }
2774 else
2775 {
2776 // *fTSDivNum =0x0A;
2777 }
2778
2779 if(*fTSDivNum>255)
2780 *fTSDivNum=255;
2781 if(*fTSDivNum<1)
2782 *fTSDivNum=1;
2783 */
2784 #if 0
2785 //printf("INTERN_DVBS_GetTsDivNum Pilot E_DMD_S2_MB_DMDTOP_DBG_9=%d\n", u8Data);
2786 /*if(u8Data) // Pilot ON
2787 printf(">>>INTERN_DVBS_GetTsDivNum Pilot ON<<<\n");
2788 else //Pilot off
2789 printf(">>>INTERN_DVBS_GetTsDivNum Pilot off<<<\n");
2790 */
2791 if(_bSerialTS)
2792 {
2793 if(u8Data)//if pilot ON
2794 {
2795 if(modulation_order==2)
2796 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90+36*22)/u32SymbolRate)) - 3);
2797 else if(modulation_order==3)
2798 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90+36*15)/u32SymbolRate)) - 3);
2799 }
2800 else
2801 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90)/u32SymbolRate)) - 3);
2802 }
2803 else//Parallel mode
2804 {
2805 if(u8Data)
2806 {
2807 if(modulation_order==2)
2808 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0+36*22)/u32SymbolRate)/8.0) - 3);
2809 else if(modulation_order==3)
2810 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0+36*15)/u32SymbolRate)/8.0) - 3);
2811 }
2812 else
2813 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0)/u32SymbolRate)/8.0) - 3);
2814 }
2815 #endif
2816 }
2817 else //S
2818 {
2819 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE + 0x3A*2, &u8Data);
2820 //u8_gCodeRate = (u8Data & 0x70)>>4;
2821 //DVBS Code Rate
2822 //switch (u8_gCodeRate)
2823 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
2824 *code_rate_reg=u8Data;
2825 switch (u8Data)
2826 {
2827 case 0x00: //CR 1/2
2828 _u8_DVBS2_CurrentCodeRate = 0;
2829 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=1_2\n"));
2830 /*
2831 if(sDMD_DVBS_Info.bSerialTS)
2832 *fTSDivNum = (288000.0/((1.0/2.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2833 else
2834 *fTSDivNum = (288000.0/((1.0/2.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2835
2836 *fTSDivNum = (*fTSDivNum-1)/2;
2837 if(*fTSDivNum>255)
2838 *fTSDivNum=255;
2839 if(*fTSDivNum<1)
2840 *fTSDivNum=1;
2841 */
2842 break;
2843 case 0x01: //CR 2/3
2844 _u8_DVBS2_CurrentCodeRate = 1;
2845 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=2_3\n"));
2846 /*
2847 if(sDMD_DVBS_Info.bSerialTS)
2848 *fTSDivNum = (MS_U8)(288000.0/((2.0/3.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2849 else
2850 *fTSDivNum = (MS_U8)(288000.0/((2.0/3.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2851
2852 *fTSDivNum = (*fTSDivNum-1)/2;
2853 if(*fTSDivNum>255)
2854 *fTSDivNum=255;
2855 if(*fTSDivNum<1)
2856 *fTSDivNum=1;
2857 */
2858 break;
2859 case 0x02: //CR 3/4
2860 _u8_DVBS2_CurrentCodeRate = 2;
2861 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=3_4\n"));
2862 /*
2863 if(sDMD_DVBS_Info.bSerialTS)
2864 *fTSDivNum = (288000.0/((3.0/4.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2865 else
2866 *fTSDivNum = (288000.0/((3.0/4.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2867 *fTSDivNum = (*fTSDivNum-1)/2;
2868 if(*fTSDivNum>255)
2869 *fTSDivNum=255;
2870 if(*fTSDivNum<1)
2871 *fTSDivNum=1;
2872 */
2873 break;
2874 case 0x03: //CR 5/6
2875 _u8_DVBS2_CurrentCodeRate = 3;
2876 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=5_6\n"));
2877 /*
2878 if(sDMD_DVBS_Info.bSerialTS)
2879 *fTSDivNum = (288000.0/((5.0/6.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2880 else
2881 *fTSDivNum = (288000.0/((5.0/6.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2882
2883 *fTSDivNum = (*fTSDivNum-1)/2;
2884 if(*fTSDivNum>255)
2885 *fTSDivNum=255;
2886 if(*fTSDivNum<1)
2887 *fTSDivNum=1;
2888 */
2889 break;
2890 case 0x04: //CR 7/8
2891 _u8_DVBS2_CurrentCodeRate = 4;
2892 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=7_8\n"));
2893 /*
2894 if(sDMD_DVBS_Info.bSerialTS)
2895 *fTSDivNum =(288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2896 else
2897 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2898
2899 *fTSDivNum = (*fTSDivNum-1)/2;
2900 if(*fTSDivNum>255)
2901 *fTSDivNum=255;
2902 if(*fTSDivNum<1)
2903 *fTSDivNum=1;
2904 */
2905 break;
2906 default:
2907 _u8_DVBS2_CurrentCodeRate = 4;
2908 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate= default 7_8\n"));
2909 /*
2910 if(sDMD_DVBS_Info.bSerialTS)
2911 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2912 else
2913 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2914
2915 *fTSDivNum = (*fTSDivNum-1)/2;
2916 if(*fTSDivNum>255)
2917 *fTSDivNum=255;
2918 if(*fTSDivNum<1)
2919 *fTSDivNum=1;
2920 */
2921 break;
2922 }
2923 } //printf("INTERN_DVBS_GetTsDivNum u8TSClk = 0x%x\n", *u8TSDivNum);
2924 return status;
2925 }
2926
INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK_TYPE eType,MS_U16 fCurrRFPowerDbm,MS_U16 fNoChannelRFPowerDbm,MS_U32 u32TimeInterval)2927 MS_BOOL INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK_TYPE eType, MS_U16 fCurrRFPowerDbm, MS_U16 fNoChannelRFPowerDbm, MS_U32 u32TimeInterval)
2928 {
2929 MS_U8 u8Data =0; //MS_U8 u8Data2 =0;
2930 MS_U8 bRet = TRUE;
2931 //MS_FLOAT fTSDivNum=0;
2932
2933 switch( eType )
2934 {
2935 case DMD_DVBS_GETLOCK:
2936 #if (INTERN_DVBS_INTERNAL_DEBUG)
2937 INTERN_DVBS_info();
2938 #endif
2939 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2940 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_GetLock manual tune=%d<<<\n", u8Data));
2941 if ((u8Data&0x02)==0x00)//manual mode
2942 {
2943 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);
2944 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_GetLock MailBox state=%d<<<\n", u8Data));
2945
2946 if((u8Data == 15) || (u8Data == 16))
2947 {
2948 if (u8Data==15)
2949 {
2950 _bDemodType=FALSE; //S
2951 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Demod DVBS Lock<<<\n"));
2952 }
2953 else if(u8Data==16)
2954 {
2955 _bDemodType=TRUE; //S2
2956 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Demod DVBS2 Lock<<<\n"));
2957 }
2958 if(g_dvbs_lock == 0)
2959 {
2960 g_dvbs_lock = 1;
2961 }
2962
2963 if(u8DemodLockFlag==0)
2964 {
2965 u8DemodLockFlag=1;
2966
2967 // caculate TS clock divider number
2968 /*
2969 INTERN_DVBS_GetTsDivNum(&fTSDivNum); //ts_div_num
2970 u8Data = (MS_U8)fTSDivNum;
2971 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_GetLock TsClkDivNum = 0x%x<<<\n", u8Data));
2972
2973 if (u8Data > 0x1F)
2974 u8Data=0x1F;
2975 //if (u8Data < 0x05) u8Data=0x05;
2976 HAL_DMD_RIU_WriteByte(0x103300, u8Data);
2977
2978 //Ts Output Enable
2979 HAL_DMD_RIU_WriteByte(0x101eaa,0x10);
2980 */
2981 }
2982 DBG_INTERN_DVBS(ULOGD("DEMOD","@INTERN_DVBS_Demod Lock+++\n"));
2983 bRet = TRUE;
2984 }
2985 else
2986 {
2987 if(g_dvbs_lock == 1)
2988 {
2989 g_dvbs_lock = 0;
2990 u8DemodLockFlag=0;
2991 }
2992 DBG_INTERN_DVBS(ULOGD("DEMOD","@INTERN_DVBS_Demod UnLock---\n"));
2993 bRet = FALSE;
2994 }
2995
2996 if(_bSerialTS==1)
2997 {
2998 if (bRet==FALSE)
2999 {
3000 _bTSDataSwap=FALSE;
3001 }
3002 else
3003 {
3004 if (_bTSDataSwap==FALSE)
3005 {
3006 _bTSDataSwap=TRUE;
3007 MDrv_SYS_DMD_VD_MBX_ReadReg( (DVBTM_REG_BASE + 0x20*2), &u8Data);//DVBTM_REG_BASE
3008 u8Data^=0x20;//h0020 h0020 5 5 reg_ts_data_reverse
3009 MDrv_SYS_DMD_VD_MBX_WriteReg( (DVBTM_REG_BASE + 0x20*2), u8Data);
3010 }
3011 }
3012 }
3013 }
3014 else
3015 {
3016 bRet = TRUE;
3017 }
3018 break;
3019
3020 default:
3021 bRet = FALSE;
3022 }
3023 return bRet;
3024 }
3025
INTERN_DVBS_GetTunrSignalLevel_PWR(MS_U16 * u16Data)3026 MS_BOOL INTERN_DVBS_GetTunrSignalLevel_PWR(MS_U16 *u16Data)// Need check debug out table
3027 {
3028 MS_BOOL status=TRUE;
3029 MS_U8 u8Data =0;
3030 //MS_U8 u8Index =0;
3031 //float fCableLess = 0.0;
3032 /*
3033 if (FALSE == INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0) )//Demod unlock
3034 {
3035 fCableLess = 0;
3036 }
3037 */
3038 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x11*2, &u8Data);//FRONTEND_AGC_DEBUG_SEL
3039 u8Data=(u8Data&0xF0)|0x03;
3040 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x11*2, u8Data);
3041
3042 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x02, &u8Data);//FRONTEND_LATCH
3043 u8Data|=0x80;
3044 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x02, u8Data);
3045
3046 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x12*2+1, &u8Data);//FRONTEND_AGC_DEBUG_OUT_R1
3047 *u16Data=u8Data;
3048 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x12*2, &u8Data);//FRONTEND_AGC_DEBUG_OUT_R0
3049 *u16Data=(*u16Data<<8)|u8Data;
3050 //printf("===========================Tuner 65535-u16Data = %d\n", (65535-u16Data));
3051 //MsOS_DelayTask(400);
3052
3053 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x02, &u8Data);//FRONTEND_LOAD0
3054 u8Data&=~(0x80);
3055 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x02, u8Data);
3056 /*
3057 if (status==FALSE)
3058 {
3059 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS GetSignalStrength fail!!! \n "));
3060 fCableLess = 0;
3061 }
3062 */
3063 // printf("#### INTERN_DVBS_GetTunrSignalLevel_PWR u16Data = %d\n", (int)u16Data);
3064 /*
3065 for (u8Index=0; u8Index < (sizeof(_u16SignalLevel)/sizeof(_u16SignalLevel[0])); u8Index++)
3066 {
3067 if ((65535 - u16Data) <= _u16SignalLevel[u8Index][0])
3068 {
3069 if (u8Index >=1)
3070 {
3071 fCableLess = (float)(_u16SignalLevel[u8Index][1])+((float)(_u16SignalLevel[u8Index][0] - (65535 - u16Data)) / (float)(_u16SignalLevel[u8Index][0] - _u16SignalLevel[u8Index-1][0]))*(float)(_u16SignalLevel[u8Index-1][1] - _u16SignalLevel[u8Index][1]);
3072 }
3073 else
3074 {
3075 fCableLess = _u16SignalLevel[u8Index][1];
3076 }
3077 }
3078 }
3079 //---------------------------------------------------
3080 if (fCableLess >= 350)
3081 fCableLess = fCableLess - 35;
3082 else if ((fCableLess < 350) && (fCableLess >= 250))
3083 fCableLess = fCableLess - 25;
3084 else
3085 fCableLess = fCableLess - 5;
3086
3087 if (fCableLess < 0)
3088 fCableLess = 0;
3089 if (fCableLess > 920)
3090 fCableLess = 920;
3091
3092 fCableLess = (-1.0)*(fCableLess/10.0);
3093
3094 //printf("===========================fCableLess2 = %.2f\n",fCableLess);
3095
3096 DBG_INTERN_DVBS(printf("INTERN_DVBS GetSignalStrength %f\n", fCableLess));
3097 */
3098 return status;
3099 }
3100
3101 /****************************************************************************
3102 Subject: To get the Post viterbi BER
3103 Function: INTERN_DVBS_GetPostViterbiBer
3104 Parmeter: Quility
3105 Return: E_RESULT_SUCCESS
3106 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBC_VIT_STATUS_NG
3107 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
3108 We will not read the Period, and have the "/256/8"
3109 *****************************************************************************/
3110
INTERN_DVBS_GetPostViterbiBer(MS_U32 * BitErr,MS_U16 * BitErrPeriod)3111 MS_BOOL INTERN_DVBS_GetPostViterbiBer(MS_U32 *BitErr, MS_U16 *BitErrPeriod)//POST BER //V
3112 {
3113 MS_BOOL status = true;
3114 MS_U8 reg = 0, reg_frz = 0;
3115 //MS_U16 BitErrPeriod;
3116 //MS_U32 BitErr;
3117
3118 /////////// Post-Viterbi BER /////////////After Viterbi
3119
3120 // freeze ,DVBSRS_BACKEND_BIT_ERR_NUM_FREEZE
3121 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1*2+1, ®_frz);//h0001 h0001 8 8 reg_ber_en
3122 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x1*2+1, reg_frz|0x01);
3123
3124 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0 ,DVBSFEC_BIT_ERR_SBLPRD_7_0
3125 // 0x47 [15:8] reg_bit_err_sblprd_15_8
3126 //KRIS register table
3127 //h0018 h0018 7 0 reg_bit_err_sblprd_7_0
3128 //h0018 h0018 15 8 reg_bit_err_sblprd_15_8
3129 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x18*2+1, ®);
3130 *BitErrPeriod = reg;
3131
3132 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x18*2, ®);
3133 *BitErrPeriod = (*BitErrPeriod << 8)|reg;
3134
3135
3136 //h001d h001d 7 0 reg_bit_err_num_7_0
3137 //h001d h001d 15 8 reg_bit_err_num_15_8
3138 //h001e h001e 7 0 reg_bit_err_num_23_16
3139 //h001e h001e 15 8 reg_bit_err_num_31_24
3140
3141 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1E*2+1, ®);
3142 *BitErr = reg;
3143 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1E*2, ®);
3144 *BitErr = (*BitErr << 8)|reg;
3145 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1D*2+1, ®);
3146 *BitErr = (*BitErr << 8)|reg;
3147 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1D*2, ®);
3148 *BitErr = (*BitErr << 8)|reg;
3149
3150 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
3151 reg_frz=reg_frz&(~0x01);
3152 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x1*2+1, reg_frz);
3153 /*
3154 if (BitErrPeriod == 0 ) //PRD
3155 BitErrPeriod = 1;
3156
3157 if (BitErr <= 0 )
3158 *postber = 0.5f / ((float)BitErrPeriod*128*188*8);
3159 else
3160 *postber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
3161
3162 if (*postber <= 0.0f)
3163 *postber = 1.0e-10f;
3164
3165 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS PostVitBER = %8.3e \n", *postber));
3166 */
3167 return status;
3168 }
3169
3170
INTERN_DVBS_GetPreViterbiBer(float * preber)3171 MS_BOOL INTERN_DVBS_GetPreViterbiBer(float *preber)//PER BER // not yet
3172 {
3173 MS_BOOL status = true;
3174 //MS_U8 reg = 0, reg_frz = 0;
3175 //MS_U16 BitErrPeriod;
3176 //MS_U32 BitErr;
3177
3178 #if 0
3179 /////////// Pre-Viterbi BER /////////////Before Viterbi
3180
3181 // freeze ,DVBSRS_BACKEND_BIT_ERR_NUM_FREEZE
3182 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x10, ®_frz);
3183 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSTFEC_REG_BASE+0x10, reg_frz|0x08);
3184
3185 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0 ,DVBSFEC_BIT_ERR_SBLPRD_7_0
3186 // 0x47 [15:8] reg_bit_err_sblprd_15_8
3187 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x19, ®);
3188 BitErrPeriod = reg;
3189
3190 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x18, ®);
3191 BitErrPeriod = (BitErrPeriod << 8)|reg;
3192
3193 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x17, ®);
3194 BitErrPeriod = (BitErrPeriod << 8)|reg;
3195
3196 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x16, ®);
3197 BitErrPeriod = (BitErrPeriod << 8)|reg;
3198 BitErrPeriod = (BitErrPeriod & 0x3FFF);
3199
3200 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
3201 // 0x6b [15:8] reg_bit_err_num_15_8
3202 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
3203 // 0x6d [15:8] reg_bit_err_num_31_24
3204 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x1F, ®);
3205 BitErr = reg;
3206
3207 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x1E, ®);
3208 BitErr = (BitErr << 8)|reg;
3209
3210 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
3211 reg_frz=reg_frz&(~0x08);
3212 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x10, reg_frz);
3213
3214 if (BitErrPeriod ==0 )//protect 0
3215 BitErrPeriod=1;
3216 if (BitErr <=0 )
3217 *perber=0.5f / (float)BitErrPeriod / 256;
3218 else
3219 *perber=(float)BitErr / (float)BitErrPeriod / 256;
3220
3221 if (*perber <= 0.0f)
3222 *perber = 1.0e-10f;
3223
3224 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS PerVitBER = %8.3e \n", *perber));
3225 #endif
3226
3227 return status;
3228 }
3229
3230 /****************************************************************************
3231 Subject: To get the Packet error
3232 Function: INTERN_DVBS_GetPacketErr
3233 Parmeter: pktErr
3234 Return: E_RESULT_SUCCESS
3235 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
3236 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
3237 We will not read the Period, and have the "/256/8"
3238 *****************************************************************************/
INTERN_DVBS_GetPacketErr(MS_U16 * pktErr)3239 MS_BOOL INTERN_DVBS_GetPacketErr(MS_U16 *pktErr)//V
3240 {
3241 MS_BOOL status = true;
3242 MS_U8 u8Data = 0;
3243 MS_U16 u16PktErr = 0;
3244
3245 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);
3246 if(!u8Data) //DVB-S2
3247 {
3248 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x02*2, &u8Data);//DVBS2FEC_OUTER_FREEZE (_REG_DVBS2FEC(0x02)+0) //[0]
3249 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE+0x02*2, u8Data|0x01);
3250
3251 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x26*2+1, &u8Data);//DVBS2FEC_BCH_EFLAG2_SUM1 (_REG_DVBS2FEC(0x2B)+1)
3252 u16PktErr = u8Data;
3253 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x26*2, &u8Data);
3254 u16PktErr = (u16PktErr << 8)|u8Data;
3255
3256 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x02*2, &u8Data);
3257 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE+0x02*2, u8Data&(~0x01));
3258 }
3259 else
3260 { //DVB-S
3261 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x19*2, &u8Data); //0x19 [7] reg_bit_err_num_freeze
3262 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x19*2, u8Data|0x80);
3263
3264 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(REG_BACKEND+0x33*2+1, &u8Data);// DVBSFEC_UNCRT_PKT_NUM_15_8 (_REG_DVBSFEC(0x1F)+1)
3265 u16PktErr = u8Data;
3266 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(REG_BACKEND+0x33*2, &u8Data);
3267 u16PktErr = (u16PktErr << 8)|u8Data;
3268
3269 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x19*2, &u8Data); //0x19 [7] reg_bit_err_num_freeze
3270 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x19*2, u8Data&(~0x80));
3271 }
3272 *pktErr = u16PktErr;
3273
3274 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS PktErr = %d \n", (int)u16PktErr));
3275
3276 return status;
3277 }
3278
3279 /****************************************************************************
3280 Subject: Read the signal to noise ratio (SNR)
3281 Function: INTERN_DVBS_GetSNR
3282 Parmeter: None
3283 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
3284 Remark:
3285 *****************************************************************************/
3286
INTERN_DVBS_GetSNR(MS_U32 * u32NDA_SNR_A,MS_U32 * u32NDA_SNR_AB)3287 MS_BOOL INTERN_DVBS_GetSNR(MS_U32 *u32NDA_SNR_A, MS_U32 *u32NDA_SNR_AB)//V
3288 {
3289 MS_BOOL status= TRUE;
3290 MS_U8 u8Data =0, reg_frz =0;
3291 //NDA SNR
3292 // MS_U32 u32NDA_SNR_A =0;
3293 //MS_U32 u32NDA_SNR_AB =0;
3294 //NDA SNR
3295 //float NDA_SNR_A =0.0;
3296 //float NDA_SNR_AB =0.0;
3297 //float NDA_SNR =0.0;
3298 //double NDA_SNR_LINEAR=0.0;
3299 //float snr_poly =0.0;
3300 //float Fixed_SNR =0.0;
3301 /*
3302 if (INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0)== FALSE)
3303 {
3304 return 0;
3305 }
3306 */
3307 // freeze
3308 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE+0x04*2, ®_frz);
3309 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_INNER_REG_BASE+0x04*2, reg_frz|0x10);//INNE_LATCH bit[4]
3310
3311 //NDA SNR_A
3312 // read Linear_SNR
3313 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x47*2, &u8Data);
3314 *u32NDA_SNR_A=(u8Data&0x03);
3315 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x46*2 + 1, &u8Data);
3316 *u32NDA_SNR_A=(*u32NDA_SNR_A<<8)|u8Data;
3317 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x46*2, &u8Data);
3318 *u32NDA_SNR_A=(*u32NDA_SNR_A<<8)|u8Data;
3319 //NDA SNR_AB
3320 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x49*2+1, &u8Data);
3321 *u32NDA_SNR_AB=(u8Data&0x3F);
3322 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x49*2, &u8Data);
3323 *u32NDA_SNR_AB = (*u32NDA_SNR_AB<<8)|u8Data;
3324 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x48*2 + 1, &u8Data);
3325 *u32NDA_SNR_AB=(*u32NDA_SNR_AB<<8)|u8Data;
3326 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x48*2, &u8Data);
3327 *u32NDA_SNR_AB=(*u32NDA_SNR_AB<<8)|u8Data;
3328
3329 //UN_freeze
3330 reg_frz=reg_frz&(~0x10);
3331 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_INNER_REG_BASE+0x08, reg_frz);
3332
3333 if (status== FALSE)
3334 {
3335 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetSNR Fail! \n"));
3336 return 0;
3337 }
3338
3339 //NDA SNR
3340 //NDA_SNR_A=(float)u32NDA_SNR_A/65536;
3341 //NDA_SNR_AB=(float)u32NDA_SNR_AB/4194304;
3342 //
3343 //since support 16,32APSK we need to add judgement
3344 /*
3345 if(modulation_order==4)
3346 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB/(2-1.252295758529242));//for 16APSK CR2/3
3347 else if(modulation_order==5)//(2-1.41333232789)
3348 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB/(2-1.41333232789));//for 32APSK CR3/4
3349 else
3350 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB);
3351
3352 NDA_SNR_LINEAR =(1/((NDA_SNR_A/NDA_SNR_AB)-1)) ;
3353
3354 if(NDA_SNR_LINEAR<=0)
3355 NDA_SNR=1.0;
3356 else
3357 NDA_SNR=10*log10(NDA_SNR_LINEAR);
3358
3359 //printf("[DVBS]: NDA_SNR ================================: %.1f\n", NDA_SNR);
3360 _f_DVBS_CurrentSNR = NDA_SNR;
3361 */
3362 /*
3363 //[DVBS/S2, QPSK/8PSK, 1/2~9/10 the same CN]
3364 snr_poly = 0.0; //use Polynomial curve fitting to fix SNR
3365 snr_poly = 0.005261367463671*pow(NDA_SNR, 3)-0.116517828301214*pow(NDA_SNR, 2)+0.744836970505452*pow(NDA_SNR, 1)-0.86727609780167;
3366 Fixed_SNR = NDA_SNR + snr_poly;
3367 //printf("[DVBS]: NDA_SNR + snr_poly =====================: %.1f\n", Fixed_SNR);
3368
3369 if (Fixed_SNR < 17.0)
3370 Fixed_SNR = Fixed_SNR;
3371 else if ((Fixed_SNR < 20.0) && (Fixed_SNR >= 17.0))
3372 Fixed_SNR = Fixed_SNR - 0.8;
3373 else if ((Fixed_SNR < 22.5) && (Fixed_SNR >= 20.0))
3374 Fixed_SNR = Fixed_SNR - 2.0;
3375 else if ((Fixed_SNR < 27.0) && (Fixed_SNR >= 22.5))
3376 Fixed_SNR = Fixed_SNR - 3.0;
3377 else if ((Fixed_SNR < 29.0) && (Fixed_SNR >= 27.0))
3378 Fixed_SNR = Fixed_SNR - 3.5;
3379 else if (Fixed_SNR >= 29.0)
3380 Fixed_SNR = Fixed_SNR - 3.0;
3381
3382 if (Fixed_SNR < 1.0)
3383 Fixed_SNR = 1.0;
3384 if (Fixed_SNR > 30.0)
3385 Fixed_SNR = 30.0;
3386 */
3387 //*f_snr = NDA_SNR;
3388 //printf("[DVBS]: NDA_SNR=============================: %.1f\n", NDA_SNR);
3389
3390 return status;
3391 }
3392
INTERN_DVBS_GetIFAGC(MS_U8 * ifagc_reg,MS_U8 * ifagc_reg_lsb,MS_U16 * ifagc_err)3393 MS_BOOL INTERN_DVBS_GetIFAGC(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err)
3394 {
3395 MS_BOOL status = true;
3396
3397 status = HAL_DMD_IFAGC_RegRead(ifagc_reg, ifagc_reg_lsb, ifagc_err);
3398
3399 return status;
3400 }
3401
3402 //SSI
INTERN_DVBS_GetSignalStrength(MS_U16 fRFPowerDbm,DMD_DVBS_DEMOD_TYPE * pDemodType,MS_U8 * u8_DVBS2_CurrentCodeRateLocal,MS_U8 * u8_DVBS2_CurrentConstellationLocal)3403 MS_BOOL INTERN_DVBS_GetSignalStrength(MS_U16 fRFPowerDbm, DMD_DVBS_DEMOD_TYPE *pDemodType, MS_U8 *u8_DVBS2_CurrentCodeRateLocal, MS_U8 *u8_DVBS2_CurrentConstellationLocal)
3404 {
3405 //-1.2~-92.2 dBm
3406 MS_BOOL status = true;
3407 MS_U8 u8Data =0;
3408 //MS_U8 _u8_DVBS2_CurrentCodeRateLocal = 0;
3409 //float ch_power_db=0.0f, ch_power_db_rel=0.0f;
3410 MS_U8 u8Data2 = 0;
3411 //MS_U8 _u8_DVBS2_CurrentConstellationLocal = 0;
3412 //DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3413
3414 //DBG_INTERN_DVBS_TIME(printf("INTERN_DVBS_GetSignalStrength, t=%ld, RF level=%f, Table=%lx\n",MsOS_GetSystemTime(), fRFPowerDbm, (MS_U32)(sDMD_DVBS_InitData->pTuner_RfagcSsi)));
3415
3416 // if (INTERN_DVBC_Lock(COFDM_TPS_LOCK))
3417 // if (INTERN_DVBC_Lock(COFDM_AGC_LOCK))
3418 // Actually, it's more reasonable, that signal level depended on cable input power level
3419 // thougth the signal isn't dvb-t signal.
3420 //
3421 // use pointer of IFAGC table to identify
3422 // case 1: RFAGC from SAR, IFAGC controlled by demod
3423 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
3424 //status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
3425 // sDMD_DVBS_InitData->pTuner_RfagcSsi, sDMD_DVBS_InitData->u16Tuner_RfagcSsi_Size,
3426 // sDMD_DVBS_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBS_InitData->u16Tuner_IfagcSsi_HiRef_Size,
3427 // sDMD_DVBS_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBS_InitData->u16Tuner_IfagcSsi_LoRef_Size,
3428 // sDMD_DVBS_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBS_InitData->u16Tuner_IfagcErr_HiRef_Size,
3429 // sDMD_DVBS_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBS_InitData->u16Tuner_IfagcErr_LoRef_Size);
3430 //ch_power_db = INTERN_DVBS_GetTunrSignalLevel_PWR();
3431 //printf("@@@@@@@@@ ch_power_db = %f \n", ch_power_db);
3432
3433
3434
3435
3436 status &= INTERN_DVBS_GetCurrentDemodType(pDemodType);
3437
3438 if((MS_U8)*pDemodType == (MS_U8)DMD_SAT_DVBS)//S
3439 {
3440 /*
3441 float fDVBS_SSI_Pref[]=
3442 {
3443 //0, 1, 2, 3, 4
3444 -78.9, -77.15, -76.14, -75.19, -74.57,//QPSK
3445 };
3446 */
3447 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE + 0x84, &u8Data);
3448 *u8_DVBS2_CurrentCodeRateLocal = (u8Data & 0x07);
3449 //ch_power_db_rel = ch_power_db - fDVBS_SSI_Pref[_u8_DVBS2_CurrentCodeRateLocal];
3450 }
3451 else
3452 {
3453 /*
3454 float fDVBS2_SSI_Pref[][11]=
3455 {
3456 // 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
3457 //1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10
3458 {-85.17, -84.08, -83.15, -81.86, -80.63, -79.77, -78.84, -78.19, -77.69, -76.68, -76.46}, //QPSK
3459 { 0.0, 0.0, 0.0, 0.0, -77.36, -76.24, -74.95, 0.0, -73.52, -72.18, -71.84} //8PSK
3460 };
3461 */
3462 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
3463 *u8_DVBS2_CurrentCodeRateLocal = (u8Data & 0x3C)>>2;
3464
3465 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
3466 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD6, &u8Data2);
3467
3468 if(((u8Data & 0x03)==0x01) && ((u8Data2 & 0x80)==0x00))
3469 {
3470 *u8_DVBS2_CurrentConstellationLocal = DMD_DVBS_QPSK;
3471 }
3472 else if (((u8Data & 0x03)==0x01) && ((u8Data2 & 0x80)==0x80))
3473 {
3474 *u8_DVBS2_CurrentConstellationLocal = DMD_DVBS_8PSK;//8PSK
3475 }
3476 //ch_power_db_rel = ch_power_db - fDVBS2_SSI_Pref[_u8_DVBS2_CurrentConstellationLocal][_u8_DVBS2_CurrentCodeRateLocal];
3477 }
3478 /*
3479 if(ch_power_db_rel <= -15.0f)
3480 {
3481 *pu16SignalBar = 0;
3482 }
3483 else if (ch_power_db_rel <= 0.0f)
3484 {
3485 *pu16SignalBar = (MS_U16)(2.0f/3 * (ch_power_db_rel+15.0f));
3486 }
3487 else if (ch_power_db_rel <= 20.0f)
3488 {
3489 *pu16SignalBar = (MS_U16)(4.0f * ch_power_db_rel + 10.0f);
3490 }
3491 else if (ch_power_db_rel <= 35.0f)
3492 {
3493 *pu16SignalBar = (MS_U16)(2.0f/3 * (ch_power_db_rel-20.0f) + 90.0);
3494 }
3495 else
3496 {
3497 *pu16SignalBar = 100;
3498 }
3499 */
3500 //printf("SSI_CH_PWR(dB) = %f \n", ch_power_db_rel);
3501 //DBG_INTERN_DVBS(printf(">>>>>Signal Strength(SSI) = %d\n", (int)*pu16SignalBar));
3502
3503 return status;
3504 }
3505
3506 //SQI
3507 /****************************************************************************
3508 Subject: To get the DVT Signal quility
3509 Function: INTERN_DVBS_GetSignalQuality
3510 Parmeter: Quility
3511 Return: E_RESULT_SUCCESS
3512 E_RESULT_FAILURE
3513 Remark: Here we have 4 level range
3514 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
3515 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
3516 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
3517 <4>.4th Range => Quality <10
3518 *****************************************************************************/
3519 #if (0)
INTERN_DVBS_GetSignalQuality(MS_U16 * quality,const DMD_DVBS_InitData * sDMD_DVBS_InitData,MS_U8 u8SarValue,float fRFPowerDbm)3520 MS_BOOL INTERN_DVBS_GetSignalQuality(MS_U16 *quality, const DMD_DVBS_InitData *sDMD_DVBS_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
3521 {
3522
3523 float fber = 0.0;
3524 //float log_ber;
3525 MS_BOOL status = TRUE;
3526 float f_snr = 0.0, ber_sqi = 0.0, cn_rel = 0.0;
3527 //MS_U8 u8Data =0;
3528 DMD_DVBS_CODE_RATE_TYPE _u8_DVBS2_CurrentCodeRateLocal ;
3529 MS_U16 bchpkt_error,BCH_Eflag2_Window;
3530 //fRFPowerDbm = fRFPowerDbm;
3531 float snr_poly =0.0;
3532 float Fixed_SNR =0.0;
3533 double eFlag_PER=0.0;
3534
3535 if (TRUE == INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0))
3536 {
3537 if(_bDemodType) //S2
3538 {
3539
3540 INTERN_DVBS_GetSNR(&f_snr);
3541 snr_poly = 0.005261367463671*pow(f_snr, 3)-0.116517828301214*pow(f_snr, 2)+0.744836970505452*pow(f_snr, 1)-0.86727609780167;
3542 Fixed_SNR = f_snr + snr_poly;
3543
3544 if (Fixed_SNR < 17.0)
3545 Fixed_SNR = Fixed_SNR;
3546 else if ((Fixed_SNR < 20.0) && (Fixed_SNR >= 17.0))
3547 Fixed_SNR = Fixed_SNR - 0.8;
3548 else if ((Fixed_SNR < 22.5) && (Fixed_SNR >= 20.0))
3549 Fixed_SNR = Fixed_SNR - 2.0;
3550 else if ((Fixed_SNR < 27.0) && (Fixed_SNR >= 22.5))
3551 Fixed_SNR = Fixed_SNR - 3.0;
3552 else if ((Fixed_SNR < 29.0) && (Fixed_SNR >= 27.0))
3553 Fixed_SNR = Fixed_SNR - 3.5;
3554 else if (Fixed_SNR >= 29.0)
3555 Fixed_SNR = Fixed_SNR - 3.0;
3556
3557
3558 if (Fixed_SNR < 1.0)
3559 Fixed_SNR = 1.0;
3560 if (Fixed_SNR > 30.0)
3561 Fixed_SNR = 30.0;
3562
3563 //BCH EFLAG2_Window, window size 0x2000
3564 BCH_Eflag2_Window=0x2000;
3565 MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE + 0x25*2 + 1, (BCH_Eflag2_Window>>8));
3566 MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE + 0x25*2 , (BCH_Eflag2_Window&0xff));
3567 INTERN_DVBS_GetPacketErr(&bchpkt_error);
3568 eFlag_PER = (float)(bchpkt_error)/(float)(BCH_Eflag2_Window);
3569 if(eFlag_PER>0)
3570 fber = 0.089267531133002*pow(eFlag_PER, 2) + 0.019640560289510*eFlag_PER + 0.0000001;
3571 else
3572 fber = 0;
3573
3574 #ifdef MSOS_TYPE_LINUX
3575 //log_ber = ( - 1) *log10f(1 / fber);
3576 if (fber > 1.0E-1)
3577 ber_sqi = (log10f(1.0f/fber))*20.0f + 8.0f;
3578 else if(fber > 8.5E-7)
3579 ber_sqi = (log10f(1.0f/fber))*20.0f - 30.0f;
3580 else
3581 ber_sqi = 100.0;
3582 #else
3583 //log_ber = ( - 1) *Log10Approx(1 / fber);
3584 if (fber > 1.0E-1)
3585 ber_sqi = (Log10Approx(1.0f/fber))*20.0f + 8.0f;
3586 else if(fber > 8.5E-7)
3587 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 30.0f;
3588 else
3589 ber_sqi = 100.0;
3590
3591 #endif
3592
3593 *quality = Fixed_SNR/30*ber_sqi;
3594 DBG_INTERN_DVBS(printf(" Fixed_SNR %f\n",Fixed_SNR));
3595 DBG_INTERN_DVBS(printf(" BCH_Eflag2_Window %d\n",BCH_Eflag2_Window));
3596 DBG_INTERN_DVBS(printf(" eFlag_PER [%f]\n fber [%8.3e]\n ber_sqi [%f]\n",eFlag_PER,fber,ber_sqi));
3597 }
3598 else //S
3599 {
3600 if (INTERN_DVBS_GetPostViterbiBer(&fber) == FALSE)//ViterbiBer
3601 {
3602 DBG_INTERN_DVBS(printf("\nGetPostViterbiBer Fail!"));
3603 return FALSE;
3604 }
3605 _fPostBer=fber;
3606
3607
3608 if (status==FALSE)
3609 {
3610 DBG_INTERN_DVBS(printf("MSB131X_DTV_GetSignalQuality GetPostViterbiBer Fail!\n"));
3611 return 0;
3612 }
3613 float fDVBS_SQI_CNref[]=
3614 { //0, 1, 2, 3, 4
3615 4.2, 5.9, 6, 6.9, 7.5,//QPSK
3616 };
3617
3618 INTERN_DVBS_GetCurrentDemodCodeRate(&_u8_DVBS2_CurrentCodeRateLocal);
3619 #if 0
3620 #ifdef MSOS_TYPE_LINUX
3621 log_ber = ( - 1.0f) *log10f(1.0f / fber); //BY modify
3622 #else
3623 log_ber = ( - 1.0f) *Log10Approx(1.0f / fber); //BY modify
3624 #endif
3625 DBG_INTERN_DVBS(printf("\nLog(BER) = %f\n",log_ber));
3626 #endif
3627 if (fber > 2.5E-2)
3628 ber_sqi = 0.0;
3629 else if(fber > 8.5E-7)
3630 #ifdef MSOS_TYPE_LINUX
3631 ber_sqi = (log10f(1.0f/fber))*20.0f - 32.0f; //40.0f;
3632 #else
3633 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 32.0f;//40.0f;
3634 #endif
3635 else
3636 ber_sqi = 100.0;
3637
3638 status &= INTERN_DVBS_GetSNR(&f_snr);
3639 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS GetSNR = %d \n", (int)f_snr));
3640
3641 cn_rel = f_snr - fDVBS_SQI_CNref[_u8_DVBS2_CurrentCodeRateLocal];
3642
3643 DBG_INTERN_DVBS(printf(" fber = %f\n",fber));
3644 DBG_INTERN_DVBS(printf(" f_snr = %f\n",f_snr));
3645 DBG_INTERN_DVBS(printf(" cn_nordig_s1 = %f\n",fDVBS_SQI_CNref[_u8_DVBS2_CurrentCodeRateLocal]));
3646 DBG_INTERN_DVBS(printf(" cn_rel = %f\n",cn_rel));
3647 DBG_INTERN_DVBS(printf(" ber_sqi = %f\n",ber_sqi));
3648
3649 if (cn_rel < -7.0f)
3650 {
3651 *quality = 0;
3652 }
3653 else if (cn_rel < 3.0)
3654 {
3655 *quality = (MS_U16)(ber_sqi*((cn_rel - 3.0)/10.0 + 1.0));
3656 }
3657 else
3658 {
3659 *quality = (MS_U16)ber_sqi;
3660 }
3661
3662
3663 }
3664 //INTERN_DVBS_GetTunrSignalLevel_PWR();//For Debug.
3665 DBG_INTERN_DVBS(printf(">>>>>Signal Quility(SQI) = %d\n", *quality));
3666 return TRUE;
3667 }
3668 else
3669 {
3670 *quality = 0;
3671 }
3672
3673 return TRUE;
3674 }
3675 #endif
3676 /****************************************************************************
3677 Subject: To get the Cell ID
3678 Function: INTERN_DVBS_Get_CELL_ID
3679 Parmeter: point to return parameter cell_id
3680
3681 Return: TRUE
3682 FALSE
3683 Remark:
3684 *****************************************************************************/
INTERN_DVBS_Get_CELL_ID(MS_U16 * cell_id)3685 MS_BOOL INTERN_DVBS_Get_CELL_ID(MS_U16 *cell_id)
3686 {
3687 MS_BOOL status = true;
3688 MS_U8 value1 = 0;
3689 MS_U8 value2 = 0;
3690
3691 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [15:8]
3692 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [7:0]
3693
3694 *cell_id = ((MS_U16)value1<<8)|value2;
3695 return status;
3696 }
3697
3698 /****************************************************************************
3699 Subject: To get the DVBC Carrier Freq Offset
3700 Function: INTERN_DVBS_Get_FreqOffset
3701 Parmeter: Frequency offset (in KHz), bandwidth
3702 Return: E_RESULT_SUCCESS
3703 E_RESULT_FAILURE
3704 Remark:
3705 *****************************************************************************/
INTERN_DVBS_Get_FreqOffset(MS_S16 * s16CFO)3706 MS_BOOL INTERN_DVBS_Get_FreqOffset(MS_S16 *s16CFO)
3707 {
3708 MS_U8 u8Data;
3709 MS_U16 u16Data;
3710 //MS_S16 s16CFO;
3711 //float FreqOffset;
3712 //MS_U32 u32FreqOffset = 0;
3713 //MS_U8 reg = 0;
3714 MS_BOOL status = TRUE;
3715
3716 DBG_INTERN_DVBS(ULOGD("DEMOD",">>> INTERN_DVBS_Get_FreqOffset DVBS_Estimated_CFO <<<\n"));
3717 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_97, &u8Data);
3718 u16Data=u8Data;
3719 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_96, &u8Data);
3720 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset
3721 if (u16Data >= 0x8000)
3722 {
3723 u16Data=0x10000- u16Data;
3724 *s16CFO=-1*u16Data;
3725 }
3726 else
3727 {
3728 *s16CFO=u16Data;
3729 }
3730 DBG_INTERN_DVBS(ULOGD("DEMOD",">>> INTERN_DVBS_Get_FreqOffset CFO = %d[KHz] <<<\n", *s16CFO));
3731 /*
3732 if(abs(s16CFO)%1000 >= 500)
3733 {
3734 if(s16CFO < 0)
3735 *pFreqOff=(s16CFO/1000)-1.0;
3736 else
3737 *pFreqOff=(s16CFO/1000)+1.0;
3738 }
3739 else
3740 *pFreqOff = s16CFO/1000;
3741 DBG_INTERN_DVBS(printf(">>> INTERN_DVBS_Get_FreqOffset *pFreqOff = %d[MHz] <<<\n", (MS_S16)*pFreqOff));
3742 */
3743 // no use.
3744 //u8BW = u8BW;
3745 /*
3746 printf("INTERN_DVBS_Get_FreqOffset\n");//DBG_INTERN_DVBS(printf("INTERN_DVBS_Get_FreqOffset\n"));
3747
3748 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x1C*2 + 1, 0x08);
3749
3750 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x05, ®);
3751 reg|=0x80;
3752 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x05, reg);
3753
3754 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x23*2, ®);
3755 u32FreqOffset=reg;
3756 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x22*2 + 1, ®);
3757 u32FreqOffset=(u32FreqOffset<<8)|reg;
3758 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x22*2, ®);
3759 u32FreqOffset=(u32FreqOffset<<8)|reg;
3760
3761 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x05, ®);
3762 reg&=~(0x80);
3763 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x05, reg);
3764
3765 FreqOffset=(float)u32FreqOffset;
3766 if (FreqOffset>=2048)
3767 {
3768 FreqOffset=FreqOffset-4096;
3769 }
3770 FreqOffset=(FreqOffset/4096)*SAMPLING_RATE_FS;
3771
3772 *pFreqOff = FreqOffset/1000; //KHz
3773 printf("INTERN_DVBS_Get_FreqOffset:%d[MHz]\n", (MS_S16)FreqOffset/1000);//DBG_INTERN_DVBS(printf("INTERN_DVBS_Get_FreqOffset:%f[MHz]\n", FreqOffset/1000));
3774 */
3775
3776 return status;
3777 }
3778
3779 /****************************************************************************
3780 Subject: To get the current modulation type at the DVB-S Demod
3781 Function: INTERN_DVBS_GetCurrentModulationType
3782 Parmeter: pointer for return QAM type
3783
3784 Return: TRUE
3785 FALSE
3786 Remark:
3787 *****************************************************************************/
INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE * pQAMMode)3788 MS_BOOL INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE *pQAMMode)
3789 {
3790 MS_U8 u8Data=0;
3791 MS_U16 u16tmp=0;
3792 MS_U8 MOD_type;
3793 MS_BOOL status = true;
3794 //DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3795
3796 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType\n"));
3797
3798 //status &= INTERN_DVBS_GetCurrentDemodType(&pDemodType);
3799
3800 // read code rate, pilot on/off, long/short FEC type, and modulation type for calculating TOP_DVBTM_TS_CLK_DIVNUM
3801 // pilot_flag => 0 : off 1 : on
3802 // fec_type_idx => 0 : normal 1 : short
3803 // mod_type_idx => 0 : QPSK 1 : 8PSK 2 : 16APSK
3804 // code_rate_idx => 0 : 1/4 1 : 1/3 2 : 2/5 3 : 1/2 4 : 3/5 5 : 2/3
3805 // 6 : 3/4 7 : 4/5 8 : 5/6 9 : 8/9 10 : 9/10
3806 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//V
3807 if(u8Data)
3808 {
3809 *pQAMMode = DMD_DVBS_QPSK;
3810 modulation_order=2;
3811 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs]ModulationType=DVBS_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS_QPSK\n"));
3812 //return TRUE;
3813 }
3814 else //S2
3815 {
3816 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x96, &u8Data);
3817 //printf(">>> INTERN_DVBS_GetCurrentModulationType INNER 0x4B = 0x%x <<<\n", u8Data);
3818 //if((u8Data & 0x0F)==0x02) //QPSK
3819 /*MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MOD_TYPE, &u8Data1);
3820 printf("@@@@@E_DMD_S2_MOD_TYPE = %d \n ",u8Data1);
3821 printf("@@@@@ E_DMD_S2_MOD_TYPE=%d \n",E_DMD_S2_MOD_TYPE);
3822
3823 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_IS_ID, &u8Data1);
3824 printf("@@@@@E_DMD_S2_IS_ID = %d \n ",u8Data1);
3825 printf("@@@@@ E_DMD_S2_IS_ID=%d \n",E_DMD_S2_IS_ID);*/
3826
3827 // INNER_DEBUG_SEL
3828 MDrv_SYS_DMD_VD_MBX_ReadReg(0x3b00+0x04*2+1, &u8Data);
3829 u8Data = u8Data & 0xc0;
3830 MDrv_SYS_DMD_VD_MBX_WriteReg(0x3b00+0x04*2+1, u8Data);
3831
3832 // reg_plscdec_debug_out
3833 // PLSCDEC info
3834 //[0:4] PLSC MODCOD
3835 //[5] dummy frame
3836 //[6] reserve frame
3837 //[7:9] modulation type
3838 //[10:13] code rate type
3839 //[14] FEC type
3840 //[15] pilot type
3841 MDrv_SYS_DMD_VD_MBX_ReadReg(0x3b00+0x6b*2 , &u8Data);
3842 u16tmp = (MS_U16)u8Data;
3843 MDrv_SYS_DMD_VD_MBX_ReadReg(0x3b00+0x6b*2+1 , &u8Data);
3844 u16tmp |= (MS_U16)u8Data << 8;
3845 MOD_type = ((MS_U8)(u16tmp>>7)&0x07); // 2:QPSK, 3:8PSK, 4:16APSK, 5:32APSK
3846
3847 if(MOD_type==2)
3848 {
3849 *pQAMMode = DMD_DVBS_QPSK;
3850 modulation_order=2;
3851 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS2_QPSK\n"));
3852 //return TRUE;
3853 }
3854 else if(MOD_type==3)
3855 {
3856 *pQAMMode = DMD_DVBS_8PSK;
3857 modulation_order=3;
3858 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_8PSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS2_8PSK\n"));
3859 //return TRUE;
3860 }
3861 else if(MOD_type==4)
3862 {
3863 *pQAMMode = DMD_DVBS_16APSK;
3864 modulation_order=4;
3865 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_16APSK\n");
3866 }
3867 else
3868 {
3869 *pQAMMode = DMD_DVBS_QPSK;
3870 modulation_order=2;
3871 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=NOT SUPPORT\n");
3872 return FALSE;
3873 }
3874
3875 }
3876
3877 return status;
3878 /*#else
3879 *pQAMMode = DMD_DVBS_QPSK;
3880 printf("[dvbs]ModulationType=DVBS_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS_QPSK\n"));
3881 //return true;
3882 #endif*/
3883 }
3884
3885 /****************************************************************************
3886 Subject: To get the current DemodType at the DVB-S Demod
3887 Function: INTERN_DVBS_GetCurrentDemodType
3888 Parmeter: pointer for return DVBS/DVBS2 type
3889
3890 Return: TRUE
3891 FALSE
3892 Remark:
3893 *****************************************************************************/
INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE * pDemodType)3894 MS_BOOL INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE *pDemodType)//V
3895 {
3896 MS_U8 u8Data=0;
3897 MS_BOOL status = true;
3898
3899 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentDemodType\n"));
3900
3901 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x80, &u8Data);//status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x80, &u8Data);
3902 //printf(">>> INTERN_DVBS_GetCurrentDemodType INNER 0x40 = 0x%x <<<\n", u8Data);
3903 //if ((u8Data & 0x01) == 0)
3904 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//E_DMD_S2_SYSTEM_TYPE 0: S2 ; 1 :S
3905 if(!u8Data) //S2
3906 {
3907 *pDemodType = DMD_SAT_DVBS2;
3908 DBG_INTERN_DVBS(ULOGD("DEMOD","[dvbs]DemodType=DVBS2\n"));
3909 }
3910 else //S
3911 {
3912 *pDemodType = DMD_SAT_DVBS;
3913 DBG_INTERN_DVBS(ULOGD("DEMOD","[dvbs]DemodType=DVBS\n"));
3914 }
3915 return status;
3916 }
3917 /****************************************************************************
3918 Subject: To get the current CodeRate at the DVB-S Demod
3919 Function: INTERN_DVBS_GetCurrentCodeRate
3920 Parmeter: pointer for return Code Rate type
3921
3922 Return: TRUE
3923 FALSE
3924 Remark:
3925 *****************************************************************************/
INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE * pCodeRate)3926 MS_BOOL INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE *pCodeRate)
3927 {
3928 MS_U8 u8Data = 0;//, u8_gCodeRate = 0;
3929 MS_BOOL status = true;
3930
3931 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate\n"));
3932 //DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3933 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);
3934 //status &= INTERN_DVBS_GetCurrentDemodType(&pDemodType);
3935 if(!u8Data)
3936 //if((MS_U8)pDemodType == (MS_U8)DMD_SAT_DVBS2 ) //S2
3937 {
3938 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
3939 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
3940 //u8_gCodeRate = (u8Data & 0x3C);
3941 //_u8_DVBS2_CurrentCodeRate = 0;
3942 switch (u8Data)
3943 //switch (u8_gCodeRate)
3944 {
3945 case 0x03:
3946 *pCodeRate = DMD_CONV_CODE_RATE_1_2;
3947 _u8_DVBS2_CurrentCodeRate = 5;//0;
3948 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=1_2\n"));
3949 break;
3950 case 0x01:
3951 *pCodeRate = DMD_CONV_CODE_RATE_1_3;
3952 _u8_DVBS2_CurrentCodeRate = 6;//1;
3953 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=1_3\n"));
3954 break;
3955 case 0x05:
3956 *pCodeRate = DMD_CONV_CODE_RATE_2_3;
3957 _u8_DVBS2_CurrentCodeRate = 7;//2;
3958 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=2_3\n"));
3959 break;
3960 case 0x00:
3961 *pCodeRate = DMD_CONV_CODE_RATE_1_4;
3962 _u8_DVBS2_CurrentCodeRate = 8;//3;
3963 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=1_4\n"));
3964 break;
3965 case 0x06:
3966 *pCodeRate = DMD_CONV_CODE_RATE_3_4;
3967 _u8_DVBS2_CurrentCodeRate = 9;//4;
3968 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=3_4\n"));
3969 break;
3970 case 0x02:
3971 *pCodeRate = DMD_CONV_CODE_RATE_2_5;
3972 _u8_DVBS2_CurrentCodeRate = 10;//5;
3973 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=2_5\n"));
3974 break;
3975 case 0x04:
3976 *pCodeRate = DMD_CONV_CODE_RATE_3_5;
3977 _u8_DVBS2_CurrentCodeRate = 11;//6;
3978 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=3_5\n"));
3979 break;
3980 case 0x07:
3981 *pCodeRate = DMD_CONV_CODE_RATE_4_5;
3982 _u8_DVBS2_CurrentCodeRate = 12;//7;
3983 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=4_5\n"));
3984 break;
3985 case 0x08:
3986 *pCodeRate = DMD_CONV_CODE_RATE_5_6;
3987 _u8_DVBS2_CurrentCodeRate = 13;//8;
3988 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=5_6\n"));
3989 break;
3990 case 0x09:
3991 *pCodeRate = DMD_CONV_CODE_RATE_8_9;
3992 _u8_DVBS2_CurrentCodeRate = 14;//9;
3993 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=8_9\n"));
3994 break;
3995 case 0x0a:
3996 *pCodeRate = DMD_CONV_CODE_RATE_9_10;
3997 _u8_DVBS2_CurrentCodeRate = 15;//10;
3998 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=9_10\n"));
3999 break;
4000 default:
4001 *pCodeRate = DMD_CONV_CODE_RATE_9_10;
4002 _u8_DVBS2_CurrentCodeRate = 15;//10;
4003 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=DVBS2_Default\n"));
4004 }
4005 }
4006 else //S
4007 {
4008 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
4009 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE + 0x3A*2, &u8Data);
4010 //u8_gCodeRate = (u8Data & 0x70)>>4;
4011 switch (u8Data)
4012 //switch (u8_gCodeRate)
4013 {
4014 case 0x00:
4015 *pCodeRate = DMD_CONV_CODE_RATE_1_2;
4016 _u8_DVBS2_CurrentCodeRate = 0;
4017 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=1_2\n"));
4018 break;
4019 case 0x01:
4020 *pCodeRate = DMD_CONV_CODE_RATE_2_3;
4021 _u8_DVBS2_CurrentCodeRate = 1;
4022 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=2_3\n"));
4023 break;
4024 case 0x02:
4025 *pCodeRate = DMD_CONV_CODE_RATE_3_4;
4026 _u8_DVBS2_CurrentCodeRate = 2;
4027 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=3_4\n"));
4028 break;
4029 case 0x03:
4030 *pCodeRate = DMD_CONV_CODE_RATE_5_6;
4031 _u8_DVBS2_CurrentCodeRate = 3;
4032 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=5_6\n"));
4033 break;
4034 case 0x04:
4035 *pCodeRate = DMD_CONV_CODE_RATE_7_8;
4036 _u8_DVBS2_CurrentCodeRate = 4;
4037 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=7_8\n"));
4038 break;
4039 default:
4040 *pCodeRate = DMD_CONV_CODE_RATE_7_8;
4041 _u8_DVBS2_CurrentCodeRate = 4;
4042 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=DVBS_Default\n"));
4043 }
4044 }
4045 return status;
4046 }
4047
4048 /****************************************************************************
4049 Subject: To get the current symbol rate at the DVB-S Demod
4050 Function: INTERN_DVBS_GetCurrentSymbolRate
4051 Parmeter: pointer pData for return Symbolrate
4052
4053 Return: TRUE
4054 FALSE
4055 Remark:
4056 *****************************************************************************/
INTERN_DVBS_GetCurrentSymbolRate(MS_U32 * u32SymbolRate)4057 MS_BOOL INTERN_DVBS_GetCurrentSymbolRate(MS_U32 *u32SymbolRate)
4058 {
4059 MS_U8 tmp = 0;
4060 MS_U16 u16SymbolRateTmp = 0;
4061
4062 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &tmp);
4063 u16SymbolRateTmp = tmp;
4064 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &tmp);
4065 u16SymbolRateTmp = (u16SymbolRateTmp<<8)|tmp;
4066
4067 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &tmp);
4068 *u32SymbolRate = (tmp<<16)|u16SymbolRateTmp;
4069
4070 DBG_INTERN_DVBS_LOCK(ULOGD("DEMOD","[dvbs]Symbol Rate=%d\n",(int)*u32SymbolRate));
4071
4072 return TRUE;
4073 }
4074
INTERN_DVBS_Version(MS_U16 * ver)4075 MS_BOOL INTERN_DVBS_Version(MS_U16 *ver)
4076 {
4077 MS_U8 status = true;
4078 MS_U8 tmp = 0;
4079 MS_U16 u16_INTERN_DVBS_Version;
4080
4081 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FW_VERSION_L, &tmp);
4082 u16_INTERN_DVBS_Version = tmp;
4083 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FW_VERSION_H, &tmp);
4084 u16_INTERN_DVBS_Version = u16_INTERN_DVBS_Version<<8|tmp;
4085 *ver = u16_INTERN_DVBS_Version;
4086
4087 return status;
4088 }
4089
INTERN_DVBS_Show_Demod_Version(void)4090 MS_BOOL INTERN_DVBS_Show_Demod_Version(void)
4091 {
4092 MS_BOOL status = true;
4093 MS_U16 u16_INTERN_DVBS_Version;
4094
4095 status &= INTERN_DVBS_Version(&u16_INTERN_DVBS_Version);
4096
4097 ULOGD("DEMOD",">>> [Macan]Demod FW Version: R%d.%d <<<\n", ((u16_INTERN_DVBS_Version>>8)&0x00FF),(u16_INTERN_DVBS_Version&0x00FF));
4098
4099
4100 return status;
4101 }
4102
INTERN_DVBS_GetRollOff(MS_U8 * pRollOff)4103 MS_BOOL INTERN_DVBS_GetRollOff(MS_U8 *pRollOff)
4104 {
4105 MS_BOOL status=TRUE;
4106 MS_U8 u8Data=0;
4107
4108 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x1E, &u8Data);//#define INNER_TR_ROLLOFF (_REG_INNER(0x0F)+0)
4109 if ((u8Data&0x03)==0x00)
4110 *pRollOff = 0; //Rolloff 0.35
4111 else if (((u8Data&0x03)==0x01) || ((u8Data&0x03)==0x03))
4112 *pRollOff = 1; //Rolloff 0.25
4113 else
4114 *pRollOff = 2; //Rolloff 0.20
4115 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetRollOff:%d\n", *pRollOff));
4116
4117 return status;
4118 }
4119
INTERN_DVBS_Get_DTV_SQuality_BAR(MS_U8 * u8_gSQValue)4120 MS_BOOL INTERN_DVBS_Get_DTV_SQuality_BAR(MS_U8 *u8_gSQValue)
4121 {
4122 MS_BOOL status=TRUE;
4123 //MS_U16 u16_gSignalQualityValue;
4124 MS_U16 _u16_packetError;
4125
4126 // status = INTERN_DVBS_GetSignalQuality(&u16_gSignalQualityValue,0,0,0);
4127 status = INTERN_DVBS_GetPacketErr(&_u16_packetError);
4128 /*
4129 if ((_u16_packetError >= 1) && (u16_gSignalQualityValue > 30)) //Average
4130 {
4131 *u8_gSQValue = 30;
4132 }
4133 else if ((_u16_packetError >= 1) && (u16_gSignalQualityValue > 10)) //Poor
4134 {
4135 *u8_gSQValue = 10;
4136 }
4137 */
4138 return status;
4139 }
4140
4141 /****************************************************************************
4142 ** Function: Read demod related information
4143 ** Polling after demod lock
4144 ** GAIN & DCR /Fine CFO & PR & IIS & IQB & SNR /PacketErr & BER
4145 ****************************************************************************/
INTERN_DVBS_Show_AGC_Info(void)4146 MS_BOOL INTERN_DVBS_Show_AGC_Info(void)
4147 {
4148 MS_BOOL status = TRUE;
4149
4150 //MS_U8 tmp = 0;
4151 //MS_U8 agc_k = 0,d0_k = 0,d0_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0,d3_k = 0,d3_ref = 0;
4152 //MS_U16 if_agc_gain = 0,d0_gain = 0,d1_gain = 0,d2_gain = 0,d3_gain = 0, agc_ref = 0;
4153 //MS_U16 if_agc_err = 0;
4154 #if 0
4155 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x08*2 + 1,&agc_k);
4156 agc_k = ((agc_k & 0xF0)>>4);
4157 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x09*2 + 1,&tmp);
4158 agc_ref = tmp;
4159 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0xE8,&tmp);
4160 //agc_ref = (agc_ref<<8)|tmp;
4161 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x38*2,&d0_k);
4162 d0_k = ((d0_k & 0xF0)>>4);
4163 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x38*2 + 1,&d0_ref);
4164 d0_ref = (d0_ref & 0xFF);
4165 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x58*2,&d1_k);
4166 d1_k = (d1_k & 0xF0)>>4;
4167 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x58*2 + 1,&d1_ref);
4168 d1_ref = (d1_ref & 0xFF);
4169 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5E*2,&d2_k);
4170 d2_k = ((d2_k & 0xF0)>>4);
4171 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x5E*2 + 1,&d2_ref);
4172 d2_ref = (d2_ref & 0xFF);
4173 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6A*2,&d3_k);
4174 d3_k = ((d3_k & 0xF0)>>4);
4175 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref);
4176 d3_ref = (d3_ref & 0xFF);
4177
4178
4179 // select IF gain to read
4180 //Debug Select
4181 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x13*2, &tmp);
4182 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x13*2, (tmp&0xF0)|0x03);
4183 //IF_AGC_GAIN
4184 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2 + 1, &tmp);
4185 if_agc_gain = tmp;
4186 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2, &tmp);
4187 if_agc_gain = (if_agc_gain<<8)|tmp;
4188
4189
4190 // select d0 gain to read.
4191 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x74*2 + 1, &tmp);
4192 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x74*2 + 1, (tmp&0xF0)|0x03);
4193 //DAGC0_GAIN
4194 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3D*2, &tmp);
4195 d0_gain = tmp;
4196 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3C*2 + 1, &tmp);
4197 d0_gain = (d0_gain<<8)|tmp;
4198 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3C*2, &tmp);
4199 d0_gain = (d0_gain<<4)|(tmp>>4);
4200
4201
4202 // select d1 gain to read.
4203 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x8C, &tmp);
4204 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x8C, (tmp&0xF0)|0x00);
4205 //DAGC1_GAIN
4206 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5C*2 + 1, &tmp);
4207 d1_gain = tmp;
4208 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5C*2, &tmp);
4209 d1_gain = (d1_gain<<8)|tmp;
4210
4211
4212 // select d2 gain to read.
4213 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x06, &tmp);
4214 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT_REG_BASE + 0x06, (tmp&0xF0)|0x03);
4215 //DAGC2_GAIN
4216 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x62*2 + 1, &tmp);
4217 d2_gain = tmp;
4218 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x62*2, &tmp);
4219 d2_gain = (d2_gain<<8)|tmp;
4220
4221
4222 // select d3 gain to read.
4223 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp);
4224 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03);
4225 //DAGC3_GAIN
4226 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6F*2, &tmp);
4227 d3_gain = tmp;
4228 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6E*2 + 1, &tmp);
4229 d3_gain = (d3_gain<<8)|tmp;
4230 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6E*2, &tmp);
4231 d3_gain = (d3_gain<<4)|(tmp>>4);
4232
4233
4234 // select IF gain err to read
4235 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x13*2, &tmp);
4236 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x13*2, (tmp&0xF0)|0x00);
4237
4238 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2 + 1, &tmp);
4239 if_agc_err = tmp;
4240 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2, &tmp);
4241 if_agc_err = (if_agc_err<<8)|tmp;
4242
4243
4244 DBG_INTERN_DVBS(printf("[dvbs]agc_k=0x%x, agc_ref=0x%x, d0_k=0x%x, d0_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x, d3_k=0x%x, d3_ref=0x%x\n",
4245 agc_k, agc_ref, d0_k, d0_ref, d1_k, d1_ref, d2_k, d2_ref, d3_k, d3_ref));
4246
4247 DBG_INTERN_DVBS(printf("[dvbs]agc_g=0x%x, d0_g=0x%x, d1_g=0x%x, d2_g=0x%x, d3_g=0x%x, agc_err=0x%x\n", if_agc_gain, d0_gain, d1_gain, d2_gain, d3_gain, if_agc_err));
4248
4249 DBG_INTERN_DVBS(printf("[dvbs]agc_k=0x%x, agc_ref=0x%x, d0_k=0x%x, d0_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x, d3_k=0x%x, d3_ref=0x%x\n",
4250 agc_k, agc_ref, d0_k, d0_ref, d1_k, d1_ref, d2_k, d2_ref, d3_k, d3_ref));
4251
4252 DBG_INTERN_DVBS(printf("[dvbs]agc_g=0x%x, d0_g=0x%x, d1_g=0x%x, d2_g=0x%x, d3_g=0x%x, agc_err=0x%x\n", if_agc_gain, d0_gain, d1_gain, d2_gain, d3_gain, if_agc_err));
4253 #endif
4254 return status;
4255 }
4256
INTERN_DVBS_info(void)4257 void INTERN_DVBS_info(void)
4258 {
4259 //status &= INTERN_DVBS_Show_Demod_Version();
4260 //status &= INTERN_DVBS_Demod_Get_Debug_Info_get_once();
4261 //status &= INTERN_DVBS_Demod_Get_Debug_Info_polling();
4262 }
4263
INTERN_DVBS_Demod_Get_Debug_Info_get_once(void)4264 MS_BOOL INTERN_DVBS_Demod_Get_Debug_Info_get_once(void)
4265 {
4266 MS_BOOL status = TRUE;
4267 //MS_U8 u8Data = 0;
4268 //MS_U16 u16Data = 0, u16Address = 0;
4269 //float psd_smooth_factor;
4270 //float srd_right_bottom_value, srd_right_top_value, srd_left_bottom_value, srd_left_top_value;
4271 //MS_U16 u32temp5;
4272 //MS_U16 srd_left, srd_right, srd_left_top, srd_left_bottom, srd_right_top, srd_right_bottom;
4273
4274 #if 0
4275 //Lock Flag
4276 printf("========================================================================\n");
4277 printf("Debug Message Flag [Lock Flag]==========================================\n");
4278
4279 u16Address = (AGC_LOCK>>16)&0xffff;
4280 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4281 if ((u16Data&(AGC_LOCK&0xffff))!=(AGC_LOCK&0xffff))
4282 printf("[DVBS]: AGC LOCK ======================: Fail. \n");
4283 else
4284 printf("[DVBS]: AGC LOCK ======================: OK. \n");
4285
4286 u16Address = (DAGC0_LOCK>>16)&0xffff;
4287 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4288 if ((u16Data&(DAGC0_LOCK&0xffff))!=(DAGC0_LOCK&0xffff))
4289 printf("[DVBS]: DAGC0 LOCK ====================: Fail. \n");
4290 else
4291 printf("[DVBS]: DAGC0 LOCK ====================: OK. \n");
4292
4293 u16Address = (DAGC1_LOCK>>16)&0xffff;
4294 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4295 if ((u16Data&(DAGC1_LOCK&0xffff))!=(DAGC1_LOCK&0xffff))
4296 printf("[DVBS]: DAGC1 LOCK ====================: Fail. \n");
4297 else
4298 printf("[DVBS]: DAGC1 LOCK ====================: OK. \n");
4299
4300 u16Address = (DAGC2_LOCK>>16)&0xffff;
4301 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4302 if ((u16Data&(DAGC2_LOCK&0xffff))!=(DAGC2_LOCK&0xffff))
4303 printf("[DVBS]: DAGC2 LOCK ====================: Fail. \n");
4304 else
4305 printf("[DVBS]: DAGC2 LOCK ====================: OK. \n");
4306
4307 u16Address = (DAGC3_LOCK>>16)&0xffff;
4308 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4309 if ((u16Data&(DAGC3_LOCK&0xffff))!=(DAGC3_LOCK&0xffff))
4310 printf("[DVBS]: DAGC3 LOCK ====================: Fail. \n");
4311 else
4312 printf("[DVBS]: DAGC3 LOCK ====================: OK. \n");
4313
4314 u16Address = (DCR_LOCK>>16)&0xffff;
4315 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4316 if ((u16Data&(DCR_LOCK&0xffff))!=(DCR_LOCK&0xffff))
4317 printf("[DVBS]: DCR LOCK ======================: Fail. \n");
4318 else
4319 printf("[DVBS]: DCR LOCK ======================: OK. \n");
4320 //Mark Coarse SRD
4321 //Mark Fine SRD
4322 /*
4323 u16Address = (CLOSE_COARSE_CFO_LOCK>>16)&0xffff;
4324 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4325 if ((u16Data&(CLOSE_COARSE_CFO_LOCK&0xffff))!=(CLOSE_COARSE_CFO_LOCK&0xffff))
4326 printf("[DVBS]: Close CFO =====================: Fail. \n");
4327 else
4328 printf("[DVBS]: Close CFO =====================: OK. \n");
4329 */
4330 u16Address = (TR_LOCK>>16)&0xffff;
4331 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4332 if ((u16Data&(TR_LOCK&0xffff))!=(TR_LOCK&0xffff))
4333 printf("[DVBS]: TR LOCK =======================: Fail. \n");
4334 else
4335 printf("[DVBS]: TR LOCK =======================: OK. \n");
4336
4337 u16Address = (FRAME_SYNC_ACQUIRE>>16)&0xffff;
4338 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4339 if ((u16Data&(FRAME_SYNC_ACQUIRE&0xffff))!=(FRAME_SYNC_ACQUIRE&0xffff))
4340 printf("[DVBS]: FS Acquire ====================: Fail. \n");
4341 else
4342 printf("[DVBS]: FS Acquire ====================: OK. \n");
4343
4344 u16Address = (PR_LOCK>>16)&0xffff;
4345 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4346 if ((u16Data&(PR_LOCK&0xffff))!=(PR_LOCK&0xffff))
4347 printf("[DVBS]: PR LOCK =======================: Fail. \n");
4348 else
4349 printf("[DVBS]: PR LOCK =======================: OK. \n");
4350
4351 u16Address = (EQ_LOCK>>16)&0xffff;
4352 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4353 if ((u16Data&(EQ_LOCK&0xffff))!=(EQ_LOCK&0xffff))
4354 printf("[DVBS]: EQ LOCK =======================: Fail. \n");
4355 else
4356 printf("[DVBS]: EQ LOCK =======================: OK. \n");
4357
4358 u16Address = (P_SYNC_LOCK>>16)&0xffff;
4359 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4360 if ((u16Data&0x0002)!=0x0002)
4361 printf("[DVBS]: P_sync ========================: Fail. \n");
4362 else
4363 printf("[DVBS]: P_sync ========================: OK. \n");
4364
4365 u16Address = (IN_SYNC_LOCK>>16)&0xffff;
4366 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4367 if ((u16Data&0x8000)!=0x8000)
4368 printf("[DVBS]: In_sync =======================: Fail. \n");
4369 else
4370 printf("[DVBS]: In_sync =======================: OK. \n");
4371 //---------------------------------------------------------
4372 //Lock Time
4373 printf("------------------------------------------------------------------------\n");
4374 printf("Debug Message [Lock Time]===============================================\n");
4375
4376 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_05, &u8Data);
4377 printf("[DVBS]: AGC Lock Time =================: %d\n",u8Data&0x00FF);
4378 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_06, &u8Data);
4379 printf("[DVBS]: DCR Lock Time =================: %d\n",u8Data&0x00FF);
4380 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_2, &u8Data);
4381 printf("[DVBS]: TR Lock Time ==================: %d\n",u8Data&0x00FF);
4382 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_3, &u8Data);
4383 printf("[DVBS]: FS Lock Time ==================: %d\n",u8Data&0x00FF);
4384 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_4, &u8Data);
4385 printf("[DVBS]: PR Lock Time ==================: %d\n",u8Data&0x00FF);
4386 //printf("[DVBS]: PLSC Lock Time ================: %d\n",(u16Data>>8)&0x00FF);//No used
4387 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_6, &u8Data);
4388 printf("[DVBS]: EQ Lock Time ==================: %d\n",u8Data&0x00FF);
4389 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_7, &u8Data);
4390 printf("[DVBS]: FEC Lock Time =================: %d\n",u8Data&0x00FF);
4391
4392 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_0, &u8Data);
4393 printf("[DVBS]: CSRD ==========================: %d\n",u8Data&0x00FF);
4394 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_1, &u8Data);
4395 printf("[DVBS]: FSRD ==========================: %d\n",u8Data&0x00FF);
4396 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_01, &u8Data);
4397 printf("[DVBS]: CCFO ==========================: %d\n",u8Data&0x00FF);
4398 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_02, &u8Data);
4399 printf("[DVBS]: FCFO ==========================: %d\n",u8Data&0x00FF);
4400 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);
4401 printf("[DVBS]: State =========================: %d\n",u8Data&0x00FF);
4402 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SUBSTATE_FLAG, &u8Data);
4403 printf("[DVBS]: SubState ======================: %d\n",u8Data&0x00FF);
4404
4405 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00H, &u8Data);
4406 u16Data = u8Data;
4407 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00L, &u8Data);
4408 u16Data = (u16Data<<8)|u8Data;
4409 printf("[DVBS]: DBG1: =========================: 0x%x\n",u16Data);
4410 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01H, &u8Data);
4411 u16Data = u8Data;
4412 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01L, &u8Data);
4413 u16Data = (u16Data<<8)|u8Data;
4414 printf("[DVBS]: DBG2: =========================: 0x%x\n",u16Data);
4415 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE02H, &u8Data);
4416 u16Data = u8Data;
4417 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE02L, &u8Data);
4418 u16Data = (u16Data<<8)|u8Data;
4419 printf("[DVBS]: DBG3: =========================: 0x%x\n",u16Data);
4420 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE03H, &u8Data);
4421 u16Data = u8Data;
4422 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE03L, &u8Data);
4423 u16Data = (u16Data<<8)|u8Data;
4424 printf("[DVBS]: DBG4: =========================: 0x%x\n",u16Data);
4425 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE04H, &u8Data);
4426 u16Data = u8Data;
4427 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE04L, &u8Data);
4428 u16Data = (u16Data<<8)|u8Data;
4429 printf("[DVBS]: DBG5: =========================: 0x%x\n",u16Data);
4430 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE05H, &u8Data);
4431 u16Data = u8Data;
4432 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE05L, &u8Data);
4433 u16Data = (u16Data<<8)|u8Data;
4434 printf("[DVBS]: DBG6: =========================: 0x%x\n",u16Data);
4435 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE06H, &u8Data);
4436 u16Data = u8Data;
4437 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE06L, &u8Data);
4438 u16Data = (u16Data<<8)|u8Data;
4439 printf("[DVBS]: EQ Sum: =======================: 0x%x\n",u16Data);
4440 //---------------------------------------------------------
4441 //FIQ Status
4442 printf("------------------------------------------------------------------------\n");
4443 printf("Debug Message [FIQ Status]==============================================\n");
4444 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00H, &u8Data);
4445 u16Data = u8Data;
4446 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00L, &u8Data);
4447 u16Data = (u16Data<<8)|u8Data;
4448
4449 if ((u16Data&0x0001)==0x0000)
4450 printf("[DVBS]: AGC Lock ======================: Fail. \n");
4451 else
4452 printf("[DVBS]: AGC Lock ======================: OK. \n");
4453
4454 if ((u16Data&0x0002)==0x0000)
4455 printf("[DVBS]: Hum Detect ====================: Fail. \n");
4456 else
4457 printf("[DVBS]: Hum Detect ====================: OK. \n");
4458
4459 if ((u16Data&0x0004)==0x0000)
4460 printf("[DVBS]: DCR Lock ======================: Fail. \n");
4461 else
4462 printf("[DVBS]: DCR Lock ======================: OK. \n");
4463
4464 if ((u16Data&0x0008)==0x0000)
4465 printf("[DVBS]: IIS Detect ====================: Fail. \n");
4466 else
4467 printf("[DVBS]: IIS Detect ====================: OK. \n");
4468
4469 if ((u16Data&0x0010)==0x0000)
4470 printf("[DVBS]: DAGC0 Lock ====================: Fail. \n");
4471 else
4472 printf("[DVBS]: DAGC0 Lock ====================: OK. \n");
4473
4474 if ((u16Data&0x0020)==0x0000)
4475 printf("[DVBS]: DAGC1 Lock ====================: Fail. \n");
4476 else
4477 printf("[DVBS]: DAGC1 Lock ====================: OK. \n");
4478
4479 if ((u16Data&0x0040)==0x0000)
4480 printf("[DVBS]: DAGC2 Lock ====================: Fail. \n");
4481 else
4482 printf("[DVBS]: DAGC2 Lock ====================: OK. \n");
4483
4484 if ((u16Data&0x0080)==0x0000)
4485 printf("[DVBS]: CCI Detect ====================: Fail. \n");
4486 else
4487 printf("[DVBS]: CCI Detect ====================: OK. \n");
4488
4489 if ((u16Data&0x0100)==0x0000)
4490 printf("[DVBS]: SRD Coarse Done ===============: Fail. \n");
4491 else
4492 printf("[DVBS]: SRD Coarse Done ===============: OK. \n");
4493
4494 if ((u16Data&0x0200)==0x0000)
4495 printf("[DVBS]: SRD Fine Done =================: Fail. \n");
4496 else
4497 printf("[DVBS]: SRD Fine Done =================: OK. \n");
4498
4499 if ((u16Data&0x0400)==0x0000)
4500 printf("[DVBS]: EQ Lock =======================: Fail. \n");
4501 else
4502 printf("[DVBS]: EQ Lock =======================: OK. \n");
4503
4504 if ((u16Data&0x0800)==0x0000)
4505 printf("[DVBS]: FineFE Done ===================: Fail. \n");
4506 else
4507 printf("[DVBS]: FineFE Done ===================: OK. \n");
4508
4509 if ((u16Data&0x1000)==0x0000)
4510 printf("[DVBS]: PR Lock =======================: Fail. \n");
4511 else
4512 printf("[DVBS]: PR Lock =======================: OK. \n");
4513
4514 if ((u16Data&0x2000)==0x0000)
4515 printf("[DVBS]: Reserved Frame ================: Fail. \n");
4516 else
4517 printf("[DVBS]: Reserved Frame ================: OK. \n");
4518
4519 if ((u16Data&0x4000)==0x0000)
4520 printf("[DVBS]: Dummy Frame ===================: Fail. \n");
4521 else
4522 printf("[DVBS]: Dummy Frame ===================: OK. \n");
4523
4524 if ((u16Data&0x8000)==0x0000)
4525 printf("[DVBS]: PLSC Done =====================: Fail. \n");
4526 else
4527 printf("[DVBS]: PLSC Done =====================: OK. \n");
4528
4529 printf("------------------------------------------------------------------------\n");
4530 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01H, &u8Data);
4531 u16Data = u8Data;
4532 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01L, &u8Data);
4533 u16Data = (u16Data<<8)|u8Data;
4534 if ((u16Data&0x0001)==0x0000)
4535 printf("[DVBS]: FS Get Info From Len ==========: Fail. \n");
4536 else
4537 printf("[DVBS]: FS Get Info From Len ==========: OK. \n");
4538
4539 if ((u16Data&0x0002)==0x0000)
4540 printf("[DVBS]: IQ Swap Detect ================: Fail. \n");
4541 else
4542 printf("[DVBS]: IQ Swap Detect ================: OK. \n");
4543
4544 if ((u16Data&0x0004)==0x0000)
4545 printf("[DVBS]: FS Acquisition ================: Fail. \n");
4546 else
4547 printf("[DVBS]: FS Acquisition ================: OK. \n");
4548
4549 if ((u16Data&0x0008)==0x0000)
4550 printf("[DVBS]: TR Lock =======================: Fail. \n");
4551 else
4552 printf("[DVBS]: TR Lock =======================: OK. \n");
4553
4554 if ((u16Data&0x0010)==0x0000)
4555 printf("[DVBS]: CLCFE Lock ====================: Fail. \n");
4556 else
4557 printf("[DVBS]: CLCFE Lock ====================: OK. \n");
4558
4559 if ((u16Data&0x0020)==0x0000)
4560 printf("[DVBS]: OLCFE Lock ====================: Fail. \n");
4561 else
4562 printf("[DVBS]: OLCFE Lock ====================: OK. \n");
4563
4564 if ((u16Data&0x0040)==0x0000)
4565 printf("[DVBS]: Fsync Found ===================: Fail. \n");
4566 else
4567 printf("[DVBS]: Fsync Found ===================: OK. \n");
4568
4569 if ((u16Data&0x0080)==0x0000)
4570 printf("[DVBS]: Fsync Lock ====================: Fail. \n");
4571 else
4572 printf("[DVBS]: Fsync Lock ====================: OK. \n");
4573
4574 if ((u16Data&0x0100)==0x0000)
4575 printf("[DVBS]: Fsync Fail Search =============: Fail. \n");
4576 else
4577 printf("[DVBS]: Fsync Fail Search =============: OK. \n");
4578
4579 if ((u16Data&0x0200)==0x0000)
4580 printf("[DVBS]: Fsync Fail Lock ===============: Fail. \n");
4581 else
4582 printf("[DVBS]: Fsync Fail Lock ===============: OK. \n");
4583
4584 if ((u16Data&0x0400)==0x0000)
4585 printf("[DVBS]: False Alarm ===================: Fail. \n");
4586 else
4587 printf("[DVBS]: False Alarm ===================: OK. \n");
4588
4589 if ((u16Data&0x0800)==0x0000)
4590 printf("[DVBS]: Viterbi In Sync ===============: Fail. \n");
4591 else
4592 printf("[DVBS]: Viterbi In Sync ===============: OK. \n");
4593
4594 if ((u16Data&0x1000)==0x0000)
4595 printf("[DVBS]: Uncrt Over ====================: Fail. \n");
4596 else
4597 printf("[DVBS]: Uncrt Over ====================: OK. \n");
4598
4599 if ((u16Data&0x2000)==0x0000)
4600 printf("[DVBS]: CLK Cnt Over ==================: Fail. \n");
4601 else
4602 printf("[DVBS]: CLK Cnt Over ==================: OK. \n");
4603
4604 //if ((u16Data&0x4000)==0x0000)
4605 // printf("[DVBS]: Data In Ready FIFO ============: Fail. \n");
4606 //else
4607 // printf("[DVBS]: Data In Ready FIFO ============: OK. \n");
4608
4609 //if ((u16Data&0x8000)==0x0000)
4610 // printf("[DVBS]: IIR Buff Busy =================: Fail. \n");
4611 //else
4612 // printf("[DVBS]: IIR Buff Busy =================: OK. \n");
4613
4614 /*
4615 printf("------------------------------------------------------------------------\n");
4616 u16Address = 0x0B64;
4617 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address+1, &u8Data);
4618 u16Data = u8Data;
4619 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address , &u8Data);
4620 u16Data = (u16Data<<8)|u8Data;
4621 if ((u16Data&0x0001)==0x0000)
4622 printf("[DVBS]: IIR Busy LDPC =================: Fail. \n");
4623 else
4624 printf("[DVBS]: IIR Busy LDPC =================: OK. \n");
4625
4626 if ((u16Data&0x0002)==0x0000)
4627 printf("[DVBS]: BCH Busy ======================: Fail. \n");
4628 else
4629 printf("[DVBS]: BCH Busy ======================: OK. \n");
4630
4631 if ((u16Data&0x0004)==0x0000)
4632 printf("[DVBS]: Oppro Ready Out ===============: Fail. \n");
4633 else
4634 printf("[DVBS]: Oppro Ready Out ===============: OK. \n");
4635
4636 if ((u16Data&0x0008)==0x0000)
4637 printf("[DVBS]: LDPC Win ======================: Fail. \n");
4638 else
4639 printf("[DVBS]: LDPC Win ======================: OK. \n");
4640
4641 if ((u16Data&0x0010)==0x0000)
4642 printf("[DVBS]: LDPC Error ====================: Fail. \n");
4643 else
4644 printf("[DVBS]: LDPC Error ====================: OK. \n");
4645
4646 if ((u16Data&0x0020)==0x0000)
4647 printf("[DVBS]: Out BCH Error =================: Fail. \n");
4648 else
4649 printf("[DVBS]: Out BCH Error =================: OK. \n");
4650
4651 if ((u16Data&0x0040)==0x0000)
4652 printf("[DVBS]: Descr BCH FEC Num Error =======: Fail. \n");
4653 else
4654 printf("[DVBS]: Descr BCH FEC Num Error =======: OK. \n");
4655
4656 if ((u16Data&0x0080)==0x0000)
4657 printf("[DVBS]: Descr BCH Data Num Error ======: Fail. \n");
4658 else
4659 printf("[DVBS]: Descr BCH Data Num Error ======: OK. \n");
4660
4661 if ((u16Data&0x0100)==0x0000)
4662 printf("[DVBS]: Packet Error Out ==============: Fail. \n");
4663 else
4664 printf("[DVBS]: Packet Error Out ==============: OK. \n");
4665
4666 if ((u16Data&0x0200)==0x0000)
4667 printf("[DVBS]: BBH CRC Error =================: Fail. \n");
4668 else
4669 printf("[DVBS]: BBH CRC Error =================: OK. \n");
4670
4671 if ((u16Data&0x0400)==0x0000)
4672 printf("[DVBS]: BBH Decode Done ===============: Fail. \n");
4673 else
4674 printf("[DVBS]: BBH Decode Done ===============: OK. \n");
4675
4676 if ((u16Data&0x0800)==0x0000)
4677 printf("[DVBS]: ISRC Calculate Done ===========: Fail. \n");
4678 else
4679 printf("[DVBS]: ISRC Calculate Done ===========: OK. \n");
4680
4681 if ((u16Data&0x1000)==0x0000)
4682 printf("[DVBS]: Syncd Check Error =============: Fail. \n");
4683 else
4684 printf("[DVBS]: Syncd Check Error =============: OK. \n");
4685
4686 //if ((u16Data&0x2000)==0x0000)
4687 // printf("[DVBS]: Syncd Check Error======: Fail. \n");
4688 //else
4689 // printf("[DVBS]: Syncd Check Error======: OK. \n");
4690
4691 if ((u16Data&0x4000)==0x0000)
4692 printf("[DVBS]: Demap Init ====================: Fail. \n");
4693 else
4694 printf("[DVBS]: Demap Init ====================: OK. \n");
4695 */
4696 //Spectrum Information
4697 printf("------------------------------------------------------------------------\n");
4698
4699 u16Address = 0x2836;
4700 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4701 psd_smooth_factor=(u16Data>>8)&0x7F;
4702
4703 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
4704 u16Data = u8Data;
4705 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
4706 u16Data = (u16Data<<8)|u8Data;
4707 u32temp5=u16Data;
4708 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13H, &u8Data);
4709 u16Data = u8Data;
4710 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
4711 u16Data = (u16Data<<8)|u8Data;
4712 u32temp5|=(u16Data<<16);
4713 if (psd_smooth_factor!=0)
4714 srd_left_top_value=(float)u32temp5/256.0/psd_smooth_factor;
4715 else
4716 srd_left_top_value=0;
4717
4718 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
4719 u16Data = u8Data;
4720 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
4721 u16Data = (u16Data<<8)|u8Data;
4722 u32temp5=u16Data;
4723 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
4724 u16Data = u8Data;
4725 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
4726 u16Data = (u16Data<<8)|u8Data;
4727 u32temp5|=(u16Data<<16);
4728 if (psd_smooth_factor!=0)
4729 srd_left_bottom_value=(float)u32temp5/256.0/psd_smooth_factor;
4730 else
4731 srd_left_bottom_value=0;
4732
4733 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
4734 u16Data = u8Data;
4735 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
4736 u16Data = (u16Data<<8)|u8Data;
4737 u32temp5=u16Data;
4738 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE17H, &u8Data);
4739 u16Data = u8Data;
4740 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE17L, &u8Data);
4741 u16Data = (u16Data<<8)|u8Data;
4742 u32temp5|=(u16Data<<16);
4743 if (psd_smooth_factor!=0)
4744 srd_right_top_value=(float)u32temp5/256.0/psd_smooth_factor;
4745 else
4746 srd_right_top_value=0;
4747
4748 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18H, &u8Data);
4749 u16Data = u8Data;
4750 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18L, &u8Data);
4751 u16Data = (u16Data<<8)|u8Data;
4752 u32temp5=u16Data;
4753 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19H, &u8Data);
4754 u16Data = u8Data;
4755 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19L, &u8Data);
4756 u16Data = (u16Data<<8)|u8Data;
4757 u32temp5|=(u16Data<<16);
4758 if (psd_smooth_factor!=0)
4759 srd_right_bottom_value=(float)u32temp5/256.0/psd_smooth_factor;
4760 else
4761 srd_right_bottom_value=0;
4762
4763 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1AH, &u8Data);
4764 u16Data = u8Data;
4765 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1AL, &u8Data);
4766 u16Data = (u16Data<<8)|u8Data;
4767 srd_left=u16Data;
4768 printf("[DVBS]: FFT Left ======================: %d, %f\n", srd_left, srd_left_top_value - srd_left_bottom_value);
4769 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1BH, &u8Data);
4770 u16Data = u8Data;
4771 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1BL, &u8Data);
4772 u16Data = (u16Data<<8)|u8Data;
4773 srd_right=u16Data;
4774 printf("[DVBS]: FFT Right =====================: %d, %f\n", srd_right, srd_right_top_value - srd_right_bottom_value);
4775 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1CH, &u8Data);
4776 u16Data = u8Data;
4777 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1CL, &u8Data);
4778 u16Data = (u16Data<<8)|u8Data;
4779 srd_left_top=u16Data;
4780 printf("[DVBS]: FFT Left Top ==================: %d, %f\n", srd_left_top, srd_left_top_value);
4781 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1DH, &u8Data);
4782 u16Data = u8Data;
4783 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1DL, &u8Data);
4784 u16Data = (u16Data<<8)|u8Data;
4785 srd_left_bottom=u16Data;
4786 printf("[DVBS]: FFT Left Bottom ===============: %d, %f\n", srd_left_bottom, srd_left_bottom_value);
4787 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1EH, &u8Data);
4788 u16Data = u8Data;
4789 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1EL, &u8Data);
4790 u16Data = (u16Data<<8)|u8Data;
4791 srd_right_top=u16Data;
4792 printf("[DVBS]: FFT Right Top =================: %d, %f\n", srd_right_top, srd_right_top_value);
4793 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1FH, &u8Data);
4794 u16Data = u8Data;
4795 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1FL, &u8Data);
4796 u16Data = (u16Data<<8)|u8Data;
4797 srd_right_bottom=u16Data;
4798 printf("[DVBS]: FFT Right Bottom ==============: %d, %f\n", srd_right_bottom, srd_right_bottom_value);
4799
4800 printf("-----------------------------------------\n");
4801 printf("[DVBS]: Left-Bottom ===================: %d\n", srd_left-srd_left_bottom);
4802 printf("[DVBS]: Left-Top ======================: %d\n", srd_left_top - srd_left);
4803 printf("[DVBS]: Right-Top =====================: %d\n", srd_right - srd_right_top);
4804 printf("[DVBS]: Right-Bottom ==================: %d\n", srd_right_bottom - srd_right);
4805
4806 if (psd_smooth_factor!=0)
4807 {
4808 if ((srd_left_top-srd_left_bottom)!=0)
4809 printf("[DVBS]: Left Slope ====================: %f\n", (srd_left_top_value - srd_left_bottom_value)/(srd_left_top-srd_left_bottom));
4810 else
4811 printf("[DVBS]: Left Slope ====================: %f\n", 0.000000);
4812
4813 if((srd_right_bottom - srd_right_top)!=0)
4814 printf("[DVBS]: Right Slope ===================: %f\n", (srd_right_top_value - srd_right_bottom_value)/(srd_right_bottom - srd_right_top));
4815 else
4816 printf("[DVBS]: Right Slope ===================: %f\n", 0.000000);
4817
4818 if (((srd_right_top_value - srd_right_bottom_value)!=0)&&((srd_right_bottom - srd_right_top))!=0)
4819 printf("[DVBS]: Slope Ratio ===================: %f\n", ((srd_left_top_value - srd_left_bottom_value)/(srd_left_top-srd_left_bottom))/((srd_right_top_value - srd_right_bottom_value)/(srd_right_bottom - srd_right_top)));
4820 else
4821 printf("[DVBS]: Slope Ratio ===================: %f\n", 0.000000);
4822 }
4823 else
4824 {
4825 printf("[DVBS]: Left Slope ======================: %d\n", 0);
4826 printf("[DVBS]: Right Slope =====================: %d\n", 0);
4827 printf("[DVBS]: Slope Ratio =====================: %d\n", 0);
4828 }
4829 #endif
4830 return status;
4831 }
4832
INTERN_DVBS_Demod_Get_Debug_Info_polling(void)4833 MS_BOOL INTERN_DVBS_Demod_Get_Debug_Info_polling(void)
4834 {
4835 MS_BOOL bRet = FALSE;
4836 #if 0
4837 MS_U8 u8Data = 0;
4838 MS_U16 u16Data = 0;
4839 MS_U16 u16Address = 0;
4840 MS_U32 u32DebugInfo_Fb = 0; //Fb, SymbolRate
4841 MS_U32 u32DebugInfo_Fs = 96000; //Fs, 96000k
4842 float AGC_IF_Gain;
4843 float DAGC0_Gain, DAGC1_Gain, DAGC2_Gain, DAGC3_Gain, DAGC0_Peak_Mean, DAGC1_Peak_Mean, DAGC2_Peak_Mean, DAGC3_Peak_Mean;
4844 short AGC_Err, DAGC0_Err, DAGC1_Err, DAGC2_Err, DAGC3_Err;
4845 float DCR_Offset_I, DCR_Offset_Q;
4846 float FineCFO_loop_input_value, FineCFO_loop_out_value;
4847 double FineCFO_loop_ki_value, TR_loop_ki;
4848 float PR_in_value, PR_out_value, PR_loop_ki, PR_loopback_ki;
4849 float IQB_Phase, IQB_Gain;
4850 MS_U16 IIS_cnt, ConvegenceLen;
4851 float Linear_SNR_dd, SNR_dd_dB, Linear_SNR_da, SNR_da_dB, SNR_nda_dB, Linear_SNR;
4852 float Packet_Err, BER;
4853 float TR_Indicator_ff, TR_SFO_Converge, Fs_value, Fb_value;
4854 float TR_Loop_Output, TR_Loop_Ki, TR_loop_input, TR_tmp0, TR_tmp1, TR_tmp2;
4855 float Eq_variance_da, Eq_variance_dd;
4856 float ndasnr_ratio, ndasnr_a, ndasnr_ab;
4857 MS_U16 BitErr, BitErrPeriod;
4858 MS_BOOL BEROver;
4859
4860 //Fb
4861 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
4862 //bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
4863 if((u8Data&0x02)==0x00) //Manual Tune
4864 {
4865 u32DebugInfo_Fb = 0x0;//_u32CurrentSR;
4866 }
4867 else //Blind Scan
4868 {
4869 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
4870 u16Data = u8Data;
4871 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
4872 u16Data = (u16Data<<8)|u8Data;
4873 u32DebugInfo_Fb = u16Data;
4874 }
4875 printf("++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
4876 printf("Fs ====================================: %lu [kHz]\n",u32DebugInfo_Fs);
4877 printf("Fb ====================================: %lu [kHz]\n",u32DebugInfo_Fb);
4878 //---------------------------------------------------------
4879 //Page1-GAIN & DCR
4880 //---------------------------------------------------------
4881 //GAIN
4882 printf("\n");
4883 printf("========================================================================\n");
4884 printf("Debug Message [GAIN & DCR]==============================================\n");
4885
4886 //Debug select
4887 u16Address = (DEBUG_SEL_IF_AGC_GAIN>>16)&0xffff;
4888 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4889 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_IF_AGC_GAIN)&0xffff);
4890 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4891
4892 //Freeze and dump
4893 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4894 //AGC_IF_GAIN
4895 u16Address = (DEBUG_OUT_AGC)&0xffff;
4896 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4897 AGC_IF_Gain=u16Data;
4898 //Unfreeze
4899 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4900
4901 AGC_IF_Gain=AGC_IF_Gain/0x8000; //(16, 15)
4902 printf("[DVBS]: AGC_IF_Gain ===================: %f\n", AGC_IF_Gain);
4903 //---------------------------------------------------------
4904 //Debug select
4905 u16Address = (DEBUG_SEL_DAGC0_GAIN>>16)&0xffff;
4906 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4907 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_GAIN)&0xffff);
4908 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4909
4910 //Freeze and dump
4911 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4912 //DAGC0_GAIN
4913 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
4914 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4915 u16Data = (u16Data>>4);
4916 DAGC0_Gain=(u16Data&0x0fff);
4917 //Unfreeze
4918 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4919 //---------------------------------------------------------
4920 //Debug select
4921 u16Address = (DEBUG_SEL_DAGC1_GAIN>>16)&0xffff;
4922 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4923 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_GAIN)&0xffff);
4924 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4925
4926 //Freeze and dump
4927 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4928 //DAGC1_GAIN
4929 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
4930 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4931 DAGC1_Gain=(u16Data&0x07ff);
4932 //Unfreeze
4933 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4934 //---------------------------------------------------------
4935 //Debug select
4936 u16Address = (DEBUG_SEL_DAGC2_GAIN>>16)&0xffff;
4937 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4938 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_GAIN)&0xffff);
4939 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4940
4941 //Freeze and dump
4942 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4943 //DAGC2_GAIN
4944 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
4945 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4946 DAGC2_Gain=(u16Data&0x0fff);
4947 //Unfreeze
4948 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4949 //---------------------------------------------------------
4950 //Debug select
4951 u16Address = (DEBUG_SEL_DAGC3_GAIN>>16)&0xffff;
4952 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4953 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_GAIN)&0xffff);
4954 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4955
4956 //Freeze and dump
4957 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4958 //DAGC3_GAIN
4959 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
4960 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4961 u16Data = (u16Data>>4);
4962 DAGC3_Gain=(u16Data&0x0fff);
4963 //Unfreeze
4964 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4965 //---------------------------------------------------------
4966
4967 DAGC0_Gain=DAGC0_Gain/0x200; //<12,9>
4968 DAGC1_Gain=DAGC1_Gain/0x200; //<11,9>
4969 DAGC2_Gain=DAGC2_Gain/0x200; //<12,9>
4970 DAGC3_Gain=DAGC3_Gain/0x200; //<12,9>
4971 printf("[DVBS]: DAGC0_Gain ====================: %f\n", DAGC0_Gain);
4972 printf("[DVBS]: DAGC1_Gain ====================: %f\n", DAGC1_Gain);
4973 printf("[DVBS]: DAGC2_Gain ====================: %f\n", DAGC2_Gain);
4974 printf("[DVBS]: DAGC3_Gain ====================: %f\n", DAGC3_Gain);
4975
4976 //---------------------------------------------------------
4977 //ERROR
4978 //Debug select
4979 u16Address = (DEBUG_SEL_AGC_ERR>>16)&0xffff;
4980 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4981 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_AGC_ERR)&0xffff);
4982 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4983
4984 //Freeze and dump
4985 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4986 //AGC_ERR
4987 u16Address = (DEBUG_OUT_AGC)&0xffff;
4988 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4989 AGC_Err=(u16Data&0x03ff);
4990 //Unfreeze
4991 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4992
4993 //Debug select
4994 u16Address = (DEBUG_SEL_DAGC0_ERR>>16)&0xffff;
4995 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4996 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_ERR)&0xffff);
4997 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4998
4999 //Freeze and dump
5000 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5001 //DAGC0_ERR
5002 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
5003 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5004 u16Data = (u16Data>>4);
5005 DAGC0_Err=(u16Data&0x7fff);
5006 //Unfreeze
5007 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5008
5009 //Debug select
5010 u16Address = (DEBUG_SEL_DAGC1_ERR>>16)&0xffff;
5011 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5012 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_ERR)&0xffff);
5013 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5014
5015 //Freeze and dump
5016 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5017 //DAGC1_ERR
5018 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
5019 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5020 DAGC1_Err=(u16Data&0x7fff);
5021 //Unfreeze
5022 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5023
5024 //Debug select
5025 u16Address = (DEBUG_SEL_DAGC2_ERR>>16)&0xffff;
5026 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5027 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_ERR)&0xffff);
5028 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5029
5030 //Freeze and dump
5031 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5032 //DAGC2_ERR
5033 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
5034 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5035 DAGC2_Err=(u16Data&0x7fff);
5036 //Unfreeze
5037 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5038
5039 //Debug select
5040 u16Address = (DEBUG_SEL_DAGC3_ERR>>16)&0xffff;
5041 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5042 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_ERR)&0xffff);
5043 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5044
5045 //Freeze and dump
5046 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5047 //DAGC3_ERR
5048 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
5049 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5050 u16Data = (u16Data>>4);
5051 DAGC3_Err=(u16Data&0x7fff);
5052 //Unfreeze
5053 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5054
5055 if (AGC_Err>=0x200)
5056 AGC_Err=AGC_Err-0x400;
5057 if (DAGC0_Err>=0x4000)
5058 DAGC0_Err=DAGC0_Err-0x8000;
5059 if (DAGC1_Err>=0x4000)
5060 DAGC1_Err=DAGC1_Err-0x8000;
5061 if (DAGC2_Err>=0x4000)
5062 DAGC2_Err=DAGC2_Err-0x8000;
5063 if (DAGC3_Err>=0x4000)
5064 DAGC3_Err=DAGC3_Err-0x8000;
5065
5066 printf("[DVBS]: AGC_Err =========================: %.3f\n", (float)AGC_Err);
5067 printf("[DVBS]: DAGC0_Err =======================: %.3f\n", (float)DAGC0_Err);
5068 printf("[DVBS]: DAGC1_Err =======================: %.3f\n", (float)DAGC1_Err);
5069 printf("[DVBS]: DAGC2_Err =======================: %.3f\n", (float)DAGC2_Err);
5070 printf("[DVBS]: DAGC3_Err =======================: %.3f\n", (float)DAGC3_Err);
5071 //---------------------------------------------------------
5072 //PEAK_MEAN
5073 //Debug select
5074 u16Address = (DEBUG_SEL_DAGC0_PEAK_MEAN>>16)&0xffff;
5075 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5076 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_PEAK_MEAN)&0xffff);
5077 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5078
5079 //Freeze and dump
5080 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5081 //DAGC0_PEAK_MEAN
5082 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
5083 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5084 u16Data = (u16Data>>4);
5085 DAGC0_Peak_Mean=(u16Data&0x0fff);
5086 //Unfreeze
5087 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5088
5089 //Debug select
5090 u16Address = (DEBUG_SEL_DAGC1_PEAK_MEAN>>16)&0xffff;
5091 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5092 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_PEAK_MEAN)&0xffff);
5093 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5094
5095 //Freeze and dump
5096 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5097 //DAGC1_PEAK_MEAN
5098 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
5099 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5100 DAGC1_Peak_Mean=(u16Data&0x0fff);
5101 //Unfreeze
5102 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5103
5104 //Debug select
5105 u16Address = (DEBUG_SEL_DAGC2_PEAK_MEAN>>16)&0xffff;
5106 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5107 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_PEAK_MEAN)&0xffff);
5108 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5109
5110 //Freeze and dump
5111 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5112 //DAGC2_PEAK_MEAN
5113 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
5114 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5115 DAGC2_Peak_Mean=(u16Data&0x0fff);
5116 //Unfreeze
5117 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5118
5119 //Debug select
5120 u16Address = (DEBUG_SEL_DAGC3_PEAK_MEAN>>16)&0xffff;
5121 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5122 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_PEAK_MEAN)&0xffff);
5123 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5124
5125 //Freeze and dump
5126 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5127 //DAGC3_PEAK_MEAN
5128 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
5129 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5130 u16Data = (u16Data>>4);
5131 DAGC3_Peak_Mean=(u16Data&0x0fff);
5132 //Unfreeze
5133 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5134
5135
5136 DAGC0_Peak_Mean = DAGC0_Peak_Mean / 0x800; //<12,11>
5137 DAGC1_Peak_Mean = DAGC1_Peak_Mean / 0x800; //<12,11>
5138 DAGC2_Peak_Mean = DAGC2_Peak_Mean / 0x800; //<12,11>
5139 DAGC3_Peak_Mean = DAGC3_Peak_Mean / 0x800; //<12,11>
5140
5141 printf("[DVBS]: DAGC0_Peak_Mean ===============: %f\n", DAGC0_Peak_Mean);
5142 printf("[DVBS]: DAGC1_Peak_Mean ===============: %f\n", DAGC1_Peak_Mean);
5143 printf("[DVBS]: DAGC2_Peak_Mean ===============: %f\n", DAGC2_Peak_Mean);
5144 printf("[DVBS]: DAGC3_Peak_Mean ===============: %f\n", DAGC3_Peak_Mean);
5145 //---------------------------------------------------------
5146 //Freeze and dump
5147 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5148
5149 u16Address = (DCR_OFFSET)&0xffff;
5150 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5151
5152 DCR_Offset_I=(u16Data&0xff);
5153 if (DCR_Offset_I >= 0x80)
5154 DCR_Offset_I = DCR_Offset_I-0x100;
5155 DCR_Offset_I = DCR_Offset_I/0x80;
5156
5157 DCR_Offset_Q=(u16Data>>8)&0xff;
5158 if (DCR_Offset_Q >= 0x80)
5159 DCR_Offset_Q = DCR_Offset_Q-0x100;
5160 DCR_Offset_Q = DCR_Offset_Q/0x80;
5161
5162 //Unfreeze
5163 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5164
5165 printf("[DVBS]: DCR_Offset_I ==================: %f\n", DCR_Offset_I);
5166 printf("[DVBS]: DCR_Offset_Q ==================: %f\n", DCR_Offset_Q);
5167 //---------------------------------------------------------
5168 ////Page1-FineCFO & PR & IIS & IQB
5169 //---------------------------------------------------------
5170 //FineCFO
5171 printf("------------------------------------------------------------------------\n");
5172 printf("Debug Message [FineCFO & PR & IIS & IQB & SNR Status]===================\n");
5173 //Debug Select
5174 u16Address = INNER_DEBUG_SEL;
5175 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5176 u16Data=((u16Data&0xC0FF)|0x0400);
5177 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5178
5179 //Freeze and dump
5180 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5181
5182 u16Address = INNEREXT_FINEFE_DBG_OUT0;
5183 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5184 FineCFO_loop_out_value=u16Data;
5185 u16Address = INNEREXT_FINEFE_DBG_OUT2;
5186 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5187 FineCFO_loop_out_value=(FineCFO_loop_out_value+(float)u16Data*pow(2.0, 16));
5188
5189 //Too large.Use 10Bit
5190 u16Address = INNEREXT_FINEFE_KI_FF0;
5191 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5192 FineCFO_loop_ki_value=u16Data;
5193 u16Address = INNEREXT_FINEFE_KI_FF2;
5194 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5195 FineCFO_loop_ki_value=(FineCFO_loop_ki_value+(float)u16Data*pow(2.0, 16));
5196 u16Address = INNEREXT_FINEFE_KI_FF4;
5197 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5198 FineCFO_loop_ki_value=(FineCFO_loop_ki_value+(double)(u16Data&0x00FF)*pow(2.0, 32));
5199 //Unfreeze
5200 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5201
5202 //---------------------------------------------------------
5203 //Debug Select
5204 u16Address = INNER_DEBUG_SEL;
5205 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5206 u16Data=((u16Data&0xC0FF)|0x0100);
5207 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5208
5209 //Freeze and dump
5210 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5211
5212 u16Address = INNEREXT_FINEFE_DBG_OUT0;
5213 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5214 FineCFO_loop_input_value=u16Data;
5215 u16Address = INNEREXT_FINEFE_DBG_OUT2;
5216 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5217 FineCFO_loop_input_value=(FineCFO_loop_input_value+(float)u16Data*pow(2.0, 16));
5218
5219 //Unfreeze
5220 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5221
5222 FineCFO_loop_ki_value = FineCFO_loop_ki_value/1024;
5223
5224 if (FineCFO_loop_out_value > 8388608)
5225 FineCFO_loop_out_value=FineCFO_loop_out_value - 16777216;
5226 if (FineCFO_loop_ki_value > 536870912)//549755813888/1024)
5227 FineCFO_loop_ki_value=FineCFO_loop_ki_value - 1073741824;//1099511627776/1024;
5228 if (FineCFO_loop_input_value> 1048576)
5229 FineCFO_loop_input_value=FineCFO_loop_input_value - 2097152;
5230
5231 FineCFO_loop_out_value = ((float)FineCFO_loop_out_value/16777216);
5232 FineCFO_loop_ki_value = ((double)FineCFO_loop_ki_value/67108864*u32DebugInfo_Fb);//68719476736/1024*Fb
5233 FineCFO_loop_input_value = ((float)FineCFO_loop_input_value/2097152);
5234
5235 printf("[DVBS]: FineCFO_loop_out_value ========: %f \n", FineCFO_loop_out_value);
5236 printf("[DVBS]: FineCFO_loop_ki_value =========: %f \n", FineCFO_loop_ki_value);
5237 printf("[DVBS]: FineCFO_loop_input_value ======: %f \n", FineCFO_loop_input_value);
5238
5239 //---------------------------------------------------------
5240 //Phase Recovery
5241 //Debug select
5242 u16Address = INNER_DEBUG_SEL;
5243 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5244 u16Data=(((u16Data&0x00FF)|0x0600)&0xffff);
5245 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5246
5247 //Freeze and dump
5248 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5249
5250 u16Address = INNER_PR_DEBUG_OUT0;
5251 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5252 PR_out_value=u16Data;
5253 if (PR_out_value>=0x1000)
5254 PR_out_value=PR_out_value-0x2000;
5255
5256 //Unfreeze
5257 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5258 //---------------------------------------------------------
5259 //Debug select
5260 u16Address = INNER_DEBUG_SEL;
5261 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5262 u16Data=(((u16Data&0x00FF)|0x0100)&0xffff);
5263 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5264
5265 //Freeze and dump
5266 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5267
5268 u16Address = INNER_PR_DEBUG_OUT0;
5269 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5270 PR_in_value=u16Data;
5271 u16Address = INNER_PR_DEBUG_OUT2;
5272 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5273 PR_in_value=(((u16Data&0x000F)<<16)|(MS_U16)PR_in_value);
5274 if (PR_in_value>=0x80000)
5275 PR_in_value=PR_in_value-0x100000;
5276
5277 //Unfreeze
5278 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5279 //---------------------------------------------------------
5280 //Debug select
5281 u16Address = INNER_DEBUG_SEL;
5282 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5283 u16Data=(((u16Data&0xC0FF)|0x0400)&0xffff);
5284 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5285
5286 //Freeze and dump
5287 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5288
5289 u16Address = INNER_PR_DEBUG_OUT0;
5290 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5291 PR_loop_ki=u16Data;
5292 u16Address = INNER_PR_DEBUG_OUT2;
5293 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5294 PR_loop_ki=(((u16Data&0x00FF)<<16)+PR_loop_ki);
5295 if (PR_loop_ki>=0x800000)
5296 PR_loop_ki=PR_loop_ki-0x1000000;
5297
5298 //Unfreeze
5299 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5300 //---------------------------------------------------------
5301 //Debug select
5302 u16Address = INNER_DEBUG_SEL;
5303 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5304 u16Data=(((u16Data&0x00FF)|0x0500)&0xffff);
5305 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5306
5307 //Freeze and dump
5308 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5309
5310 u16Address = INNER_PR_DEBUG_OUT0;
5311 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5312 PR_loopback_ki=u16Data;
5313 u16Address = INNER_PR_DEBUG_OUT2;
5314 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5315 PR_loopback_ki=(((u16Data&0x00FF)<<16)+PR_loopback_ki);
5316 if (PR_loopback_ki>=0x800000)
5317 PR_loopback_ki=PR_loopback_ki-0x1000000;
5318
5319 //Unfreeze
5320 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5321
5322 PR_out_value = ((float)PR_out_value/4096);
5323 PR_in_value = ((float)PR_in_value/131072);
5324 PR_loop_ki = ((float)PR_loop_ki/67108864*u32DebugInfo_Fb);
5325 PR_loopback_ki = ((float)PR_loopback_ki/67108864*u32DebugInfo_Fb);
5326
5327 printf("[DVBS]: PR_out_value ==================: %f\n", PR_out_value);
5328 printf("[DVBS]: PR_in_value ===================: %f\n", PR_in_value);
5329 printf("[DVBS]: PR_loop_ki ====================: %f\n", PR_loop_ki);
5330 printf("[DVBS]: PR_loopback_ki ================: %f\n", PR_loopback_ki);
5331 //---------------------------------------------------------
5332 //IIS
5333 //Freeze and dump
5334 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5335
5336 u16Address = (IIS_COUNT0)&0xffff;
5337 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5338 IIS_cnt=u16Data;
5339 u16Address = (IIS_COUNT2)&0xffff;
5340 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5341 IIS_cnt=(u16Data&0x1f)<<16|IIS_cnt;
5342
5343 printf("[DVBS]: IIS_cnt =======================: %d\n", IIS_cnt);
5344
5345 //Unfreeze
5346 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5347 //IQB
5348 //Freeze and dump
5349 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5350
5351 u16Address = (IQB_PHASE)&0xffff;
5352 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5353 IQB_Phase=u16Data&0x3FF;
5354 if (IQB_Phase>=0x200)
5355 IQB_Phase=IQB_Phase-0x400;
5356 IQB_Phase=IQB_Phase/0x400*180;
5357
5358 u16Address = (IQB_GAIN)&0xffff;
5359 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5360 IQB_Gain=u16Data&0x7FF;
5361 IQB_Gain=IQB_Gain/0x400;
5362
5363 printf("[DVBS]: IQB_Phase =====================: %f\n", IQB_Phase);
5364 printf("[DVBS]: IQB_Gain ======================: %f\n", IQB_Gain);
5365
5366 //Unfreeze
5367 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5368 //---------------------------------------------------------
5369 //SNR
5370 //Freeze and dump
5371 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5372
5373 Eq_variance_da=0;
5374 u16Address = 0x249E;
5375 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5376 Eq_variance_da=u16Data;
5377 u16Address = 0x24A0;
5378 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5379 Eq_variance_da=((float)(u16Data&0x03fff)*pow(2.0, 16)+Eq_variance_da)/pow(2.0, 29);
5380
5381 if (Eq_variance_da==0)
5382 Eq_variance_da=1;
5383 Linear_SNR_da=1.0/Eq_variance_da;
5384 SNR_da_dB=10*log10(Linear_SNR_da);
5385
5386 Eq_variance_dd=0;
5387 u16Address = 0x24A2;
5388 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5389 Eq_variance_dd=u16Data;
5390 u16Address = 0x24A4;
5391 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5392 Eq_variance_dd=(((float)(u16Data&0x3fff)*65536)+Eq_variance_dd)/pow(2.0, 29);
5393
5394 if (Eq_variance_dd==0)
5395 Eq_variance_dd=1;
5396 Linear_SNR_dd=1.0/Eq_variance_dd;
5397 SNR_dd_dB=10*log10(Linear_SNR_dd);
5398
5399 ndasnr_a=0;
5400 u16Address = 0x248C;
5401 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5402 ndasnr_a=u16Data;
5403 u16Address = 0x248E;
5404 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5405 ndasnr_a=(((float)(u16Data&0x0003)*pow(2.0, 16))+ndasnr_a)/65536;
5406
5407 ndasnr_ab=0;
5408 u16Address = 0x2490;
5409 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5410 ndasnr_ab=u16Data;
5411 u16Address = 0x2492;
5412 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5413 ndasnr_ab=(((float)(u16Data&0x03ff)*pow(2.0, 16))+ndasnr_ab)/4194304;
5414
5415 ndasnr_ab=sqrt(ndasnr_ab);
5416 if (ndasnr_ab==0)
5417 ndasnr_ab=1;
5418 ndasnr_ratio=(float)ndasnr_a/ndasnr_ab;
5419 if (ndasnr_ratio> 1)
5420 SNR_nda_dB=10*log10(1/(ndasnr_ratio - 1));
5421 else
5422 SNR_nda_dB=0;
5423
5424 u16Address = 0x24BA;
5425 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5426 Linear_SNR=u16Data;
5427 u16Address = 0x24BC;
5428 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5429 Linear_SNR=(((float)(u16Data&0x0007)*pow(2.0, 16))+Linear_SNR)/64;
5430 if (Linear_SNR==0)
5431 Linear_SNR=1;
5432 Linear_SNR=10*log10(Linear_SNR);
5433
5434 //Unfreeze
5435 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5436 printf("[DVBS]: SNR ===========================: %.2f\n", Linear_SNR);
5437 printf("[DVBS]: SNR_DA_dB =====================: %.2f\n", SNR_da_dB);
5438 printf("[DVBS]: SNR_DD_dB =====================: %.2f\n", SNR_dd_dB);
5439 printf("[DVBS]: SNR_NDA_dB ====================: %.2f\n", SNR_nda_dB);
5440 //---------------------------------------------------------
5441 printf("------------------------------------------------------------------------\n");
5442 printf("Debug Message [DVBS - PacketErr & BER]==================================\n");
5443 //BER
5444 //freeze
5445 u16Address = 0x2103;
5446 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5447 u16Data=u16Data|0x0001;
5448 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5449
5450 // bank 17 0x18 [7:0] reg_bit_err_sblprd_7_0 [15:8] reg_bit_err_sblprd_15_8
5451 u16Address = 0x2166;
5452 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5453 Packet_Err=u16Data;
5454
5455 printf("[DVBS]: Packet Err ====================: %.3E\n", Packet_Err);
5456
5457 /////////// Post-Viterbi BER /////////////
5458 // bank 7 0x18 [7:0] reg_bit_err_sblprd_7_0
5459 // [15:8] reg_bit_err_sblprd_15_8
5460 u16Address = 0x2146;
5461 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5462 BitErrPeriod=u16Data;
5463
5464 // bank 17 0x1D [7:0] reg_bit_err_num_7_0 [15:8] reg_bit_err_num_15_8
5465 // bank 17 0x1E [7:0] reg_bit_err_num_23_16 [15:8] reg_bit_err_num_31_24
5466 u16Address = 0x216A;
5467 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5468 BitErr=u16Data;
5469 u16Address = 0x216C;
5470 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5471 BitErr=(u16Data<<16)|BitErr;
5472
5473 if (BitErrPeriod ==0 )//protect 0
5474 BitErrPeriod=1;
5475 if (BitErr <=0 )
5476 BER=0.5 / (float)(BitErrPeriod*128*188*8);
5477 else
5478 BER=(float)(BitErr) / (float)(BitErrPeriod*128*188*8);
5479
5480 printf("[DVBS]: Post-Viterbi BER ==============: %.3E\n", BER);
5481
5482 // bank 7 0x19 [7] reg_bit_err_num_freeze
5483 u16Address = 0x2103;
5484 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5485 u16Data=u16Data&(~0x0001);
5486 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5487
5488 /////////// Pre-Viterbi BER /////////////
5489 // bank 17 0x08 [3] reg_rd_freezeber
5490 u16Address = 0x2110;
5491 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5492 u16Data=u16Data|0x0008;
5493 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5494
5495 // bank 17 0x0b [7:0] reg_ber_timerl [15:8] reg_ber_timerm
5496 // bank 17 0x0c [5:0] reg_ber_timerh
5497 u16Address = 0x2116;
5498 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5499 BitErrPeriod=u16Data;
5500 u16Address = 0x2118;
5501 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5502 BitErrPeriod=((u16Data&0x3f)<<16)|BitErrPeriod;
5503
5504 // bank 17 0x0f [7:0] reg_ber_7_0 [15:8] reg_ber_15_8
5505 u16Address = 0x211E;
5506 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5507 BitErr=u16Data;
5508
5509 // bank 17 0x0D [13:8] reg_cor_intstat_reg
5510 u16Address = 0x211A;
5511 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5512 if (u16Data & 0x1000)
5513 {
5514 BEROver = true;
5515 }
5516 else
5517 {
5518 BEROver = false;
5519 }
5520
5521 if (BitErrPeriod ==0 )//protect 0
5522 BitErrPeriod=1;
5523 if (BitErr <=0 )
5524 BER=0.5 / (float)(BitErrPeriod) / 256;
5525 else
5526 BER=(float)(BitErr) / (float)(BitErrPeriod) / 256;
5527 printf("[DVBS]: Pre-Viterbi BER ===============: %.3E\n", BER);
5528
5529 // bank 17 0x08 [3] reg_rd_freezeber
5530 u16Address = 0x2110;
5531 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5532 u16Data=u16Data&(~0x0008);
5533 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5534
5535 u16Address = 0x2188;
5536 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5537 ConvegenceLen = ((u16Data>>8)&0xFF);
5538 printf("[DVBS]: ConvegenceLen =================: %d\n", ConvegenceLen);
5539
5540 //---------------------------------------------------------
5541 //Timing Recovery
5542 //Debug select
5543 u16Address = (INNER_DEBUG_SEL_TR>>16)&0xffff;
5544 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5545 u16Data=(((u16Data&0x00ff)|INNER_DEBUG_SEL_TR)&0xffff);
5546 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5547
5548 //Freeze and dump
5549 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5550
5551 u16Address = (TR_INDICATOR_FF0)&0xffff;
5552 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5553 TR_Indicator_ff=u16Data;
5554 u16Address = (TR_INDICATOR_FF0)&0xffff;
5555 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5556 TR_Indicator_ff=((u16Data<<16) | (MS_U16)TR_Indicator_ff)&0x7fffff;
5557 if (TR_Indicator_ff >= 0x400000)
5558 TR_Indicator_ff=TR_Indicator_ff - 0x800000;
5559
5560 //Unfreeze
5561 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5562
5563 //Debug select
5564 u16Address = (DEBUG_SEL_TR_SFO_CONVERGE>>16)&0xffff;
5565 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5566 u16Data=(((u16Data&0x00ff)|DEBUG_SEL_TR_SFO_CONVERGE)&0xffff);
5567 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5568
5569 //Freeze and dump
5570 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5571
5572 u16Address = (TR_INDICATOR_FF0)&0xffff;
5573 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5574 TR_SFO_Converge=u16Data;
5575 u16Address = (TR_INDICATOR_FF0)&0xffff;
5576 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5577 TR_SFO_Converge=((u16Data<<16) | (MS_U16)TR_SFO_Converge)&0x7fffff;
5578 if (TR_SFO_Converge >= 0x400000)
5579 TR_SFO_Converge=TR_SFO_Converge - 0x800000;
5580
5581 u16Address = INNER_TR_LOPF_VALUE_DEBUG0;
5582 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5583 TR_loop_ki=u16Data;
5584 u16Address = INNER_TR_LOPF_VALUE_DEBUG2;
5585 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5586 TR_loop_ki=((float)u16Data*pow(2.0, 16))+TR_loop_ki;
5587 u16Address = INNER_TR_LOPF_VALUE_DEBUG4;
5588 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5589 TR_loop_ki=(((double)(u16Data&0x01ff)*pow(2.0, 32))+ TR_loop_ki);
5590 if (TR_loop_ki>=pow(2.0, 40))
5591 TR_loop_ki=TR_loop_ki-pow(2.0, 41);
5592
5593 //Unfreeze
5594 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5595
5596 //Debug select
5597 u16Address = (DEBUG_SEL_TR_INPUT>>16)&0xffff;
5598 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5599 u16Data=(((u16Data&0x00ff)|DEBUG_SEL_TR_INPUT)&0xffff);
5600 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5601
5602 //Freeze and dump
5603 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5604
5605 u16Address = (TR_INDICATOR_FF0)&0xffff;
5606 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5607 TR_loop_input=u16Data;
5608 //banknum=(TR_INDICATOR_FF1>>8)&0xff;
5609 //addr=(TR_INDICATOR_FF1)&0xff;
5610 //if(InformRead(banknum, addr, &data)==FALSE) return;
5611 //TR_loop_input=((float)((data&0x00ff)<<16) + TR_loop_input);
5612 if (TR_loop_input >= 0x8000)
5613 TR_loop_input=TR_loop_input - 0x10000;
5614
5615 //Unfreeze
5616 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5617
5618 Fs_value=u32DebugInfo_Fs;
5619 Fb_value=u32DebugInfo_Fb;
5620 TR_tmp0=(float)TR_SFO_Converge/0x200000;
5621 TR_tmp2=TR_loop_ki/pow(2.0, 39);
5622 TR_tmp1=(float)Fs_value/2/Fb_value;
5623
5624 TR_Indicator_ff = (TR_Indicator_ff/0x400);
5625 TR_Loop_Output = (TR_tmp0/TR_tmp1*1000000);
5626 TR_Loop_Ki = (TR_tmp2/TR_tmp1*1000000);
5627 TR_loop_input = (TR_loop_input/0x8000);
5628
5629 printf("[DVBS]: TR_Indicator_ff================: %f \n", TR_Indicator_ff);
5630 printf("[DVBS]: TR_Loop_Output=================: %f [ppm]\n", TR_Loop_Output);
5631 printf("[DVBS]: TR_Loop_Ki=====================: %f [ppm]\n", TR_Loop_Ki);
5632 printf("[DVBS]: TR_loop_input==================: %f \n", TR_loop_input);
5633 #endif
5634 bRet=true;
5635 return bRet;
5636 }
5637
5638 //------------------------------------------------------------------
5639 // END Get And Show Info Function
5640 //------------------------------------------------------------------
5641
5642 //------------------------------------------------------------------
5643 // BlindScan Function
5644 //------------------------------------------------------------------
5645
INTERN_DVBS_BlindScan_Start(MS_U16 u16StartFreq,MS_U16 u16EndFreq)5646 MS_BOOL INTERN_DVBS_BlindScan_Start(MS_U16 u16StartFreq,MS_U16 u16EndFreq)
5647 {
5648 MS_BOOL status=TRUE;
5649 MS_U8 u8Data=0;
5650
5651 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_Start+\n"));
5652
5653 _u16BlindScanStartFreq=u16StartFreq;
5654 _u16BlindScanEndFreq=u16EndFreq;
5655 _u16TunerCenterFreq=0;
5656 _u16ChannelInfoIndex=0;
5657
5658 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5659 u8Data&=0xd0;
5660 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5661
5662 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)_u16BlindScanStartFreq&0x00ff);
5663 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(_u16BlindScanStartFreq>>8)&0x00ff);
5664
5665 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_Start- _u16BlindScanStartFreq%d u16StartFreq %d u16EndFreq %d\n", _u16BlindScanStartFreq, u16StartFreq, u16EndFreq));
5666
5667 return status;
5668 }
5669
INTERN_DVBS_BlindScan_NextFreq(MS_BOOL * bBlindScanEnd)5670 MS_BOOL INTERN_DVBS_BlindScan_NextFreq(MS_BOOL* bBlindScanEnd)
5671 {
5672 MS_BOOL status=TRUE;
5673 MS_U8 u8Data=0;
5674
5675 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_NextFreq+\n"));
5676
5677 * bBlindScanEnd=FALSE;
5678
5679 if (_u16TunerCenterFreq >=_u16BlindScanEndFreq)
5680 {
5681 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_NextFreq . _u16TunerCenterFreq %d _u16BlindScanEndFreq%d\n", _u16TunerCenterFreq, _u16BlindScanEndFreq));
5682 * bBlindScanEnd=TRUE;
5683
5684 return status;
5685 }
5686 //Set Tuner Frequency
5687 MsOS_DelayTask(10);
5688
5689 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5690 if ((u8Data&0x02)==0x00)//Manual Tune
5691 {
5692 u8Data&=~(0x28);
5693 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5694 u8Data|=0x02;
5695 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5696 u8Data|=0x01;
5697 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5698 }
5699 else
5700 {
5701 u8Data&=~(0x28);
5702 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5703 }
5704
5705 return status;
5706 }
5707
INTERN_DVBS_BlindScan_GetTunerFreq(MS_U16 * u16TunerCenterFreq,MS_U16 * u16TunerCutOffFreq)5708 MS_BOOL INTERN_DVBS_BlindScan_GetTunerFreq(MS_U16 *u16TunerCenterFreq, MS_U16 *u16TunerCutOffFreq)
5709 {
5710 MS_BOOL status=TRUE;
5711 MS_U8 u8Data=0;
5712 MS_U16 u16WaitCount;
5713 MS_U16 u16TunerCutOff;
5714
5715 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_SetTunerFreq+\n"));
5716
5717 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5718 if ((u8Data&0x02)==0x02)
5719 {
5720 u8Data|=0x08;
5721 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5722 u16WaitCount=0;
5723 do
5724 {
5725 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
5726 u16WaitCount++;
5727 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
5728 MsOS_DelayTask(1);
5729 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
5730 }
5731 else if((u8Data&0x01)==0x01)
5732 {
5733 u8Data|=0x20;
5734 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5735 u16WaitCount=0;
5736 do
5737 {
5738 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
5739 u16WaitCount++;
5740 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
5741 MsOS_DelayTask(1);
5742 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
5743 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5744 u8Data|=0x02;
5745 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5746 }
5747 u16WaitCount=0;
5748
5749 _u16TunerCenterFreq=0;
5750
5751 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, &u8Data);
5752 //printf("INTERN_DVBS_BlindScan_GetTunerFreq E_DMD_S2_BS_Tuner_Center_Freq_H=%d\n", u8Data);//RRRRR
5753 _u16TunerCenterFreq=u8Data;
5754 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, &u8Data);
5755 //printf("INTERN_DVBS_BlindScan_GetTunerFreq E_DMD_S2_BS_Tuner_Center_Freq_L=%d\n", u8Data);//RRRRR
5756 _u16TunerCenterFreq=(_u16TunerCenterFreq<<8)|u8Data;
5757
5758 *u16TunerCenterFreq = _u16TunerCenterFreq;
5759 //claire test
5760 u16TunerCutOff=44000;
5761 if(_u16TunerCenterFreq<=990)//980
5762 {
5763
5764 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_BALANCE_TRACK, &u8Data);
5765 if(u8Data==0x01)
5766 {
5767 if(_u16TunerCenterFreq<970)//970
5768 {
5769 u16TunerCutOff=10000;
5770 }
5771 else
5772 {
5773 u16TunerCutOff=20000;
5774 }
5775 u8Data=0x02;
5776 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_BALANCE_TRACK, u8Data);
5777 }
5778 else if(u8Data==0x02)
5779 {
5780 u8Data=0x00;
5781 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_BALANCE_TRACK, u8Data);
5782 }
5783 }
5784 *u16TunerCutOffFreq = u16TunerCutOff;
5785
5786 //end claire test
5787
5788 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_SetTunerFreq- _u16TunerCenterFreq:%d\n", _u16TunerCenterFreq));
5789
5790
5791 return status;
5792 }
5793
INTERN_DVBS_BlindScan_WaitCurFreqFinished(MS_U8 * u8Progress,MS_U8 * u8FindNum,MS_U8 * substate_reg,MS_U32 * u32Data,MS_U16 * symbolrate_reg,MS_U16 * CFO_reg)5794 MS_BOOL INTERN_DVBS_BlindScan_WaitCurFreqFinished(MS_U8* u8Progress,MS_U8 *u8FindNum, MS_U8 *substate_reg, MS_U32 *u32Data, MS_U16 *symbolrate_reg, MS_U16 *CFO_reg)
5795 {
5796 MS_BOOL status=TRUE;
5797 //MS_U32 u32Data=0;
5798 MS_U16 u16Data=0;
5799 MS_U8 u8Data=0, u8Data2=0;
5800 MS_U16 u16WaitCount;
5801
5802 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_WaitCurFreqFinished+\n"));
5803
5804 u16WaitCount=0;
5805 *u8FindNum=0;
5806 *u8Progress=0;
5807
5808 do
5809 {
5810 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data); //State=BlindScan
5811 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_BLINDSCAN_CHECK, &u8Data2); //SubState=BlindScan
5812 u16WaitCount++;
5813 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_BlindScan_WaitCurFreqFinished State: 0x%x Status: 0x%x u16WaitCount:%d\n", u8Data, u8Data2, u16WaitCount));
5814 //printf("INTERN_DVBS_BlindScan_WaitCurFreqFinished State: 0x%x Status: 0x%x u16WaitCount:%d\n", u8Data, u8Data2, u16WaitCount);
5815
5816 MsOS_DelayTask(1);
5817 }while(((u8Data!=17)||(u8Data2!=0xff))&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));//E_DMD_S2_STATE_FLAG
5818
5819
5820
5821 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DUMMY_REG_2, &u8Data);
5822 u16Data=u8Data;
5823
5824
5825 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_WaitCurFreqFinished OuterCheckStatus:0x%x\n", u16Data));
5826
5827 if (u16WaitCount>=INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
5828 {
5829 status=false;
5830 ULOGD("DEMOD","Debug blind scan wait finished time out!!!!\n");
5831 }
5832 else
5833 {
5834
5835 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SUBSTATE_FLAG, &u8Data);//SubState
5836 *substate_reg=u8Data;
5837 if (u8Data==0)
5838 {
5839
5840 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
5841 *u32Data=u8Data;
5842 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
5843 *u32Data=(*u32Data<<8)|u8Data;
5844 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
5845 *u32Data=(*u32Data<<8)|u8Data;
5846 //_u16ChannelInfoArray[0][_u16ChannelInfoIndex]=((*u32Data+500)/1000);
5847 //_u16LockedCenterFreq=((*u32Data+500)/1000); //Center Freq
5848
5849
5850 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
5851 u16Data=u8Data;
5852 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
5853 u16Data=(u16Data<<8)|u8Data;
5854 *symbolrate_reg=u16Data;
5855 //_u16ChannelInfoArray[1][_u16ChannelInfoIndex]=(u16Data);//Symbol Rate
5856 //_u16LockedSymbolRate=u16Data;
5857 //_u16ChannelInfoIndex++;
5858 //*u8FindNum=_u16ChannelInfoIndex;
5859 //printf("claire debug blind scan: find TP frequency %d SR %d index %d\n",_u16LockedCenterFreq,_u16LockedSymbolRate,_u16ChannelInfoIndex);
5860
5861
5862 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
5863 u16Data=u8Data;
5864 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
5865 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset_Locked
5866 *CFO_reg=u16Data;
5867 /*
5868 if (u16Data*1000 >= 0x8000)
5869 {
5870 u16Data=0x10000- u16Data*1000;
5871 _s16CurrentCFO=-1*u16Data/1000;
5872 }
5873 else
5874 {
5875 _s16CurrentCFO=u16Data;
5876 }
5877 */
5878 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
5879 u16Data=u8Data;
5880 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
5881 u16Data=(u16Data<<8)|u8Data;
5882 _u16CurrentStepSize=u16Data; //Tuner_Frequency_Step
5883
5884
5885 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18H, &u8Data);
5886 u16Data=u8Data;
5887 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18L, &u8Data);
5888 u16Data=(u16Data<<8)|u8Data;
5889 _u16PreLockedHB=u16Data; //Pre_Scanned_HB
5890
5891
5892 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19H, &u8Data);
5893 u16Data=u8Data;
5894 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19L, &u8Data);
5895 u16Data=(u16Data<<8)|u8Data;
5896 _u16PreLockedLB=u16Data; //Pre_Scanned_LB
5897
5898
5899 DBG_INTERN_DVBS(ULOGD("DEMOD","Current Locked CF:%d BW:%d BWH:%d BWL:%d CFO:%d Step:%d\n", _u16LockedCenterFreq, _u16LockedSymbolRate,_u16PreLockedHB, _u16PreLockedLB, _s16CurrentCFO, _u16CurrentStepSize));
5900 }
5901 else if (u8Data==1)
5902 {
5903 //printf("claire debug blind scan: no find TP\n");
5904
5905
5906 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, &u8Data);
5907 u16Data=u8Data;
5908 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, &u8Data);
5909 u16Data=(u16Data<<8)|u8Data;
5910 _u16NextCenterFreq=u16Data;
5911
5912
5913 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
5914 u16Data=u8Data;
5915 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
5916 u16Data=(u16Data<<8)|u8Data;
5917 _u16PreLockedHB=u16Data; //Pre_Scanned_HB
5918
5919
5920
5921 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13H, &u8Data);
5922 u16Data=u8Data;
5923 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
5924 u16Data=(u16Data<<8)|u8Data;
5925 _u16PreLockedLB=u16Data; //Pre_Scanned_LB
5926
5927
5928 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
5929 u16Data=u8Data;
5930 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
5931 u16Data=(u16Data<<8)|u8Data;
5932 _u16CurrentSymbolRate=u16Data; //Fine_Symbol_Rate
5933
5934
5935 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
5936 u16Data=u8Data;
5937 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
5938 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset
5939 *CFO_reg=u16Data;
5940 /*
5941 if (u16Data*1000 >= 0x8000)
5942 {
5943 u16Data=0x1000- u16Data*1000;
5944 _s16CurrentCFO=-1*u16Data/1000;
5945 }
5946 else
5947 {
5948 _s16CurrentCFO=u16Data;
5949 }
5950 */
5951 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
5952 u16Data=u8Data;
5953 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
5954 u16Data=(u16Data<<8)|u8Data;
5955 _u16CurrentStepSize=u16Data; //Tuner_Frequency_Step
5956
5957
5958 DBG_INTERN_DVBS(ULOGD("DEMOD","Pre Locked CF:%d BW:%d HBW:%d LBW:%d Current CF:%d BW:%d CFO:%d Step:%d\n", _u16LockedCenterFreq, _u16LockedSymbolRate,_u16PreLockedHB, _u16PreLockedLB, _u16NextCenterFreq-_u16CurrentStepSize, _u16CurrentSymbolRate, _s16CurrentCFO, _u16CurrentStepSize));
5959 }
5960 }
5961 *u8Progress=100;
5962
5963 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_WaitCurFreqFinished- u8Progress: %d u8FindNum %d\n", *u8Progress, *u8FindNum));
5964
5965 return status;
5966 }
5967
INTERN_DVBS_BlindScan_Cancel(void)5968 MS_BOOL INTERN_DVBS_BlindScan_Cancel(void)
5969 {
5970 MS_BOOL status=TRUE;
5971 MS_U8 u8Data=0;
5972 MS_U16 u16Data;
5973
5974 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_Cancel+\n"));
5975
5976 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5977 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
5978 u8Data&=0xF0;
5979 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5980 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
5981
5982 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E1, 0x00);
5983 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E0, 0x00);
5984 u16Data = 0x0000;
5985 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)u16Data&0x00ff);
5986 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(u16Data>>8)&0x00ff);
5987
5988 _u16TunerCenterFreq=0;
5989 _u16ChannelInfoIndex=0;
5990
5991 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_Cancel-\n"));
5992
5993 return status;
5994 }
5995
INTERN_DVBS_BlindScan_End(void)5996 MS_BOOL INTERN_DVBS_BlindScan_End(void)
5997 {
5998 MS_BOOL status=TRUE;
5999 MS_U8 u8Data=0;
6000 MS_U16 u16Data;
6001
6002 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_End+\n"));
6003
6004 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6005 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6006 u8Data&=0xF0;
6007 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6008 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6009
6010 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E1, 0x00);
6011 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E0, 0x00);
6012 u16Data = 0x0000;
6013 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)u16Data&0x00ff);
6014 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(u16Data>>8)&0x00ff);
6015
6016 _u16TunerCenterFreq=0;
6017 _u16ChannelInfoIndex=0;
6018
6019 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_End-\n"));
6020
6021 return status;
6022 }
6023
INTERN_DVBS_BlindScan_GetChannel(MS_U16 u16ReadStart,MS_U16 * u16TPNum,HAL_DEMOD_MS_FE_CARRIER_PARAM * pTable)6024 MS_BOOL INTERN_DVBS_BlindScan_GetChannel(MS_U16 u16ReadStart,MS_U16* u16TPNum,HAL_DEMOD_MS_FE_CARRIER_PARAM *pTable)
6025 {
6026 MS_BOOL status=TRUE;
6027 MS_U16 u16TableIndex;
6028
6029 *u16TPNum=_u16ChannelInfoIndex-u16ReadStart;
6030 for(u16TableIndex = 0; u16TableIndex < (*u16TPNum); u16TableIndex++)
6031 {
6032 pTable[u16TableIndex].u32Frequency = _u16ChannelInfoArray[0][_u16ChannelInfoIndex-1];
6033 pTable[u16TableIndex].SatParam.u32SymbolRate = _u16ChannelInfoArray[1][_u16ChannelInfoIndex-1];
6034 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_GetChannel Freq: %d SymbolRate: %d\n", (int)pTable[u16TableIndex].u32Frequency, (int)pTable[u16TableIndex].SatParam.u32SymbolRate));
6035 }
6036 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_u16TPNum:%d\n", *u16TPNum));
6037
6038 return status;
6039 }
6040
INTERN_DVBS_BlindScan_GetCurrentFreq(MS_U32 * u32CurrentFeq)6041 MS_BOOL INTERN_DVBS_BlindScan_GetCurrentFreq(MS_U32 *u32CurrentFeq)
6042 {
6043 MS_BOOL status=TRUE;
6044 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_BlindScan_GetCurrentFreq+\n"));
6045
6046 *u32CurrentFeq=_u16TunerCenterFreq;
6047 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_BlindScan_GetCurrentFreq-: %d\n", _u16TunerCenterFreq));
6048 return status;
6049 }
6050
6051 //------------------------------------------------------------------
6052 // END BlindScan Function
6053 //------------------------------------------------------------------
6054
6055 //------------------------------------------------------------------
6056 // DiSEqc Function
6057 //------------------------------------------------------------------
INTERN_DVBS_DiSEqC_Init(void)6058 MS_BOOL INTERN_DVBS_DiSEqC_Init(void)
6059 {
6060 MS_BOOL status = true;
6061 MS_U8 u8Data = 0;
6062
6063 //Clear status
6064 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6065 u8Data=(u8Data|0x3E)&(~0x3E);
6066 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6067
6068 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, 0x00);
6069 //Tone En
6070 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC0, &u8Data);
6071 u8Data=(u8Data&(~0x06))|(0x06);
6072 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, u8Data);
6073
6074 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_DiSEqC_Init\n"));
6075
6076 return status;
6077 }
6078
INTERN_DVBS_DiSEqC_SetTone(MS_BOOL bTone1)6079 MS_BOOL INTERN_DVBS_DiSEqC_SetTone(MS_BOOL bTone1)
6080 {
6081 MS_BOOL status=TRUE;
6082 MS_U8 u8Data=0;
6083 MS_U8 u8ReSet22k=0;
6084
6085 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC4, 0x01);//0x62;DVBS2_DISEQC_TX1
6086 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, 0x4E);//0x60
6087 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCC, 0x88);//0x66
6088
6089 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);//0x61
6090 u8ReSet22k=u8Data;
6091
6092 if (bTone1==TRUE)
6093 {
6094 //Tone burst 1
6095 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, 0x19);
6096 _u8ToneBurstFlag=1;
6097 }
6098 else
6099 {
6100 //Tone burst 0
6101 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, 0x11);
6102 _u8ToneBurstFlag=2;
6103 }
6104 //DIG_DISEQC_TX_EN
6105 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6106 //u8Data=u8Data&~(0x01);//Tx Disable
6107 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6108
6109 MsOS_DelayTask(1);
6110 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);//0x66 high byte DVBS2_DISEQC_TX_EN
6111 u8Data=u8Data|0x3E; //Status clear
6112 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6113 MsOS_DelayTask(10);
6114 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6115 u8Data=u8Data&~(0x3E);
6116 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6117 MsOS_DelayTask(1);
6118
6119 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
6120 u8Data=u8Data|0x01; //Tx Enable
6121 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
6122
6123 MsOS_DelayTask(30);//(100)
6124 //For ToneBurst 22k issue.
6125 u8Data=u8ReSet22k;
6126 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);//0x61
6127
6128 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_DiSEqC_SetTone:%d\n", bTone1));
6129 //MsOS_DelayTask(100);
6130 return status;
6131 }
6132
INTERN_DVBS_DiSEqC_SetLNBOut(MS_BOOL bLow)6133 MS_BOOL INTERN_DVBS_DiSEqC_SetLNBOut(MS_BOOL bLow)
6134 {
6135 MS_BOOL status=TRUE;
6136 MS_U8 u8Data=0;
6137
6138 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6139 if (bLow==TRUE)
6140 {
6141 u8Data=(u8Data|0x40); //13V
6142 }
6143 else
6144 {
6145 u8Data=(u8Data&(~0x40));//18V
6146 }
6147 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);
6148
6149 return status;
6150 }
6151
INTERN_DVBS_DiSEqC_GetLNBOut(MS_BOOL * bLNBOutLow)6152 MS_BOOL INTERN_DVBS_DiSEqC_GetLNBOut(MS_BOOL* bLNBOutLow)
6153 {
6154 MS_BOOL status=TRUE;
6155 MS_U8 u8Data=0;
6156
6157 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6158 if( (u8Data&0x40)==0x40)
6159 {
6160 * bLNBOutLow=TRUE;
6161 }
6162 else
6163 {
6164 * bLNBOutLow=FALSE;
6165 }
6166
6167 return status;
6168 }
6169
INTERN_DVBS_DiSEqC_Set22kOnOff(MS_BOOL b22kOn)6170 MS_BOOL INTERN_DVBS_DiSEqC_Set22kOnOff(MS_BOOL b22kOn)
6171 {
6172 MS_BOOL status=TRUE;
6173 MS_U8 u8Data=0;
6174
6175 //Set DiSeqC 22K
6176 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCC, 0x44); //Set 11K-->22K
6177
6178 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6179
6180 if (b22kOn==TRUE)
6181 {
6182 u8Data=(u8Data&0xc7);
6183 u8Data=(u8Data|0x08);
6184 }
6185 else
6186 {
6187 u8Data=(u8Data&0xc7);
6188 }
6189 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);
6190
6191 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_DiSEqC_Set22kOnOff:%d\n", b22kOn));
6192 return status;
6193 }
6194
INTERN_DVBS_DiSEqC_Get22kOnOff(MS_BOOL * b22kOn)6195 MS_BOOL INTERN_DVBS_DiSEqC_Get22kOnOff(MS_BOOL* b22kOn)
6196 {
6197 MS_BOOL status=TRUE;
6198 MS_U8 u8Data=0;
6199
6200 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6201 if ((u8Data&0x38)==0x08)
6202 {
6203 *b22kOn=TRUE;
6204 }
6205 else
6206 {
6207 *b22kOn=FALSE;
6208 }
6209
6210 return status;
6211 }
6212
INTERN_DVBS_DiSEqC_SendCmd(MS_U8 * pCmd,MS_U8 u8CmdSize)6213 MS_BOOL INTERN_DVBS_DiSEqC_SendCmd(MS_U8* pCmd,MS_U8 u8CmdSize)
6214 {
6215 MS_BOOL status=TRUE;
6216 MS_U8 u8Data;
6217 MS_U8 u8Index;
6218 MS_U16 u16WaitCount;
6219 /*
6220 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6221 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6222 u8Data=(u8Data&~(0x10));
6223 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6224 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6225 */
6226 #if 0 //For Unicable command timing
6227 u16WaitCount=0;
6228 do
6229 {
6230 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data);
6231 //printf(">>> INTERN_DVBS_DiSEqC_SendCmd DiSEqC Status = 0x%x <<<\n", u8Data);
6232 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6233 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6234 MsOS_DelayTask(1);
6235 u16WaitCount++;
6236 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
6237
6238 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
6239 {
6240 DBG_INTERN_DVBS(printf("INTERN_DVBS DiSEqC Send Command Busy!!!\n"));
6241 return FALSE;
6242 }
6243 #endif
6244
6245 //u16Address=0x0BC4;
6246 for (u8Index=0; u8Index < u8CmdSize; u8Index++)
6247 {
6248 u8Data=*(pCmd+u8Index);
6249 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC4 + u8Index, u8Data);//#define DVBS2_DISEQC_TX1 (_REG_DVBS2(0x62)+0)//[7:0]
6250 DBG_INTERN_DVBS(ULOGD("DEMOD","=============INTERN_DVBS_DiSEqC_SendCmd(Demod1) = 0x%X\n",u8Data));
6251 }
6252
6253 //set DiSEqC Tx Length, Odd Enable, Tone Burst Mode
6254 u8Data=((u8CmdSize-1)&0x07)|0x40;
6255 if (_u8ToneBurstFlag==1)
6256 {
6257 u8Data|=0x80;//0x20;
6258 }
6259 else if (_u8ToneBurstFlag==2)
6260 {
6261 u8Data|=0x20;//0x80;
6262 }
6263 _u8ToneBurstFlag=0;
6264 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_8, u8Data);
6265
6266 //add this only for check mailbox R/W
6267 #if 1
6268 DBG_INTERN_DVBS(ULOGD("DEMOD"," Write into E_DMD_S2_MB_DMDTOP_DBG_8 = 0x%X!!!\n",u8Data));
6269 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_8, &u8Data);
6270 DBG_INTERN_DVBS(ULOGD("DEMOD"," Read from E_DMD_S2_MB_DMDTOP_DBG_8 = 0x%X!!!\n",u8Data));
6271 #endif
6272
6273 MsOS_DelayTask(25);//MsOS_DelayTask(10);
6274 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);//#define TOP_WR_DBG_90 (_REG_DMDTOP(0x3A)+0)
6275 //u8Data=u8Data|0x10;
6276 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data|0x10);//enable DiSEqC_Data_Tx
6277 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); DBG_INTERN_DVBS(printf(">>>+++ INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X +++<<<\n",u8Data));
6278 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); DBG_INTERN_DVBS(printf(">>>+++ INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d +++<<<\n",u8Data));
6279
6280 #if 1 //For Unicable command timing???
6281 u16WaitCount=0;
6282 do
6283 {
6284 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); DBG_INTERN_DVBS(printf(">>>*** INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X ***<<<\n",u8Data));
6285 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); DBG_INTERN_DVBS(printf(">>>*** INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d ***<<<\n",u8Data));
6286 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6287 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6288 MsOS_DelayTask(1);
6289 u16WaitCount++;
6290 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)) ;
6291
6292 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
6293 {
6294 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS DiSEqC Send Command Busy!!!\n"));
6295 return FALSE;
6296 }
6297 else
6298 {
6299 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS DiSEqC Send Command Success!!!\n"));
6300 return TRUE;
6301 }
6302
6303
6304 #endif
6305 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); printf(">>>--- INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X ---<<<\n",u8Data);
6306 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); printf(">>>--- INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d ---<<<\n",u8Data+1);
6307
6308 return status;
6309 }
6310
INTERN_DVBS_DiSEqC_SetTxToneMode(MS_BOOL bTxTone22kOff)6311 MS_BOOL INTERN_DVBS_DiSEqC_SetTxToneMode(MS_BOOL bTxTone22kOff)
6312 {
6313 MS_BOOL status=TRUE;
6314 MS_U8 u8Data=0;
6315
6316 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xD7, &u8Data);//h006b h006b 15 15 reg_diseqc_tx_tone_mode
6317 if (bTxTone22kOff==TRUE)
6318 {
6319 u8Data=(u8Data|0x80); //1: without 22K.
6320 }
6321 else
6322 {
6323 u8Data=(u8Data&(~0x80)); //0: with 22K.
6324 }
6325 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xD7, u8Data);
6326
6327 return status;
6328 }
6329
INTERN_DVBS_UnicableAGCCheckPower(MS_BOOL pbAGCCheckPower)6330 MS_BOOL INTERN_DVBS_UnicableAGCCheckPower(MS_BOOL pbAGCCheckPower)
6331 {
6332 //MS_BOOL status = TRUE;
6333 MS_U8 u8Data=0;
6334
6335 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, 0x00);
6336
6337 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6338 u8Data &= 0xFE;//clean bit0
6339 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6340
6341 if (pbAGCCheckPower == FALSE)//0
6342 {
6343 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6344 u8Data &= 0xFE;//clean bit0
6345 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6346 //printf("CMD=MS_FALSE==============================\n");
6347 }
6348 else
6349 {
6350 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6351 u8Data |= 0x01; //bit1=1
6352 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6353 //printf("CMD=MS_TRUE==============================\n");
6354 }
6355
6356 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6357 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6358 u8Data &= 0xF0;
6359 u8Data |= 0x01;
6360 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6361 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6362 MsOS_DelayTask(500);
6363
6364 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6365 u8Data &= 0x80; //Read bit7
6366 if (u8Data == 0x80)
6367 {
6368 u8Data = 0x00;
6369 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6370 u8Data = 0x00;
6371 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6372 return TRUE;
6373 }
6374 else
6375 {
6376 u8Data = 0x00;
6377 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6378 u8Data = 0x00;
6379 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6380 return FALSE;
6381 }
6382 }
6383
6384 //------------------------------------------------------------------
6385 // END DiSEqc Function
6386 //------------------------------------------------------------------
6387 //------------------------------------------------------------------
6388 // R/W Function
6389 //------------------------------------------------------------------
INTERN_DVBS_WriteReg2bytes(MS_U16 u16Addr,MS_U16 u16Data)6390 MS_BOOL INTERN_DVBS_WriteReg2bytes(MS_U16 u16Addr, MS_U16 u16Data)
6391 {
6392 MS_BOOL bRet= TRUE;
6393 bRet &= MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr, (MS_U8)u16Data&0x00ff);
6394 bRet &= MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr + 0x0001, (MS_U8)(u16Data>>8)&0x00ff);
6395 return bRet;
6396 }
6397
INTERN_DVBS_ReadReg2bytes(MS_U16 u16Addr,MS_U16 * pu16Data)6398 MS_BOOL INTERN_DVBS_ReadReg2bytes(MS_U16 u16Addr, MS_U16 *pu16Data)
6399 {
6400 MS_BOOL bRet= TRUE;
6401 MS_U8 u8Data =0;
6402 MS_U16 u16Data =0;
6403
6404 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr + 0x0001, &u8Data);
6405 u16Data = u8Data;
6406 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr, &u8Data);
6407 *pu16Data = (u16Data<<8)|u8Data;
6408
6409 return bRet;
6410 }
6411
6412 //Frontend Freeze
INTERN_DVBS_DTV_FrontendSetFreeze(void)6413 MS_BOOL INTERN_DVBS_DTV_FrontendSetFreeze(void)
6414 {
6415 MS_BOOL bRet= TRUE;
6416 MS_U16 u16Address;
6417 MS_U16 u16Data=0;
6418
6419 u16Address = (FRONTEND_FREEZE_DUMP>>16)&0xffff;
6420 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6421 u16Data|=(FRONTEND_FREEZE_DUMP&0xffff);
6422 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6423
6424 return bRet;
6425 }
6426
INTERN_DVBS_DTV_FrontendUnFreeze(void)6427 MS_BOOL INTERN_DVBS_DTV_FrontendUnFreeze(void)
6428 {
6429 MS_BOOL bRet= TRUE;
6430 MS_U16 u16Address;
6431 MS_U16 u16Data=0;
6432
6433 u16Address = (FRONTEND_FREEZE_DUMP>>16)&0xffff;
6434 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6435 u16Data&=~(FRONTEND_FREEZE_DUMP&0xffff);
6436 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6437
6438 return bRet;
6439 }
6440
6441 //Inner Freeze
INTERN_DVBS_DTV_InnerSetFreeze(void)6442 MS_BOOL INTERN_DVBS_DTV_InnerSetFreeze(void)
6443 {
6444 MS_BOOL bRet= TRUE;
6445 MS_U16 u16Address;
6446 MS_U16 u16Data=0;
6447
6448 u16Address = (INNER_FREEZE_DUMP>>16)&0xffff;
6449 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6450 u16Data|=(INNER_FREEZE_DUMP&0xffff);
6451 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6452
6453 return bRet;
6454 }
6455
INTERN_DVBS_DTV_InnerUnFreeze(void)6456 MS_BOOL INTERN_DVBS_DTV_InnerUnFreeze(void)
6457 {
6458 MS_BOOL bRet= TRUE;
6459 MS_U16 u16Address;
6460 MS_U16 u16Data=0;
6461
6462 u16Address = (INNER_FREEZE_DUMP>>16)&0xffff;
6463 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6464 u16Data&=~(INNER_FREEZE_DUMP&0xffff);
6465 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6466
6467 return bRet;
6468 }
6469 //------------------------------------------------------------------
6470 // END R/W Function
6471 //------------------------------------------------------------------
6472
6473
6474 /***********************************************************************************
6475 Subject: read register
6476 Function: MDrv_1210_IIC_Bypass_Mode
6477 Parmeter:
6478 Return:
6479 Remark:
6480 ************************************************************************************/
6481 //void MDrv_1210_IIC_Bypass_Mode(MS_BOOL enable)
6482 //{
6483 // UNUSED(enable);
6484 // if (enable)
6485 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x10); // IIC by-pass mode on
6486 // else
6487 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x00); // IIC by-pass mode off
6488 //}
6489
6490