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Searched refs:HDMITX_HDCP_REG_BASE (Results 1 – 18 of 18) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/
H A DhalHDCPTx.c168 {HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x8000, 0x8000}, // Enable HDCP encryption
169 …{HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x001C, 0x0000}, //[4]: 1: km new mode; 0: km old m…
174 {HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0008},
179 {HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0000},
473 MHal_HDMITx_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_LN_04+(i/2), (Lm[i]<<8) | Lm[i-1]); in MHal_HDMITx_HdcpCheckBksvLn()
479 MHal_HDMITx_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_LN_SEED_07, (temp<<8) | Lm[6]); in MHal_HDMITx_HdcpCheckBksvLn()
507 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0100, 0x0100); in MHal_HDMITx_HdcpWriteAn()
508 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, BIT1, BIT1); in MHal_HDMITx_HdcpWriteAn()
509 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, BIT1, 0); in MHal_HDMITx_HdcpWriteAn()
518 temp = MHal_HDMITx_Read(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_AN_08+i); in MHal_HDMITx_HdcpWriteAn()
[all …]
H A DhalHDMITx.c776 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0E00, HDCP_mode << 8); in MHal_HDMITX_SetHDCPConfig()
787 return (MHal_HDMITx_Read(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MI_0C + idx)); in MHal_HDMITX_GetM02Bytes()
1614 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0400); in MHal_HDMITx_SetHDCPOnOff()
1616 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0000); in MHal_HDMITx_SetHDCPOnOff()
1618 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0008); in MHal_HDMITx_SetHDCPOnOff()
1621 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0000); in MHal_HDMITx_SetHDCPOnOff()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/
H A DhalHDCPTx.c147 {HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x8000, 0x8000}, // Enable HDCP encryption
148 …{HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x001C, 0x0000}, //[4]: 1: km new mode; 0: km old m…
153 {HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0008},
158 {HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0000},
452 MHal_HDMITx_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_LN_04+(i/2), (Lm[i]<<8) | Lm[i-1]); in MHal_HDMITx_HdcpCheckBksvLn()
458 MHal_HDMITx_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_LN_SEED_07, (temp<<8) | Lm[6]); in MHal_HDMITx_HdcpCheckBksvLn()
486 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0100, 0x0100); in MHal_HDMITx_HdcpWriteAn()
487 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, BIT1, BIT1); in MHal_HDMITx_HdcpWriteAn()
488 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, BIT1, 0); in MHal_HDMITx_HdcpWriteAn()
497 temp = MHal_HDMITx_Read(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_AN_08+i); in MHal_HDMITx_HdcpWriteAn()
[all …]
H A DhalHDMITx.c749 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0E00, HDCP_mode << 8); in MHal_HDMITX_SetHDCPConfig()
760 return (MHal_HDMITx_Read(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MI_0C + idx)); in MHal_HDMITX_GetM02Bytes()
1610 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0400); in MHal_HDMITx_SetHDCPOnOff()
1612 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0000); in MHal_HDMITx_SetHDCPOnOff()
1614 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0008); in MHal_HDMITx_SetHDCPOnOff()
1617 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0000); in MHal_HDMITx_SetHDCPOnOff()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/
H A DhalHDCPTx.c168 {HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x8000, 0x8000}, // Enable HDCP encryption
169 …{HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x001C, 0x0000}, //[4]: 1: km new mode; 0: km old m…
174 {HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0008},
179 {HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0000},
473 MHal_HDMITx_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_LN_04+(i/2), (Lm[i]<<8) | Lm[i-1]); in MHal_HDMITx_HdcpCheckBksvLn()
479 MHal_HDMITx_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_LN_SEED_07, (temp<<8) | Lm[6]); in MHal_HDMITx_HdcpCheckBksvLn()
507 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0100, 0x0100); in MHal_HDMITx_HdcpWriteAn()
508 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, BIT1, BIT1); in MHal_HDMITx_HdcpWriteAn()
509 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, BIT1, 0); in MHal_HDMITx_HdcpWriteAn()
518 temp = MHal_HDMITx_Read(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_AN_08+i); in MHal_HDMITx_HdcpWriteAn()
[all …]
H A DhalHDMITx.c920 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0E00, HDCP_mode << 8); in MHal_HDMITX_SetHDCPConfig()
931 return (MHal_HDMITx_Read(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MI_0C + idx)); in MHal_HDMITX_GetM02Bytes()
1738 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0400); in MHal_HDMITx_SetHDCPOnOff()
1740 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0000); in MHal_HDMITx_SetHDCPOnOff()
1742 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0008); in MHal_HDMITx_SetHDCPOnOff()
1745 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0000); in MHal_HDMITx_SetHDCPOnOff()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/
H A DhalHDCPTx.c168 {HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x8000, 0x8000}, // Enable HDCP encryption
169 …{HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x001C, 0x0000}, //[4]: 1: km new mode; 0: km old m…
174 {HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0008},
179 {HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0000},
473 MHal_HDMITx_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_LN_04+(i/2), (Lm[i]<<8) | Lm[i-1]); in MHal_HDMITx_HdcpCheckBksvLn()
479 MHal_HDMITx_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_LN_SEED_07, (temp<<8) | Lm[6]); in MHal_HDMITx_HdcpCheckBksvLn()
507 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0100, 0x0100); in MHal_HDMITx_HdcpWriteAn()
508 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, BIT1, BIT1); in MHal_HDMITx_HdcpWriteAn()
509 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, BIT1, 0); in MHal_HDMITx_HdcpWriteAn()
518 temp = MHal_HDMITx_Read(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_AN_08+i); in MHal_HDMITx_HdcpWriteAn()
[all …]
H A DhalHDMITx.c786 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0E00, HDCP_mode << 8); in MHal_HDMITX_SetHDCPConfig()
797 return (MHal_HDMITx_Read(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MI_0C + idx)); in MHal_HDMITX_GetM02Bytes()
1626 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0400); in MHal_HDMITx_SetHDCPOnOff()
1628 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0000); in MHal_HDMITx_SetHDCPOnOff()
1630 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0008); in MHal_HDMITx_SetHDCPOnOff()
1633 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0000); in MHal_HDMITx_SetHDCPOnOff()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/
H A DhalHDCPTx.c168 {HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x8000, 0x8000}, // Enable HDCP encryption
169 …{HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x001C, 0x0000}, //[4]: 1: km new mode; 0: km old m…
174 {HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0008},
179 {HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0000},
473 MHal_HDMITx_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_LN_04+(i/2), (Lm[i]<<8) | Lm[i-1]); in MHal_HDMITx_HdcpCheckBksvLn()
479 MHal_HDMITx_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_LN_SEED_07, (temp<<8) | Lm[6]); in MHal_HDMITx_HdcpCheckBksvLn()
507 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0100, 0x0100); in MHal_HDMITx_HdcpWriteAn()
508 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, BIT1, BIT1); in MHal_HDMITx_HdcpWriteAn()
509 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, BIT1, 0); in MHal_HDMITx_HdcpWriteAn()
518 temp = MHal_HDMITx_Read(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_AN_08+i); in MHal_HDMITx_HdcpWriteAn()
[all …]
H A DhalHDMITx.c975 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0E00, HDCP_mode << 8); in MHal_HDMITX_SetHDCPConfig()
986 return (MHal_HDMITx_Read(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MI_0C + idx)); in MHal_HDMITX_GetM02Bytes()
1824 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0400); in MHal_HDMITx_SetHDCPOnOff()
1826 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0000); in MHal_HDMITx_SetHDCPOnOff()
1828 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0008); in MHal_HDMITx_SetHDCPOnOff()
1831 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0000); in MHal_HDMITx_SetHDCPOnOff()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/
H A DhalHDCPTx.c168 {HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x8000, 0x8000}, // Enable HDCP encryption
169 …{HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x001C, 0x0000}, //[4]: 1: km new mode; 0: km old m…
174 {HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0008},
179 {HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0000},
473 MHal_HDMITx_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_LN_04+(i/2), (Lm[i]<<8) | Lm[i-1]); in MHal_HDMITx_HdcpCheckBksvLn()
479 MHal_HDMITx_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_LN_SEED_07, (temp<<8) | Lm[6]); in MHal_HDMITx_HdcpCheckBksvLn()
507 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0100, 0x0100); in MHal_HDMITx_HdcpWriteAn()
508 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, BIT1, BIT1); in MHal_HDMITx_HdcpWriteAn()
509 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, BIT1, 0); in MHal_HDMITx_HdcpWriteAn()
518 temp = MHal_HDMITx_Read(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_AN_08+i); in MHal_HDMITx_HdcpWriteAn()
[all …]
H A DhalHDMITx.c798 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0E00, HDCP_mode << 8); in MHal_HDMITX_SetHDCPConfig()
809 return (MHal_HDMITx_Read(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MI_0C + idx)); in MHal_HDMITX_GetM02Bytes()
1689 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0400); in MHal_HDMITx_SetHDCPOnOff()
1691 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0000); in MHal_HDMITx_SetHDCPOnOff()
1693 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0008); in MHal_HDMITx_SetHDCPOnOff()
1696 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0000); in MHal_HDMITx_SetHDCPOnOff()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/include/
H A DregHDMITx.h117 #define HDMITX_HDCP_REG_BASE (0x172B00U) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/include/
H A DregHDMITx.h117 #define HDMITX_HDCP_REG_BASE (0x172B00U) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/include/
H A DregHDMITx.h117 #define HDMITX_HDCP_REG_BASE (0x172B00U) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/include/
H A DregHDMITx.h117 #define HDMITX_HDCP_REG_BASE (0x172B00U) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/include/
H A DregHDMITx.h117 #define HDMITX_HDCP_REG_BASE (0x172100U) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/include/
H A DregHDMITx.h117 #define HDMITX_HDCP_REG_BASE (0x172100U) macro