Home
last modified time | relevance | path

Searched refs:E_FIQEXPH_START (Results 1 – 25 of 42) sorted by relevance

12

/utopia/UTPA2-700.0.x/mxlib/hal/mustang/
H A DhalIRQTBL.h279 E_FIQEXPH_START = CONFIG_FIQEXPH_BASE_ADDRESS, enumerator
280 E_FIQ_48 = E_FIQEXPH_START + 0,
281 E_FIQ_49 = E_FIQEXPH_START + 1,
282 E_FIQ_50 = E_FIQEXPH_START + 2,
283 E_FIQ_51 = E_FIQEXPH_START + 3,
284 E_FIQ_52 = E_FIQEXPH_START + 4,
285 E_FIQ_53 = E_FIQEXPH_START + 5,
286 E_FIQ_54 = E_FIQEXPH_START + 6,
287 E_FIQ_55 = E_FIQEXPH_START + 7,
288 E_FIQ_56 = E_FIQEXPH_START + 8,
[all …]
H A DregCHIP.h207 #define FIQEXPH_AEON_TO_MIPS_VPE1 (0x01 << (E_FIQ_48 - E_FIQEXPH_START))
208 #define FIQEXPH_AEON_TO_MIPS_VPE0 (0x01 << (E_FIQ_49 - E_FIQEXPH_START))
209 #define FIQEXPH_AEON_TO_8051 (0x01 << (E_FIQ_50 - E_FIQEXPH_START))
210 #define FIQEXPH_AU_SPDIF_TX_CS0 (0x01 << (E_FIQ_51 - E_FIQEXPH_START))
211 #define FIQEXPH_AU_SPDIF_TX_CS1 (0x01 << (E_FIQ_52 - E_FIQEXPH_START))
212 #define FIQEXPH_PCM_DMA (0x01 << (E_FIQ_53 - E_FIQEXPH_START))
213 #define FIQEXPH_U3_DPHY (0x01 << (E_FIQ_54 - E_FIQEXPH_START))
214 #define FIQEXPH_GPIO3 (0x01 << (E_FIQ_55 - E_FIQEXPH_START))
215 #define FIQEXPH_GPIO4 (0x01 << (E_FIQ_56 - E_FIQEXPH_START))
216 #define FIQEXPH_GPIO5 (0x01 << (E_FIQ_57 - E_FIQEXPH_START))
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/curry/
H A DregCHIP.h255 #define FIQEXPH_AEON_TO_MIPS_VPE1 (0x01 << (E_FIQ_48 - E_FIQEXPH_START))
256 #define FIQEXPH_AEON_TO_MIPS_VPE0 (0x01 << (E_FIQ_49 - E_FIQEXPH_START))
257 #define FIQEXPH_AEON_TO_8051 (0x01 << (E_FIQ_50 - E_FIQEXPH_START))
258 #define FIQEXPH_AU_SPDIF_TX_CS0 (0x01 << (E_FIQ_51 - E_FIQEXPH_START))
259 #define FIQEXPH_AU_SPDIF_TX_CS1 (0x01 << (E_FIQ_52 - E_FIQEXPH_START))
260 #define FIQEXPH_PCM_DMA (0x01 << (E_FIQ_53 - E_FIQEXPH_START))
261 #define FIQEXPH_U3_DPHY (0x01 << (E_FIQ_54 - E_FIQEXPH_START))
262 #define FIQEXPH_GPIO3 (0x01 << (E_FIQ_55 - E_FIQEXPH_START))
263 #define FIQEXPH_GPIO4 (0x01 << (E_FIQ_56 - E_FIQEXPH_START))
264 #define FIQEXPH_GPIO5 (0x01 << (E_FIQ_57 - E_FIQEXPH_START))
[all …]
H A DhalIRQTBL.h342 E_FIQEXPH_START = CONFIG_FIQEXPH_BASE_ADDRESS, enumerator
343 E_FIQ_48 = E_FIQEXPH_START + 0,
344 E_FIQ_49 = E_FIQEXPH_START + 1,
345 E_FIQ_50 = E_FIQEXPH_START + 2,
346 E_FIQ_51 = E_FIQEXPH_START + 3,
347 E_FIQ_52 = E_FIQEXPH_START + 4,
348 E_FIQ_53 = E_FIQEXPH_START + 5,
349 E_FIQ_54 = E_FIQEXPH_START + 6,
350 E_FIQ_55 = E_FIQEXPH_START + 7,
351 E_FIQ_56 = E_FIQEXPH_START + 8,
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/k7u/
H A DregCHIP.h255 #define FIQEXPH_AEON_TO_MIPS_VPE1 (0x01 << (E_FIQ_48 - E_FIQEXPH_START))
256 #define FIQEXPH_AEON_TO_MIPS_VPE0 (0x01 << (E_FIQ_49 - E_FIQEXPH_START))
257 #define FIQEXPH_AEON_TO_8051 (0x01 << (E_FIQ_50 - E_FIQEXPH_START))
258 #define FIQEXPH_AU_SPDIF_TX_CS0 (0x01 << (E_FIQ_51 - E_FIQEXPH_START))
259 #define FIQEXPH_AU_SPDIF_TX_CS1 (0x01 << (E_FIQ_52 - E_FIQEXPH_START))
260 #define FIQEXPH_PCM_DMA (0x01 << (E_FIQ_53 - E_FIQEXPH_START))
261 #define FIQEXPH_U3_DPHY (0x01 << (E_FIQ_54 - E_FIQEXPH_START))
262 #define FIQEXPH_GPIO3 (0x01 << (E_FIQ_55 - E_FIQEXPH_START))
263 #define FIQEXPH_GPIO4 (0x01 << (E_FIQ_56 - E_FIQEXPH_START))
264 #define FIQEXPH_GPIO5 (0x01 << (E_FIQ_57 - E_FIQEXPH_START))
[all …]
H A DhalIRQTBL.h342 E_FIQEXPH_START = CONFIG_FIQEXPH_BASE_ADDRESS, enumerator
343 E_FIQ_48 = E_FIQEXPH_START + 0,
344 E_FIQ_49 = E_FIQEXPH_START + 1,
345 E_FIQ_50 = E_FIQEXPH_START + 2,
346 E_FIQ_51 = E_FIQEXPH_START + 3,
347 E_FIQ_52 = E_FIQEXPH_START + 4,
348 E_FIQ_53 = E_FIQEXPH_START + 5,
349 E_FIQ_54 = E_FIQEXPH_START + 6,
350 E_FIQ_55 = E_FIQEXPH_START + 7,
351 E_FIQ_56 = E_FIQEXPH_START + 8,
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/k6lite/
H A DregCHIP.h255 #define FIQEXPH_AEON_TO_MIPS_VPE1 (0x01 << (E_FIQ_48 - E_FIQEXPH_START))
256 #define FIQEXPH_AEON_TO_MIPS_VPE0 (0x01 << (E_FIQ_49 - E_FIQEXPH_START))
257 #define FIQEXPH_AEON_TO_8051 (0x01 << (E_FIQ_50 - E_FIQEXPH_START))
258 #define FIQEXPH_AU_SPDIF_TX_CS0 (0x01 << (E_FIQ_51 - E_FIQEXPH_START))
259 #define FIQEXPH_AU_SPDIF_TX_CS1 (0x01 << (E_FIQ_52 - E_FIQEXPH_START))
260 #define FIQEXPH_PCM_DMA (0x01 << (E_FIQ_53 - E_FIQEXPH_START))
261 #define FIQEXPH_U3_DPHY (0x01 << (E_FIQ_54 - E_FIQEXPH_START))
262 #define FIQEXPH_GPIO3 (0x01 << (E_FIQ_55 - E_FIQEXPH_START))
263 #define FIQEXPH_GPIO4 (0x01 << (E_FIQ_56 - E_FIQEXPH_START))
264 #define FIQEXPH_GPIO5 (0x01 << (E_FIQ_57 - E_FIQEXPH_START))
[all …]
H A DhalIRQTBL.h342 E_FIQEXPH_START = CONFIG_FIQEXPH_BASE_ADDRESS, enumerator
343 E_FIQ_48 = E_FIQEXPH_START + 0,
344 E_FIQ_49 = E_FIQEXPH_START + 1,
345 E_FIQ_50 = E_FIQEXPH_START + 2,
346 E_FIQ_51 = E_FIQEXPH_START + 3,
347 E_FIQ_52 = E_FIQEXPH_START + 4,
348 E_FIQ_53 = E_FIQEXPH_START + 5,
349 E_FIQ_54 = E_FIQEXPH_START + 6,
350 E_FIQ_55 = E_FIQEXPH_START + 7,
351 E_FIQ_56 = E_FIQEXPH_START + 8,
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/k6/
H A DregCHIP.h255 #define FIQEXPH_AEON_TO_MIPS_VPE1 (0x01 << (E_FIQ_48 - E_FIQEXPH_START))
256 #define FIQEXPH_AEON_TO_MIPS_VPE0 (0x01 << (E_FIQ_49 - E_FIQEXPH_START))
257 #define FIQEXPH_AEON_TO_8051 (0x01 << (E_FIQ_50 - E_FIQEXPH_START))
258 #define FIQEXPH_AU_SPDIF_TX_CS0 (0x01 << (E_FIQ_51 - E_FIQEXPH_START))
259 #define FIQEXPH_AU_SPDIF_TX_CS1 (0x01 << (E_FIQ_52 - E_FIQEXPH_START))
260 #define FIQEXPH_PCM_DMA (0x01 << (E_FIQ_53 - E_FIQEXPH_START))
261 #define FIQEXPH_U3_DPHY (0x01 << (E_FIQ_54 - E_FIQEXPH_START))
262 #define FIQEXPH_GPIO3 (0x01 << (E_FIQ_55 - E_FIQEXPH_START))
263 #define FIQEXPH_GPIO4 (0x01 << (E_FIQ_56 - E_FIQEXPH_START))
264 #define FIQEXPH_GPIO5 (0x01 << (E_FIQ_57 - E_FIQEXPH_START))
[all …]
H A DhalIRQTBL.h342 E_FIQEXPH_START = CONFIG_FIQEXPH_BASE_ADDRESS, enumerator
343 E_FIQ_48 = E_FIQEXPH_START + 0,
344 E_FIQ_49 = E_FIQEXPH_START + 1,
345 E_FIQ_50 = E_FIQEXPH_START + 2,
346 E_FIQ_51 = E_FIQEXPH_START + 3,
347 E_FIQ_52 = E_FIQEXPH_START + 4,
348 E_FIQ_53 = E_FIQEXPH_START + 5,
349 E_FIQ_54 = E_FIQEXPH_START + 6,
350 E_FIQ_55 = E_FIQEXPH_START + 7,
351 E_FIQ_56 = E_FIQEXPH_START + 8,
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/kano/
H A DregCHIP.h255 #define FIQEXPH_AEON_TO_MIPS_VPE1 (0x01 << (E_FIQ_48 - E_FIQEXPH_START))
256 #define FIQEXPH_AEON_TO_MIPS_VPE0 (0x01 << (E_FIQ_49 - E_FIQEXPH_START))
257 #define FIQEXPH_AEON_TO_8051 (0x01 << (E_FIQ_50 - E_FIQEXPH_START))
258 #define FIQEXPH_AU_SPDIF_TX_CS0 (0x01 << (E_FIQ_51 - E_FIQEXPH_START))
259 #define FIQEXPH_AU_SPDIF_TX_CS1 (0x01 << (E_FIQ_52 - E_FIQEXPH_START))
260 #define FIQEXPH_PCM_DMA (0x01 << (E_FIQ_53 - E_FIQEXPH_START))
261 #define FIQEXPH_U3_DPHY (0x01 << (E_FIQ_54 - E_FIQEXPH_START))
262 #define FIQEXPH_GPIO3 (0x01 << (E_FIQ_55 - E_FIQEXPH_START))
263 #define FIQEXPH_GPIO4 (0x01 << (E_FIQ_56 - E_FIQEXPH_START))
264 #define FIQEXPH_GPIO5 (0x01 << (E_FIQ_57 - E_FIQEXPH_START))
[all …]
H A DhalIRQTBL.h342 E_FIQEXPH_START = CONFIG_FIQEXPH_BASE_ADDRESS, enumerator
343 E_FIQ_48 = E_FIQEXPH_START + 0,
344 E_FIQ_49 = E_FIQEXPH_START + 1,
345 E_FIQ_50 = E_FIQEXPH_START + 2,
346 E_FIQ_51 = E_FIQEXPH_START + 3,
347 E_FIQ_52 = E_FIQEXPH_START + 4,
348 E_FIQ_53 = E_FIQEXPH_START + 5,
349 E_FIQ_54 = E_FIQEXPH_START + 6,
350 E_FIQ_55 = E_FIQEXPH_START + 7,
351 E_FIQ_56 = E_FIQEXPH_START + 8,
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/messi/
H A DhalIRQTBL.h313 E_FIQEXPH_START = CONFIG_FIQEXPH_BASE_ADDRESS, enumerator
314 E_FIQ_48 = E_FIQEXPH_START + 0,
315 E_FIQ_49 = E_FIQEXPH_START + 1,
316 E_FIQ_50 = E_FIQEXPH_START + 2,
317 E_FIQ_51 = E_FIQEXPH_START + 3,
318 E_FIQ_52 = E_FIQEXPH_START + 4,
319 E_FIQ_53 = E_FIQEXPH_START + 5,
320 E_FIQ_54 = E_FIQEXPH_START + 6,
321 E_FIQ_55 = E_FIQEXPH_START + 7,
322 E_FIQ_56 = E_FIQEXPH_START + 8,
[all …]
H A DregCHIP.h208 #define FIQEXPH_GPIO8 (0x01 << (E_FIQ_49 - E_FIQEXPH_START))
209 #define FIQEXPH_GPIO9 (0x01 << (E_FIQ_50 - E_FIQEXPH_START))
210 #define FIQEXPH_USB1 (0x01 << (E_FIQ_51 - E_FIQEXPH_START))
211 #define FIQEXPH_UHC1 (0x01 << (E_FIQ_52 - E_FIQEXPH_START))
212 #define FIQEXPH_LDM_DMA1 (0x01 << (E_FIQ_53 - E_FIQEXPH_START))
213 #define FIQEXPH_LDM_DMA0 (0x01 << (E_FIQ_54 - E_FIQEXPH_START))
214 #define FIQEXPH_GPIO3 (0x01 << (E_FIQ_55 - E_FIQEXPH_START))
215 #define FIQEXPH_GPIO4 (0x01 << (E_FIQ_56 - E_FIQEXPH_START))
216 #define FIQEXPH_GPIO5 (0x01 << (E_FIQ_57 - E_FIQEXPH_START))
217 #define FIQEXPH_GPIO6 (0x01 << (E_FIQ_58 - E_FIQEXPH_START))
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/mainz/
H A DhalIRQTBL.h313 E_FIQEXPH_START = CONFIG_FIQEXPH_BASE_ADDRESS, enumerator
314 E_FIQ_48 = E_FIQEXPH_START + 0,
315 E_FIQ_49 = E_FIQEXPH_START + 1,
316 E_FIQ_50 = E_FIQEXPH_START + 2,
317 E_FIQ_51 = E_FIQEXPH_START + 3,
318 E_FIQ_52 = E_FIQEXPH_START + 4,
319 E_FIQ_53 = E_FIQEXPH_START + 5,
320 E_FIQ_54 = E_FIQEXPH_START + 6,
321 E_FIQ_55 = E_FIQEXPH_START + 7,
322 E_FIQ_56 = E_FIQEXPH_START + 8,
[all …]
H A DregCHIP.h208 #define FIQEXPH_GPIO8 (0x01 << (E_FIQ_49 - E_FIQEXPH_START))
209 #define FIQEXPH_GPIO9 (0x01 << (E_FIQ_50 - E_FIQEXPH_START))
210 #define FIQEXPH_USB1 (0x01 << (E_FIQ_51 - E_FIQEXPH_START))
211 #define FIQEXPH_UHC1 (0x01 << (E_FIQ_52 - E_FIQEXPH_START))
212 #define FIQEXPH_LDM_DMA1 (0x01 << (E_FIQ_53 - E_FIQEXPH_START))
213 #define FIQEXPH_LDM_DMA0 (0x01 << (E_FIQ_54 - E_FIQEXPH_START))
214 #define FIQEXPH_GPIO3 (0x01 << (E_FIQ_55 - E_FIQEXPH_START))
215 #define FIQEXPH_GPIO4 (0x01 << (E_FIQ_56 - E_FIQEXPH_START))
216 #define FIQEXPH_GPIO5 (0x01 << (E_FIQ_57 - E_FIQEXPH_START))
217 #define FIQEXPH_GPIO6 (0x01 << (E_FIQ_58 - E_FIQEXPH_START))
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/manhattan/
H A DhalIRQTBL.h323 E_FIQEXPH_START = CONFIG_FIQEXPH_BASE_ADDRESS, enumerator
324 E_FIQ_48 = E_FIQEXPH_START + 0,
325 E_FIQ_49 = E_FIQEXPH_START + 1,
326 E_FIQ_50 = E_FIQEXPH_START + 2,
327 E_FIQ_51 = E_FIQEXPH_START + 3,
328 E_FIQ_52 = E_FIQEXPH_START + 4,
329 E_FIQ_53 = E_FIQEXPH_START + 5,
330 E_FIQ_54 = E_FIQEXPH_START + 6,
331 E_FIQ_55 = E_FIQEXPH_START + 7,
332 E_FIQ_56 = E_FIQEXPH_START + 8,
[all …]
H A DregCHIP.h307 …QEXPH_USB_INT1 (0x1 << (E_FIQEXPH_USB1 - E_FIQEXPH_START) )
308 …QEXPH_UHC_INT1 (0x1 << (E_FIQEXPH_UHC1 - E_FIQEXPH_START) )
309 …QEXPH_USB_INT2 (0x1 << (E_FIQEXPH_USB2 - E_FIQEXPH_START) )
310 …QEXPH_UHC_INT2 (0x1 << (E_FIQEXPH_UHC2 - E_FIQEXPH_START) )
311 …QEXPH_EXT_GPIO_INT3 (0x1 << (E_FIQEXPH_EXT_GPIO_INT3 - E_FIQEXPH_START) )
312 …QEXPH_EXT_GPIO_INT4 (0x1 << (E_FIQEXPH_EXT_GPIO_INT4 - E_FIQEXPH_START) )
313 …QEXPH_EXT_GPIO_INT5 (0x1 << (E_FIQEXPH_EXT_GPIO_INT5 - E_FIQEXPH_START) )
314 …QEXPH_EXT_GPIO_INT6 (0x1 << (E_FIQEXPH_EXT_GPIO_INT6 - E_FIQEXPH_START) )
315 …QEXPH_PWM_RP_L (0x1 << (E_FIQEXPH_PWM_RP_L - E_FIQEXPH_START) )
316 …QEXPH_PWM_FP_L (0x1 << (E_FIQEXPH_PWM_FP_L - E_FIQEXPH_START) )
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/marcus/
H A DhalIRQTBL.h323 E_FIQEXPH_START = CONFIG_FIQEXPH_BASE_ADDRESS, enumerator
324 E_FIQ_48 = E_FIQEXPH_START + 0,
325 E_FIQ_49 = E_FIQEXPH_START + 1,
326 E_FIQ_50 = E_FIQEXPH_START + 2,
327 E_FIQ_51 = E_FIQEXPH_START + 3,
328 E_FIQ_52 = E_FIQEXPH_START + 4,
329 E_FIQ_53 = E_FIQEXPH_START + 5,
330 E_FIQ_54 = E_FIQEXPH_START + 6,
331 E_FIQ_55 = E_FIQEXPH_START + 7,
332 E_FIQ_56 = E_FIQEXPH_START + 8,
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/maxim/
H A DhalIRQTBL.h323 E_FIQEXPH_START = CONFIG_FIQEXPH_BASE_ADDRESS, enumerator
324 E_FIQ_48 = E_FIQEXPH_START + 0,
325 E_FIQ_49 = E_FIQEXPH_START + 1,
326 E_FIQ_50 = E_FIQEXPH_START + 2,
327 E_FIQ_51 = E_FIQEXPH_START + 3,
328 E_FIQ_52 = E_FIQEXPH_START + 4,
329 E_FIQ_53 = E_FIQEXPH_START + 5,
330 E_FIQ_54 = E_FIQEXPH_START + 6,
331 E_FIQ_55 = E_FIQEXPH_START + 7,
332 E_FIQ_56 = E_FIQEXPH_START + 8,
[all …]
H A DregCHIP.h307 …QEXPH_USB_INT1 (0x1 << (E_FIQEXPH_USB1 - E_FIQEXPH_START) )
308 …QEXPH_UHC_INT1 (0x1 << (E_FIQEXPH_UHC1 - E_FIQEXPH_START) )
309 …QEXPH_USB_INT2 (0x1 << (E_FIQEXPH_USB2 - E_FIQEXPH_START) )
310 …QEXPH_UHC_INT2 (0x1 << (E_FIQEXPH_UHC2 - E_FIQEXPH_START) )
311 …QEXPH_EXT_GPIO_INT3 (0x1 << (E_FIQEXPH_EXT_GPIO_INT3 - E_FIQEXPH_START) )
312 …QEXPH_EXT_GPIO_INT4 (0x1 << (E_FIQEXPH_EXT_GPIO_INT4 - E_FIQEXPH_START) )
313 …QEXPH_EXT_GPIO_INT5 (0x1 << (E_FIQEXPH_EXT_GPIO_INT5 - E_FIQEXPH_START) )
314 …QEXPH_EXT_GPIO_INT6 (0x1 << (E_FIQEXPH_EXT_GPIO_INT6 - E_FIQEXPH_START) )
315 …QEXPH_PWM_RP_L (0x1 << (E_FIQEXPH_PWM_RP_L - E_FIQEXPH_START) )
316 …QEXPH_PWM_FP_L (0x1 << (E_FIQEXPH_PWM_FP_L - E_FIQEXPH_START) )
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/maserati/
H A DhalIRQTBL.h323 E_FIQEXPH_START = CONFIG_FIQEXPH_BASE_ADDRESS, enumerator
324 E_FIQ_48 = E_FIQEXPH_START + 0,
325 E_FIQ_49 = E_FIQEXPH_START + 1,
326 E_FIQ_50 = E_FIQEXPH_START + 2,
327 E_FIQ_51 = E_FIQEXPH_START + 3,
328 E_FIQ_52 = E_FIQEXPH_START + 4,
329 E_FIQ_53 = E_FIQEXPH_START + 5,
330 E_FIQ_54 = E_FIQEXPH_START + 6,
331 E_FIQ_55 = E_FIQEXPH_START + 7,
332 E_FIQ_56 = E_FIQEXPH_START + 8,
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/M7821/
H A DhalIRQTBL.h330 E_FIQEXPH_START = CONFIG_FIQEXPH_BASE_ADDRESS, enumerator
331 E_FIQ_48 = E_FIQEXPH_START + 0,
332 E_FIQ_49 = E_FIQEXPH_START + 1,
333 E_FIQ_50 = E_FIQEXPH_START + 2,
334 E_FIQ_51 = E_FIQEXPH_START + 3,
335 E_FIQ_52 = E_FIQEXPH_START + 4,
336 E_FIQ_53 = E_FIQEXPH_START + 5,
337 E_FIQ_54 = E_FIQEXPH_START + 6,
338 E_FIQ_55 = E_FIQEXPH_START + 7,
339 E_FIQ_56 = E_FIQEXPH_START + 8,
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/M7621/
H A DhalIRQTBL.h330 E_FIQEXPH_START = CONFIG_FIQEXPH_BASE_ADDRESS, enumerator
331 E_FIQ_48 = E_FIQEXPH_START + 0,
332 E_FIQ_49 = E_FIQEXPH_START + 1,
333 E_FIQ_50 = E_FIQEXPH_START + 2,
334 E_FIQ_51 = E_FIQEXPH_START + 3,
335 E_FIQ_52 = E_FIQEXPH_START + 4,
336 E_FIQ_53 = E_FIQEXPH_START + 5,
337 E_FIQ_54 = E_FIQEXPH_START + 6,
338 E_FIQ_55 = E_FIQEXPH_START + 7,
339 E_FIQ_56 = E_FIQEXPH_START + 8,
[all …]
H A DregCHIP.h313 …QEXPH_USB_INT1 (0x1 << (E_FIQEXPH_USB1 - E_FIQEXPH_START) )
314 …QEXPH_UHC_INT1 (0x1 << (E_FIQEXPH_UHC1 - E_FIQEXPH_START) )
315 …QEXPH_USB_INT2 (0x1 << (E_FIQEXPH_USB2 - E_FIQEXPH_START) )
316 …QEXPH_UHC_INT2 (0x1 << (E_FIQEXPH_UHC2 - E_FIQEXPH_START) )
317 …QEXPH_EXT_GPIO_INT3 (0x1 << (E_FIQEXPH_EXT_GPIO_INT3 - E_FIQEXPH_START) )
318 …QEXPH_EXT_GPIO_INT4 (0x1 << (E_FIQEXPH_EXT_GPIO_INT4 - E_FIQEXPH_START) )
319 …QEXPH_EXT_GPIO_INT5 (0x1 << (E_FIQEXPH_EXT_GPIO_INT5 - E_FIQEXPH_START) )
320 …QEXPH_EXT_GPIO_INT6 (0x1 << (E_FIQEXPH_EXT_GPIO_INT6 - E_FIQEXPH_START) )
321 …QEXPH_PWM_RP_L (0x1 << (E_FIQEXPH_PWM_RP_L - E_FIQEXPH_START) )
322 …QEXPH_PWM_FP_L (0x1 << (E_FIQEXPH_PWM_FP_L - E_FIQEXPH_START) )
[all …]

12