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/rockchip-linux_mpp/utils/
H A Dosd3_test.c79 static MPP_RET translate_argb(RK_U8 *src, RK_U8 *dst, RK_U32 width, RK_U32 height, in translate_argb() argument
95 cfg->stride = width * 4; in translate_argb()
96 memcpy(dst, src, width * height * 4); in translate_argb()
101 cfg->stride = width * 4; in translate_argb()
103 for (i = 0; i < width; i++) { in translate_argb()
104 dst[j * width * 4 + i * 4 + 0] = src[j * width * 4 + i * 4 + 0]; in translate_argb()
105 dst[j * width * 4 + i * 4 + 1] = src[j * width * 4 + i * 4 + 3]; in translate_argb()
106 dst[j * width * 4 + i * 4 + 2] = src[j * width * 4 + i * 4 + 2]; in translate_argb()
107 dst[j * width * 4 + i * 4 + 3] = src[j * width * 4 + i * 4 + 1]; in translate_argb()
115 cfg->stride = width * 4; in translate_argb()
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H A Dutils.c64 RK_U32 width = 0; in dump_mpp_frame_to_file() local
75 width = mpp_frame_get_width(frame); in dump_mpp_frame_to_file()
105 RK_U8 *tmp_v = tmp + width * height / 2; in dump_mpp_frame_to_file()
108 fwrite(base_y, 1, width, fp); in dump_mpp_frame_to_file()
111 for (j = 0; j < width / 2; j++) { in dump_mpp_frame_to_file()
115 tmp_u += width / 2; in dump_mpp_frame_to_file()
116 tmp_v += width / 2; in dump_mpp_frame_to_file()
119 fwrite(tmp, 1, width * height, fp); in dump_mpp_frame_to_file()
129 fwrite(base_y, 1, width, fp); in dump_mpp_frame_to_file()
132 fwrite(base_c, 1, width, fp); in dump_mpp_frame_to_file()
[all …]
/rockchip-linux_mpp/mpp/base/test/
H A Dmpp_sys_cfg_st_test.c17 RK_U32 width = 4096; in main() local
29 h_stride_cfg.width = width; in main()
40 byte_stride_cfg.width = width; in main()
61 size_cfg.width = width; in main()
/rockchip-linux_mpp/mpp/hal/rkdec/
H A Dvdpu34x_com.c56 RK_S32 vdpu34x_get_rcb_buf_size(Vdpu34xRcbInfo *info, RK_S32 width, RK_S32 height) in vdpu34x_get_rcb_buf_size() argument
60 offset += update_size_offset(info, 139, offset, width, RCB_DBLK_ROW); in vdpu34x_get_rcb_buf_size()
61 offset += update_size_offset(info, 133, offset, width, RCB_INTRA_ROW); in vdpu34x_get_rcb_buf_size()
62 offset += update_size_offset(info, 134, offset, width, RCB_TRANSD_ROW); in vdpu34x_get_rcb_buf_size()
63 offset += update_size_offset(info, 136, offset, width, RCB_STRMD_ROW); in vdpu34x_get_rcb_buf_size()
64 offset += update_size_offset(info, 137, offset, width, RCB_INTER_ROW); in vdpu34x_get_rcb_buf_size()
65 offset += update_size_offset(info, 140, offset, width, RCB_SAO_ROW); in vdpu34x_get_rcb_buf_size()
66 offset += update_size_offset(info, 141, offset, width, RCB_FBC_ROW); in vdpu34x_get_rcb_buf_size()
230 RK_U32 vdpu34x_get_colmv_size(RK_U32 width, RK_U32 height, RK_U32 ctu_size, in vdpu34x_get_colmv_size() argument
238 RK_U32 seg_cnt_w = MPP_ALIGN(width, segment_w) / segment_w; in vdpu34x_get_colmv_size()
[all …]
H A Dvdpu382_com.c56 RK_S32 vdpu382_get_rcb_buf_size(Vdpu382RcbInfo *info, RK_S32 width, RK_S32 height) in vdpu382_get_rcb_buf_size() argument
60 offset += update_size_offset(info, 139, offset, width, RCB_DBLK_ROW); in vdpu382_get_rcb_buf_size()
61 offset += update_size_offset(info, 133, offset, width, RCB_INTRA_ROW); in vdpu382_get_rcb_buf_size()
62 offset += update_size_offset(info, 134, offset, width, RCB_TRANSD_ROW); in vdpu382_get_rcb_buf_size()
63 offset += update_size_offset(info, 136, offset, width, RCB_STRMD_ROW); in vdpu382_get_rcb_buf_size()
64 offset += update_size_offset(info, 137, offset, width, RCB_INTER_ROW); in vdpu382_get_rcb_buf_size()
65 offset += update_size_offset(info, 140, offset, width, RCB_SAO_ROW); in vdpu382_get_rcb_buf_size()
66 offset += update_size_offset(info, 141, offset, width, RCB_FBC_ROW); in vdpu382_get_rcb_buf_size()
258 RK_U32 vdpu382_get_colmv_size(RK_U32 width, RK_U32 height, RK_U32 ctu_size, in vdpu382_get_colmv_size() argument
266 RK_U32 seg_cnt_w = MPP_ALIGN(width, segment_w) / segment_w; in vdpu382_get_colmv_size()
[all …]
H A Dvdpu384a_com.c46 RK_S32 vdpu384a_get_rcb_buf_size(Vdpu384aRcbInfo *info, RK_S32 width, RK_S32 height) in vdpu384a_get_rcb_buf_size() argument
50 offset += update_size_offset(info, 140, offset, width, RCB_STRMD_ROW); in vdpu384a_get_rcb_buf_size()
51 offset += update_size_offset(info, 142, offset, width, RCB_STRMD_TILE_ROW); in vdpu384a_get_rcb_buf_size()
52 offset += update_size_offset(info, 144, offset, width, RCB_INTER_ROW); in vdpu384a_get_rcb_buf_size()
53 offset += update_size_offset(info, 146, offset, width, RCB_INTER_TILE_ROW); in vdpu384a_get_rcb_buf_size()
54 offset += update_size_offset(info, 148, offset, width, RCB_INTRA_ROW); in vdpu384a_get_rcb_buf_size()
55 offset += update_size_offset(info, 150, offset, width, RCB_INTRA_TILE_ROW); in vdpu384a_get_rcb_buf_size()
56 offset += update_size_offset(info, 152, offset, width, RCB_FILTERD_ROW); in vdpu384a_get_rcb_buf_size()
57 offset += update_size_offset(info, 154, offset, width, RCB_FILTERD_PROTECT_ROW); in vdpu384a_get_rcb_buf_size()
58 offset += update_size_offset(info, 156, offset, width, RCB_FILTERD_TILE_ROW); in vdpu384a_get_rcb_buf_size()
[all …]
H A Dvdpu383_com.c45 RK_S32 vdpu383_get_rcb_buf_size(Vdpu383RcbInfo *info, RK_S32 width, RK_S32 height) in vdpu383_get_rcb_buf_size() argument
49 offset += update_size_offset(info, 140, offset, width, RCB_STRMD_ROW); in vdpu383_get_rcb_buf_size()
50 offset += update_size_offset(info, 142, offset, width, RCB_STRMD_TILE_ROW); in vdpu383_get_rcb_buf_size()
51 offset += update_size_offset(info, 144, offset, width, RCB_INTER_ROW); in vdpu383_get_rcb_buf_size()
52 offset += update_size_offset(info, 146, offset, width, RCB_INTER_TILE_ROW); in vdpu383_get_rcb_buf_size()
53 offset += update_size_offset(info, 148, offset, width, RCB_INTRA_ROW); in vdpu383_get_rcb_buf_size()
54 offset += update_size_offset(info, 150, offset, width, RCB_INTRA_TILE_ROW); in vdpu383_get_rcb_buf_size()
55 offset += update_size_offset(info, 152, offset, width, RCB_FILTERD_ROW); in vdpu383_get_rcb_buf_size()
56 offset += update_size_offset(info, 154, offset, width, RCB_FILTERD_PROTECT_ROW); in vdpu383_get_rcb_buf_size()
57 offset += update_size_offset(info, 156, offset, width, RCB_FILTERD_TILE_ROW); in vdpu383_get_rcb_buf_size()
/rockchip-linux_mpp/mpp/
H A Dmpp_impl.c161 RK_U32 width = mpp_frame_get_width(frame); in dump_frame() local
175 RK_U32 img_w = width / step; in dump_frame()
196 width = img_w; in dump_frame()
200 for (j = 0; j < width; j++) in dump_frame()
202 pdes += width; in dump_frame()
206 pdes = tmp + width * height; in dump_frame()
208 for (j = 0; j < width; j++) in dump_frame()
210 pdes += width; in dump_frame()
214 size = width * height * 1.5; in dump_frame()
231 RK_U8 *tmp_line = (RK_U8 *)mpp_malloc(RK_U16, width); in dump_frame()
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/rockchip-linux_mpp/tools/
H A Dresolution_test.sh65 width=${cur_rsl%x*}
69 [ "${width}" -gt 8192 ] && frm_cnt=2
77 …cur_enc_cmd="${enc_tool} -w ${width} -h ${height} -n ${frm_cnt} -t ${cur_type} -o ${enc_out_norm_p…
87 …cur_enc_cmd="${enc_tool} -w ${width} -h ${height} -n ${frm_cnt} -t ${cur_type} -o ${enc_out_kmpp_p…
98 …cur_dec_cmd="${dec_tool} -i ${enc_out_norm_path} -w ${width} -h ${height} -t ${cur_type} -o ${dec_…
107 …cur_dec_cmd="${dec_tool} -i ${enc_out_kmpp_path} -w ${width} -h ${height} -t ${cur_type} -o ${dec_…
/rockchip-linux_mpp/test/
H A Dvpu_api_test.c39 RK_U32 width; member
154 cmdCxt->width = atoi(argv[optindex]); in parse_options()
260 if ((cmd->have_input == 0) || (cmd->width <= 0) || (cmd->height <= 0) in vpu_encode_demo()
267 cmd->width, cmd->height, cmd->coding, in vpu_encode_demo()
301 ctx->width = cmd->width; in vpu_encode_demo()
315 enc_out->data = (RK_U8 *)malloc(cmd->width * cmd->height); in vpu_encode_demo()
331 ctx->width = cmd->width; in vpu_encode_demo()
339 enc_param->width = cmd->width; in vpu_encode_demo()
389 w_align = ((ctx->width + 15) & (~15)); in vpu_encode_demo()
392 readOneFrameSize = ctx->width * ctx->height * 3 / 2; in vpu_encode_demo()
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H A Dmpi_enc_test.c101 RK_U32 width; member
247 mpp_venc_kcfg_set_u32(init_kcfg, "max_width", p->width); in kmpp_cfg_init()
273 p->width = cmd->width; in test_ctx_init()
276 (MPP_ALIGN(cmd->width, 16)); in test_ctx_init()
315 p->cam_ctx = camera_source_init(cmd->file_input, 4, p->width, p->height, p->fmt); in test_ctx_init()
382 … p->header_size = MPP_ALIGN(MPP_ALIGN(p->width, 16) * MPP_ALIGN(p->height, 16) / 16, SZ_4K); in test_ctx_init()
384 p->header_size = MPP_ALIGN(p->width, 16) * MPP_ALIGN(p->height, 16) / 16; in test_ctx_init()
441 p->bps = p->width * p->height / 8 * (p->fps_out_num / p->fps_out_den); in test_mpp_enc_cfg_setup()
446 mpp_enc_cfg_set_s32(cfg, "prep:width", p->width); in test_mpp_enc_cfg_setup()
731 mpp_enc_roi_init(&p->roi_ctx, p->width, p->height, p->type, 4); in test_mpp_enc_cfg_setup()
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/rockchip-linux_mpp/mpp/legacy/
H A Dvpu_api_legacy.cpp98 RK_S32 width = cfg->width; in vpu_api_set_enc_cfg() local
126 mpp_log("width %4d height %4d format %d:%x\n", width, height, cfg->format, fmt); in vpu_api_set_enc_cfg()
133 mpp_assert(width); in vpu_api_set_enc_cfg()
137 mpp_enc_cfg_set_s32(enc_cfg, "prep:width", width); in vpu_api_set_enc_cfg()
143 mpp_enc_cfg_set_s32(enc_cfg, "prep:hor_stride", MPP_ALIGN(width, 16)); in vpu_api_set_enc_cfg()
149 mpp_enc_cfg_set_s32(enc_cfg, "prep:hor_stride", 2 * MPP_ALIGN(width, 16)); in vpu_api_set_enc_cfg()
153 mpp_enc_cfg_set_s32(enc_cfg, "prep:hor_stride", 3 * MPP_ALIGN(width, 16)); in vpu_api_set_enc_cfg()
159 mpp_enc_cfg_set_s32(enc_cfg, "prep:hor_stride", 4 * MPP_ALIGN(width, 16)); in vpu_api_set_enc_cfg()
234 static int copy_align_raw_buffer_to_dest(RK_U8 *dst, RK_U8 *src, RK_U32 width, in copy_align_raw_buffer_to_dest() argument
242 RK_U32 hor_stride = MPP_ALIGN(width, 16); in copy_align_raw_buffer_to_dest()
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/rockchip-linux_mpp/mpp/hal/vpu/common/
H A Dvepu_common.c158 static RK_S32 check_stride_by_pixel(RK_S32 workaround, RK_S32 width, in check_stride_by_pixel() argument
161 if (!workaround && hor_stride < width * pixel_size) { in check_stride_by_pixel()
163 hor_stride, width, pixel_size); in check_stride_by_pixel()
187 RK_U32 get_vepu_pixel_stride(VepuStrideCfg *cfg, RK_U32 width, RK_U32 stride, MppFrameFormat fmt) in get_vepu_pixel_stride() argument
197 if (cfg->stride != stride || cfg->width != width) { in get_vepu_pixel_stride()
201 cfg->width = width; in get_vepu_pixel_stride()
219 if (check_stride_by_pixel(cfg->is_pixel_stride, cfg->width, in get_vepu_pixel_stride()
239 if (check_stride_by_pixel(cfg->is_pixel_stride, cfg->width, in get_vepu_pixel_stride()
259 if (check_stride_by_pixel(cfg->is_pixel_stride, cfg->width, in get_vepu_pixel_stride()
H A Dvepu_common.h49 RK_U32 width; member
60 RK_U32 width; member
82 RK_U32 get_vepu_pixel_stride(VepuStrideCfg *cfg, RK_U32 width,
/rockchip-linux_mpp/mpp/vproc/rga/
H A Drga.c164 RK_U32 width = mpp_frame_get_width(frame); in config_rga_image() local
178 img->act_w = width; in config_rga_image()
251 RK_U32 width = mpp_frame_get_width(dst); in rga_control() local
254 request->clip.xmax = width - 1; in rga_control()
348 RK_U32 width = mpp_frame_get_width(frame); in rga_dup_field() local
360 mpp_assert(width > 0 && height > 0); in rga_dup_field()
361 if (fmt != RGA_FMT_YCbCr_420_SP || width == 0 || height == 0) { in rga_dup_field()
367 fd, width, height, h_str, v_str, fmt); in rga_dup_field()
374 request->src.act_w = width; in rga_dup_field()
382 request->dst.act_w = width; in rga_dup_field()
/rockchip-linux_mpp/kmpp/base/test/
H A Dkmpp_frame_test.c25 rk_u32 width = 1920; in main() local
33 TEST_CHECK(ret, kmpp_frame_set_width, frame, width); in main()
39 mpp_assert(val == width); in main()
/rockchip-linux_mpp/mpp/hal/rkdec/h265d/
H A Dhal_h265d_vdpu382.c220 RK_S32 width, height; in hal_h265d_v382_output_pps_packet() local
249 width = (dxva_cxt->pp.PicWidthInMinCbsY << log2_min_cb_size); in hal_h265d_v382_output_pps_packet()
252 mpp_put_bits(&bp, width , 16); in hal_h265d_v382_output_pps_packet()
342 RK_S32 ctu_width_in_pic = (width + in hal_h265d_v382_output_pps_packet()
362 RK_S32 pic_in_cts_width = (width + in hal_h265d_v382_output_pps_packet()
384 column_width[0] = (width + MaxCUWidth - 1) / MaxCUWidth; in hal_h265d_v382_output_pps_packet()
440 RK_S32 width, RK_S32 height, void *dxva) in h265d_refine_rcb_size() argument
451 width = MPP_ALIGN(width, ctu_size); in h265d_refine_rcb_size()
455 if (width >= 8192) { in h265d_refine_rcb_size()
458 rcb_bits = (MPP_ALIGN(width, ctu_size) + factor - 1) / factor * 24 + ext_align_size; in h265d_refine_rcb_size()
[all …]
H A Dhal_h265d_vdpu34x.c227 RK_S32 width, height; in hal_h265d_v345_output_pps_packet() local
256 width = (dxva_cxt->pp.PicWidthInMinCbsY << log2_min_cb_size); in hal_h265d_v345_output_pps_packet()
259 mpp_put_bits(&bp, width , 16); in hal_h265d_v345_output_pps_packet()
349 RK_S32 ctu_width_in_pic = (width + in hal_h265d_v345_output_pps_packet()
369 RK_S32 pic_in_cts_width = (width + in hal_h265d_v345_output_pps_packet()
391 column_width[0] = (width + MaxCUWidth - 1) / MaxCUWidth; in hal_h265d_v345_output_pps_packet()
451 RK_S32 width, height; in hal_h265d_output_pps_packet() local
482 width = (dxva_cxt->pp.PicWidthInMinCbsY << log2_min_cb_size); in hal_h265d_output_pps_packet()
485 mpp_put_bits(&bp, width , 16);//yandong in hal_h265d_output_pps_packet()
575 RK_S32 ctu_width_in_pic = (width + in hal_h265d_output_pps_packet()
[all …]
/rockchip-linux_mpp/inc/
H A Dmpp_sys_cfg_st.h18 RK_U32 width; member
30 RK_U32 width; member
51 RK_U32 width; member
/rockchip-linux_mpp/mpp/base/
H A Dmpp_sys_cfg.c81 …ENTRY(dec_buf_chk, width, u32, RK_U32, MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_WIDTH, …
264 static RK_S32 get_afbc_min_size(RK_S32 width, RK_S32 height, RK_S32 bpp) in get_afbc_min_size() argument
274 width = MPP_ALIGN(width, 16); in get_afbc_min_size()
278 n_blocks = (width * height) / AFBC_SUPERBLOCK_PIXELS; in get_afbc_min_size()
326 sys_cfg_dbg_dec_buf("org pixel wxh: [%d %d]\n", cfg->width, cfg->height); in mpp_sys_dec_buf_chk_proc()
334 aligned_pixel = MPP_ALIGN(cfg->width, 64); in mpp_sys_dec_buf_chk_proc()
341 aligned_pixel = MPP_ALIGN(cfg->width, 64); in mpp_sys_dec_buf_chk_proc()
345 aligned_pixel = MPP_ALIGN(cfg->width, 64); in mpp_sys_dec_buf_chk_proc()
349 aligned_pixel = MPP_ALIGN(cfg->width, 16); in mpp_sys_dec_buf_chk_proc()
423 aligned_pixel = cfg->width; in mpp_sys_dec_buf_chk_proc()
[all …]
/rockchip-linux_mpp/mpp/hal/rkdec/vp9d/
H A Dhal_vp9d_vdpu34x.c64 RK_S32 width; member
275 RK_S32 width, RK_S32 height, void* data) in vp9d_refine_rcb_size() argument
283 width = MPP_ALIGN(width, VP9_CTU_SIZE); in vp9d_refine_rcb_size()
286 if (width > 4096) in vp9d_refine_rcb_size()
287 rcb_bits = MPP_ALIGN(width, 64) * 232 + ext_align_size; in vp9d_refine_rcb_size()
292 if (width > 8192) in vp9d_refine_rcb_size()
293 rcb_bits = (MPP_ALIGN(width - 8192, 4) << 1) + ext_align_size; in vp9d_refine_rcb_size()
304 rcb_bits = width * 36 + ext_align_size; in vp9d_refine_rcb_size()
309 rcb_bits = width * 48 + ext_align_size; in vp9d_refine_rcb_size()
312 rcb_bits = width * (1 + 16 * bit_depth) + num_tiles * 192 * bit_depth + ext_align_size; in vp9d_refine_rcb_size()
[all …]
H A Dhal_vp9d_vdpu382.c64 RK_S32 width; member
276 RK_S32 width, RK_S32 height, void* data) in vp9d_refine_rcb_size() argument
284 width = MPP_ALIGN(width, VP9_CTU_SIZE); in vp9d_refine_rcb_size()
287 if (width >= 4096) in vp9d_refine_rcb_size()
288 rcb_bits = MPP_ALIGN(width, 64) * 232 + ext_align_size; in vp9d_refine_rcb_size()
294 if (width >= 8192) in vp9d_refine_rcb_size()
295 rcb_bits = (MPP_ALIGN(width - 8192, 4) << 1) + ext_align_size; in vp9d_refine_rcb_size()
308 rcb_bits = width * 36 + ext_align_size; in vp9d_refine_rcb_size()
315 rcb_bits = width * 2 * 11 + ext_align_size; in vp9d_refine_rcb_size()
319 rcb_bits = width * (0.5 + 16 * bit_depth) + num_tiles_col * 192 * bit_depth + ext_align_size; in vp9d_refine_rcb_size()
[all …]
H A Dhal_vp9d_vdpu383.c58 RK_S32 width; member
380 RK_S32 width, RK_S32 height, void* data) in vp9d_refine_rcb_size() argument
391 width = MPP_ALIGN(width, VP9_CTU_SIZE); in vp9d_refine_rcb_size()
394 if (width > 4096) in vp9d_refine_rcb_size()
395 rcb_bits = ((width + 63) / 64) * 250; in vp9d_refine_rcb_size()
402 rcb_bits = ((width + 63) / 64) * 2368; in vp9d_refine_rcb_size()
411 rcb_bits = MPP_ALIGN(width, 512) * (bit_depth + 2); in vp9d_refine_rcb_size()
422 if (width > 4096) in vp9d_refine_rcb_size()
424 rcb_bits = (RK_U32)(MPP_ALIGN(width, 64) * (41 * bit_depth + 13)); in vp9d_refine_rcb_size()
451 RK_S32 width = vp9_ver_align(pic_param->width); in hal_vp9d_rcb_info_update() local
[all …]
/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_vdpu34x.c152 RK_S32 width; member
796 RK_S32 width, RK_S32 height) in h264d_refine_rcb_size() argument
803 width = MPP_ALIGN(width, H264_CTU_SIZE); in h264d_refine_rcb_size()
806 if (width > 4096) in h264d_refine_rcb_size()
807 rcb_bits = ((width + 15) / 16) * 154 * (mbaff ? 2 : 1); in h264d_refine_rcb_size()
812 if (width > 8192) in h264d_refine_rcb_size()
813 rcb_bits = ((width - 8192 + 3) / 4) * 2; in h264d_refine_rcb_size()
824 rcb_bits = width * 42; in h264d_refine_rcb_size()
829 rcb_bits = width * 44; in h264d_refine_rcb_size()
832 rcb_bits = width * (2 + (mbaff ? 12 : 6) * bit_depth); in h264d_refine_rcb_size()
[all …]
/rockchip-linux_mpp/mpp/codec/dec/dummy/
H A Ddummy_dec_api.c193 RK_U32 width, height; in dummy_dec_parse() local
204 width = DUMMY_DEC_FRAME_WIDTH; in dummy_dec_parse()
214 width = DUMMY_DEC_FRAME_NEW_WIDTH; in dummy_dec_parse()
218 mpp_frame_set_width(frame, width); in dummy_dec_parse()
220 mpp_frame_set_hor_stride(frame, MPP_ALIGN(width, 16)); in dummy_dec_parse()

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