64     RK_S32          width;  member
275                                  RK_S32 width, RK_S32 height, void* data)  in vp9d_refine_rcb_size()  argument
283     width = MPP_ALIGN(width, VP9_CTU_SIZE);  in vp9d_refine_rcb_size()
286     if (width > 4096)  in vp9d_refine_rcb_size()
287         rcb_bits = MPP_ALIGN(width, 64) * 232 + ext_align_size;  in vp9d_refine_rcb_size()
292     if (width > 8192)  in vp9d_refine_rcb_size()
293         rcb_bits = (MPP_ALIGN(width - 8192, 4) << 1) + ext_align_size;  in vp9d_refine_rcb_size()
304     rcb_bits = width * 36 + ext_align_size;  in vp9d_refine_rcb_size()
309     rcb_bits = width * 48 + ext_align_size;  in vp9d_refine_rcb_size()
312     rcb_bits = width * (1 + 16 * bit_depth) + num_tiles * 192 * bit_depth + ext_align_size;  in vp9d_refine_rcb_size()
318         rcb_bits = 8 * width * bit_depth + ext_align_size;  in vp9d_refine_rcb_size()
339     RK_S32 width  = vp9_ver_align(pic_param->width);  in hal_vp9d_rcb_info_update()  local
343         hw_ctx->width != width ||  in hal_vp9d_rcb_info_update()
346         hw_ctx->rcb_buf_size = vdpu34x_get_rcb_buf_size(hw_ctx->rcb_info, width, height);  in hal_vp9d_rcb_info_update()
347         vp9d_refine_rcb_size(hw_ctx->rcb_info, hw_regs, width, height, pic_param);  in hal_vp9d_rcb_info_update()
375         hw_ctx->width          = width;  in hal_vp9d_rcb_info_update()
385     RK_U32 width = pic_param->width;  in hal_vp9d_vdpu34x_setup_colmv_buf()  local
390     mv_size = vdpu34x_get_colmv_size(width, height, VP9_CTU_SIZE, colmv_byte, colmv_size, compress);  in hal_vp9d_vdpu34x_setup_colmv_buf()
536             (hw_ctx->ls_info.last_width != pic_param->width) ||  in hal_vp9d_vdpu34x_gen_regs()
779 …vp9_hw_regs->vp9d_param.reg75.last_widthheight_eqcur           = (pic_param->width == hw_ctx->ls_i…  in hal_vp9d_vdpu34x_gen_regs()
827     hw_ctx->ls_info.last_width = pic_param->width;  in hal_vp9d_vdpu34x_gen_regs()
832                      pic_param->width, pic_param->height,  in hal_vp9d_vdpu34x_gen_regs()