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/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dlowlevel.S34 ldr x1, =GICC_BASE
53 ldr x1, =GICC_BASE_64K
75 switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
83 ldr x1, =0x00000010
99 ldr x1, =0x00000020
102 ldr x1, =0x00000020
109 ldr x1, =CCI_MN_RNF_NODEID_LIST
115 ldr x1, =0x00FF000C
118 ldr x1, =0x00FF000C
121 ldr x1, =0x00FF000C
[all …]
/rk3399_rockchip-uboot/arch/arm/lib/
H A Drelocate_64.S30 adrp x1, __image_copy_start /* x1 <- address bits [31:12] */
31 add x1, x1, :lo12:__image_copy_start/* x1 <- address bits [11:00] */
32 subs x9, x0, x1 /* x9 <- Run to copy offset */
44 ldr x1, _TEXT_BASE /* x1 <- Linked &__image_copy_start */
45 subs x9, x0, x1 /* x9 <- Link to copy offset */
47 adrp x1, __image_copy_start /* x1 <- address bits [31:12] */
48 add x1, x1, :lo12:__image_copy_start/* x1 <- address bits [11:00] */
52 ldp x10, x11, [x1], #16 /* copy from source address [x1] */
54 cmp x1, x2 /* until source end address [x2] */
66 ldp x0, x1, [x2], #16 /* (x0,x1) <- (SRC location, fixup) */
[all …]
H A Dcrt0_aarch64_efi.S122 stp x0, x1, [sp, #16]
124 mov x3, x1
126 adrp x1, _DYNAMIC
127 add x1, x1, #:lo12:_DYNAMIC
131 ldp x0, x1, [sp, #16]
H A Dcrt0_64.S135 mov x1, sp
137 csel x0, x0, x1, ne
145 ldr x1, =__bss_end /* this is auto-relocated! */
148 cmp x0, x1
153 ldr x1, [x18, #GD_RELOCADDR] /* dest_addr */
H A Dccn504.S29 ldr x9, [x0, x1]
55 mov x10, x1
76 mov x10, x1
/rk3399_rockchip-uboot/arch/arm/dts/
H A Darmada-7040-db-nand.dts77 pin-func = < 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0
117 0x3 0x3 0x0 0x2 0x0 0x1 0x1 0x1 0x1 0x1
118 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x9 0xa
120 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1 0x1 0x1
121 0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe
131 #address-cells = <0x1>;
132 #size-cells = <0x1>;
H A Ddragonboard410c.dts32 #address-cells = <0x1>;
33 #size-cells = <0x1>;
40 #address-cells = <0x1>;
83 index = <0x1>;
92 #address-cells = <0x1>;
93 #size-cells = <0x1>;
96 reg = <0x0 0x1>;
97 #address-cells = <0x1>;
98 #size-cells = <0x1>;
119 reg = <0x1 0x1>;
H A Darmada-8040-db.dts107 0x9 0x9 0x8 0x8 0x1 0x1 0x1 0x1 0x1 0x1
108 0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe
114 * Lane 0: PCIe0 (x1)
119 * Lane 5: PCIe2 (x1)
206 * Lane 0: PCIe0 (x1)
210 * Lane 4: PCIe1 (x1)
211 * Lane 5: PCIe2 (x1)
H A Drv1108-sdram-ddr3-400.dtsi11 0x1
16 0x1
17 0x1
51 0x1
H A Dzynq-zturn-myir.dts46 gpios = <&gpio0 0x72 0x1>;
53 gpios = <&gpio0 0x73 0x1>;
60 gpios = <&gpio0 0x74 0x1>;
67 gpios = <&gpio0 0x0 0x1>;
74 gpios = <&gpio0 0x9 0x1>;
88 #address-cells = <0x1>;
93 gpios = <&gpio0 0x32 0x1>;
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/
H A Dstart.S72 ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */
73 sub x9, x0, x1 /* x9 <- Run-vs-link offset */
77 ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
99 switch_el x1, 3f, 2f, 1f
124 mov x1, #CR_I
126 mov x1, #0
130 orr x0, x0, x1
137 orr x0, x0, x1
150 orr x0, x0, x1
162 switch_el x1, 3f, 1f, 1f
[all …]
H A Dsec_firmware_asm.S29 str w3, [x1]
47 mov x1, 0x0
70 mov x2, x1
71 mov x1, x4
H A Dcache.S73 mov x1, x0
146 cmp x0, x1
173 cmp x0, x1
235 movn x1, #(CR_M | CR_C | CR_I)
236 and x1, x2, x1
238 3: msr sctlr_el3, x1
240 2: msr sctlr_el2, x1
242 1: msr sctlr_el1, x1
/rk3399_rockchip-uboot/doc/device-tree-bindings/spmi/
H A Dspmi-sandbox.txt7 - #address-cells: 0x1 - childs slave ID address
8 - #size-cells: 0x1
14 #address-cells = <0x1>;
15 #size-cells = <0x1>;
18 reg = <0x0 0x1>;
19 #address-cells = <0x1>;
20 #size-cells = <0x1>;
H A Dspmi-msm.txt13 - #address-cells: 0x1 - childs slave ID address
14 - #size-cells: 0x1
24 #address-cells = <0x1>;
25 #size-cells = <0x1>;
/rk3399_rockchip-uboot/drivers/rkflash/
H A Drk_sftl_arm_v8.S31 str w3, [x1]
70 adrp x1, .LANCHOR1
72 str w0, [x1, #:lo12:.LANCHOR1]
73 adrp x1, .LANCHOR2
74 ldrh w1, [x1, #:lo12:.LANCHOR2]
98 adrp x1, .LANCHOR5
112 strh w0, [x1, #:lo12:.LANCHOR5]
116 strh w0, [x1, #:lo12:.LANCHOR5]
142 ldrh w3, [x1, #:lo12:.LANCHOR5]
143 adrp x1, .LANCHOR16
[all …]
/rk3399_rockchip-uboot/drivers/rknand/
H A Drk_ftl_arm_v8.S17 adrp x1, .LANCHOR0
18 add x1, x1, :lo12:.LANCHOR0
20 add x2, x1, x0
22 ldr x0, [x1, x0]
54 ubfx x1, x0, 5, 11
56 lsl x1, x1, 2
60 ldr w0, [x3, x1]
62 str w0, [x3, x1]
74 ldrb w3, [x1, 1]
89 add x6, x1, x3
[all …]
H A Drk_zftl_arm_v8.S26 add x6, x1, x3
37 adrp x1, .LANCHOR0
39 ldrb w1, [x1, #:lo12:.LANCHOR0]
44 adrp x1, .LANCHOR2
46 ldrh w3, [x1, #:lo12:.LANCHOR2]
80 ldr x1, [x0]
84 cmp x19, x1
92 cmp x19, x1
94 adrp x1, .LANCHOR5
97 add x1, x1, :lo12:.LANCHOR5
[all …]
H A Drk_zftl_spl_arm_v8.S26 add x6, x1, x3
37 adrp x1, .LANCHOR0
39 ldrb w1, [x1, #:lo12:.LANCHOR0]
44 adrp x1, .LANCHOR2
46 ldrh w3, [x1, #:lo12:.LANCHOR2]
80 ldr x1, [x0]
84 cmp x19, x1
92 cmp x19, x1
94 adrp x1, .LANCHOR5
97 add x1, x1, :lo12:.LANCHOR5
[all …]
/rk3399_rockchip-uboot/doc/device-tree-bindings/pmic/
H A Dpm8916.txt8 - #address-cells: 0x1 (peripheral ID)
9 - #size-cells: 0x1 (size of peripheral register space)
15 reg = <0x0 0x1>;
16 #address-cells = <0x1>;
17 #size-cells = <0x1>;
/rk3399_rockchip-uboot/arch/mips/dts/
H A Dnexys4ddr.dts30 xlnx,duplex = <0x1>;
31 xlnx,include-global-buffers = <0x1>;
33 xlnx,include-mdio = <0x1>;
35 xlnx,rx-ping-pong = <0x1>;
36 xlnx,s-axi-id-width = <0x1>;
37 xlnx,tx-ping-pong = <0x1>;
/rk3399_rockchip-uboot/arch/x86/include/asm/arch-quark/acpi/
H A Dlpc.asl111 IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
112 IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
113 IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
114 IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
115 IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
116 IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
117 IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
/rk3399_rockchip-uboot/arch/arm/mach-tegra/
H A Dlowlevel_init.S17 ldr x1, =PRM_RSTCTRL
18 ldr w3, [x1]
21 str w3, [x1]
/rk3399_rockchip-uboot/drivers/ram/rockchip/sdram_inc/rk3308/
H A Dsdram-rk3308-ddr2-detect-393.inc9 .rank = 0x1,
14 .dbw = 0x1,
15 .bw = 0x1
H A Dsdram-rk3308-ddr3-detect-393.inc9 .rank = 0x1,
14 .dbw = 0x1,
15 .bw = 0x1

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